Semiconductor Devices

Abstract

To provide a semiconductor device that can improve electrical characteristics in structures containing SiC.SOLUTION: A semiconductor device 1 includes a SiC semiconductor layer 2 having a first main surface 3 and a second main surface 4, a semiconductor element formed on the first main surface 3, a group of ridges 12 including a plurality of ridges 11 formed at intervals along the first direction X and second direction Y on the second main surface 4, and an electrode 10 directly connected to the ridges 12 on the second main surface 4.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device including a SiC substrate, a Schottky barrier diode formed on the front surface of the SiC substrate, and an ohmic electrode layer formed on the back surface of the SiC substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-198780 Summary of the Invention [Problem to be solved by the invention]

[0004] One embodiment provides a semiconductor device that can improve electrical characteristics in a structure that includes SiC. [Means for solving the problem]

[0005] One embodiment provides a semiconductor device including a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from one another on the second main surface, some of the raised portions having first portions that overlap each other when viewed in a first direction that is one of the surface directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions.

[0006] One embodiment provides a semiconductor device including: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of protrusions including a plurality of protrusions formed at intervals from one another along a first direction and a second direction intersecting the first direction on the second main surface; and an electrode directly connected to the group of protrusions on the second main surface.

[0007] One embodiment provides a semiconductor device including: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer having an active region and a peripheral region; a semiconductor element formed on the first main surface; a group of protrusions including a plurality of protrusions formed at intervals from one another in a first direction and a second direction intersecting the first direction on the second main surface; and an electrode directly connected to the group of protrusions on the second main surface, wherein the electrode has an uneven surface shape, and the peripheral region is formed to surround the active region. In these semiconductor devices, the group of protrusions can increase the connection area of ​​the electrodes with respect to the second main surface, thereby improving the electrical characteristics.

[0008] The above and other objects, features and advantages will become more apparent from the following description of the embodiments with reference to the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a perspective view showing a semiconductor device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a top view of the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a bottom view of the semiconductor device shown in FIG. 1, showing a first embodiment of the raised portion group. [Figure 4A] FIG. 4A is a diagram showing a second example of the group of raised portions. [Figure 4B] FIG. 4B is a diagram showing a third example of the raised portion group. [Figure 4C] FIG. 4C is a diagram showing a fourth example of the raised portion group. [Figure 4D] FIG. 4D is a diagram showing a fifth example of the group of raised portions. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV shown in FIG. [Figure 6A] 6A is a top view showing a semiconductor wafer used to manufacture the semiconductor device shown in FIG. [Figure 6B]FIG. 6B is a bottom view of the semiconductor wafer shown in FIG. 6A, showing the state after the grinding step and the annealing treatment. [Figure 7] FIG. 7 is a flowchart illustrating an example of a method for manufacturing the semiconductor device shown in FIG. [Figure 8A] FIG. 8A is a cross-sectional view showing a method for manufacturing the semiconductor device shown in FIG. [Figure 8B] FIG. 8B is a cross-sectional view showing a step subsequent to FIG. 8A. [Figure 8C] FIG. 8C is a cross-sectional view showing a step subsequent to FIG. 8B. [Figure 8D] FIG. 8D is a cross-sectional view showing a step subsequent to FIG. 8C. [Figure 8E] FIG. 8E is a cross-sectional view showing a step subsequent to FIG. 8D. [Figure 8F] FIG. 8F is a cross-sectional view showing a step subsequent to FIG. 8E. [Figure 8G] FIG. 8G is a cross-sectional view showing a step subsequent to FIG. 8F. [Figure 8H] FIG. 8H is a cross-sectional view showing a step subsequent to FIG. 8G. [Figure 8I] FIG. 8I is a cross-sectional view showing a step subsequent to FIG. 8H. [Figure 8J] FIG. 8J is a cross-sectional view showing a step subsequent to FIG. 8I. [Figure 8K] FIG. 8K is a cross-sectional view showing a step subsequent to FIG. 8J. [Figure 8L] FIG. 8L is a cross-sectional view showing a step subsequent to FIG. 8K. [Figure 8M] FIG. 8M is a cross-sectional view showing a step subsequent to FIG. 8L. [Figure 8N] FIG. 8N is a cross-sectional view showing a step subsequent to FIG. 8M. [Figure 8O] FIG. 8O is a cross-sectional view showing a step subsequent to FIG. 8N. [Figure 8P] FIG. 8P is a cross-sectional view showing a step subsequent to FIG. 8O. [Figure 8Q] FIG. 8Q is a cross-sectional view showing a step subsequent to FIG. 8P. [Figure 8R]FIG. 8R is a cross-sectional view showing a step subsequent to FIG. 8Q. [Figure 9] FIG. 9 is a graph showing the relationship between the resistance value and the thickness of the metal layer. [Figure 10] FIG. 10 is a graph showing the relationship between the resistance value and the overlap amount of the laser irradiation position. [Figure 11] FIG. 11 is a bottom view corresponding to FIG. 2, showing a semiconductor device according to a second embodiment of the present invention. [Figure 12] FIG. 12 is a cross-sectional view corresponding to FIG. 5, showing a semiconductor device according to a third embodiment of the present invention. [Figure 13] FIG. 13 is a cross-sectional view corresponding to FIG. 5, showing a semiconductor device according to a fourth embodiment of the present invention. [Figure 14] FIG. 14 is a top view showing the semiconductor device according to the fifth embodiment of the present invention, in which the structure above the first main surface of the SiC semiconductor layer is removed. [Figure 15] FIG. 15 is a cross-sectional view taken along line XV-XV shown in FIG. [Figure 16] FIG. 16 is a top view showing a semiconductor device according to a sixth embodiment of the present invention, in which the structure above the first main surface of the SiC semiconductor layer is removed. [Figure 17] FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. [Figure 18] FIG. 18 is a top view showing a semiconductor device according to a seventh embodiment of the present invention. [Figure 19] FIG. 19 is a bottom view of the semiconductor device shown in FIG. [Figure 20] FIG. 20 is an enlarged view of a region XX shown in FIG. 18, with the structure above the first main surface of the SiC semiconductor layer removed. [Figure 21] FIG. 21 is a cross-sectional view taken along line XXI-XXI in FIG. [Figure 22] FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. [Figure 23]FIG. 23 is an enlarged view of region XXIII in FIG. [Figure 24] FIG. 24 is a graph illustrating the sheet resistance. [Figure 25] FIG. 25 is an enlarged view of a region corresponding to FIG. 20, and is an enlarged view for explaining the structure of the semiconductor device according to the eighth embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view taken along line XXVI-XXVI shown in FIG. [Figure 27] FIG. 27 is a cross-sectional view of a region corresponding to FIG. 21, illustrating the structure of a semiconductor device according to a ninth embodiment of the present invention. [Figure 28] FIG. 28 is an enlarged view of a region corresponding to FIG. 20, and is an enlarged view for explaining the structure of the semiconductor device according to the tenth embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view of a region corresponding to FIG. 21, and is a plan view for explaining the structure of a semiconductor device according to an eleventh embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Fig. 1 is a perspective view showing a semiconductor device 1 according to a first embodiment of the present invention. Fig. 2 is a top view of the semiconductor device 1 shown in Fig. 1. Fig. 3 is a bottom view of the semiconductor device 1 shown in Fig. 1, showing a first embodiment of a raised portion group 12.

[0011] 1, semiconductor device 1 has SiC (silicon carbide) semiconductor layer 2 including SiC single crystal. SiC semiconductor layer 2 may include 4H—SiC single crystal.

[0012] The SiC semiconductor layer 2 has an off-angle tilted from the (0001) plane by an angle of 10° or less with respect to the [11-20] direction. More specifically, the off-angle is 0° or more and 4° or less (for example, 2° or 4°). The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, in the range of 2°±10% or 4°±10%.

[0013] The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, and 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed from a normal direction thereof (hereinafter simply referred to as "plan view").

[0014] Side surface 5A faces side surface 5D. Side surface 5B faces side surface 5C. Four side surfaces 5A to 5D each extend in a plane along a normal direction to first main surface 3 and second main surface 4. Each of side surfaces 5A to 5D may have a length of 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0015] 1 and 2, an insulating layer 6, an electrode 7, an insulating layer 8, and a resin layer 9 are formed on the first main surface 3. An electrode 10 is formed on the second main surface 4. The structures of the insulating layer 6, the electrode 7, the insulating layer 8, the resin layer 9, and the electrode 10 will be described later.

[0016] 3 and the enlarged view of FIG. 3, a group of raised portions 12 including a plurality of raised portions 11 is formed on the second main surface 4. The plurality of raised portions 11 are portions of the second main surface 4 that are raised along the normal direction of the second main surface 4.

[0017] The multiple protrusions 11 are formed at intervals along an arbitrary first direction X and a second direction Y intersecting the first direction X. The first direction X is one of the planar directions of the first main surface 3 of the SiC semiconductor layer 2.

[0018] In this embodiment, the first direction X is set to a direction parallel to the side surfaces 5B and 5D. More specifically, the second direction Y is a direction perpendicular to the first direction X. That is, in this embodiment, the second direction Y is set to a direction parallel to the side surfaces 5A and 5C.

[0019] The ridge group 12 has a first portion 17 in which some of the plurality of ridges 11 overlap in the first direction X when viewed in the first direction X. The ridge group 12 has a second portion 18 in which some of the plurality of ridges 11 are formed apart from the first portion 17 and overlap in the first direction X when viewed in the first direction X.

[0020] The plurality of raised portions 11 are continuously formed along the first direction X. More specifically, the plurality of raised portions 11 have a scattered pattern in which they are scattered at intervals along the first direction X and the second direction Y.

[0021] The plurality of raised portions 11 are formed continuously along the first direction X while maintaining this scattered pattern. In this embodiment, the plurality of raised portions 11 are formed from the periphery on one side surface 5A to the periphery on the other side surface 5C in plan view.

[0022] The distances between the plurality of raised portions 11 formed at intervals in the first direction X in the raised portion group 12 may be different from each other. The distances between the plurality of raised portions 11 formed at intervals in the second direction Y in the raised portion group 12 may be different from each other.

[0023] The plurality of protrusions 11 may be formed with non-uniform shapes, sizes, and thicknesses. The thickness of a protrusion 11 is the distance from the base to the top (tip) of the protrusion 11 in the normal direction to the second main surface 4.

[0024] The plurality of raised portions 11 may each have a size of more than 0 μm and not more than 10 μm in plan view. The thickness of each raised portion 11 may be more than 0 μm and not more than 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.

[0025] The thickness of each protrusion 11 may be greater than 0 nm and less than 500 nm, greater than 0 nm and less than 1 nm, greater than 1 nm and less than 50 nm, greater than 50 nm and less than 100 nm, greater than 100 nm and less than 200 nm, greater than 200 nm and less than 300 nm, greater than 300 nm and less than 400 nm, or greater than 400 nm and less than 500 nm.

[0026] The group of raised portions 12 is formed in a range narrower than the width of the side surfaces 5A to 5D (side surfaces 5A and 5C in this embodiment) on the second main surface 4. The group of raised portions 12 may be formed in a range of 1 / 1000 to 1 / 5 of the width of the side surfaces 5A to 5D (side surfaces 5A and 5C in this embodiment).

[0027] The group of raised portions 12 may be formed in a range of 1 / 1000 to 1 / 500, 1 / 500 to 1 / 100, 1 / 100 to 1 / 50, 1 / 50 to 1 / 100, 1 / 50 to 1 / 100, or 1 / 100 to 1 / 100, or 1 / 10 to 1 / 50, or 1 / 10 to 1 / 50, or 1 / 10 to 1 / 50, of the width of the side surfaces 5A to 5D.

[0028] The group of raised portions 12 may be formed in a range of 1 / 200 to 1 / 10 of the width of the side surfaces 5A to 5D (side surfaces 5A and 5C in this embodiment). The group of raised portions 12 may be formed in a range of 10 μm to 200 μm in the second direction Y.

[0029] The ridge group 12 may be formed in a range of 10 μm to 50 μm, 50 μm to 100 μm, 100 μm to 150 μm, or 150 μm to 200 μm in the second direction Y. The ridge group 12 may be formed in a range of 50 μm to 150 μm, or 80 μm to 120 μm in the second direction Y.

[0030] The raised portion group 12 has a layout in which, when viewed from the first direction X, the plurality of raised portions 11 overlap in the first direction X. The raised portion group 12 forms a raised portion group region 13 extending in a band shape along the first direction X by a collective pattern of the plurality of raised portions 11 continuously scattered along the first direction X.

[0031] In other words, the protuberance group region 13 includes a plurality of protuberances 11 (protuberance groups 12) formed in a band-shaped region extending along the first direction X on the second main surface 4. A plurality of protuberance groups 12 (protuberance group regions 13) having such a configuration are formed on the second main surface 4 at intervals along the second direction Y.

[0032] That is, the scattered pattern of the multiple raised portions 11 is formed intermittently when viewed in the second direction Y. The distance between the multiple raised portion groups 12 may be 1% or more and 25% or less of the area in which the raised portion groups 12 are formed. The distance between the multiple raised portion groups 12 may be 1% or more and 5% or less, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, or 20% or more and 25% or less of the area in which the raised portion groups 12 are formed.

[0033] The distance between adjacent raised portion groups 12 in the second direction Y may be greater than 0 μm and less than 100 μm. The distance between the raised portion groups 12 may be greater than 0 μm and less than 20 μm, greater than 20 μm and less than 40 μm, greater than 40 μm and less than 60 μm, greater than 60 μm and less than 80 μm, or greater than 80 μm and less than 100 μm. The distance between the raised portion groups 12 may be greater than 5 μm and less than 50 μm.

[0034] The first direction X may be set to the [11-20] direction, and the second direction Y may be set to the [1-100] direction. That is, the ridge group 12 may form a strip-shaped ridge group region 13 extending substantially parallel to or parallel to the [11-20] direction, and a plurality of the ridge group regions 13 may be formed at intervals along the [1-100] direction.

[0035] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. That is, the ridge group 12 may form a strip-shaped ridge group region 13 extending substantially parallel to or parallel to the [1-100] direction, and a plurality of ridge group regions 13 may be formed at intervals along the [11-20] direction.

[0036] Spaces 14 are defined in the regions between adjacent groups of raised portions 12 in the second direction Y on the second main surface 4. The spaces 14 do not have a dotted pattern including a plurality of raised portions 11.

[0037] The spaces 14 are partitioned into strips extending parallel to the first direction X by adjacent raised portion groups 12 (raised portion group regions 13). As a result, a stripe pattern including raised portion groups 12 and spaces 14 alternately formed along the second direction Y is formed on the second main surface 4.

[0038] A plurality of grooves 16 are formed in the second main surface 4. The grooves 16 are shown by lines in Figure 3 and the enlarged view of Figure 3. The grooves 16 are formed in the ridge groups 12 and the spaces 14.

[0039] The plurality of grooves 16 include grinding marks formed by grinding the second wafer main surface 43 of the SiC semiconductor wafer 41, which will be described later. Therefore, the direction in which the grooves 16 extend varies depending on the position at which the SiC semiconductor layer 2 is cut out from the SiC semiconductor wafer 41.

[0040] The grooves 16 may extend substantially parallel to or parallel to each of the ridge groups 12. The grooves 16 may include portions that intersect with the ridge groups 12. The grooves 16 may extend along a direction that intersects or is perpendicular to each of the ridge groups 12. The grooves 16 may extend linearly or in an arcuate shape.

[0041] Some of the multiple ridges 11 included in each ridge group 12 are formed at intervals along the grooves 16. In other words, each ridge group 12 includes a third portion 19 in which some of the multiple ridges 11 are formed at intervals along the grooves 16 in a plan view.

[0042] Each of the protrusion groups 12 is formed by, for example, an annealing process. The plurality of protrusions 11 may be laser processing marks formed by a laser annealing process.

[0043] The plurality of protrusions 11 (third portion 19 of protrusion group 12) along groove 16 may be formed by an annealing treatment method for the irregularities defined by grooves 16 on second main surface 4 (second wafer main surface 43 of SiC semiconductor wafer 41).

[0044] As shown in FIGS. 4A to 4D, each of the protrusion groups 12 can take various forms by adjusting the annealing treatment conditions (here, the laser annealing treatment conditions).

[0045] FIG. 4A is a diagram showing a second example of each of the protrusion groups 12. As shown in FIG.

[0046] 4A, the raised portion group 12 may include a convexly curved raised portion 11 that extends along the first direction X in a plan view and protrudes along the second direction Y (toward the side surface 5B in FIG. 4A). The raised portion 11 may be formed by a plurality of raised portions 11 that overlap each other.

[0047] The distance between the two most distant points on the raised portions 11 may be 1 μm or more and 200 μm or less (approximately 50 μm in this embodiment). The distance between adjacent raised portions 11 in the first direction X is set to a value equal to or more than 10% of the size of the raised portions 11. The raised portions 11 are formed by shifting the laser irradiation positions of adjacent raised portions 11 in the first direction X.

[0048] FIG. 4B is a diagram showing a third example of the raised portion group 12. As shown in FIG.

[0049] 4B, the raised portion group 12 may include a raised portion 11 that extends along the second direction Y in a plan view and is concavely curved and recessed along the first direction X. The raised portion 11 may be formed by a plurality of raised portions 11 that overlap each other.

[0050] The distance between the two furthest points on each raised portion 11 may be 1 μm or more and 200 μm or less (approximately 50 μm in this embodiment). The raised portions 11 are formed by overlapping adjacent laser irradiation positions by 50% or more and 70% or less.

[0051] FIG. 4C is a diagram showing a fourth example of the raised portion group 12. As shown in FIG.

[0052] 4C , the raised portion group 12 may include linear raised portions 11 that extend along the second direction Y in a plan view and are recessed along the first direction X. The raised portions 11 may have protrusions that protrude along the first direction X. The raised portions 11 may be formed by a plurality of raised portions 11 that overlap each other.

[0053] The distance between the two furthest points on the raised portion 11 may be 1 μm or more and 200 μm or less (approximately 50 μm in this embodiment). The raised portions 11 are formed by overlapping adjacent laser irradiation positions in a range of 70% or more and 90% or less.

[0054] FIG. 4D is a diagram showing a fifth example of the protrusion group 12. As shown in FIG.

[0055] As shown in FIG. 4D, the ridge group 12 may have a layout in which a ridge row including a plurality of ridges 11 spaced apart along the second direction Y is formed at intervals along the first direction X.

[0056] The distance between the two furthest points on the raised portion 11 may be 1 μm or more and 200 μm or less (approximately 5 μm in this embodiment). The raised portions 11 are formed by overlapping adjacent laser irradiation positions in a range of 90% or more and less than 100%.

[0057] FIG. 5 is a cross-sectional view taken along line VV shown in FIG.

[0058] 5, in this embodiment, SiC semiconductor layer 2 has a layered structure including an n+ type SiC semiconductor substrate 21 and an n type SiC epitaxial layer 22. SiC semiconductor substrate 21 forms second main surface 4. SiC epitaxial layer 22 forms first main surface 3. SiC semiconductor substrate 21 and SiC epitaxial layer 22 form side surfaces 5A to 5D.

[0059] The thickness of the SiC semiconductor substrate 21 may be 5 μm or more and 400 μm or less. The thickness of the SiC semiconductor substrate 21 may be 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, or 350 μm or more and 400 μm or less.

[0060] The thickness of the SiC semiconductor substrate 21 is preferably 80 μm or more and 200 μm or less (for example, about 150 μm). By reducing the thickness of the SiC semiconductor substrate 21, the resistance value can be reduced by shortening the current path.

[0061] SiC epitaxial layer 22 forms first main surface 3 and part of side surfaces 5A to 5D. SiC epitaxial layer 22 may have a thickness of 1 μm or more and 100 μm or less.

[0062] The thickness of the SiC epitaxial layer 22 may be 1 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 22 is preferably 5 μm or more and 15 μm or less (for example, about 10 μm).

[0063] The n-type impurity concentration of SiC epitaxial layer 22 is equal to or lower than the n-type impurity concentration of SiC semiconductor substrate 21. The n-type impurity concentration of SiC semiconductor substrate 21 may be equal to or higher than 1.0×10 cm and equal to or lower than 1.0×10 cm. The n-type impurity concentration of SiC epitaxial layer 22 may be equal to or higher than 1.0×10 cm and equal to or lower than 1.0×10 cm.

[0064] 5 and an enlarged view of FIG. 5, the above-described ridge group 12 and groove 16 are formed in SiC semiconductor substrate 21. A modified layer 4a, in which part of the SiC in SiC semiconductor layer 2 (SiC semiconductor substrate 21) is modified to have different properties, is formed in the surface layer portion of second main surface 4. Modified layer 4a is formed by annealing second main surface 4.

[0065] The modified layer 4a contains Si atoms and C atoms. More specifically, the modified layer 4a has a carbon density that is lower than the carbon density of the region outside the modified layer 4a in the SiC semiconductor layer 2 (SiC semiconductor substrate 21).

[0066] The modified layer 4a has a silicon density that exceeds the carbon density. That is, the modified layer 4a includes a Si modified layer in which SiC in the SiC semiconductor layer 2 (SiC semiconductor substrate 21) is modified to Si. The modified layer 4a may be a Si amorphous layer.

[0067] The modified layer 4a may include lattice defects resulting from the modification of SiC, that is, the modified layer 4a may include a lattice defect region having defect levels introduced due to the modification of SiC.

[0068] In this embodiment, the modified layer 4a is formed in a region along the raised portion groups 12 in the surface layer portion of the second main surface 4. The plurality of raised portions 11 in each raised portion group 12 are formed by the modified layer 4a. In other words, the plurality of raised portions 11 includes the modified layer 4a.

[0069] In this embodiment, the modified layer 4a is also formed in the spaces 14. The modified layer 4a extends from the ridge group 12 to the spaces 14. That is, the annealing treatment for the second main surface 4 also extends to the spaces 14.

[0070] Due to the presence of the raised portions 11, the thickness of the modified layer 4a along the raised portion group 12 is greater than or equal to the thickness of the modified layer 4a along the spaces 14. More specifically, the thickness of the modified layer 4a along the raised portion group 12 is greater than the thickness of the modified layer 4a along the spaces 14.

[0071] The thickness of the modified layer 4a may be 1 nm or more and 1000 nm or less. The thickness Ta of the region of the modified layer 4a where the protrusion 11 is formed may be 50 nm or more and 1000 nm or less. The thickness Tb of the region of the modified layer 4a outside the protrusion 11 may be 1 nm or more and 300 nm or less.

[0072] The thickness Ta may be 50 nm or more and 100 nm or less, 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, 400 nm or more and 500 nm or less, 500 nm or more and 600 nm or less, 600 nm or more and 700 nm or less, 700 nm or more and 800 nm or less, 800 nm or more and 900 nm or less, or 900 nm or more and 1000 nm or less.

[0073] The thickness Tb may be 1 nm or more and 10 nm or less, 10 nm or more and 50 nm or less, 50 nm or more and 100 nm or less, 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or more and 300 nm or less.

[0074] The thickness Tb may be 1 / 2 or less, 1 / 3 or less, 1 / 4 or less, 1 / 5 or less, 1 / 6 or less, 1 / 7 or less, 1 / 8 or less, 1 / 9 or less, 1 / 10 or less, 1 / 11 or less, 1 / 12 or less, 1 / 13 or less, 1 / 14 or less, 1 / 15 or less, 1 / 16 or less, 1 / 17 or less, 1 / 18 or less, 1 / 19 or less, or 1 / 20 or less of the thickness Ta.

[0075] The resistance value of the second main surface 4 when the ridge groups 12 are not present on the second main surface 4 is greater than the resistance value of the second main surface 4 when the ridge groups 12 are present on the second main surface 4. In other words, the plurality of ridge groups 12 have, as an electrical characteristic, a resistance value that is equal to or less than the resistance value of the SiC single crystal alone.

[0076] More specifically, the plurality of ridge groups 12 have a resistance value less than the resistance value of the SiC single crystal alone. Also, the plurality of ridge groups 12 have a resistance value less than the resistance value of the spaces 14. More specifically, the plurality of ridge groups 12 have a resistance value less than the resistance value of the spaces 14.

[0077] The resistance value, which is an electrical characteristic of the ridge group 12, is reduced by the modified layer 4a. That is, the resistance value of the ridge group 12 is equal to or less than the resistance value of the SiC single crystal due to the modified layer 4a. The resistance value, which is an electrical characteristic of the space 14, is also equal to or less than the resistance value of the SiC single crystal due to the modified layer 4a.

[0078] The electrode 10 described above is formed on the second main surface 4. The electrode 10 is directly connected to the second main surface 4. The electrode 10 covers the ridge groups 12 on the second main surface 4. In this embodiment, the electrode 10 covers the plurality of ridge groups 12 collectively.

[0079] The electrode 10 is formed in a film shape following the outer surface of the ridge group 12 (the outer surfaces of the plurality of ridges 11) and the inner surfaces of the grooves 16. As a result, the portion of the outer surface of the electrode 10 that covers the ridge group 12 (the plurality of ridges 11) has a ridge 10a that ridges in a direction away from the second main surface 4. Furthermore, the portion of the outer surface of the electrode 10 that covers the grooves 16 has a recess 10b that is recessed toward the second main surface 4.

[0080] The electrode 10 forms an ohmic contact with the second main surface 4. More specifically, the electrode 10 forms an ohmic contact with the ridge group 12. More specifically, the electrode 10 forms an ohmic contact with the plurality of ridge groups 12. In this embodiment, the electrode 10 also forms an ohmic contact with the space 14.

[0081] Electrode 10 has a layered structure including multiple electrode layers stacked on second principal surface 4. In this embodiment, electrode 10 has a four-layer structure including a Ti layer 31, a Ni layer 32, an Au layer 33, and an Ag layer 34 stacked in this order from second principal surface 4.

[0082] The Ti layer 31, Ni layer 32, Au layer 33, and Ag layer 34 are formed in the form of films conforming to the outer surfaces of the protrusion group 12 (the outer surfaces of the plurality of protrusions 11) and the inner surfaces of the grooves 16. The protrusions 10a and recesses 10b of the electrode 10 are formed on the outer surface of the Ag layer 34.

[0083] The Ti layer 31 is directly connected to the second main surface 4. The Ti layer 31 collectively covers the plurality of protrusion groups 12, and forms ohmic contact with the second main surface 4. In this embodiment, the Ti layer 31 also forms ohmic contact with the spaces 14.

[0084] The Ni layer 32 covers almost the entire area or the entire area of ​​the Ti layer 31. The Au layer 33 covers almost the entire area or the entire area of ​​the Ni layer 32. The Ag layer 34 covers almost the entire area or the entire area of ​​the Au layer 33.

[0085] The thickness of the Ti layer 31 may be 0.01 μm or more and 5 μm or less (for example, about 0.07 μm), and the thickness of the Ni layer 32 may be 0.1 μm or more and 40 μm or less (for example, about 1.2 μm).

[0086] The thickness of the Au layer 33 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 34 may be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). The electrode 10 may have a single-layer structure made up of the Ti layer 31, the Ni layer 32, the Au layer 33, or the Ag layer 34.

[0087] The electrode 10 forms an ohmic contact with the second main surface 4 without a silicide layer mainly containing silicide therebetween. The electrode 10 forms an ohmic contact with the protrusion group 12 without a silicide layer mainly containing silicide therebetween.

[0088] Electrode 10 forms ohmic contact with second main surface 4 without a carbon layer mainly composed of carbon therebetween. Electrode 10 forms ohmic contact with protrusion group 12 without a carbon layer mainly composed of carbon therebetween.

[0089] The electrode 10 does not include a region in which a material containing silicide as a main component is formed in a layer shape, nor does the electrode 10 include a region in which a material containing carbon as a main component is formed in a layer shape.

[0090] The electrode 10 engages with the uneven portion defined by the ridge group 12 (plurality of ridges 11) and the plurality of grooves 16. The contact area of ​​the electrode 10 with the second principal surface 4 is increased by the ridge group 12 (plurality of ridges 11). This increases the adhesive force of the electrode 10 with the second principal surface 4. The contact area of ​​the electrode 10 with the second principal surface 4 is also increased by the plurality of grooves 16.

[0091] An n-type diode region 23 is formed in the SiC epitaxial layer 22. A portion of the diode region 23 is exposed from the first main surface 3. In this embodiment, the diode region 23 is formed by utilizing a portion of the SiC epitaxial layer 22.

[0092] The diode region 23 may be formed by introducing an n-type impurity (donor) into a surface layer portion of the SiC epitaxial layer 22. In this case, the diode region 23 may have an n-type impurity concentration higher than the n-type impurity concentration of the SiC epitaxial layer 22.

[0093] The diode region 23 is formed in the center of the first main surface 3 in a plan view. The diode region 23 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view. The diode region 23 may also be formed in a circular shape in a plan view.

[0094] An impurity region 24 is formed around the diode region 23 in the surface layer portion of the SiC epitaxial layer 22. The impurity region 24 is a region into which p-type impurities (acceptors) are introduced along the periphery of the diode region 23. The impurity region 24 has a p-type impurity concentration higher than the n-type impurity concentration of the SiC epitaxial layer 22.

[0095] In this embodiment, the p-type impurities forming the impurity region 24 are not subjected to activation treatment. The impurity region 24 is formed as a non-semiconductor region that is not a p-type semiconductor region. The p-type impurities forming the impurity region 24 may be activated. In this case, the impurity region 24 becomes a p-type semiconductor region.

[0096] The impurity region 24 extends in a strip shape along the periphery of the diode region 23. In this embodiment, the impurity region 24 is formed in an endless shape (a square ring shape) surrounding the diode region 23. The impurity region 24 is also called a guard ring region. The inner periphery of the impurity region 24 defines the diode region 23.

[0097] The impurity regions 24 may be exposed from the side surfaces 5A to 5D. The impurity regions 24 may be formed at intervals from the side surfaces 5A to 5D toward the inner region.

[0098] The insulating layer 6 is formed on the first main surface 3. The insulating layer 6 may contain silicon oxide. The insulating layer 6 has an opening 25 that exposes the diode region 23. In this embodiment, the opening 25 also exposes the boundary between the diode region 23 and the impurity region 24. The opening 25 is formed in a quadrangle shape having four sides parallel to the side surfaces 5A to 5D in a plan view.

[0099] An electrode 7 is formed on the first main surface 3 on the diode region 23. The electrode 7 forms a Schottky junction with the diode region 23. This forms a Schottky barrier diode D with the electrode 7 as the anode and the diode region 23 as the cathode.

[0100] The peripheral edge of electrode 7 is formed in an inner region at a distance from side surfaces 5A to 5D. The peripheral edge of electrode 7 may overlap impurity region 24 in plan view. Electrode 7 is formed in a quadrangle shape having four sides parallel to side surfaces 5A to 5D in plan view.

[0101] The electrode 7 has a covering portion 26. The covering portion 26 extends from above the first main surface 3 onto the insulating layer 6, and covers a part of the insulating layer 6. The width of the covering portion 26 may be equal to or greater than the line width of the ridge group 12.

[0102] The electrode 7 includes at least one of aluminum, copper, molybdenum, nickel, an aluminum-copper alloy, an aluminum-silicon alloy, and an aluminum-silicon-copper alloy. In this embodiment, the electrode 7 includes an aluminum-copper alloy.

[0103] The aforementioned insulating layer 8 is formed on the insulating layer 6. In this embodiment, the insulating layer 8 contains silicon nitride. The insulating layer 8 may contain silicon oxide instead of or in addition to silicon nitride. The insulating layer 8 covers the electrode 7. The insulating layer 8 has a first opening 27 that exposes the electrode 7.

[0104] In this embodiment, first opening 27 covers the peripheral edge of electrode 7 and exposes the inner region of electrode 7. First opening 27 is formed in a quadrilateral shape having four sides parallel to side surfaces 5A to 5D in plan view.

[0105] The resin layer 9 is formed on the insulating layer 8. In this embodiment, the resin layer 9 contains a photosensitive resin. The resin layer 9 may contain a negative-type or positive-type photosensitive resin.

[0106] In this embodiment, the resin layer 9 contains polybenzoxazole, which is an example of a positive-type photosensitive resin. The resin layer 9 may contain polyimide, which is an example of a negative-type photosensitive resin.

[0107] The resin layer 9 is formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D in a plan view. The peripheral portion of the resin layer 9 is formed in an inward region from the side surfaces 5A to 5D with a gap therebetween, exposing the first main surface 3. More specifically, the peripheral portion of the resin layer 9 exposes the insulating layer 8.

[0108] A second opening 28 is formed in the inner portion of the resin layer 9. The second opening 28 communicates with the first opening 27 and exposes the electrode 7. The inner wall of the second opening 28 may be located outside the first opening 27. The inner wall of the second opening 28 may be located inside the first opening 27.

[0109] Fig. 6A is a top view showing SiC semiconductor wafer 41 used in manufacturing semiconductor device 1 shown in Fig. 1. Fig. 6B is a bottom view of SiC semiconductor wafer 41 shown in Fig. 6A, showing a state after second wafer main surface 43 of SiC semiconductor wafer 41 has been subjected to a grinding process and an annealing process.

[0110] 6A and 6B, the SiC semiconductor wafer 41 is made of a disk-shaped, plate-like SiC single crystal. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43.

[0111] The SiC semiconductor wafer 41 may include a 4H—SiC single crystal. The first wafer main surface 42 has an off-angle inclined from the (0001) plane to the [11-20] direction by an angle of 10° or less. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, in the range of 2°±10% or 4°±10%.

[0112] The SiC semiconductor wafer 41 includes one or more (one in this embodiment) orientation flats 45 formed on the wafer side surface 44. The orientation flat 45 is formed as an example of a mark indicating the crystal orientation. The orientation flat 45 includes a notch formed on the periphery of the SiC semiconductor wafer 41. In this embodiment, the orientation flat 45 extends linearly along the [11-20] direction.

[0113] The first wafer main surface 42 is an element formation surface on which semiconductor elements (in this embodiment, Schottky barrier diodes D) are formed. A plurality of device formation regions 46 each corresponding to a semiconductor device 1 are defined on the first wafer main surface 42.

[0114] In this embodiment, the device formation regions 46 are arranged in a matrix along the [11-20] direction ([-1-120] direction) and the [1-100] direction ([-1100] direction).

[0115] The plurality of device forming regions 46 are partitioned by lattice-shaped dicing lines 47. The semiconductor device 1 is cut out by cutting the SiC semiconductor wafer 41 along the peripheries (dicing lines 47) of the plurality of device forming regions 46.

[0116] Referring to FIG. 6B, after second wafer main surface 43 has been subjected to the grinding step and annealing treatment, a plurality of protrusion groups 12 and a plurality of grinding marks 48 are formed on second wafer main surface 43.

[0117] The plurality of ridge groups 12 are formed in stripes that are substantially parallel or parallel to the orientation flat 45. The plurality of ridge groups 12 may also be formed in stripes that intersect or are perpendicular to the orientation flat 45.

[0118] The plurality of grinding marks 48 each extend in an arc shape from the center toward the periphery of the SiC semiconductor wafer 41. The plurality of grinding marks 48 generally include grinding marks 48 that intersect with the [11-20] direction and the [1-100] direction.

[0119] The plurality of grinding marks 48 include grinding marks 48 that extend substantially parallel to or parallel to the [11-20] direction or the [1-100] direction in a portion where a tangent to the arc is along the [11-20] direction or the [1-100] direction. Grooves 16 formed in second main surface 4 of SiC semiconductor layer 2 may be formed by some of grinding marks 48.

[0120] Fig. 7 is a flowchart for explaining an example of a method for manufacturing the semiconductor device 1 shown in Fig. 1. Figs. 8A to 8R are cross-sectional views showing a method for manufacturing the semiconductor device 1 shown in Fig. 1. Figs. 8A to 8R show only one device formation region 46.

[0121] 8A, first, the above-mentioned n+ type SiC semiconductor wafer 41 is prepared (step S1 in FIG. 7). The SiC semiconductor wafer 41 serves as a base for the SiC semiconductor substrate 21.

[0122] 8B, an n-type SiC epitaxial layer 22 is formed on the first wafer main surface 42 (step S2 in FIG. 7). The SiC epitaxial layer 22 is formed by growing SiC from above the first wafer main surface 42 by epitaxial growth.

[0123] 8C, diode region 23 is defined in the main surface of SiC epitaxial layer 22. Next, impurity region 24 is formed in the surface portion of SiC epitaxial layer 22 so as to define diode region 23 (step S3 in FIG. 7). In this step, p-type impurities are introduced into the surface portion of SiC epitaxial layer 22 by ion implantation using ion implantation mask 51.

[0124] Next, referring to FIG. 8D, an insulating layer 6 is formed on the main surface of the SiC epitaxial layer 22 (Step S4 in FIG. 7). The insulating layer 6 may contain silicon oxide. The insulating layer 6 may be formed by a thermal oxidation process or a CVD (Chemical Vapor Deposition) method.

[0125] Next, referring to FIG. 8E, unnecessary portions of the insulating layer 6 are removed (step S5 in FIG. 7). The unnecessary portions of the insulating layer 6 may be removed by an etching method (e.g., wet etching) using a mask 52 having a predetermined pattern. The mask 52 has openings 53 that expose areas in the insulating layer 6 where the openings 25 are to be formed. As a result, the openings 25 are formed in the insulating layer 6.

[0126] Next, referring to FIG. 8F, electrode 7 is formed on the main surface of SiC epitaxial layer 22 (Step S6 in FIG. 7). Electrode 7 may include an aluminum-copper alloy. Electrode 7 may be formed by sputtering or CVD.

[0127] Next, referring to FIG. 8G, unnecessary portions of electrode 7 are removed (step S7 in FIG. 7). The unnecessary portions of electrode 7 may be removed by etching (e.g., dry etching) using a mask 54 having a predetermined pattern. As a result, electrode 7 is patterned into a predetermined shape.

[0128] Next, referring to FIG. 8H, an insulating layer 8 is formed on the insulating layer 6 so as to cover the electrode 7 (Step S8 in FIG. 7). The insulating layer 8 includes silicon nitride. The insulating layer 8 may be formed by a CVD method.

[0129] Next, referring to FIG. 8I, unnecessary portions of insulating layer 8 are removed (step S9 in FIG. 7). The unnecessary portions of insulating layer 8 may be removed by etching (e.g., wet etching) using a mask 55 having a predetermined pattern. Mask 55 has openings 56 that expose areas of insulating layer 8 where first openings 27 are to be formed. In this way, first openings 27 are formed in insulating layer 8.

[0130] Next, referring to FIG. 8J, a resin layer 9 is applied onto the insulating layer 8 so as to cover the electrodes 7 (step S12 in FIG. 7). In this embodiment, the resin layer 9 contains polybenzoxazole as an example of a positive-type photosensitive resin.

[0131] Next, the resin layer 9 is selectively exposed to light and then developed (step S11 in FIG. 7), thereby forming in the resin layer 9 second openings 28 communicating with the first openings 27 and dicing openings 57 exposing the dicing lines 47.

[0132] Next, referring to FIG. 8K, the second wafer main surface 43 is ground (step S12 in FIG. 7). In this step, the second wafer main surface 43 is ground using abrasive grains having a grit size of 500 or more. The grit size of the abrasive grains is preferably 1000 or more and 5000 or less. This leaves a plurality of grinding marks 48 on the second wafer main surface 43 (also see FIG. 6B). Furthermore, the second wafer main surface 43 is planarized and the SiC semiconductor wafer 41 is thinned at the same time.

[0133] Next, referring to FIG. 8L, a metal layer 61 is formed on the second wafer main surface 43 (step S13 in FIG. 7). In this embodiment, the metal layer 61 is made of a Ni layer. The Ni layer may be formed by a sputtering method. The thickness of the Ni layer may be 100 Å or more and 1000 Å or less.

[0134] Next, referring to Fig. 8M, an annealing process is performed on the second wafer main surface 43 (Step S14 in Fig. 7). In this step, a laser annealing process is performed as an example of the annealing process.

[0135] In the laser annealing method, a pulsed laser beam having a laser diameter φ of 50 μm or more and 200 μm or less (for example, about 100 μm) is used. The pulsed laser beam is a UV laser beam having a wavelength in the ultraviolet region. The energy of the pulsed laser beam may be 1.0 J / cm or more and 4.0 J / cm or less (for example, about 3.0 J / cm).

[0136] The pulsed laser light is applied to the second wafer main surface 43 through the metal layer 61. In parallel with the irradiation of the second wafer main surface 43 with the pulsed laser light, the irradiation position of the pulsed laser light on the second wafer main surface 43 is moved along the orientation flat 45. One or more raised portions 11 are formed in the region of the second wafer main surface 43 where the pulsed laser light is applied.

[0137] Furthermore, a modified layer 4a is formed in the region of the second wafer main surface 43 where the pulsed laser light is applied, in which the SiC of the SiC semiconductor wafer 41 is modified to have other properties. More specifically, the SiC of the SiC semiconductor wafer 41 is modified to Si by heating, causing C atoms to desorb and / or sublimate from the SiC.

[0138] As a result, a modified layer 4a including a Si modified layer is formed. The modified layer 4a may include a silicon amorphous layer. The modified layer 4a may include C atoms. One or more raised portions 11 formed on the second wafer main surface 43 may be formed by this modified layer 4a. As a result, one raised portion group 12 including multiple raised portions 11 and extending along the orientation flat 45 ([11-20] direction) is formed on the second wafer main surface 43.

[0139] After one protrusion group 12 (protrusion group region 13) is formed, the irradiation position of the pulsed laser beam is moved in the [1-100] direction. Then, in parallel with the irradiation of the second wafer main surface 43 with the pulsed laser beam, the irradiation position of the pulsed laser beam with respect to the second wafer main surface 43 is moved along the orientation flat 45.

[0140] As a result, another group of ridges 12 extending substantially parallel to or parallel to one group of ridges 12 is formed on the second wafer main surface 43. In the laser annealing method, such steps are repeated until a plurality of groups of ridges 12 are formed over substantially the entire area or the entire area of ​​the second wafer main surface 43 (see also FIG. 6B).

[0141] In this embodiment, the metal layer 61 that has undergone the laser annealing process has a layered structure including a carbon layer 62, a NiSi (nickel silicide) layer 63, and a Ni layer 64, which are layered in this order from the second wafer main surface 43 side. That is, the laser annealing process includes a step of reacting the metal layer 61 with the SiC semiconductor wafer 41 to convert it into a silicide. More specifically, the laser annealing process includes a step of forming the NiSi layer 63.

[0142] In the laser annealing method, in addition to the NiSi layer 63, a carbon layer 62 containing C atoms is formed as a by-product in the metal layer 61. The carbon layer 62 is formed by the precipitation of C atoms that constituted SiC.

[0143] In the metal layer 61, the carbon layer 62 and the NiSi layer 63 can be the starting points for peeling. In other words, although the metal layer 61 can be used as the electrode 10 as it is, the metal layer 61 has the problem of poor connection and an increase in resistance due to the poor connection. Therefore, it is preferable to form a metal layer different from the metal layer 61 as the electrode 10.

[0144] The temperature applied to the metal layer 61 in forming the NiSi layer 63 is equal to or higher than the melting point of the electrode 7 (for example, 1000°C or higher). The laser annealing method can locally increase the temperature of the second wafer main surface 43, thereby suppressing the temperature rise of the electrode 7. Therefore, melting of the electrode 7 can be appropriately suppressed.

[0145] 8N, a step of removing the metal layer 61 is performed. The step of removing the metal layer 61 is performed until the second wafer main surface 43 is exposed.

[0146] In this step, first, the NiSi layer 63 and the Ni layer 64 in the metal layer 61 are removed (step S15 in FIG. 7). The NiSi layer 63 and the Ni layer 64 may be removed by wet etching.

[0147] Next, referring to Figure 8O, the carbon layer 62 in the metal layer 61 is removed (step S16 in Figure 7). The carbon layer 62 may be removed by dry etching.

[0148] 8P, residues of the NiSi layer 63 and the Ni layer 64 adhering to the second wafer main surface 43 are removed (step S17 in FIG. 7). The NiSi layer 63 and the Ni layer 64 may be removed by wet etching.

[0149] Next, referring to FIG. 8Q, residue of the carbon layer 62 adhering to the second wafer main surface 43 is removed (step S18 in FIG. 7). The carbon layer 62 may be removed by dry etching. Next, the native oxide film is removed from the second wafer main surface 43 (step S19 in FIG. 7). The native oxide film may be removed by wet etching.

[0150] In this manner, in this embodiment, the step of removing the Ni-containing layer (NiSi layer 63 and Ni layer 64) and the step of removing the carbon-containing layer (carbon layer 62) are repeated twice. This allows the metal layer 61 to be properly removed. After the step of removing the metal layer 61, the second wafer main surface 43, the resistance of which has been reduced by the laser annealing process, is exposed.

[0151] 8R, the electrode 10 is formed on the second wafer main surface 43 (step S20 in FIG. 7). This step includes forming a Ti layer 31, a Ni layer 32, an Au layer 33, and an Ag layer 34 in this order on the second wafer main surface 43. The Ti layer 31, the Ni layer 32, the Au layer 33, and the Ag layer 34 may each be formed by sputtering.

[0152] Of the electrode 10, the Ti layer 31 is directly connected to the second wafer main surface 43. The Ti layer 31 collectively covers the plurality of protrusion groups 12, and forms ohmic contact with the plurality of protrusion groups 12 and with the plurality of spaces 14.

[0153] Next, the SiC semiconductor wafer 41 is cut along the peripheries (dicing lines 47) of the plurality of device formation regions 46 (step S21 in FIG. 7). As a result, a plurality of semiconductor devices 1 are cut out from the SiC semiconductor wafer 41. Through the steps including those described above, the semiconductor device 1 is manufactured.

[0154] Fig. 9 is a graph showing the relationship between the resistance value and the thickness of the metal layer 61. In Fig. 9, the vertical axis represents the resistance value (on-resistance) [Ω·cm2], and the horizontal axis represents the thickness [Å] of the metal layer 61.

[0155] In Fig. 9, "X" represents the overlap amount [μm] between adjacent laser irradiation positions in the first direction X. In Fig. 9, "Y" represents the distance [μm] between adjacent laser irradiation positions in the second direction Y.

[0156] "+Y" means that adjacent laser irradiation positions are separated from each other in the second direction Y. "-Y" means that adjacent laser irradiation positions overlap with each other in the second direction Y. The laser diameter φ of the laser light is approximately 100 μm. The energy of the laser light is measured with a fixed predetermined value.

[0157] FIG. 9 shows a first polygonal line A1, a second polygonal line B1, a third polygonal line C1, and a fourth polygonal line D1.

[0158] The first broken line A1 shows the relationship when (X, Y) = (90 μm, 50 μm). The second broken line B1 shows the relationship when (X, Y) = (65 μm, 50 μm). The third broken line C1 shows the relationship when (X, Y) = (85 μm, -10 μm). The fourth broken line D1 shows the relationship when (X, Y) = (80 μm, 15 μm).

[0159] With reference to the first to fourth broken lines A1 to D1, it was found that the resistance value tends to increase as the thickness of the metal layer 61 decreases. This is thought to be because when the thickness of the metal layer 61 is small, a portion of the metal layer 61 is sublimated by the irradiation of the pulsed laser light, and the annealing process is not carried out appropriately.

[0160] On the other hand, it was found that the resistance value decreases when the thickness of the metal layer 61 increases to a certain extent. When the thickness of the metal layer 61 is 500 Å or more, the resistance value becomes 2 Ω·cm2 or less, regardless of the amount of overlap of the irradiation position.

[0161] 9, it was found that the resistance value on the second main surface 4 depends on the thickness of the metal layer 61 formed during the manufacturing process. It was also found that the resistance value can be optimized by adjusting the thickness of the metal layer 61 and the amount of overlap between adjacent laser irradiation positions.

[0162] Fig. 10 is a graph showing the relationship between the resistance value and the overlap amount of the laser irradiation positions. In Fig. 10, the vertical axis represents the resistance value (on-resistance) [Ω·cm2]. In Fig. 10, the horizontal axis represents the overlap amount [μm] of adjacent laser irradiation positions in the first direction X. The thickness of the metal layer 61 is fixed to a predetermined value.

[0163] FIG. 10 shows a first polygonal line A2, a second polygonal line B2, a third polygonal line C2, and a fourth polygonal line D2.

[0164] The first broken line A2 shows the relationship when the laser beam energy is 1.5 J / cm2. The second broken line B2 shows the relationship when the laser beam energy is 2.0 J / cm2. The third broken line C2 shows the relationship when the laser beam energy is 2.5 J / cm2. The fourth broken line D2 shows the relationship when the laser beam energy is 3.0 J / cm2.

[0165] With reference to the first to fourth broken lines A2 to D2, it was found that the resistance value decreases as the laser beam energy increases. Furthermore, even when the laser beam energy is fixed, it was found that the resistance value can be reduced by increasing the overlap amount between adjacent laser irradiation positions.

[0166] 10, it was found that the resistance value on the second main surface 4 depends on the energy of the laser light and the amount of overlap between adjacent laser irradiation positions. It was also found that the resistance value can be optimized by adjusting these factors.

[0167] As described above, according to the semiconductor device 1, the group of protrusions 12 can increase the connection area of ​​the electrode 10 with respect to the second main surface 4. This can improve the electrical characteristics.

[0168] More specifically, the electrode 10 forms ohmic contact with the ridge group 12. This makes it possible to obtain good ohmic characteristics between the SiC semiconductor layer 2 and the electrode 10, thereby improving the electrical characteristics.

[0169] Furthermore, according to the semiconductor device 1, the electrode 10 is directly connected to the second main surface 4. More specifically, the electrode 10 forms ohmic contact with the protrusion group 12 without a carbon layer therebetween. The electrode 10 also forms ohmic contact with the protrusion group 12 without a silicide layer therebetween.

[0170] The carbon layer and silicide layer are likely to become the starting point of peeling. Therefore, a structure in which the electrode 10 is directly connected to the second main surface 4 can appropriately suppress connection failure and an increase in resistance value due to connection failure.

[0171] 11 is a bottom view corresponding to FIG. 2, showing a semiconductor device 71 according to a second embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0172] 11, the semiconductor device 71 has a plurality of protrusion groups 12 including a first protrusion group 12A and a second protrusion group 12B. The first protrusion group 12A includes a plurality of first protrusions 11A formed on the second main surface 4. The plurality of first protrusions 11A are portions of the second main surface 4 that protrude in the normal direction to the second main surface 4.

[0173] The multiple first raised portions 11A are formed at intervals from one another along a first direction X and a second direction Y that intersects with the first direction X. Some of the multiple first raised portions 11A have first portions 17A that overlap with the first direction X when viewed from the first direction X.

[0174] In addition, the first raised portion 11A has a second portion 18A in which some of the multiple first raised portions 11A are formed at a distance from the first portion 17A and overlap with the first direction X when viewed in the first direction.

[0175] The plurality of first raised portions 11A are continuously formed along the first direction X. More specifically, the plurality of first raised portions 11A have a scattered pattern in which they are scattered at intervals along the first direction X and the second direction Y.

[0176] The plurality of first raised portions 11A are formed continuously along the first direction X while maintaining this scattered pattern. In this embodiment, the scattered pattern of the plurality of first raised portions 11A is formed from the periphery on one side surface 5A to the periphery on the other side surface 5C in plan view.

[0177] The first raised portion group 12A has a layout in which the plurality of raised portions 11 overlap in the first direction X when viewed from the first direction X. As a result, the first raised portion group 12A forms a first raised portion group region 13A extending in a band shape along the first direction X by a collective pattern of the plurality of raised portions 11 continuously scattered along the first direction X.

[0178] The second raised portion group 12B includes a plurality of second raised portions 11B formed on the second main surface 4. The plurality of second raised portions 11B are portions that rise on the second main surface 4 in the normal direction of the second main surface 4.

[0179] The multiple second raised portions 11B are formed at intervals from one another along the first direction X and a second direction Y that intersects with the first direction X. The second raised portion group 12B has first portions 17B where some of the multiple second raised portions 11B overlap with the second direction Y when viewed from the second direction Y.

[0180] In addition, the second ridge group 12B has a second portion 18B in which some of the multiple second ridges 11B are formed at a distance from the first portion 17B and overlap with the second direction Y when viewed in the second direction.

[0181] The second raised portions 11B are continuously formed along the second direction Y. More specifically, the second raised portions 11B have a scattered pattern in which they are scattered at intervals along the first direction X and the second direction Y.

[0182] The plurality of second raised portions 11B are continuously formed along the second direction Y while maintaining this scattered pattern. In this embodiment, the scattered pattern of the plurality of second raised portions 11B is formed from the periphery on one side surface 5B to the periphery on the other side surface 5D in plan view.

[0183] The second raised portion group 12B has a layout in which the multiple second raised portions 11B overlap in the second direction Y when viewed from the second direction Y. As a result, the second raised portion group 12B forms a second raised portion group region 13B extending in a band shape along the second direction Y by a collective pattern of the multiple second raised portions 11B continuously scattered along the second direction Y.

[0184] The second ridge group 12B (second ridge group region 13B) crosses the first ridge group 12A (first ridge group region 13A). This forms an intersection region 72 on the second main surface 4. The intersection region 72 includes the first ridge group 12A (first ridge group region 13A) and the second ridge group 12B (second ridge group region 13B) that intersect with each other.

[0185] In this embodiment, a plurality of first raised portion groups 12A are formed at intervals along the second direction Y on the second main surface 4. That is, the scattered pattern of the plurality of first raised portions 11A is formed intermittently in the second direction Y.

[0186] In this embodiment, the second raised portion groups 12B are formed at intervals along the first direction X on the second main surface 4. That is, the scattered pattern of the second raised portions 11B is formed intermittently in the first direction X.

[0187] Therefore, in this embodiment, the intersection regions 72 are formed in a matrix arrangement spaced apart from one another along the first direction X and the second direction Y. Furthermore, the first ridge group 12A and the second ridge group 12B define spaces 14. The spaces 14 are formed in a matrix arrangement spaced apart from one another along the first direction X and the second direction Y.

[0188] The first ridges 11A and the second ridges 11B may overlap each other in the intersection region 72. The thicknesses of the first ridges 11A and the second ridges 11B formed in the intersection region 72 may be greater than the thicknesses of the first ridges 11A and the second ridges 11B formed in the region outside the intersection region 72.

[0189] Furthermore, the number of the multiple first raised portions 11A and the multiple second raised portions 11B formed in the intersection region 72 may be greater than the number of the first raised portions 11A and the second raised portions 11B formed in the region outside the intersection region 72.

[0190] The first direction X may be set to the [11-20] direction, and the second direction Y may be set to the [1-100] direction. In other words, the first ridge group 12A (first ridge group region 13A) may be formed substantially parallel to or parallel to the [11-20] direction, and the second ridge group 12B (second ridge group region 13B) may be formed substantially parallel to or parallel to the [1-100] direction.

[0191] The first direction X may be set to the [1-100] direction, and the second direction Y may be set to the [11-20] direction. That is, the first ridge group 12A (first ridge group region 13A) may be formed substantially parallel to or parallel to the [1-100] direction, and the second ridge group 12B (second ridge group region 13B) may be formed substantially parallel to or parallel to the [11-20] direction.

[0192] The first raised portion 11A and the first raised portion group 12A correspond to the raised portion 11 and the raised portion group 12 according to the first embodiment. The description of the raised portion 11 and the raised portion group 12 according to the first embodiment applies mutatis mutandis to the description of the first raised portion 11A and the first raised portion group 12A, and other specific descriptions of the first raised portion 11A and the first raised portion group 12A will be omitted.

[0193] The second raised portion 11B and the second raised portion group 12B correspond to the raised portion 11 and the raised portion group 12 according to the first embodiment. The description of the raised portion 11 and the raised portion group 12 according to the first embodiment applies mutatis mutandis to other descriptions of the second raised portion 11B and the second raised portion group 12B, and other specific descriptions of the second raised portion 11B and the second raised portion group 12B will be omitted.

[0194] In this embodiment, the electrode 10 covers the first ridge group 12A and the second ridge group 12B on the second main surface 4. In this embodiment, the electrode 10 collectively covers the plurality of first ridge groups 12A and the plurality of second ridge groups 12B.

[0195] The electrode 10 is formed in a film shape following the outer surfaces of the first ridge group 12A (outer surfaces of the first ridges 11A), the outer surfaces of the second ridge group 12B (outer surfaces of the second ridges 11B), and the inner surfaces of the grooves 16.

[0196] As a result, although not shown, raised portions 10a are formed on the outer surface of electrode 10 in portions covering the outer surfaces of first raised portion group 12A (outer surfaces of first raised portions 11A) and second raised portion group 12B (outer surfaces of second raised portions 11B). In addition, recessed portions 10b are formed on the outer surface of electrode 10 in portions covering grooves 16.

[0197] The electrode 10 forms an ohmic contact with the second main surface 4. More specifically, the electrode 10 forms an ohmic contact with the first protrusion group 12A and the second protrusion group 12B.

[0198] More specifically, the electrode 10 forms ohmic contact with the plurality of first ridge groups 12A and the plurality of second ridge groups 12B. In this embodiment, the electrode 10 also forms ohmic contact with the space 14.

[0199] The portion of the electrode 10 covering the first ridge group 12A and the second ridge group 12B engages with the uneven portion defined by the plurality of first ridge groups 12A, the plurality of second ridge groups 12B and the plurality of grooves 16.

[0200] The contact area of ​​the electrode 10 with the second main surface 4 is increased by the plurality of first ridge groups 12A and the plurality of second ridge groups 12B. The contact area of ​​the electrode 10 with the second main surface 4 is also increased by the plurality of grooves 16. This increases the adhesion of the electrode 10 with the second main surface 4.

[0201] The semiconductor device 71 having such a structure is manufactured by carrying out the following steps in the process of FIG. 8M (step S14 in FIG. 7) described above.

[0202] First, a laser annealing process is used to form a plurality of first ridge groups 12A along a direction substantially parallel to or parallel to the orientation flat 45. Next, a laser annealing process is used to form a plurality of second ridge groups 12B along a direction intersecting (orthogonal to) the orientation flat 45.

[0203] In this step, a plurality of first raised portion groups 12A may be formed in a direction intersecting (orthogonal to) the orientation flat 45, and a plurality of second raised portion groups 12B may be formed substantially parallel to or parallel to the orientation flat 45. Thereafter, through the steps of Figures 8N to 8R, the semiconductor device 71 is manufactured.

[0204] The first ridge group 12A and the second ridge group 12B may be formed in any order. Thus, the first ridge group 12A may be formed after the second ridge group 12B is formed. The first ridge group 12A and the second ridge group 12B may be formed alternately.

[0205] As described above, the semiconductor device 71 can also achieve the same effects as those described for the semiconductor device 1.

[0206] 12 is a cross-sectional view corresponding to FIG. 5, showing a semiconductor device 81 according to a third embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0207] In the semiconductor device 81, the electrode 10 has a three-layer structure including a Ni layer 32, an Au layer 33, and an Ag layer 34 stacked in this order from the second main surface 4.

[0208] The Ni layer 32 is directly connected to the second main surface 4. The Ni layer 32 collectively covers the plurality of protrusion groups 12. The Ni layer 32 forms ohmic contact with the protrusion groups 12 and with the spaces 14.

[0209] The Au layer 33 covers almost the entire area or the entire area of ​​the Ni layer 32. The Ag layer 34 covers almost the entire area or the entire area of ​​the Au layer 33. The electrode 10 having such a structure is formed by omitting the step of forming the Ti layer 31 in step S20 of FIG.

[0210] As described above, the semiconductor device 81 can also achieve the same effects as those described for the semiconductor device 1. In the semiconductor device 81, the electrode 10 may have a single-layer structure made of the Ni layer 32.

[0211] 13 is a cross-sectional view corresponding to FIG. 5, showing a semiconductor device 91 according to a fourth embodiment of the present invention. In the following, structures corresponding to those described with respect to the semiconductor device 1 are given the same reference numerals, and descriptions thereof will be omitted.

[0212] In the semiconductor device 91, the electrode 10 includes a metal layer 61, an Au layer 33, and an Ag layer 34. In this embodiment, the metal layer 61 has a layered structure including a carbon layer 62, a NiSi layer 63, and a Ni layer 64, which are layered in this order from the second main surface 4 side.

[0213] The metal layer 61 is connected to the second main surface 4. The metal layer 61 collectively covers the plurality of ridge groups 12. The metal layer 61 forms ohmic contact with the ridge groups 12 and with the spaces 14. The Au layer 33 covers almost the entire area or the entire area of ​​the metal layer 61. The Ag layer 34 covers almost the entire area or the entire area of ​​the Au layer 33.

[0214] A semiconductor device 91 having such a structure is formed by omitting the steps of removing the metal layer 61 shown in Figures 8N to 8Q (steps S15 to S19 in Figure 7). In this semiconductor device 91, an Au layer 33 and an Ag layer 34 are formed on the metal layer 61 in the step shown in Figure 8R.

[0215] As described above, according to semiconductor device 91, since electrode 10 includes carbon layer 62 and NiSi layer 63, the connection strength of electrode 10 cannot be increased as much as in semiconductor device 1, but it can achieve substantially the same effects as those described for semiconductor device 1. In semiconductor device 91, electrode 10 may have a laminated structure made of metal layer 61.

[0216] Fig. 14 is a top view showing a semiconductor device 92 according to a fifth embodiment of the present invention, with the structure above the first main surface 3 removed. Fig. 15 is a cross-sectional view taken along line XV-XV shown in Fig. 14. In the following, structures corresponding to those described with respect to the semiconductor device 1 will be given the same reference numerals, and descriptions thereof will be omitted.

[0217] 14 and 15 , semiconductor device 92 has a JBS (Junction Barrier Schottky) structure 93 formed in a surface layer portion of first main surface 3. More specifically, JBS structure 93 includes n-type diode region 23 and p-type diode region 94. Diode region 94 forms a pn junction with diode region 23.

[0218] In this embodiment, the plurality of diode regions 94 are formed at intervals from one another in the surface layer portion of the diode region 23. The plurality of diode regions 94 are each formed in a strip shape extending parallel to an arbitrary first direction X. The plurality of diode regions 94 are formed at intervals from one another along a second direction Y intersecting the first direction X.

[0219] As a result, the plurality of diode regions 94 are arranged in a stripe pattern in plan view, sandwiching the diode region 23. The plurality of diode regions 94 each form a pn junction with the corresponding diode region 23.

[0220] When the first direction X is set to the [11-20] direction, the plurality of diode regions 94 may extend substantially parallel to or parallel to the [11-20] direction. When the first direction X is set to the [1-100] direction, the plurality of diode regions 94 may extend substantially parallel to or parallel to the [1-100] direction.

[0221] In this embodiment, the plurality of diode regions 94 extend in the same direction as the plurality of ridge groups 12. The plurality of diode regions 94 may also extend in a direction intersecting (orthogonal to) the plurality of ridge groups 12.

[0222] The electrode 7 forms a Schottky junction with the diode region 23 on the first main surface 3. This forms a Schottky barrier diode D with the electrode 7 as an anode and the diode region 23 as a cathode.

[0223] The electrode 7 forms an ohmic contact with the diode region 94 on the first principal surface 3. As a result, a pn junction diode Dpn is formed in the surface layer portion of the first principal surface 3, with the diode region 94 serving as the anode and the diode region 23 serving as the cathode.

[0224] As described above, the semiconductor device 92 can also achieve the same effects as those described for the semiconductor device 1. Furthermore, the semiconductor device 92 has a JBS structure 93 including the diode region 23 and the diode region 94 in the surface layer portion of the first main surface 3.

[0225] In the JBS structure 93, a depletion layer expands from the pn junction between the diode region 23 and the diode region 94. This reduces the electric field of the Schottky junction formed between the electrode 7 and the diode region 23. As a result, the leakage current can be reduced. The structures according to the first to fourth embodiments described above may be combined into a semiconductor device 92.

[0226] Fig. 16 is a top view showing a semiconductor device 95 according to a sixth embodiment of the present invention, with the structure above the first main surface 3 removed. Fig. 17 is a cross-sectional view taken along line XVII-XVII shown in Fig. 16. In the following, structures corresponding to those described with respect to the semiconductor device 1 will be given the same reference numerals, and descriptions thereof will be omitted.

[0227] 16 and 17, in semiconductor device 95, impurity region 24 includes a plurality of (for example, not less than 2 and not more than 20) impurity regions formed in a surface layer portion of first main surface 3. In this embodiment, impurity region 24 includes three impurity regions 24A, 24B, and 24C.

[0228] The impurity regions 24A to 24C are formed in this order at intervals along a direction away from the diode region 23. The impurity regions 24A to 24C each extend in a strip shape along the periphery of the diode region 23. The impurity regions 24A to 24C may each be formed in an endless shape (a quadrangular ring shape) surrounding the diode region 23.

[0229] Of the impurity regions 24A to 24C, the impurity region 24A located at the innermost position may define the diode region 23. The impurity region 24B surrounds the impurity region 24A. The impurity region 24C surrounds the impurity region 24B.

[0230] As described above, the semiconductor device 95 can also achieve the same effects as those described for the semiconductor device 1. The structures according to the first to fifth embodiments described above may be combined with the semiconductor device 95.

[0231] Fig. 18 is a top view showing a semiconductor device 101 according to a seventh embodiment of the present invention. Fig. 19 is a bottom view of the semiconductor device 101 shown in Fig. 18. Fig. 20 is an enlarged view of region XX shown in Fig. 18, with the structure above the first main surface 103 of the SiC semiconductor layer 102 removed. Fig. 21 is a cross-sectional view taken along line XXI-XXI in Fig. 20. Fig. 22 is a cross-sectional view taken along line XXII-XXII in Fig. 20. Fig. 23 is an enlarged view of region XXIII in Fig. 22.

[0232] 18 to 23, a semiconductor device 101 has a SiC semiconductor layer 102 including a SiC (silicon carbide) single crystal. The SiC semiconductor layer 102 may include a 4H—SiC single crystal.

[0233] The 4H—SiC single crystal has an off-angle tilted from the

[0001] plane by an angle of 10° or less with respect to the [11-20] direction. The off-angle may be 0° or more and 4° or less. The off-angle may be greater than 0° and less than 4°. The off-angle is typically set to 2° or 4°, more specifically, within the range of 2°±10% or 4°±10%.

[0234] The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, and 105D connecting the first main surface 103 and the second main surface 104. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular in this embodiment) in a plan view (hereinafter simply referred to as "plan view") seen from the normal direction thereof.

[0235] Side surface 105A faces side surface 105C. Side surface 105B faces side surface 105D. The four side surfaces 105A to 105D each extend in a plane along the normal direction of first main surface 103 and second main surface 104. The length of each of side surfaces 105A to 105D may be 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less).

[0236] The SiC semiconductor layer 102 includes an active region 106 and an outer region 107. The active region 106 is a region in which a vertical MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed. The outer region 107 is a region outside the active region 106.

[0237] The active region 106 is formed in the center of the SiC semiconductor layer 102, spaced apart from the side surfaces 105A to 105D in a plan view. The active region 106 is formed in a quadrangular shape (rectangular in this embodiment) having four sides parallel to the four side surfaces 105A to 105D in a plan view.

[0238] The outer region 107 is formed in a region between the side surfaces 105A to 105D and the periphery of the active region 106. The outer region 107 is formed in an endless shape (quadratic ring shape) surrounding the active region 106 in a plan view.

[0239] A gate pad 108, gate fingers 109, and a source pad 110 are formed on the first main surface 103. The gate pad 108, gate fingers 109, and source pad 110 may include aluminum and / or copper.

[0240] The gate pad 108 is formed in a region along the side surface 105A in a plan view. The gate pad 108 is formed in a region along the center of the side surface 105A in a plan view. The gate pad 108 may be formed along a corner connecting any two of the four side surfaces 105A to 105D in a plan view.

[0241] The gate pad 108 is formed in a rectangular shape in a plan view. The gate pad 108 is drawn out from the outer region 107 into the active region 106 in a plan view, and crosses the boundary between the outer region 107 and the active region 106.

[0242] The gate fingers 109 include outer gate fingers 109A and inner gate fingers 109B. The outer gate fingers 109A extend from the gate pad 108 to the outer region 107. The outer gate fingers 109A extend in a strip shape in the outer region 107.

[0243] In this embodiment, the outer gate fingers 109A are formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102, and define the active region 106 from three directions.

[0244] The inner gate finger 109B is drawn out from the gate pad 108 to the active region 106. The inner gate finger 109B extends in a strip shape in the active region 106. The inner gate finger 109B extends from the side surface 105B toward the side surface 105D.

[0245] The source pad 110 is formed in the active region 106 at a distance from the gate pad 108 and the gate fingers 109. The source pad 110 covers the region defined by the gate pad 108 and the gate fingers 109 in a plan view and is formed in an inverted C shape.

[0246] A gate voltage is applied to the gate pad 108 and the gate fingers 109. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the source pad 110. The source voltage may be a reference voltage (for example, a GND voltage).

[0247] A resin layer 111 is formed on the first main surface 103. For clarity, the resin layer 111 is shown by hatching in Figure 18. The resin layer 111 covers the gate pad 108, the gate fingers 109, and the source pad 110.

[0248] The resin layer 111 may contain a negative or positive photosensitive resin. In this embodiment, the resin layer 111 contains polybenzoxazole as an example of a positive photosensitive resin. The resin layer 111 may also contain polyimide as an example of a negative photosensitive resin.

[0249] The peripheral portion of the resin layer 111 is formed at an interval inward from the side surfaces 105A to 105D, and exposes the first main surface 103. More specifically, the peripheral portion of the resin layer 111 exposes the interlayer insulating layer 161, which will be described later.

[0250] A gate pad opening 112 and a source pad opening 113 are formed in the inner portion of the resin layer 111. The gate pad opening 112 exposes the gate pad 108. The source pad opening 113 exposes the source pad 110.

[0251] 19 and 23, a ridge group 115 including a plurality of ridges 114, spaces 116, and grooves 117 are formed on second main surface 104. The ridge group 115 (the plurality of ridges 114), spaces 116, and grooves 117 include regions facing active region 106 and outer region 107, respectively.

[0252] The group of raised portions 115 (plurality of raised portions 114), the spaces 116 and the grooves 117 have structures corresponding to the group of raised portions 12 (plurality of raised portions 11), the spaces 14 and the grooves 16 according to the first embodiment (see also Figures 3 to 5, etc.).

[0253] The description of the ridge group 12 (multiple ridges 11), spaces 14 and grooves 16 in the first embodiment shall apply mutatis mutandis to the description of the ridge group 115, spaces 116 and grooves 117 in this embodiment, and other specific descriptions of the ridge group 115 (multiple ridges 114), spaces 116 and grooves 117 will be omitted.

[0254] The ridge group 115, the spaces 116, and the grooves 117 may have structures corresponding to the ridge group 12, the spaces 14, and the grooves 16 of the semiconductor device 71 according to the second embodiment (see also FIG. 11). In this case, the description of the ridge group 12, the spaces 14, and the grooves 16 according to the second embodiment applies mutatis mutandis to the description of the ridge group 115, the spaces 116, and the grooves 117 according to this embodiment.

[0255] 20 to 22, in this embodiment, SiC semiconductor layer 102 has a layered structure including an n+ type SiC semiconductor substrate 121 and an n type SiC epitaxial layer 122. Second main surface 104 is formed by SiC semiconductor substrate 121. First main surface 103 is formed by SiC epitaxial layer 122.

[0256] The thickness of the SiC semiconductor substrate 121 may be 5 μm or more and 400 μm or less. The thickness of the SiC semiconductor substrate 121 may be 5 μm or more and 50 μm or less, 50 μm or more and 100 μm or less, 100 μm or more and 150 μm or less, 150 μm or more and 200 μm or less, 200 μm or more and 250 μm or less, 250 μm or more and 300 μm or less, 300 μm or more and 350 μm or less, or 350 μm or more and 400 μm or less.

[0257] The thickness of SiC semiconductor substrate 121 is preferably 80 μm or more and 200 μm or less (for example, about 150 μm). By reducing the thickness of SiC semiconductor substrate 121, the resistance value can be reduced by shortening the current path.

[0258] The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 may be 1 μm or more and 25 μm or less, 25 μm or more and 50 μm or less, 50 μm or more and 75 μm or less, or 75 μm or more and 100 μm or less. The thickness of the SiC epitaxial layer 122 is preferably 5 μm or more and 15 μm or less (for example, about 10 μm).

[0259] The n-type impurity concentration of the SiC epitaxial layer 122 is equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 121. The n-type impurity concentration of the SiC epitaxial layer 122 is lower than the n-type impurity concentration of the SiC semiconductor substrate 121.

[0260] The n-type impurity concentration of the SiC semiconductor substrate 121 may be 1.0×10 18 cm −3 or more and 1.0×10 21 cm −3 or less. The n-type impurity concentration of the SiC epitaxial layer 122 may be 1.0×10 15 cm −3 or more and 1.0×10 18 cm −3 or less.

[0261] In this embodiment, SiC epitaxial layer 122 has a plurality of regions having different n-type impurity concentrations along the normal direction of first main surface 103. More specifically, SiC epitaxial layer 122 includes high-concentration region 122a having a relatively high n-type impurity concentration, and low-concentration region 122b having a lower n-type impurity concentration than high-concentration region 122a.

[0262] The high concentration region 122a is formed in a region on the first major surface 103 side. The low concentration region 122b is formed in a region on the second major surface 104 side with respect to the high concentration region 122a.

[0263] The n-type impurity concentration of the high concentration region 122a may be 1×10 16 cm −3 or more and 1×10 18 cm −3 or less, and the n-type impurity concentration of the low concentration region 122b may be 1×10 15 cm −3 or more and 1×10 16 cm −3 or less.

[0264] The thickness of the high concentration region 122a is equal to or less than the thickness of the low concentration region 122b. More specifically, the thickness of the high concentration region 122a is less than the thickness of the low concentration region 122b. In other words, the thickness of the high concentration region 122a is less than half of the total thickness of the SiC epitaxial layer 122.

[0265] 23, the raised portion group 115 (plurality of raised portions 114) and the grooves 117 are formed in the SiC semiconductor substrate 121. A modified layer 104a, in which part of the SiC in the SiC semiconductor layer 102 (SiC semiconductor substrate 121) is modified to have different properties, is formed in the surface layer portion of the second main surface 104. The modified layer 104a is formed by annealing the second main surface 104.

[0266] The modified layer 104a includes Si atoms and C atoms. More specifically, the modified layer 104a has a carbon density that is lower than the carbon density of the region outside the modified layer 104a in the SiC semiconductor layer 102 (SiC semiconductor substrate 121).

[0267] The modified layer 104a has a silicon density that exceeds the carbon density. That is, the modified layer 104a includes a Si modified layer in which SiC in the SiC semiconductor layer 102 (SiC semiconductor substrate 121) is modified to Si. The Si modified layer may be a Si amorphous layer.

[0268] The modified layer 104a may include lattice defects resulting from the modification of SiC, i.e., the modified layer 104a may include a lattice defect region having defect levels introduced due to the modification of SiC.

[0269] In this embodiment, the modified layer 104a is formed in a region on the second main surface 104 that is aligned with the raised portion groups 115. As a result, the plurality of raised portions 114 in each raised portion group 115 are formed by the modified layer 104a.

[0270] In this embodiment, the modified layer 104a is also formed in the spaces 116. The modified layer 104a extends from the protrusion group 115 to the spaces 116. In other words, the annealing treatment for the second main surface 104 also extends to the spaces 116.

[0271] The thickness of the modified layer 104a along the ridge group 115 is greater than or equal to the thickness of the modified layer 104a along the space 116 due to the presence of the ridge 114. More specifically, the thickness of the modified layer 104a along the ridge group 115 is greater than the thickness of the modified layer 104a along the space 116.

[0272] The resistance value of second main surface 104 when ridge group 115 is not present on second main surface 104 is greater than the resistance value of second main surface 104 when ridge group 115 is present on second main surface 104.

[0273] That is, the plurality of ridge groups 115 have, as an electrical characteristic, a resistance value that is equal to or less than the resistance value of the SiC single crystal alone. More specifically, the plurality of ridge groups 115 have a resistance value that is less than the resistance value of the SiC single crystal alone. Furthermore, the plurality of ridge groups 115 have a resistance value that is equal to or less than the resistance value of the spaces 116. More specifically, the plurality of ridge groups 115 have a resistance value that is less than the resistance value of the spaces 116.

[0274] The resistance value, which is an electrical characteristic of the ridge group 115, is reduced by the modified layer 104a. That is, the resistance value of the ridge group 115 is equal to or less than the resistance value of the SiC single crystal due to the modified layer 104a. The resistance value, which is an electrical characteristic of the space 116, is also equal to or less than the resistance value of the SiC single crystal due to the modified layer 104a.

[0275] A drain pad 123 is formed on the second main surface 104. The maximum voltage that can be applied between the source pad 110 and the drain pad 123 in the off state may be 1000V or more and 10000V or less.

[0276] 23, the drain pad 123 is directly connected to the second main surface 104. The drain pad 123 covers the protrusion groups 115 on the second main surface 104. In this embodiment, the drain pad 123 covers the plurality of protrusion groups 115 collectively.

[0277] The drain pad 123 is formed in the shape of a film following the outer surface of the protuberance group 115 (the outer surfaces of the plurality of protuberances 114) and the inner surfaces of the grooves 117. As a result, a protuberance 123a protruding in a direction away from the second main surface 104 is formed on the outer surface of the drain pad 123 in a portion covering the outer surface of the protuberance group 115 (the outer surfaces of the plurality of protuberances 114). In addition, a recess 123b recessed toward the second main surface 104 is formed on the outer surface of the drain pad 123 in a portion covering the grooves 117.

[0278] The drain pad 123 forms an ohmic contact with the second main surface 104. More specifically, the drain pad 123 forms an ohmic contact with the protrusion group 115.

[0279] More specifically, the drain pad 123 forms ohmic contact with the plurality of protrusion groups 115. In this form, the drain pad 123 also forms ohmic contact with the spaces 116.

[0280] The drain pad 123 has a layered structure including a plurality of electrode layers stacked on the second main surface 104. In this embodiment, the drain pad 123 has a four-layer structure including a Ti layer 124, a Ni layer 125, an Au layer 126, and an Ag layer 127 stacked in this order from the second main surface 104.

[0281] The Ti layer 124, the Ni layer 125, the Au layer 126, and the Ag layer 127 are formed in the form of films conforming to the outer surfaces of the protrusion group 115 (the outer surfaces of the plurality of protrusions 114) and the inner surfaces of the grooves 117. The protrusions 123a and the recesses 123b of the drain pad 123 are formed on the outer surface of the Ag layer 127.

[0282] The Ti layer 124 is directly connected to the second main surface 104. The Ti layer 124 collectively covers the plurality of protrusion groups 115, and forms ohmic contact with the second main surface 104. In this embodiment, the Ti layer 124 also forms ohmic contact with the spaces 116.

[0283] The Ni layer 125 covers almost the entire area or the entire area of ​​the Ti layer 124. The Au layer 126 covers almost the entire area or the entire area of ​​the Ni layer 125. The Ag layer 127 covers almost the entire area or the entire area of ​​the Au layer 126.

[0284] The thickness of the Ti layer 124 may be 0.01 μm or more and 5 μm or less (for example, about 0.07 μm), and the thickness of the Ni layer 125 may be 0.1 μm or more and 40 μm or less (for example, about 1.2 μm).

[0285] The thickness of the Au layer 126 may be 0.1 μm or more and 40 μm or less (for example, about 0.07 μm). The thickness of the Ag layer 127 may be 0.1 μm or more and 40 μm or less (for example, about 0.3 μm). The drain pad 123 may have a single-layer structure made up of the Ti layer 124, the Ni layer 125, the Au layer 126, or the Ag layer 127.

[0286] The drain pad 123 forms an ohmic contact with the second main surface 104 without a silicide layer mainly containing silicide therebetween. The drain pad 123 forms an ohmic contact with each of the protrusion groups 115 without a silicide layer mainly containing silicide therebetween.

[0287] The drain pad 123 forms an ohmic contact with the second main surface 104 without a carbon layer mainly composed of carbon therebetween. The drain pad 123 forms an ohmic contact with each of the protrusion groups 115 without a carbon layer mainly composed of carbon therebetween.

[0288] The drain pad 123 does not include a region in which a material containing silicide as a main component is formed in a layer shape, nor does the drain pad 123 include a region in which a material containing carbon as a main component is formed in a layer shape.

[0289] The drain pad 123 may have a structure similar to that of the electrode 10 according to the third embodiment. The drain pad 123 may have a structure similar to that of the electrode 10 according to the fourth embodiment.

[0290] The SiC semiconductor substrate 121 is formed as a drain region 128 of the MISFET. The SiC epitaxial layer 122 is formed as a drift region 129 of the MISFET.

[0291] A p-type body region 131 is formed in a surface layer portion of the first main surface 103 in the active region 106. The p-type impurity concentration of the body region 131 may be 1×10 cm or more and 1×10 cm or less. The active region 106 is defined by the body region 131.

[0292] A plurality of gate trenches 135 are formed in the surface layer portion of the first main surface 103 in the active region 106. The plurality of gate trenches 135 are formed along the first direction X at intervals.

[0293] The multiple gate trenches 135 are formed in a band shape extending substantially parallel to or parallel to the second direction Y. The multiple gate trenches 135 are formed in a stripe shape extending substantially parallel to or parallel to the second direction Y in plan view. That is, in this embodiment, the multiple gate trenches 135 intersect with the multiple raised portion groups 115 in plan view.

[0294] The plurality of ridge groups 115 may be formed in stripes extending substantially parallel to or parallel to the second direction Y. In this case, the plurality of gate trenches 135 may extend substantially parallel to or parallel to the plurality of ridge groups 115 in plan view.

[0295] The multiple gate trenches 135 may be formed in stripes extending parallel to the first direction X. In this case, the multiple gate trenches 135 may extend substantially parallel to or parallel to the multiple raised portion groups 115 in plan view.

[0296] That is, each gate trench 135 may extend substantially parallel to or parallel to the [11-20] direction. Also, each gate trench 135 may extend substantially parallel to or parallel to the [1-100] direction that is perpendicular to the [11-20] direction.

[0297] In this embodiment, each gate trench 135 extends in a strip shape from the peripheral edge on one side (side surface 105B side) to the peripheral edge on the other side (side surface 105D side) on the first main surface 103 in plan view.

[0298] Each gate trench 135 crosses an intermediate portion between one peripheral edge portion and the other peripheral edge portion of the first main surface 103. One end of each gate trench 135 is located at one peripheral edge portion of the first main surface 103. The other end of each gate trench 135 is located at the other peripheral edge portion of the first main surface 103.

[0299] Each gate trench 135 has a length on the order of millimeters (1 mm or more). In this embodiment, the length of each gate trench 135 is 1 mm or more and 10 mm or less (e.g., 2 mm or more and 5 mm or less). The total extension of the one or more gate trenches 135 per unit area may be 0.5 μm / μm2 or more and 0.75 μm / μm2 or less.

[0300] Each gate trench 135 includes an active trench portion 135a and a contact trench portion 135b. The active trench portion 135a is a portion of the gate trench 135 formed in the active region 106. The contact trench portion 135b is a portion of the gate trench 135 drawn out from the active trench portion 135a to the outer region 107.

[0301] Each gate trench 135 penetrates the body region 131 and reaches the SiC epitaxial layer 122. The bottom wall of each gate trench 135 is located within the SiC epitaxial layer 122. More specifically, the bottom wall of each gate trench 135 is located in a high concentration region 122a of the SiC epitaxial layer 122.

[0302] The depth of the gate trench 135 may be 0.5 μm or more and 3 μm or less in the normal direction to the first main surface 103. The depth of the gate trench 135 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 4 μm or less. The depth of the gate trench 135 is preferably 0.5 μm or more and 1.0 μm or less.

[0303] The width in the first direction X of the gate trench 135 may be 0.1 μm or more and 2 μm or less. The width in the first direction X of the gate trench 135 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less. The width in the first direction X of the gate trench 135 is preferably 0.1 μm or more and 0.5 μm or less.

[0304] An opening edge 136 of each gate trench 135 includes a curved portion 137 that curves inward of the gate trench 135. The opening edge 136 of the gate trench 135 is a corner that connects the first main surface 103 and the sidewall of the gate trench 135. The electric field at the opening edge 136 of the gate trench 135 is alleviated by the curved portion 137.

[0305] An n+ type source region 138 is formed in a surface portion of the body region 131 in a region along the sidewall of the gate trench 135. The n-type impurity concentration of the source region 138 may be 1.0×10 cm or more and 1.0×10 cm or less. A plurality of source regions 138 are formed along one sidewall and the other sidewall of the gate trench 135 in the first direction X.

[0306] The source regions 138 are each formed in a strip shape extending substantially parallel to or parallel to the second direction Y. The source regions 138 are formed in a stripe shape in plan view. Like the gate trenches 135, the source regions 138 intersect with the raised portion groups 115 in plan view.

[0307] A gate insulating layer 139 and a gate electrode layer 140 are formed in each gate trench 135. The gate insulating layer 139 and the gate electrode layer 140 are indicated by hatching in FIG.

[0308] The gate insulating layer 139 includes silicon oxide. The gate insulating layer 139 may include other insulating films such as silicon nitride. The gate insulating layer 139 is formed in the form of a film along the inner wall surface of the gate trench 135. The gate insulating layer 139 defines a recess space within the gate trench 135.

[0309] The gate insulating layer 139 includes a first region 139a, a second region 139b, and a third region 139c. The first region 139a is formed along the sidewall of the gate trench 135. The second region 139b is formed along the bottom wall of the gate trench 135. The third region 139c is formed along the first main surface 103.

[0310] The thickness T1 of the first region 139a of the gate insulating layer 139 is smaller than the thickness T2 of the second region 139b of the gate insulating layer 139 and the thickness T3 of the third region 139c of the gate insulating layer 139.

[0311] The ratio T2 / T1 of the thickness T2 of the second region 139b to the thickness T1 of the first region 139a may be equal to or greater than 2 and equal to or less than 5. The ratio T3 / T1 of the thickness T3 of the third region 139c to the thickness T1 of the first region 139a may be equal to or greater than 2 and equal to or less than 5.

[0312] The thickness T1 of the first region 139a may be 0.01 μm or more and 0.2 μm or less, the thickness T2 of the second region 139b may be 0.05 μm or more and 0.5 μm or less, and the thickness T3 of the third region 139c may be 0.05 μm or more and 0.5 μm or less.

[0313] By forming the first region 139a thin, it is possible to suppress an increase in carriers induced in the region of the body region 131 near the sidewall of the gate trench 135. This makes it possible to suppress an increase in channel resistance. By forming the second region 139b thick, it is possible to alleviate electric field concentration on the bottom wall of the gate trench 135.

[0314] By forming the third region 139c thick, it is possible to improve the breakdown voltage of the gate insulating layer 139 in the vicinity of the opening edge portion 136 of the gate trench 135. By forming the third region 139c thick, it is possible to prevent the third region 139c from being lost due to etching.

[0315] This can prevent the first region 139a from being removed by etching due to the disappearance of the third region 139c, and as a result, the gate electrode layer 140 can be appropriately opposed to the SiC semiconductor layer 102 with the gate insulating layer 139 interposed therebetween.

[0316] The gate electrode layer 140 is embedded in the gate trench 135 with a gate insulating layer 139 sandwiched therebetween. More specifically, the gate electrode layer 140 is embedded in a recess space defined by the gate insulating layer 139 within the gate trench 135. The gate electrode layer 140 is controlled by a gate voltage.

[0317] The gate electrode layer 140 is formed in a wall shape extending along the normal direction of the first main surface 103 in a cross-sectional view. The gate electrode layer 140 has an upper end portion located on the opening side of the gate trench 135. The upper end portion of the gate electrode layer 140 is formed in a curved shape recessed toward the bottom wall of the gate trench 135.

[0318] The cross-sectional area of ​​the gate electrode layer 140 may be 0.05 μm 2 or more and 0.5 μm 2 or less. The cross-sectional area of ​​the gate electrode layer 140 is the cross-sectional area when the gate electrode layer 140 is cut in a direction perpendicular to the direction in which the gate trench 135 extends.

[0319] The cross-sectional area of ​​the gate electrode layer 140 may be 0.05 μm to 0.1 μm, 0.1 μm to 0.2 μm, 0.2 μm to 0.3 μm, 0.3 μm to 0.4 μm, or 0.4 μm to 0.5 μm. The cross-sectional area of ​​the gate electrode layer 140 is defined as the product of the depth of the gate electrode layer 140 and the width of the gate electrode layer 140.

[0320] The depth of the gate electrode layer 140 is the distance from the top to the bottom of the gate electrode layer 140. The width of the gate electrode layer 140 is the width of the gate electrode layer 140 at the midpoint between the top and bottom ends of the gate electrode layer 140.

[0321] When the upper end is a curved surface (in this embodiment, a curved surface recessed downward), the position of the upper end of the gate electrode layer 140 is set to the middle position on the upper surface of the gate electrode layer 140.

[0322] The gate electrode layer 140 includes p-type polysilicon doped with p-type impurities, which may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0323] The p-type impurity concentration of the gate electrode layer 140 is equal to or higher than the p-type impurity concentration of the body region 131. More specifically, the p-type impurity concentration of the gate electrode layer 140 is higher than the p-type impurity concentration of the body region 131.

[0324] The p-type impurity concentration of the gate electrode layer 140 may be 1×10 cm or more and 1×10 cm or less. The sheet resistance of the gate electrode layer 140 may be 10 Ω / □ or more and 500 Ω / □ or less (approximately 200 Ω / □ in this embodiment).

[0325] 20 and 22, a gate wiring layer 141 is formed in the outer region 107. The gate wiring layer 141 is electrically connected to the gate pad 108 and the gate finger 109.

[0326] The gate wiring layer 141 is formed on the first major surface 103. More specifically, the gate wiring layer 141 is formed on the third region 139c of the gate insulating layer 139.

[0327] In this embodiment, the gate wiring layer 141 is formed along the gate fingers 109. The gate wiring layer 141 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102, and defines the active region 106 from three directions.

[0328] The gate wiring layer 141 is connected to the gate electrode layer 140 exposed from the contact trench portion 135b of each gate trench 135. In this embodiment, the gate wiring layer 141 is formed by an extension portion that is extended from the gate electrode layer 140 onto the first main surface 103. An upper end portion of the gate wiring layer 141 is connected to an upper end portion of the gate electrode layer 140.

[0329] 21, a low resistance electrode layer 142 is formed on the gate electrode layer 140. The low resistance electrode layer 142 covers the upper end of the gate electrode layer 140 in the gate trench 135.

[0330] The low-resistance electrode layer 142 includes a conductive material having a sheet resistance lower than the sheet resistance of the gate electrode layer 140. The sheet resistance of the low-resistance electrode layer 142 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance of the low-resistance electrode layer 142 may be 0.01 Ω / □ or more and 0.1 Ω / □ or less, 0.1 Ω / □ or more and 1 Ω / □ or less, 1 Ω / □ or more and 2 Ω / □ or less, 2 Ω / □ or more and 4 Ω / □ or less, 4 Ω / □ or more and 6 Ω / □ or less, 6 Ω / □ or more and 8 Ω / □ or less, or 8 Ω / □ or more and 10 Ω / □ or less.

[0331] The current supplied into the gate trench 135 flows through the low-resistance electrode layer 142, which has a relatively low sheet resistance, and is transmitted to the gate electrode layer 140. This allows the entire gate electrode layer 140 to quickly transition from an OFF state to an ON state, thereby suppressing delays in switching response.

[0332] In particular, in the case of a gate trench 135 having a length on the order of millimeters (1 mm or more), it takes time for the current to propagate, but delays in switching response can be appropriately suppressed by the low-resistance electrode layer 142. In other words, the low-resistance electrode layer 142 is formed as a current diffusion electrode layer that diffuses the current within the gate trench 135.

[0333] The low resistance electrode layer 142 is formed in a film shape and has a connection portion 142a that contacts the upper end of the gate electrode layer 140 and a non-connection portion 142b on the opposite side.

[0334] The connection portion 142a and the non-connection portion 142b of the low resistance electrode layer 142 may be formed in a curved shape following the upper end portion of the gate electrode layer 140. The connection portion 142a and the non-connection portion 142b may take various forms.

[0335] The entire connecting portion 142a may be located above the first main surface 103. The entire connecting portion 142a may be located below the first main surface 103. The connecting portion 142a may include a portion located above the first main surface 103. The connecting portion 142a may include a portion located below the first main surface 103. The central portion of the connecting portion 142a may be located below the first main surface 103, and the peripheral portion of the connecting portion 142a may be located above the first main surface 103.

[0336] The entire non-connected portion 142b may be located above the first main surface 103. The entire non-connected portion 142b may be located below the first main surface 103. The non-connected portion 142b may include a portion located above the first main surface 103. The non-connected portion 142b may include a portion located below the first main surface 103. The central portion of the non-connected portion 142b may be located below the first main surface 103, and the peripheral portion of the non-connected portion 142b may be located above the first main surface 103.

[0337] The low resistance electrode layer 142 has an edge 142c that contacts the gate insulating layer 139. The edge 142c contacts a corner of the gate insulating layer 139 that connects the first region 139a and the second region 139b.

[0338] The edge portion 142c is formed on the first main surface 103 side of the bottom of the source region 138. The edge portion 142c is formed on the first main surface 103 side of the boundary between the body region 131 and the source region 138. The edge portion 142c faces the source region 138 with the gate insulating layer 139 interposed therebetween. The edge portion 142c does not face the body region 131 with the gate insulating layer 139 interposed therebetween.

[0339] This makes it possible to prevent a current path from being formed in the region of the gate insulating layer 139 between the low-resistance electrode layer 142 and the body region 131. The current path can be formed by undesired diffusion of the electrode material of the low-resistance electrode layer 142 into the gate insulating layer 139.

[0340] In particular, a structure in which the edge 142c of the low resistance electrode layer 142 is connected to the third region 139c (corner of the gate insulating layer 139) of the relatively thick gate insulating layer 139 is effective in reducing the risk of a current path.

[0341] In the normal direction of the first main surface 103, the thickness TR of the low-resistance electrode layer 142 is equal to or less than the thickness TG of the gate electrode layer 140 (TR≦TG). More specifically, the thickness TR of the low-resistance electrode layer 142 is equal to or less than half the thickness TG of the gate electrode layer 140 (TR≦TG / 2).

[0342] The ratio TR / TG of the thickness TR of the low resistance electrode layer 142 to the thickness TG of the gate electrode layer 140 is not less than 0.01 and not more than 1. The ratio TR / TG may be not less than 0.01 and not more than 0.1, not less than 0.1 and not more than 0.25, not less than 0.25 and not more than 0.5, not less than 0.5 and not more than 0.75, or not less than 0.75 and not more than 1.

[0343] The thickness TG of the gate electrode layer 140 may be 0.5 μm or more and 3 μm or less, or 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0344] The thickness TR of the low resistance electrode layer 142 may be 0.01 μm or more and 3 μm or less. The thickness TR may be 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0345] 22 , in this embodiment, the low-resistance electrode layer 142 also covers the upper end of the gate wiring layer 141. The portion of the low-resistance electrode layer 142 that covers the upper end of the gate wiring layer 141 is integrally formed with the portion of the low-resistance electrode layer 142 that covers the upper end of the gate electrode layer 140.

[0346] The low-resistance electrode layer 142 covers the entire gate electrode layer 140 and the entire gate wiring layer 141. A current supplied from the gate pad 108 and the gate finger 109 to the gate wiring layer 141 flows through the low-resistance electrode layer 142, which has a relatively low sheet resistance, and is transmitted to the gate electrode layer 140 and the gate wiring layer 141.

[0347] This allows the entire gate electrode layer 140 to be quickly transitioned from an OFF state to an ON state via the gate wiring layer 141. This makes it possible to suppress delays in switching response. In particular, in the case of a gate trench 135 having a length on the order of millimeters (1 mm or more), delays in switching response can be appropriately suppressed by the low-resistance electrode layer 142 covering the upper end of the gate wiring layer 141.

[0348] The low-resistance electrode layer 142 includes a polycide layer. The polycide layer is formed by silicidating a portion of the gate electrode layer 140 that forms a surface layer with a metal material. More specifically, the polycide layer is made of a p-type polycide layer containing p-type impurities added to p-type polysilicon (gate electrode layer 140).

[0349] In this embodiment, the low-resistance electrode layer 142 has a resistivity of 10 μΩ·cm to 110 μΩ·cm. The resistivity of the low-resistance electrode layer 142 may be 10 μΩ·cm to 25 μΩ·cm, 25 μΩ·cm to 50 μΩ·cm, 50 μΩ·cm to 75 μΩ·cm, 75 μΩ·cm to 100 μΩ·cm, or 100 μΩ·cm to 110 μΩ·cm. The low-resistance electrode layer 142 contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2.

[0350] Among these species, NiSi, CoSi2 and TiSi2 are particularly suitable for the polycide layer forming the low resistance electrode layer 142 because they have relatively small resistivity and temperature dependency.

[0351] Furthermore, the inventors' experiments showed that when TiSi2 was used as the material for the low-resistance electrode layer 142, an increase in the leakage current between the gate and source was observed when a low electric field was applied. In contrast, when CoSi2 was used, no increase in the leakage current between the gate and source was observed when a low electric field was applied. Considering that NiSi has issues with heat resistance compared to CoSi2, CoSi2 is most preferable as the polycide layer for forming the low-resistance electrode layer 142.

[0352] When the low-resistance electrode layer 142 is formed, the sheet resistance in the gate trench 135 is equal to or less than the sheet resistance of the gate electrode layer 140 alone. The sheet resistance in the gate trench 135 is preferably equal to or less than the sheet resistance of n-type polysilicon doped with n-type impurities.

[0353] The sheet resistance in the gate trench 135 is approximated to the sheet resistance of the low-resistance electrode layer 142. That is, the sheet resistance in the gate trench 135 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 135 may be 0.01 Ω / □ or more and 0.1 Ω / □ or less, 0.1 Ω / □ or more and 1 Ω / □ or less, 1 Ω / □ or more and 2 Ω / □ or less, 2 Ω / □ or more and 4 Ω / □ or less, 4 Ω / □ or more and 6 Ω / □ or less, 6 Ω / □ or more and 8 Ω / □ or less, or 8 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 135 is preferably less than 10 Ω / □.

[0354] 20 and 21 again, a plurality of source trenches 145 are formed in the first main surface 103 in the active region 106. Each source trench 145 is formed in a region between two adjacent gate trenches 135.

[0355] Each source trench 145 is formed in a strip shape extending substantially parallel to or parallel to the second direction Y. The source trenches 145 are formed in a stripe shape in plan view. Like the gate trenches 135, the source trenches 145 intersect with the raised portion groups 115 in plan view.

[0356] Each source trench 145 penetrates the body region 131 and reaches the SiC epitaxial layer 122. The bottom wall of each source trench 145 is located within the SiC epitaxial layer 122. More specifically, the bottom wall of each source trench 145 is located in a high concentration region 122a of the SiC epitaxial layer 122.

[0357] The depth of the source trench 145 may be approximately equal to the depth of the gate trench 135. The depth of the source trench 145 may be equal to or greater than the depth of the gate trench 135.

[0358] The pitch between the centers of adjacent source trenches 145 in the first direction X may be 1.5 μm or more and 3 μm or less. The pitch between the centers of the source trenches 145 may be 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, or 2.5 μm or more and 3 μm or less.

[0359] The depth of source trench 145 may be 0.5 μm or more and 10 μm or less in the normal direction to first main surface 103. The depth of source trench 145 may be 0.5 μm or more and 1 μm or less, 1 μm or more and 2.5 μm or less, 2.5 μm or more and 5 μm or less, 5 μm or more and 7.5 μm or less, or 7.5 μm or more and 10 μm or less.

[0360] The width in the first direction X of the source trench 145 may be 0.1 μm or more and 2 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

[0361] The width in the first direction X of the source trench 145 may be approximately equal to the width in the first direction X of the gate trench 135. The width in the first direction X of the source trench 145 may be equal to or greater than the width in the first direction X of the gate trench 135.

[0362] An opening edge 146 of each source trench 145 includes a curved portion 147 that curves inward of the source trench 145. The opening edge 146 of the source trench 145 is a corner that connects the first main surface 103 and the sidewall of the source trench 145.

[0363] The electric field at the opening edge 146 of the source trench 145 is dispersed along the curved portion 147. This allows the electric field concentration at the opening edge 146 of the source trench 145 to be alleviated.

[0364] In the SiC semiconductor layer 102, p+ type contact regions 148 are formed in regions along the side walls of the source trenches 145. A plurality of contact regions 148 are formed on one side surface and the other side surface of one source trench 145.

[0365] The contact regions 148 are formed at intervals along the second direction Y. The contact regions 148 are formed at intervals along the first direction X from the gate trench 135.

[0366] A p-type deep well region 149 is formed in a region of the SiC semiconductor layer 102 along the inner wall of the source trench 145. The deep well region 149 is formed in a strip shape extending along the source trench 145. The deep well region 149 extends along the inner wall of the source trench 145.

[0367] More specifically, the deep well region 149 extends along the sidewall of the source trench 145 and covers the bottom wall of the source trench 145 through the edge portion. The deep well region 149 is continuous with the body region 131 at the sidewall of the source trench 145.

[0368] The deep well region 149 has a bottom located on the second main surface 104 side with respect to the bottom wall of the gate trench 135. The deep well region 149 is formed in the high concentration region 122a of the SiC epitaxial layer 122.

[0369] The p-type impurity concentration of the deep well region 149 may be approximately equal to the p-type impurity concentration of the body region 131. The p-type impurity concentration of the deep well region 149 may be greater than the p-type impurity concentration of the body region 131. The p-type impurity concentration of the deep well region 149 may be less than the p-type impurity concentration of the body region 131.

[0370] The p-type impurity concentration of the deep well region 149 may be equal to or lower than the p-type impurity concentration of the contact region 148. The p-type impurity concentration of the deep well region 149 may be lower than the p-type impurity concentration of the contact region 148. The p-type impurity concentration of the deep well region 149 may be equal to or higher than 1.0×10 cm and equal to or lower than 1.0×10 cm.

[0371] A source insulating layer 150 and a source electrode layer 151 are formed in each source trench 145. In Fig. 2, the source insulating layer 150 and the source electrode layer 151 are shown by hatching for clarity.

[0372] The source insulating layer 150 may contain silicon oxide. The source insulating layer 150 is formed in the form of a film along the inner wall surface of the source trench 145, and defines a recess space within the source trench 145.

[0373] The source insulating layer 150 includes a first region 150a and a second region 150b. The first region 150a is formed along the sidewall of the source trench 145. The second region 150b is formed along the bottom wall of the source trench 145.

[0374] A thickness T11 of the first region 150a of the source insulating layer 150 is smaller than a thickness T12 of the second region 150b of the source insulating layer 150. A ratio T12 / T11 of the thickness T12 of the second region 150b to the thickness T11 of the first region 150a may be 2 or more and 5 or less.

[0375] The thickness T11 of the first region 150a may be 0.01 μm or more and 0.2 μm or less, and the thickness T12 of the second region 150b may be 0.05 μm or more and 0.5 μm or less.

[0376] The thickness T11 of the first region 150a may be approximately equal to the thickness T1 of the first region 139a of the gate insulating layer 139. The thickness T12 of the second region 150b may be approximately equal to the thickness T2 of the second region 139b of the gate insulating layer 139.

[0377] The source insulating layer 150 exposes the opening edge portion 146 of the source trench 145. More specifically, the source insulating layer 150 exposes the source region 138 and the contact region 148 from the opening edge portion 146 of the source trench 145.

[0378] More specifically, the first region 150a of the source insulating layer 150 has an upper end portion located on the opening side of the source trench 145. The upper end portion of the first region 150a is formed below the first main surface 103.

[0379] The upper end of the first region 150a exposes the sidewall of the source trench 145 on the opening side of the source trench 145. In this way, the first region 150a exposes the source region 138 and the contact region 148 from the opening edge portion 146 of the source trench 145.

[0380] The source electrode layer 151 is embedded in the source trench 145 with the source insulating layer 150 sandwiched therebetween. More specifically, the source electrode layer 151 is embedded in a recess space defined by the source insulating layer 150 within the source trench 145. The source electrode layer 151 is controlled by a source voltage.

[0381] The source electrode layer 151 has an upper end portion located on the opening side of the source trench 145. The upper end portion of the source electrode layer 151 is formed below the first main surface 103.

[0382] The upper end of the source electrode layer 151 may be formed flush with the upper end of the source insulating layer 150. The upper end of the source electrode layer 151 may protrude above the upper end of the source insulating layer 150.

[0383] The upper end of the source electrode layer 151 may be located lower than the upper end of the source insulating layer 150. The thickness of the source electrode layer 151 may be 0.5 μm to 10 μm (for example, about 1 μm). The thickness of the source electrode layer 151 may be 0.5 μm to 1 μm, 1 μm to 2 μm, 2 μm to 4 μm, 4 μm to 6 μm, 6 μm to 8 μm, or 8 μm to 10 μm.

[0384] The source electrode layer 151 preferably contains polysilicon, which has properties similar to those of SiC, thereby reducing stress generated in the SiC semiconductor layer 102. The source electrode layer 151 preferably contains p-type polysilicon doped with p-type impurities.

[0385] In this case, the source electrode layer 151 can be formed simultaneously with the gate electrode layer 140. The p-type impurity may contain at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

[0386] The p-type impurity concentration of the source electrode layer 151 is equal to or higher than the p-type impurity concentration of the body region 131. More specifically, the p-type impurity concentration of the source electrode layer 151 is higher than the p-type impurity concentration of the body region 131.

[0387] The p-type impurity concentration of the source electrode layer 151 may be 1×10 cm or more and 1×10 cm or less. The sheet resistance of the source electrode layer 151 may be 10 Ω / □ or more and 500 Ω / □ or less. The sheet resistance of the source electrode layer 151 may be 10 Ω / □ or more and 50 Ω / □ or less, 50 Ω / □ or more and 100 Ω / □ or less, 100 Ω / □ or more and 200 Ω / □ or less, 200 Ω / □ or more and 300 Ω / □ or less, 300 Ω / □ or more and 400 Ω / □ or less, or 400 Ω / □ or more and 500 Ω / □ or less.

[0388] The p-type impurity concentration of the source electrode layer 151 may be approximately equal to the p-type impurity concentration of the gate electrode layer 140. The sheet resistance of the source electrode layer 151 may be approximately equal to the sheet resistance of the gate electrode layer 140.

[0389] The source electrode layer 151 may contain n-type polysilicon instead of p-type polysilicon, or may contain at least one of tungsten, aluminum, copper, an aluminum alloy, and a copper alloy instead of p-type polysilicon.

[0390] As described above, the semiconductor device 101 has a trench gate electrode structure 152 and a trench source electrode structure 153. The trench gate electrode structure 152 includes a gate trench 135, a gate insulating layer 139, a gate electrode layer 140, and a low-resistance electrode layer 142. The trench source electrode structure 153 includes a source trench 145, a source insulating layer 150, and a source electrode layer 151.

[0391] 21 and 22 , an interlayer insulating layer 161 is formed on the first main surface 103. The interlayer insulating layer 161 selectively covers the active region 106 and the outer region 107. The interlayer insulating layer 161 covers the trench gate electrode structure 152 in the active region 106, and covers the gate wiring layer 141 in the outer region 107.

[0392] The interlayer insulating layer 161 may contain silicon oxide or silicon nitride. A gate contact hole 162 and a source contact hole 163 are formed in the interlayer insulating layer 161.

[0393] The gate contact hole 162 exposes the gate wiring layer 141 (low resistance electrode layer 142) in the outer region 107. The source contact hole 163 exposes the source region 138, the contact region 148, and the trench source electrode structure 153 in the active region 106. A gate pad 108, a gate finger 109, and a source pad 110 are formed on the interlayer insulating layer 161.

[0394] The gate finger 109 extends from above the interlayer insulating layer 161 into the gate contact hole 162. The gate finger 109 is electrically connected to the low-resistance electrode layer 142 in the gate contact hole 162. This allows an electrical signal from the gate pad 108 to be transmitted to the gate electrode layer 140 via the low-resistance electrode layer 142, which has a relatively low resistance value.

[0395] The source pad 110 extends from above the interlayer insulating layer 161 into the source contact hole 163. The source pad 110 is electrically connected to the source region 138, the contact region 148, and the source electrode layer 151 within the source contact hole 163. The source electrode layer 151 may be formed by utilizing a portion of the source pad 110.

[0396] Fig. 24 is a graph for explaining sheet resistance. In Fig. 24, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents items. Fig. 24 shows a first bar graph L1, a second bar graph L2, and a third bar graph L3.

[0397] The first bar graph L1 represents the sheet resistance of n-type polysilicon. The second bar graph L2 represents the sheet resistance of p-type polysilicon. The third bar graph L3 represents the sheet resistance in the gate trench 135 when a low-resistance electrode layer 142 is formed on the p-type polysilicon. Here, the low-resistance electrode layer 142 contains TiSi2 (p-type titanium silicide).

[0398] Referring to the first bar graph L1, the sheet resistance of the n-type polysilicon was 10 Ω / □. Referring to the second bar graph L2, the sheet resistance of the p-type polysilicon was 200 Ω / □. Referring to the third bar graph L3, the sheet resistance when the low resistance electrode layer 142 was formed on the p-type polysilicon was 2 Ω / □.

[0399] P-type polysilicon has a work function different from that of n-type polysilicon, and by burying p-type polysilicon in the gate trench 135, the gate threshold voltage Vth can be increased by about 1V.

[0400] However, p-type polysilicon has a sheet resistance several tens of times (approximately 20 times) higher than that of n-type polysilicon. Therefore, when p-type polysilicon is used as the material for gate electrode layer 140, the energy loss increases significantly as the parasitic resistance in gate trench 135 (hereinafter simply referred to as "gate resistance") increases.

[0401] In contrast, in a structure having a low-resistance electrode layer 142 on p-type polysilicon, the sheet resistance can be reduced to one hundredth or less compared to a structure without the low-resistance electrode layer 142. Furthermore, in a structure having the low-resistance electrode layer 142, the sheet resistance can be reduced to one fifth or less compared to a gate electrode layer 140 including n-type polysilicon.

[0402] As described above, according to the semiconductor device 101, the group of raised portions 115 can increase the connection area of ​​the drain pad 123 with the second main surface 104. This can improve the electrical characteristics.

[0403] More specifically, the drain pad 123 forms ohmic contact with the protrusion group 115. This makes it possible to obtain good ohmic characteristics between the SiC semiconductor layer 102 and the drain pad 123, thereby improving the electrical characteristics.

[0404] Furthermore, according to the semiconductor device 101, a trench gate electrode structure 152 is formed in which a gate electrode layer 140 is embedded in the gate trench 135 with a gate insulating layer 139 sandwiched therebetween. In this trench gate electrode structure 152, the gate electrode layer 140 is covered with a low-resistance electrode layer 142 in the limited space of the gate trench 135.

[0405] The gate electrode layer 140 includes p-type polysilicon, which can increase the gate threshold voltage Vth, and the low resistance electrode layer 142 includes a conductive material having a sheet resistance lower than that of p-type polysilicon.

[0406] This reduces the gate resistance, which in turn allows current to be efficiently spread along the trench gate electrode structure 152, thereby reducing switching delay.

[0407] In particular, the structure in which the gate electrode layer 140 is covered with the low-resistance electrode layer 142 eliminates the need to increase the p-type impurity concentration in the body region 131. Therefore, the gate threshold voltage Vth can be increased while preventing an increase in channel resistance.

[0408] Furthermore, in the semiconductor device 101, the gate wiring layer 141 is covered with the low resistance electrode layer 142 in the outer region 107. This also makes it possible to reduce the gate resistance of the gate wiring layer 141.

[0409] In particular, in a structure in which the gate electrode layer 140 and the gate wiring layer 141 are covered with the low-resistance electrode layer 142, the current can be efficiently diffused along the trench gate electrode structure 152. Therefore, the switching delay can be appropriately reduced.

[0410] Fig. 25 is an enlarged view of a region corresponding to Fig. 20, and is an enlarged view for explaining the structure of a semiconductor device 171 according to an eighth embodiment of the present invention. Fig. 26 is a cross-sectional view taken along line XXVI-XXVI shown in Fig. 25. In the following, structures corresponding to those of semiconductor device 101 are given the same reference numerals, and descriptions thereof will be omitted.

[0411] 25 and 26, in semiconductor device 171, outer gate trench 172 is formed in first main surface 103 in outer region 107. Outer gate trench 172 extends in outer region 107 in a strip shape.

[0412] The outer gate trench 172 extends along the gate finger 109 in a region below the gate finger 109. More specifically, the outer gate trench 172 is formed along three side surfaces 105A, 105B, and 105D of the SiC semiconductor layer 102, and defines the active region 106 from three directions. The outer gate trench 172 may be formed in an endless shape (for example, a rectangular ring shape) surrounding the active region 106.

[0413] The outer gate trench 172 communicates with the contact trench portion 135b of each gate trench 135. As a result, the outer gate trench 172 and the gate trench 135 are formed by a single trench.

[0414] A gate wiring layer 141 is buried in the outer gate trench 172. The gate wiring layer 141 is connected to the gate electrode layer 140 at the communicating portion between the outer gate trench 172 and the contact trench portion 135b.

[0415] In this embodiment, the low-resistance electrode layer 142 covers the upper surface of the gate wiring layer 141 in the outer gate trench 172. Therefore, the low-resistance electrode layer 142 covering the gate electrode layer 140 and the low-resistance electrode layer 142 covering the gate wiring layer 141 are both located within one trench.

[0416] As described above, the semiconductor device 171 can also achieve the same effects as those described for the semiconductor device 101. Furthermore, with the semiconductor device 171, it is not necessary to extend the gate wiring layer 141 onto the first main surface 103.

[0417] This makes it possible to prevent the gate wiring layer 141 from facing the SiC semiconductor layer 102 across the gate insulating layer 139 at the opening edge portions of the gate trench 135 and the outer gate trench 172. As a result, it is possible to prevent electric field concentration at the opening edge portions of the gate trench 135.

[0418] 27 is a cross-sectional view of a region corresponding to FIG. 21, illustrating the structure of a semiconductor device 181 according to the ninth embodiment of the present invention. In the following, structures corresponding to those of the semiconductor device 101 are given the same reference numerals and will not be described again.

[0419] 27 , in semiconductor device 181, each source trench 145 is formed deeper than gate trench 135. The bottom wall of each source trench 145 is located on the second main surface 104 side relative to the bottom wall of gate trench 135. More specifically, the bottom wall of each source trench 145 is located in high concentration region 122a of SiC epitaxial layer 122.

[0420] The ratio of the depth of the source trench 145 to the depth of the gate trench 135 may be 1.5 or greater, provided that the bottom wall of the source trench 145 is located within the high concentration region 122a. The ratio of the depth of the source trench 145 to the depth of the gate trench 135 is preferably 2 or greater.

[0421] The depth of the gate trench 135 may be 0.5 μm or more and 3 μm or less (for example, about 1 μm), and the depth of the source trench 145 may be 0.75 μm or more and 10 μm or less (for example, about 2 μm).

[0422] Similar to the semiconductor device 101, the contact region 148 extends along the inner wall of the source trench 145 and has a bottom located on the second main surface 104 side with respect to the bottom wall of the gate trench 135. The contact region 148 is formed in the high concentration region 122a of the SiC epitaxial layer 122.

[0423] As described above, the semiconductor device 181 can also achieve the same effects as those described for the semiconductor device 101.

[0424] 28 is a plan view of a region corresponding to FIG. 20, and is a plan view for explaining the structure of a semiconductor device 191 according to a tenth embodiment of the present invention. In the following, structures corresponding to those of the semiconductor device 101 are given the same reference numerals and will not be described again.

[0425] 28, in this embodiment, the gate trench 135 is formed in a lattice shape in plan view. The gate trench 135 integrally includes a plurality of gate trenches 135 extending parallel to the first direction X and a plurality of gate trenches 135 extending substantially parallel to or parallel to the second direction Y.

[0426] The first main surface 103 is partitioned into a plurality of cell regions 192 in a matrix by gate trenches 135. Each cell region 192 is formed in a quadrangular shape in plan view. A source trench 145 is formed in each of the plurality of cell regions 192. The source trench 145 may be formed in a quadrangular shape in plan view.

[0427] The cross-sectional view taken along line XXI-XXI in Fig. 28 is substantially the same as the cross-sectional view shown in Fig. 21. The cross-sectional view taken along line XXII-XXII in Fig. 28 is substantially the same as the cross-sectional view shown in Fig. 22.

[0428] As described above, the semiconductor device 191 can also achieve the same effects as those described for the semiconductor device 101. The gate trench 135 having a structure formed in a lattice shape instead of a stripe shape can also be applied to other forms.

[0429] Fig. 29 is a cross-sectional view of a region corresponding to Fig. 21, and is a plan view for explaining the structure of a semiconductor device 201 according to an eleventh embodiment of the present invention. In the following, structures corresponding to those of the semiconductor device 101 are given the same reference numerals and will not be described again.

[0430] 29, in a semiconductor device 201, an SiC semiconductor layer 102 includes a p+ type SiC semiconductor substrate 202 instead of an n+ type SiC semiconductor substrate 121. The p+ type SiC semiconductor substrate 202 is formed as a collector region of an IGBT (Insulated Gate Bipolar Transistor).

[0431] The description of the semiconductor device 101 applies mutatis mutandis to the description of the semiconductor device 201, with the "source" of the MISFET being read as the "emitter" of the IGBT, and the "drain" of the MISFET being read as the "collector" of the IGBT.

[0432] That is, the source pad 110 and the source region 138 are respectively referred to as the emitter pad (110) and the emitter region (138), and the drain pad 123 and the drain region 128 are respectively referred to as the collector electrode layer (123) and the collector region (128).

[0433] As described above, the semiconductor device 201 can also achieve the same effects as those described for the semiconductor device 101.

[0434] Although the present invention has been described above with reference to certain preferred embodiments, it is possible to embody the invention in other forms.

[0435] In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is reversed may be adopted, i.e., a p-type portion may be made n-type, and an n-type portion may be made p-type.

[0436] In the above-described embodiments, examples have been described in which the SiC semiconductor layers 2, 102 have a layered structure including the SiC semiconductor substrates 21, 121 and the SiC epitaxial layers 22, 122. However, the SiC semiconductor layers 2, 102 may have a single-layer structure made of the SiC semiconductor substrates 21, 121. Alternatively, the SiC semiconductor layers 2, 102 may have a single-layer structure made of the SiC epitaxial layers 22, 122.

[0437] In the above-described first to sixth embodiments, examples have been described in which electrode 10 includes Ti layer 31, Ni layer 32, Au layer 33, and / or Ag layer 34. However, electrode 10 may include an Al layer instead of or in addition to Ti layer 31, Ni layer 32, Au layer 33, and / or Ag layer 34.

[0438] The electrode 10 may have a laminated structure in which at least two of a Ti layer 31, a Ni layer 32, an Au layer 33, an Ag layer 34, and an Al layer are laminated in any manner, or may have a single layer structure including an Al layer.

[0439] In the seventh to eleventh embodiments described above, the SiC epitaxial layer 122 having the high concentration region 122a and the low concentration region 122b is formed by epitaxial growth. However, the SiC epitaxial layer 122 can also be formed by the following process.

[0440] First, an SiC epitaxial layer 122 having a relatively low n-type impurity concentration is formed by epitaxial growth. Next, n-type impurities are introduced into the surface layer of the SiC epitaxial layer 122 by ion implantation. This results in the formation of an SiC epitaxial layer 122 having a high-concentration region 122a and a low-concentration region 122b.

[0441] In the seventh to eleventh embodiments described above, examples have been described in which the gate electrode layer 140 and the gate wiring layer 141 include p-type polysilicon doped with p-type impurities. However, when an increase in the gate threshold voltage Vth is not important, the gate electrode layer 140 and the gate wiring layer 141 may include n-type polysilicon doped with n-type impurities instead of p-type polysilicon.

[0442] That is, the low-resistance electrode layer 142 may include n-type polycide. In this case, the low-resistance electrode layer 142 may be formed by silicidating a surface layer of n-type polysilicon with a metal material. With such a structure, it is possible to reduce the gate resistance.

[0443] In the seventh to eleventh embodiments described above, examples have been described in which the drain pad 123 includes the Ti layer 124, the Ni layer 125, the Au layer 126, and / or the Ag layer 127. The drain pad 123 may include an Al layer instead of or in addition to the Ti layer 124, the Ni layer 125, the Au layer 126, and / or the Ag layer 127.

[0444] In the seventh to eleventh embodiments described above, the drain pad 123 may have a laminated structure in which at least two of the Ti layer 124, the Ni layer 125, the Au layer 126, the Ag layer 127, and the Al layer are laminated in any manner. The drain pad 123 may also have a single layer structure including an Al layer.

[0445] The structure of the semiconductor device 201 according to the eleventh embodiment may be adopted in the seventh to tenth embodiments. That is, in the seventh to tenth embodiments, the p+ type SiC semiconductor substrate 202 may be adopted instead of the n+ type SiC semiconductor substrate 21, 121. In this case, in the description of each of the above-described embodiments, "source" should be read as "emitter" and "drain" should be read as "collector."

[0446] Examples of features extracted from this specification and drawings are given below.

[0447] [A1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a raised portion group including a plurality of raised portions formed at intervals from one another on the second main surface; and an electrode directly connected to the raised portion group on the second main surface.

[0448] In this semiconductor device, the ridges increase the connection area of ​​the electrodes to the second main surface, thereby improving electrical characteristics. Furthermore, in this semiconductor device, the electrodes are directly connected to the ridges, which reduces the increase in resistance due to poor connection.

[0449] [A2] The semiconductor device according to A1, wherein the electrodes are connected to the group of raised portions without a silicide layer therebetween.

[0450] [A3] The semiconductor device according to A1 or A2, wherein the electrodes are connected to the group of raised portions without a carbon layer therebetween.

[0451] [A4] The semiconductor device according to any one of A1 to A3, wherein the electrode contains at least one of Ti, Ni, Au, and Ag.

[0452] [A5] The semiconductor device according to any one of A1 to A4, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0453] [A6] The semiconductor device according to any one of A1 to A4, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0454] [A7] The semiconductor device described in any one of A1 to A6, wherein the group of raised portions has first portions in which some of the plurality of raised portions overlap each other when viewed from a first direction, which is one of the surface directions of the second main surface.

[0455] [A8] The semiconductor device described in A7, wherein the group of raised portions has second portions in which some of the plurality of raised portions are formed at a distance from the first portion when viewed in the first direction and overlap each other when viewed in the first direction.

[0456] [A9] The semiconductor device according to A7 or A8, wherein the group of raised portions is one of the planar directions of the first main surface, and is formed at intervals along a second direction that intersects with the first direction.

[0457] [A10] The semiconductor device according to A9, wherein the distance between adjacent groups of raised portions is 100 μm or less.

[0458] [A11] The semiconductor device according to A10, wherein the distance is 50 μm or less.

[0459] [A12] The semiconductor device according to A10 or A11, wherein the distance is 20 μm or less.

[0460] [A13] The semiconductor device according to any one of A7 to A12, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [11-20] direction of 4H—SiC.

[0461] [A14] The semiconductor device according to any one of A7 to A12, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [1-100] direction of 4H—SiC.

[0462] [A15] The semiconductor device according to A13 or A14, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10° or less from the (0001) plane of 4H—SiC to the [11-20] direction.

[0463] [A16] The semiconductor device according to A15, wherein the off angle is equal to or greater than 0° and equal to or less than 4°.

[0464] [A17] The semiconductor device according to A15 or A16, wherein the off angle is greater than 0° and less than 4°.

[0465] [A18] The semiconductor device according to any one of A7 to A17, wherein the group of raised portions is formed on the second main surface in a range of 10 μm to 200 μm in a direction perpendicular to the first direction.

[0466] [A19] The semiconductor device according to A18, wherein the range is 50 μm or more and 150 μm or less.

[0467] [A20] The semiconductor device according to A18 or A14, wherein the range is 80 μm or more and 120 μm or less.

[0468] [A21] The semiconductor device according to any one of A1 to A20, further including a groove formed in the second main surface.

[0469] [A22] The semiconductor device according to A21, wherein the groove includes a portion that intersects with the group of raised portions.

[0470] [A23] The semiconductor device described in A21 or A22, wherein the group of raised portions includes a portion in which some of the plurality of raised portions are formed at intervals along the groove in a plan view seen from the normal direction of the second main surface.

[0471] [A24] The semiconductor device according to any one of A1 to A23, wherein the semiconductor element includes a Schottky barrier diode.

[0472] [A25] The semiconductor device according to any one of A1 to A23, wherein the semiconductor element includes a field effect transistor.

[0473] [B1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from one another on the second main surface, some of the raised portions having first portions that overlap each other when viewed in a first direction that is one of the surface directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions.

[0474] According to this semiconductor device, the group of protrusions can increase the connection area of ​​the electrodes with respect to the second main surface, thereby improving the electrical characteristics.

[0475] [B2] The semiconductor device described in B1, wherein the group of raised portions has second portions in which some of the plurality of raised portions are formed at a distance from the first portion when viewed in the first direction and overlap each other when viewed in the first direction.

[0476] [B3] The semiconductor device according to B1 or B2, wherein the group of raised portions is one of the planar directions of the first main surface and is formed at intervals along a second direction that intersects with the first direction.

[0477] [B4] The semiconductor device according to B3, wherein the distance between adjacent groups of the raised portions is 100 μm or less.

[0478] [B5] The semiconductor device according to B4, wherein the distance is 50 μm or less.

[0479] [B6] The semiconductor device according to B4 or B5, wherein the distance is 20 μm or less.

[0480] [B7] The semiconductor device according to any one of B1 to B6, wherein the group of raised portions is formed on the second main surface in a range of 10 μm to 200 μm in a direction perpendicular to the first direction.

[0481] [B8] The semiconductor device according to B7, wherein the range is 50 μm or more and 150 μm or less.

[0482] [B9] The semiconductor device according to B7 or B8, wherein the range is 80 μm or more and 120 μm or less.

[0483] [B10] The semiconductor device according to any one of B1 to B9, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [11-20] direction of the 4H—SiC.

[0484] [B11] The semiconductor device according to any one of B1 to B9, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [1-100] direction of the 4H—SiC.

[0485] [B12] The semiconductor device according to B10 or B11, wherein the SiC semiconductor layer has an off-axis angle inclined at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane of the 4H—SiC.

[0486] [B13] The semiconductor device according to B12, wherein the off angle is equal to or greater than 0° and equal to or less than 4°.

[0487] [B14] The semiconductor device according to B12 or B13, wherein the off angle is greater than 0° and less than 4°.

[0488] [B15] The semiconductor device according to any one of B1 to B14, wherein the electrode contains at least one of Ti, Ni, Au, and Ag.

[0489] [B16] The semiconductor device according to any one of B1 to B15, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0490] [B17] The semiconductor device according to any one of B1 to B15, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0491] [B18] The semiconductor device according to any one of B1 to B17, further including a groove formed in the second main surface of the SiC semiconductor layer.

[0492] [B19] The semiconductor device according to B18, wherein the groove includes a portion that intersects with the group of raised portions.

[0493] [B20] The semiconductor device described in B18 or B19, wherein the group of raised portions includes a portion in which some of the plurality of raised portions are formed at intervals along the groove in a plan view seen from the normal direction of the second main surface.

[0494] [B21] The semiconductor device according to any one of B1 to B20, wherein the semiconductor element includes a Schottky barrier diode.

[0495] [B22] The semiconductor device according to any one of B1 to B20, wherein the semiconductor element includes a field effect transistor.

[0496] [C1] A semiconductor device comprising: a semiconductor layer having a main surface in which a gate trench is formed; a gate insulating layer formed along an inner wall of the gate trench; a gate electrode layer including p-type polysilicon doped with p-type impurities and embedded in the gate trench with the gate insulating layer sandwiched therebetween; and a low-resistance electrode layer including a conductive material having a sheet resistance lower than the sheet resistance of the gate electrode layer and covering the gate electrode layer.

[0497] According to this semiconductor device, a trench gate electrode structure is formed in which a gate electrode layer is buried in a gate trench with a gate insulating layer sandwiched therebetween. In this trench gate electrode structure, the gate electrode layer is covered with a low-resistance electrode layer.

[0498] The gate electrode layer contains p-type polysilicon, which allows for an increase in gate threshold voltage. The low-resistance electrode layer contains a conductive material with a sheet resistance lower than that of p-type polysilicon, which allows for a reduction in gate resistance.

[0499] [C2] The semiconductor device according to C1, wherein the low resistance electrode layer includes a polycide layer in which the p-type polysilicon is silicided with a metal material.

[0500] [C3] The semiconductor device according to C2, wherein the polycide layer contains at least one of TiSi, TiSi2, NiSi, CoSi, CoSi2, MoSi2, and WSi2.

[0501] [C4] The semiconductor device according to any one of C1 to C3, wherein the low resistance electrode layer is formed in a film shape.

[0502] [C5] The semiconductor device according to any one of C1 to C4, wherein the low resistance electrode layer has a thickness equal to or less than the thickness of the gate electrode layer.

[0503] [C6] The semiconductor device according to any one of C1 to C5, wherein the gate insulating layer includes a first region formed along a side wall of the gate trench and a second region formed along a bottom wall of the gate trench, and the thickness of the second region of the gate insulating layer is equal to or greater than the thickness of the first region of the gate insulating layer.

[0504] [C7] The semiconductor device described in C6, wherein the gate insulating layer has a third region covering a main surface of the semiconductor layer, and the thickness of the third region of the gate insulating layer is equal to or greater than the thickness of the first region of the gate insulating layer.

[0505] [C8] The semiconductor device according to any one of C1 to C7, wherein the gate trench has a curved portion that curves inward of the gate trench at an opening edge portion that connects the main surface of the semiconductor layer and the sidewall of the gate trench.

[0506] [C9] The semiconductor device according to any one of C1 to C7, wherein the gate trench has an inclined portion that slopes downward from the main surface of the semiconductor layer toward the side wall of the gate trench at an opening edge portion that connects the main surface of the semiconductor layer and the side wall of the gate trench.

[0507] [C10] The semiconductor device according to any one of C1 to C9, wherein the gate insulating layer includes a bulging portion that bulges into the gate trench at an opening edge portion of the gate trench, and the low resistance electrode layer is in contact with the bulging portion of the gate insulating layer.

[0508] [C11] The semiconductor device according to C10, wherein the bulging portion of the gate insulating layer protrudes in a curved shape toward the inside of the gate trench.

[0509] [C12] The semiconductor device according to any one of C1 to C11, further including a source region, a body region, and a drain region formed in this order from the main surface of the semiconductor layer in a thickness direction along a side wall of the gate trench, and the low resistance electrode layer faces the source region with the gate insulating layer sandwiched therebetween.

[0510] [C13] The semiconductor device according to any one of C1 to C12, further including an emitter region, a body region, and a collector region formed in this order from the main surface of the semiconductor layer toward the thickness direction along the sidewall of the gate trench, and the low resistance electrode layer faces the emitter region with the gate insulating layer sandwiched therebetween.

[0511] [C14] The semiconductor device according to any one of C1 to C13, wherein the semiconductor layer contains SiC.

[0512] [C15] A method for manufacturing a semiconductor device, comprising: forming a gate trench in a main surface of a semiconductor layer; forming a gate insulating layer along an inner wall of the gate trench; forming a gate electrode layer by embedding p-type polysilicon doped with p-type impurities into the gate trench with the gate insulating layer sandwiched therebetween; and forming a low-resistance electrode layer by covering the gate electrode layer with a conductive material having a sheet resistance lower than that of the gate electrode layer.

[0513] [C16] The method for manufacturing a semiconductor device according to C15, wherein the step of forming the low resistance electrode layer includes a step of forming a polycide layer covering the gate electrode layer by silicidating a surface portion of the gate electrode layer with a metal material.

[0514] [C17] The method for manufacturing a semiconductor device according to C16, wherein the metal material includes at least one of Ti, Ni, Co, Mo, and W.

[0515] [C18] The method for manufacturing a semiconductor device according to any one of C15 to C17, wherein the step of forming the low resistance electrode layer includes a step of forming the low resistance electrode layer having a thickness equal to or less than that of the gate electrode layer.

[0516] [D1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from one another on the second main surface, some of the raised portions having first portions that overlap each other when viewed in a first direction that is one of the surface directions of the second main surface; a groove formed in the second main surface of the SiC semiconductor layer; and an electrode formed on the second main surface and connected to the group of raised portions.

[0517] [D2] The semiconductor device according to D1, wherein the groove includes a portion that intersects with the group of raised portions.

[0518] [D3] The semiconductor device described in D1 or D2, wherein the group of raised portions includes a portion in which some of the plurality of raised portions are formed at intervals along the groove when viewed in a plan view from the normal direction of the second main surface.

[0519] [D4] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from one another on the second main surface, some of the raised portions having first portions that overlap each other when viewed in a first direction that is one of the surface directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions, wherein the group of raised portions is formed at intervals along a second direction that is one of the surface directions of the first main surface and intersects the first direction.

[0520] [D5] The semiconductor device according to D4, wherein the distance between adjacent groups of the raised portions is 100 μm or less.

[0521] [D6] The semiconductor device according to D5, wherein the distance is 50 μm or less.

[0522] [D7] The semiconductor device according to D5 or D6, wherein the distance is 20 μm or less.

[0523] [D8] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from one another on the second main surface, some of the raised portions having first portions that overlap each other when viewed in a first direction that is one of the surface directions of the second main surface; and an electrode formed on the second main surface and connected to the group of raised portions, wherein the group of raised portions is formed on the second main surface in a range of 10 μm or more and 200 μm or less in a direction perpendicular to the first direction.

[0524] [D9] The semiconductor device according to D8, wherein the range is 50 μm or more and 150 μm or less.

[0525] [D10] The semiconductor device according to D8 or D9, wherein the range is 80 μm or more and 120 μm or less.

[0526] [D11] A semiconductor device described in any one of D1 to D10, wherein the group of raised portions has second portions in which some of the plurality of raised portions are formed at a distance from the first portion when viewed in the first direction and overlap each other when viewed in the first direction.

[0527] [D12] The semiconductor device according to any one of D1 to D11, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [11-20] direction of the 4H—SiC.

[0528] [D13] The semiconductor device according to any one of D1 to D11, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [1-100] direction of the 4H—SiC.

[0529] [D14] The semiconductor device according to D12 or D13, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10° or less with respect to the [11-20] direction from the (0001) plane of the 4H—SiC.

[0530] [D15] The semiconductor device according to D14, wherein the off angle is equal to or greater than 0° and equal to or less than 4°.

[0531] [D16] The semiconductor device according to D14 or D15, wherein the off angle is greater than 0° and less than 4°.

[0532] [D17] The semiconductor device according to any one of D1 to D16, wherein the electrode contains at least one of Ti, Ni, Au, and Ag.

[0533] [D18] The semiconductor device according to any one of D1 to D17, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0534] [D19] The semiconductor device according to any one of D1 to D17, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0535] [D20] The semiconductor device according to any one of D1 to D19, wherein the semiconductor element includes a Schottky barrier diode.

[0536] [D21] The semiconductor device according to any one of D1 to D19, wherein the semiconductor element includes a field effect transistor.

[0537] [E1] A semiconductor device comprising: a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed at intervals from one another in a first direction and a second direction intersecting the first direction on the second main surface; an electrode directly connected to the group of raised portions on the second main surface; and a SiC layer formed in a surface layer portion of the second main surface, the SiC layer having a higher silicon density than the SiC semiconductor layer, wherein the group of raised portions is formed in the SiC layer.

[0538] [E2] The semiconductor device according to E1, wherein the electrodes are connected to the group of raised portions without a silicide layer therebetween.

[0539] [E3] The semiconductor device according to E1 or E2, wherein a space in which the protrusions are not formed is defined adjacent to the group of protrusions on the second main surface, and the SiC layer includes a portion along the group of protrusions and a portion along the space.

[0540] [E4] The semiconductor device according to any one of E1 to E3, wherein the electrode contains at least one of Ti, Ni, Au, and Ag.

[0541] [E5] The semiconductor device according to any one of E1 to E4, wherein the electrode includes a Ti layer in contact with the group of raised portions.

[0542] [E6] The semiconductor device according to any one of E1 to E4, wherein the electrode includes a Ni layer in contact with the group of raised portions.

[0543] [E7] The semiconductor device according to any one of E1 to E6, wherein the raised portion group has a layout in which a plurality of the raised portions overlap in the first direction when viewed from the first direction.

[0544] [E8] The semiconductor device according to any one of E1 to E7, wherein the raised portion group has a layout in which a plurality of the raised portions are formed continuously in the first direction.

[0545] [E9] The semiconductor device according to any one of E1 to E8, wherein the plurality of raised portion groups are formed at intervals in the second direction.

[0546] [E10] The semiconductor device according to E9, wherein the distance between adjacent groups of the raised portions is 100 μm or less.

[0547] [E11] The semiconductor device according to any one of E1 to E10, wherein the group of raised portions is formed in a range of 10 μm to 200 μm in the second direction.

[0548] [E12] The semiconductor device according to any one of E1 to E11, further including a groove formed in the second main surface.

[0549] [E13] The semiconductor device according to E12, wherein the grooves intersect with the group of raised portions.

[0550] [E14] The semiconductor device according to E12 or E13, wherein the group of raised portions includes a plurality of the raised portions formed along the grooves.

[0551] [E15] The semiconductor device according to any one of E1 to E14, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [11-20] direction.

[0552] [E16] The semiconductor device according to any one of E1 to E14, wherein the SiC semiconductor layer contains 4H—SiC, and the first direction is a [1-100] direction.

[0553] [E17] The semiconductor device according to E15 or E16, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10° or less toward the [11-20] direction with respect to the (0001) plane.

[0554] [E18] The semiconductor device according to E17, wherein the off angle is equal to or greater than 0° and equal to or less than 4°.

[0555] [E19] The semiconductor device according to any one of E1 to E18, wherein the semiconductor element includes a Schottky barrier diode.

[0556] [E20] The semiconductor device according to any one of E1 to E18, wherein the semiconductor element includes a field effect transistor.

[0557] [A1] to [A25], [B1] to [B22], [C1] to [C18], [D1] to [D21] and [E1] to [E20] can be combined in any manner.

[0558] This specification does not limit any combination of the features shown in the first to eleventh embodiments. The first to eleventh embodiments can be combined in any manner and in any form. In other words, the features shown in the first to eleventh embodiments can be combined in any manner and in any form.

[0559] This application corresponds to Japanese Patent Application No. 2018-068567 filed with the Japan Patent Office on March 30, 2018, and Japanese Patent Application No. 2018-068568 filed with the Japan Patent Office on March 30, 2018, the entire disclosures of which are incorporated herein by reference.

[0560] Although the embodiments of the present invention have been described in detail, these are merely examples used to clarify the technical content of the present invention, and the present invention should not be construed as being limited to these examples, and the scope of the present invention is limited only by the appended claims. [Explanation of symbols]

[0561] 1. Semiconductor device 2 SiC semiconductor layer 3 First main surface 4 Second main surface 10 electrodes 11 Ridges 11A 1st ridge group 11B 2nd ridge group 15 Ridge 16 groove 21 SiC semiconductor substrate 31 Ti layer 32 Ni layers 62 carbon layer 63 NiSi layer 71 Semiconductor Devices 81 Semiconductor devices 91 Semiconductor devices 101 Semiconductor device 102 SiC semiconductor layer 103 First main surface 104 Second main surface 114 Ridges 116 Groove 121 SiC semiconductor substrate 124 Ti layer 125 Ni layer 171 Semiconductor devices 181 Semiconductor devices 191 Semiconductor devices 201 Semiconductor devices 202 SiC semiconductor substrate D Schottky barrier diode X 1st direction Y Second direction

Claims

1. a SiC semiconductor layer having a first main surface on one side and a second main surface on the other side, the SiC semiconductor layer having an active region and a peripheral region; a semiconductor element formed on the first main surface; a group of raised portions including a plurality of raised portions formed on the second main surface at intervals in a first direction and a second direction intersecting the first direction; an electrode directly connected to the group of ridges on the second main surface, The electrode has an uneven surface shape, the peripheral region is formed to surround the active region, A plurality of the raised portion groups are provided, The plurality of raised portion groups are formed in a stripe pattern.

2. The semiconductor device according to claim 1 , further comprising an impurity region formed in a quadrangular ring shape on said first main surface.

3. 3. The semiconductor device according to claim 1, wherein the semiconductor element includes a field effect transistor.

4. A semiconductor device as described in Claim 2, wherein the impurity region is exposed from a side surface of the SiC semiconductor layer.

5. further comprising a gate pad covering a portion of the first main surface; 5. The semiconductor device according to claim 1, wherein the gate pad is provided at the center of one side of the SiC semiconductor layer.

6. 6. The semiconductor device according to claim 1, wherein the electrode includes a Ti layer.

7. 6. The semiconductor device according to claim 1, wherein the electrode includes a Ni layer.

8. the electrode includes a Ti layer and a Ni layer; 6. The semiconductor device according to claim 1, wherein the Ni layer covers the Ti layer.

9. 9. The semiconductor device according to claim 6, wherein the thickness of said Ti layer is 0.01 [mu]m or more and 5 [mu]m or less.

10. 9. The semiconductor device according to claim 7, wherein the Ni layer has a thickness of 40 [mu]m or less.

11. 11. The semiconductor device according to claim 1, wherein the electrodes are connected to the group of raised portions without an NiSi layer therebetween.

12. The semiconductor device according to any one of claims 1 to 11, wherein the group of raised portions forms a group of raised portions area extending in a band shape along the first direction by a collective pattern of a plurality of the raised portions continuously scattered along the first direction.

13. 13. The semiconductor device according to claim 1, wherein the group of raised portions has a layout in which a plurality of the raised portions are formed continuously in the first direction.

14. 14. The semiconductor device according to claim 1, wherein a plurality of said raised portion groups are formed at intervals in said second direction.

15. 15. The semiconductor device according to claim 14, wherein the distance between adjacent groups of said raised portions is 100 [mu]m or less.

16. 16. The semiconductor device according to claim 1, wherein the group of raised portions is formed in a range of 10 μm to 200 μm in the second direction.

17. the SiC semiconductor layer contains 4H—SiC, 17. The semiconductor device according to claim 1, wherein the first direction is a [11-20] direction.

18. the SiC semiconductor layer contains 4H—SiC, 17. The semiconductor device according to claim 1, wherein the first direction is a [1-100] direction.

19. 19. The semiconductor device according to claim 17, wherein the SiC semiconductor layer has an off-angle tilted at an angle of 10 degrees or less toward the [11-20] direction with respect to the (0001) plane.

20. 20. The semiconductor device according to claim 19, wherein the off angle is equal to or greater than 0° and equal to or less than 4°.

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