Transformer and semiconductor devices

Abstract

To provide a transformer device that can increase the creepage distance without increasing the chip size, and a semiconductor device.SOLUTION: A transformer device includes a first coil, a conductor provided outside the first coil in a plan view and having the same reference potential as the first coil, a first insulating layer provided in an upper part of the first coil, a second coil provided on an upper surface of the first insulating layer, a second insulating layer provided between the second coil and the conductor so as to generate a space between the first insulating layer and the second insulating layer, and a third insulating layer covering the first insulating layer, the second insulating layer, the second coil, and the conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a transformer device and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a technique for forming a coreless transformer on a semiconductor substrate as a means for transmitting signals between two circuits that operate at different reference potentials. This coreless transformer is formed by a coil electrically connected to each of the two circuits. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-270490 Summary of the Invention [Problem to be solved by the invention]

[0004] However, with the above method, the two coils have different reference potentials, so there is a concern that when a potential difference occurs, the coils may discharge to unintended locations. To prevent this discharge, it is necessary to ensure a creepage distance. However, ensuring the creepage distance requires an increase in chip size, which raises the issue of increased costs.

[0005] In order to solve the above-mentioned problems, a first object of the present disclosure is to provide a transformer device that can increase the creepage distance without increasing the chip size.

[0006] A second object of the present disclosure is to provide a semiconductor device that can increase the creepage distance without increasing the chip size. [Means for solving the problem]

[0007] An aspect of the present disclosure is preferably a transformer device comprising: a first coil; a conductor that is located outside the first coil in a planar view and has the same reference potential as the first coil; a first insulating layer that is located on top of the first coil; a second coil that is located on the top surface of the first insulating layer; the second insulating layer that is located between the second coil and the conductor so as to create a gap between the second coil and the first insulating layer; and a third insulating layer that covers the first insulating layer, the second insulating layer, the second coil, and the conductor. [Effects of the Invention]

[0008] According to aspects of the present disclosure, the creepage distance can be increased without increasing the chip size. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a configuration of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] 2 is a cross-sectional view illustrating a creepage distance of the transformer device according to the first embodiment of the present disclosure. FIG. [Figure 3] 1 is a plan view illustrating a creepage distance of a transformer device according to a first embodiment of the present disclosure. [Figure 4] FIG. 10 is a cross-sectional view showing a transformer device according to a second embodiment of the present disclosure. [Figure 5] FIG. 10 is a cross-sectional view showing a transformer device according to a third embodiment of the present disclosure. [Figure 6] FIG. 10 is a cross-sectional view showing a transformer device according to a fourth embodiment of the present disclosure. [Figure 7] FIG. 10 is a cross-sectional view showing a transformer device according to a fifth embodiment of the present disclosure. [Figure 8] FIG. 10 is a cross-sectional view showing a transformer device according to a sixth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] Embodiment 1 1 is a cross-sectional view showing the configuration of a semiconductor device according to a first embodiment of the present disclosure. Semiconductor device 200 includes a transformer device 100. Transformer device 100 has a substrate 1. Substrate 1 may be a semiconductor substrate made of a material such as silicon or a silicon compound, or may be a substrate made of an insulator such as glass, a wide bandgap semiconductor such as SiC, GaN, or diamond, or an SOI (Silicon On Insulator).

[0011] An insulating layer 2 is formed on the upper surface of the substrate 1. If the substrate 1 is a semiconductor substrate, the insulating layer 2 may be formed as a thermal oxide film, or may be formed by coating TEOS or SiO2, or the like.

[0012] A wiring layer 3 is formed on the upper surface of the insulating layer 2. The wiring layer 3 is part of a path connecting a wiring layer 9 (described later) and a circuit region 15 (described later). The wiring layer 3 is generally formed by sputtering or the like using Al or a compound containing Al as a material, and patterned by wet etching or dry etching. However, the wiring layer 3 may be formed by plating, vapor deposition, or other methods instead of sputtering. The wiring layer 3 may also be formed from a metal such as Cu, or from other conductors.

[0013] An insulating layer 4 is formed on the upper surface of the wiring layer 3. The insulating layer 4 is generally formed by coating TEOS or SiO2, but other insulating materials may also be used.

[0014] A wiring layer 5 is formed on the upper surface of the insulating layer 4. The wiring layer 5 is a spiral first coil with pads 11 and 12 at its ends. The pad 11 is connected to the wiring layer 5 through the wiring layer 3 and via 6. The wiring layer 5 is magnetically coupled to a wiring layer 9, which will be described later, to form a coreless transformer.

[0015] The wiring layer 5 is generally formed by sputtering or the like using Al or a compound containing Al as a material, and then patterned by wet etching or dry etching. However, it may also be formed by plating, vapor deposition, or other methods instead of sputtering. It may also be formed of a metal such as Cu, or other conductors.

[0016] An insulating layer 7 is formed on the upper surfaces of the insulating layer 4 and the wiring layer 5. The insulating layer 4 is generally formed from SiN or polyimide, but other insulating materials may also be used.

[0017] An insulating layer 8 is formed on the upper surface of the insulating layer 7. The insulating layer 8 may be an organic insulating layer such as polyimide, or an insulating layer such as an oxide film.

[0018] A wiring layer 9 is formed on the upper surface of the insulating layer 8. The wiring layer 9 is a second spiral coil having pads 13 and 14 as its ends. The wiring layer 9 is magnetically coupled to the wiring layer 5 to form a coreless transformer.

[0019] Furthermore, the wiring layer 9 is generally formed by sputtering or the like using Al or a compound containing Al as a material, and then patterned by wet etching or dry etching. However, it may also be formed by plating, vapor deposition, or other methods instead of sputtering. It may also be formed of a metal such as Cu, or other conductors.

[0020] An insulating layer 10 is formed on the upper surfaces of the insulating layer 8 and the wiring layer 9. Note that the insulating layer 10 may be formed on the upper surface of the insulating layer 7 excluding the pads 11, 12, and 14, or on the upper surface of the region 25.

[0021] The transformer device 100 includes an insulating layer 26. The insulating layer 26 may be an organic insulating layer such as polyimide, or may be an insulating layer such as an oxide film. The thickness of the insulating layer 26 is preferably equal to or greater than the thickness of the insulating layer 8. The insulating layer 26 may be formed so as to be separated from the insulating layer 8 by a region 25, which will be described later.

[0022] Region 25 exists between insulating layer 26 and insulating layer 8. Region 25 is located outside wiring layer 9 within insulating layer 8 and penetrates to insulating layer 7. For example, region 25 is formed so as to surround wiring layer 9, pad 13, and pad 14, thereby separating insulating layer 26 from insulating layer 8. Region 25 may be formed by exposing or developing polyimide, or by etching.

[0023] It is also possible to arrange a plurality of regions 25. Furthermore, the region 25 may be formed only in the transformer device 100, and in a part of the semiconductor device region 180 and the semiconductor device region 190 described later.

[0024] Region 25, like the top surfaces of insulating layers 7, 10, and 26, is covered with insulating layer 27. Insulating layer 27 may be formed by resin sealing or gel sealing, or may be an insulating layer such as a polyimide or oxide film formed by a semiconductor process.

[0025] The semiconductor device 200 includes a semiconductor device region 180. Although the semiconductor device region 180 is shown as a separate chip here, it may be formed within the same chip. In this case, each connection may be made by a wiring layer instead of by wire bonding.

[0026] The semiconductor device region 180 has a circuit region 15. The circuit region 15 is a circuit region that operates the wiring layer 5. The circuit region 15 is connected to a wire bond 18 via a pad 16. The wire bond 18 is connected to a pad 12. The circuit region 15 is also connected to a wire bond 19 via a pad 17. The wire bond 19 is connected to a pad 11.

[0027] The semiconductor device 200 also includes a semiconductor device region 190. Although the semiconductor device region 190 is shown as a separate chip here, it may be formed within the same chip. In this case, each connection may be made by a wiring layer instead of by wire bonding.

[0028] The semiconductor device region 190 has a circuit region 20. The circuit region 20 is a circuit region that operates the wiring layer 9. The circuit region 20 is connected to a wire bond 23 via a pad 21. The wire bond 23 is connected to a pad 13. The circuit region 20 is also connected to a wire bond 24 via a pad 22. The wire bond 24 is connected to a pad 14.

[0029] FIG. 2 is a cross-sectional view showing the creepage distance of the transformer device according to the first embodiment of the present disclosure. The black arrow in FIG. 2 indicates the creepage distance from wiring layer 9 to wiring layer 5. The creepage distance is the shortest distance when electricity flows between conductors along the surface of an insulator. If an insulator exists between conductors, a short circuit does not occur within the insulator. Therefore, a short circuit that occurs between conductors is caused by electricity flowing between the conductors along the surface of the insulating layer. In other words, by ensuring a sufficient creepage distance, short circuits between conductors can be prevented.

[0030] The creepage distance from wiring layer 9 to wiring layer 5 referred to here is the distance when tracing a path along the surface of the insulating layer from pad 13, which is the end of wiring layer 9, to pad 28. Pad 28 is any pad connected to wiring layer 5.

[0031] The discharge path is assumed to be a conductor having the same reference potential as the coil, such as the pads and wiring formed in the wiring layer 3 or the wiring layer 5, the wires connected to the pads, or the substrate on which the transformer device of the present disclosure is mounted.

[0032] Here, the reference potential of circuit region 15 is defined as a first reference potential, and the reference potential of circuit region 20 is defined as a second reference potential. Circuit region 15 is a circuit region that operates wiring layer 5. Therefore, the reference potential of wiring layer 5 is the first reference potential. Similarly, circuit region 20 is a circuit region that operates wiring layer 9. Therefore, the reference potential of wiring layer 9 is the second reference potential.

[0033] Conventional transformer devices do not have region 25. Therefore, when the second reference potential is higher than the first reference potential, it is necessary to ensure a creepage distance from wiring layer 9 to wiring layer 5 in order to insulate wiring layer 9 from pad 28. This, for example, requires an increase in chip size, which poses a problem of increased costs.

[0034] However, by forming the region 25 in the transformer device 100, the creepage distance from the wiring layer 9 to the wiring layer 5 can be increased. That is, even if the second reference potential is higher than the first reference potential, there is no need to increase the region for insulating the wiring layer 9 from the pad 28. This makes it possible to increase the creepage distance without suppressing an increase in the chip size.

[0035] 2 shows an example in which the thickness of insulating layer 26 is equal to the thickness of insulating layer 8. On the other hand, if the thickness of insulating layer 26 is greater than the thickness of insulating layer 8, that is, if the upper surface of insulating layer 26 is located higher than the upper surface of insulating layer 8, the creepage distance described above will be further increased. Therefore, it is preferable that the thickness of insulating layer 26 is equal to or greater than the thickness of insulating layer 8.

[0036] 3 is a plan view showing the creepage distance of the transformer device according to the first embodiment of the present disclosure. Note that in FIG. 3, a part of the transformer device 100 is shown in plan view to make the creepage distance easier to understand. For this reason, only some components are shown, excluding the insulating layer 27 that covers the entire device.

[0037] As mentioned above, the creepage distance is the shortest distance that electricity flows between conductors along the surface of an insulator. Therefore, the creepage distance shown in Figure 2 is equal to the shortest path between the wiring layer 9 and the pad 28 when viewed in Figure 3.

[0038] The insulating capability of the transformer device 100 of this embodiment may be increased by sealing the top surface with resin or the like.

[0039] In the transformer device 100 of this embodiment, the coil is formed by the wiring layer 3, the wiring layer 5, and the wiring layer 9, but other wiring layers may be formed above or below these. In addition, the wiring layer 3 may be omitted by using a diffusion layer formed in the substrate by a semiconductor process.

[0040] Furthermore, the coil formed by the wiring layer 5 and the wiring layer 9 may be changed to a flat plate, thereby achieving the same effect as an element that transmits signals by capacitive coupling.

[0041] Embodiment 2 4 is a cross-sectional view showing a transformer device according to embodiment 2 of the present disclosure. Transformer device 110 of this embodiment differs from embodiment 1 in that insulating layer 7 has a thin region in the range facing region 25.

[0042] The transformer device 110 includes an insulating layer 7a. The insulating layer 7a differs from the insulating layer 7 in that the thickness of the insulating layer 7a is reduced in the area where the insulating layer 7 and the region 25 face each other.

[0043] When the transformer device 110 includes the insulating layer 7a, the distance from the pad 13, which is the end of the wiring layer 9, to the pad 28 is longer than when the insulating layer 7a is not present. That is, the insulating layer 7a increases the creepage distance from the wiring layer 9 to any location that operates at the first reference potential compared to the transformer device 100. As a result, there is an effect that the area for insulating the wiring layer 9 from the any location that operates at the first reference potential can be further reduced.

[0044] Embodiment 3 5 is a cross-sectional view showing a transformer device according to embodiment 3 of the present disclosure. Transformer device 120 of this embodiment differs from embodiment 1 in that insulating layer 29 is formed between insulating layer 7 and insulating layer 8.

[0045] The transformer device 120 includes an insulating layer 29. The insulating layer 29 is formed on the upper surface of the insulating layer 7 and on the lower surface of the insulating layer 8. For example, a thicker insulating layer is needed to ensure the required insulating ability between the wiring layer 5 and the wiring layer 9, but there may be a limit to the thickness of the insulating layer that can be formed in one process. In this case, by forming the insulating layer 29 in addition to the insulating layer 8, it is possible to ensure a sufficient thickness for the entire insulating layer.

[0046] When the transformer device 120 includes the insulating layer 29, the distance from the pad 13, which is the end of the wiring layer 9, to the pad 28 can be made longer than when the insulating layer 29 is not present. That is, the insulating layer 29 increases the creepage distance from the wiring layer 9 to any location that operates at the first reference potential compared to the transformer device 100. As a result, there is an effect that the area for insulating the wiring layer 9 from the any location that operates at the first reference potential can be further reduced.

[0047] Embodiment 4 6 is a cross-sectional view of a transformer device according to a fourth embodiment of the present disclosure. Transformer device 130 of this embodiment differs from that of the third embodiment in that insulating layer 29 has a thin region in the area facing region 25.

[0048] The transformer device 130 includes an insulating layer 29a. The insulating layer 29a differs from the insulating layer 29 in that the thickness of the insulating layer 29a is reduced in the area where the insulating layer 29 faces the region 25. The region with a reduced thickness may be formed by etching or by exposure to light.

[0049] When the transformer device 130 includes the insulating layer 29a, the distance from the pad 13, which is the end of the wiring layer 9, to the pad 28 is longer than when the insulating layer 29 is present. That is, the insulating layer 29a increases the creepage distance from the wiring layer 9 to any location that operates at the first reference potential compared to the transformer device 120. As a result, there is an effect that the area for insulating the wiring layer 9 from the any location that operates at the first reference potential can be further reduced.

[0050] Fifth embodiment 7 is a cross-sectional view of a transformer device according to embodiment 5 of the present disclosure. Transformer device 140 of this embodiment differs from embodiment 3 in that insulating layer 29 has a through region in the area facing region 25.

[0051] The transformer device 140 includes an insulating layer 29b. The insulating layer 29b differs from the insulating layer 29 in that the insulating layer 29b has a through region in the area where the insulating layer 29 faces the region 25. The through region may be formed by etching or by photoexposure.

[0052] When the transformer device 140 includes the insulating layer 29b, the distance from the pad 13, which is the end of the wiring layer 9, to the pad 28 is longer than when the insulating layer 29a is present. That is, the insulating layer 29b increases the creepage distance from the wiring layer 9 to any location that operates at the first reference potential compared to the transformer device 130. As a result, there is an effect that the area for insulating the wiring layer 9 from the any location that operates at the first reference potential can be further reduced.

[0053] Sixth embodiment 8 is a cross-sectional view of a transformer device according to a sixth embodiment of the present disclosure. Transformer device 150 of this embodiment differs from that of the fifth embodiment in that insulating layer 26 has a recess on the upper surface.

[0054] The transformer device 150 includes an insulating layer 26a. The insulating layer 26a differs from the insulating layer 26 in that the insulating layer 26a has a recess on its upper surface. The recess may be formed by etching or by photoexposure.

[0055] When the transformer device 150 includes the insulating layer 26a, the distance from the pad 13, which is the end of the wiring layer 9, to the pad 28 is longer than when the insulating layer 29a is present. That is, the insulating layer 29b increases the creepage distance from the wiring layer 9 to any location that operates at the first reference potential compared to the transformer device 140. As a result, there is an effect that the area for insulating the wiring layer 9 from the any location that operates at the first reference potential can be further reduced.

[0056] Note that the embodiments described in this disclosure are merely examples and can be modified, omitted, or combined as appropriate. Furthermore, the terms "upper" and "lower" in this disclosure refer to one direction of a transformer device or semiconductor device as the upper direction, and the opposite direction as the lower direction. In other words, the upper and lower directions of a transformer device or semiconductor device during manufacture or use are not limited.

[0057] Below, the aspects of the present disclosure will be summarized as appendices.

[0058] (Appendix 1) A first coil; a conductor that is provided outside the first coil in a plan view and has the same reference potential as the first coil; a first insulating layer provided on an upper portion of the first coil; a second coil provided on the top surface of the first insulating layer; a second insulating layer provided between the second coil and the conductor such that a gap is formed between the second insulating layer and the first insulating layer; a third insulating layer covering the first insulating layer, the second insulating layer, the second coil, and the conductor; A transformer device comprising: (Appendix 2) The upper surface of the second insulating layer is located higher than the upper surface of the first insulating layer. 1. A transformer device as described in Appendix 1. (Appendix 3) a fourth insulating layer provided on an upper surface of the first coil; The fourth insulating layer has a thin region in a region facing the gap. Transformer device according to claim 1 or 2. Transformer device according to claim 1. (Appendix 4) a fifth insulating layer between the first coil and the first insulating layer; 4. A transformer device according to any one of claims 1 to 3. (Appendix 5) The fifth insulating layer has a thin region in a region facing the gap. Transformer apparatus as described in Appendix 4. (Appendix 6) The fifth insulating layer has a through region in a region facing the gap. Transformer apparatus as described in Appendix 4. (Appendix 7) The second insulating layer has a recess on its upper surface. 7. A transformer device according to any one of claims 1 to 6. (Appendix 8) The first insulating layer and the second insulating layer are organic insulating layers. 8. A transformer device according to any one of claims 1 to 7. (Appendix 9) The first coil and the second coil are formed of flat plates. 9. A transformer device according to any one of claims 1 to 8. (Appendix 10) Made of wide bandgap semiconductors 10. A transformer device according to any one of claims 1 to 9. (Appendix 11) 11. The transformer device of claim 10, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. (Appendix 12) A transformer device according to any one of appendices 1 to 11; a first semiconductor circuit electrically connected to the first coil; a second semiconductor circuit electrically connected to the second coil; A semiconductor device comprising: (Appendix 13) The transformer device, the first semiconductor circuit, and the second semiconductor circuit are formed on the same chip. 13. The semiconductor device according to claim 12. [Explanation of symbols]

[0059] 2. Insulation layer 4. Insulation layer 7. Insulation layer 7a Insulating layer 8. Insulating layer 10 Insulating layer 25 areas 26 Insulating layer 26a Insulating layer 27 Insulating layer 29a Insulating layer 29b Insulating layer 100 Transformer equipment 110 Transformer equipment 120 Transformer equipment 130 Transformer equipment 140 Transformer equipment 150 Transformer equipment 200 Semiconductor device

Claims

1. A first coil; a conductor that is provided outside the first coil in a plan view and has the same reference potential as the first coil; a first insulating layer provided on an upper portion of the first coil; a second coil provided on the top surface of the first insulating layer; a second insulating layer provided between the second coil and the conductor such that a gap is formed between the second insulating layer and the first insulating layer; a third insulating layer covering the first insulating layer, the second insulating layer, the second coil, and the conductor; A transformer device comprising:

2. The upper surface of the second insulating layer is located higher than the upper surface of the first insulating layer. The transformer device according to claim 1 .

3. a fourth insulating layer provided on an upper surface of the first coil; The fourth insulating layer has a thin region in a region facing the gap. The transformer device according to claim 1 .

4. a fifth insulating layer between the first coil and the first insulating layer; The transformer device according to claim 1 .

5. The fifth insulating layer has a thin region in a region facing the gap. The transformer device according to claim 4 .

6. The fifth insulating layer has a through region in a region facing the gap. The transformer device according to claim 4 .

7. The second insulating layer has a recess on its upper surface. The transformer device according to claim 1 .

8. The first insulating layer and the second insulating layer are organic insulating layers. The transformer device according to claim 1 .

9. The first coil and the second coil are formed of flat plates. The transformer device according to claim 1 .

10. Made of wide bandgap semiconductors The transformer device according to claim 1 .

11. The transformer device according to claim 10, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride based material, or diamond.

12. A transformer device according to any one of claims 1 to 11; a first semiconductor circuit electrically connected to the first coil; a second semiconductor circuit electrically connected to the second coil; A semiconductor device comprising:

13. The transformer device, the first semiconductor circuit, and the second semiconductor circuit are formed on the same chip. The semiconductor device according to claim 12.

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