Tag checking device and method

Abstract

The apparatus includes a tag check circuit responsive to the target address, the tag check circuit identifying a guard tag stored in the memory system associated with a block of one or more memory locations that includes the target memory location identified by the target address, performing a tag check based on the guard tag and an address tag associated with the target address, and performing an error response action in response to detecting a mismatch in the tag check. The apparatus also includes a tag mapping storage circuit that stores mapping information indicating a mapping between guard tag values ​​and corresponding address tag values. The tag check circuit remaps at least one of the guard tags and the address tags based on the mapping information stored by the tag mapping storage circuit to generate a remapped tag for use in the tag check.

Description

[Technical Field]

[0001] The present technique relates to the field of data processing, and more particularly to performing tag checking.

[0002] Software executed by a data processing device is typically written in a high-level programming language and then compiled into code according to an instruction set architecture supported by the device on which the software is executed. For example, the software may originally be written in a higher-level language such as Java, C, or C++ and then compiled into a natively supported instruction set architecture (ISA) such as x86 or Arm®. Some higher-level programming languages, such as Java, are considered memory-safe because they include run-time error detection checks to check for certain errors related to memory accesses. In contrast, memory-unsafe languages, such as C and C++, do not include such run-time error checks. The persistent prevalence of memory-unsafe languages ​​means that there may be numerous memory-related errors in code compiled according to a given instruction set architecture that may be vulnerable to exploitation by attackers or other malicious actors. Such errors may include: A bounds violation, where an array index supplied by the code is outside the legal bounds of the array. Use-of-free errors, where a memory location is accessed after it has already been deallocated or freed. Use-after-return, where a memory access to an address associated with a variable used within a function (such as a value on the stack) occurs after the function has already returned. Out-of-scope use errors, where a variable is accessed outside the scope in which it is declared, · A use-before-initialization error, where the memory address associated with a variable is accessed before the variable is initialized.

[0003] These are just a few examples of memory-related errors that can cause unpredictable behavior and potentially provide avenues for attackers to exploit.

[0004] At least some examples provide an apparatus comprising: a tag check circuit responsive to a target address, the tag check circuit identifying a guard tag stored in the memory system associated with a block of one or more memory locations, the block including a target memory location identified by the target address, performing a tag check based on the guard tag and an address tag associated with the target address, and performing an error response action in response to detecting a mismatch in the tag check; and a tag mapping storage circuit storing mapping information indicating a mapping between guard tag values ​​and corresponding address tag values, the tag check circuit configured to remap at least one of the guard tags and the address tags based on the mapping information stored by the tag mapping storage circuit to generate a remapped tag for use in the tag check.

[0005] At least some examples provide a method including: in response to a target address, identifying a guard tag stored in a memory system associated with a block of one or more memory locations, the block including the target memory location identified by the target address; performing a tag check based on the guard tag and an address tag associated with the target address; and performing an error response action in response to detecting a mismatch in the tag check, the method including remapping at least one of the guard tag and the address tag based on mapping information indicating a mapping between the guard tag values ​​and corresponding address tag values ​​to generate a remapped tag for use in the tag check.

[0006] At least some examples provide a computer program for controlling a host data processing apparatus to provide an instruction execution environment, the computer program comprising: tag checking program logic responsive to a target address, the tag checking program logic identifying a guard tag stored in the memory system associated with a block of one or more memory locations, the block including a target memory location identified by the target address, performing a tag check based on the guard tag and an address tag associated with the target address, and performing an error response action in response to detecting a mismatch in the tag check; and tag mapping maintaining program logic maintaining mapping information indicating a mapping between the guard tag values ​​and corresponding address tag values, the tag checking program logic configured to remap at least one of the guard tags and the address tags based on the mapping information maintained by the tag mapping maintaining program logic to generate a remapped tag for use in the tag check.

[0007] The storage medium may store the computer program described above. The storage medium may be a non-transitory storage medium.

[0008] Further aspects, features, and advantages of the present technique will become apparent from the following description of examples, read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 illustrates a schematic diagram of an example of a data processing device. [Figure 2] 10 illustrates an exemplary tag check involving a comparison based on a guard tag and an address tag. [Figure 3] FIG. 10 is a flow diagram illustrating a method for performing tag checking involving remapping address tags and / or guard tags. [Figure 4] 10 illustrates an exemplary tag check that remaps guard tags. [Figure 5] 10 shows a remapped guard tag and an exemplary tag check where the address tag is longer than the guard tag. [Figure 6] 10 illustrates a remapped guard tag and another exemplary tag check where the address tag is longer than the guard tag. [Figure 7] 10 illustrates an exemplary tag check for remapping address tags. [Figure 8] 10 illustrates an exemplary tag check involving a check based on permission information. [Figure 9] 10 illustrates another exemplary tag check involving a check based on permission information. [Figure 10] 10 illustrates an exemplary tag check involved in selecting a set of mapping information to use based on the type of access requested. [Figure 11] 10 illustrates an exemplary tag check involved in selecting a set of mapping information to use based on the thread being executed. [Figure 12] 1 illustrates schematically an apparatus for configuring tag mapping. [Figure 13] 10 illustrates an example of a tag mapping configuration where each guard tag value is associated with a different address tag value. [Figure 14] 10 shows an example of a tag mapping configuration in which certain address tag values ​​are excluded from selection. [Figure 15] 10 shows an example of a tag mapping update where certain guard tag values ​​are excluded from the update. [Figure 16] 10 shows an example of a tag mapping configuration where all guard tag values ​​are mapped to the same address tag value. [Figure 17] 1 shows an example of a simulator that supports tag checking and tag remapping.

[0010] Some specific examples are described below, and it will be understood that the invention is not limited to these precise examples.

[0011] One approach to protecting against certain memory usage errors of the type described above involves providing a guard tag stored in the memory system in association with one or more blocks of memory locations. A tag check can be performed based on a target address identifying a particular addressed location within the memory system (e.g., when a tag-protected memory access operation is requested), and a tag check circuit can perform a comparison based on an address tag associated with the target address and a guard tag stored in the memory system in association with the block of one or more memory locations that includes the addressed location identified by the target address. The tag check circuit can generate an indication of whether a match is detected between the guard tag and the address tag. This indication can be used to control whether the memory access is allowed to succeed, whether subsequent operations can succeed, or can simply be reported while allowing the memory access to continue normally. Thus, error response actions can be taken in response to a mismatch being detected in the tag check performed on the guard tag and the address tag.

[0012] This can be useful, for example, because a compiler compiling code based on a memory-unsafe language, such as C or C++, can set guard tags for blocks of memory that the code expects to access to specific values ​​when initializing regions of memory and associate corresponding address tag values ​​with target addresses that point to those blocks. If a memory usage error occurs—for example, if an address pointer is used out of scope or extends outside the bounds of its initialized scope—the guard tag associated with the addressed location may not match the address tag associated with the target address, in which case an indication of whether a match was found can be used to trigger some kind of error handling response or error reporting mechanism. The particular response taken may depend on the specific needs of the software being executed or the particular microarchitectural implementation of the architecture. Thus, even if a high-level language does not have a means to perform run-time error checks to protect against memory access errors, the ISA used for the compiled code may include architectural features for performing such checks.

[0013] However, it may be desirable to prevent particular threads of a process from reusing address tags used by other threads of the process to access data associated with those other threads. Although each process typically has its own set of associated page tables that specify permission information for that process, threads of a process share the process's page tables, and therefore the permission information stored in the page tables associated with a process is common to all threads of that process. Therefore, permissions implemented by a memory management unit (MMU) may not be suitable for enforcing protection between threads of the same process.

[0014] One example where it may be desirable to prevent threads of a process from accessing data associated with other threads of that process is in the context of browser tabs. To execute code, such as JavaScript code, on a web page, a browser may implement a virtual machine, which puts the code into a form executable by the virtual machine and then executes the code. Even if there are not enough resources to implement complete process isolation by running each browser tab in a separate process, it may be useful to keep browser tabs isolated to ensure that code associated with one browser tab cannot accidentally or maliciously access data associated with another browser tab.

[0015] The present technique provides support for remapping of at least one of the guard tag and address tag involved in the tag check, and for the tag check to be based on at least one remapped tag. In this way, different mappings between tags can be used for threads that are kept isolated from one another. Even if a thread attempts to reuse a target address and address tag combination used by a different thread, which causes a match between the address tag and the guard tag associated with the target address, the guard tag and / or address tag can be remapped differently so that the tag check will detect a mismatch when the tag is reused (even though the two threads are accessing the same physical address in memory). Thus, a thread attempting to access data belonging to another thread can be identified, and appropriate action may be taken (e.g., the two threads may correspond to browser tabs, as in the example above).

[0016] This approach allows sandboxing of portions of code without having to use a different process for each sandbox, and avoids the overhead of having to relocate guard tags in memory or maintaining a separate set of page tables for each sandbox. Also, because different guard tag values ​​can be assigned to different parts of a single page, resulting in different mappings between guard tags and address tags for different threads, such an approach allows for per-thread control of access rights to memory at a finer granularity than the page-level granularity typically used by page tables that point to, e.g., 4KB, 16KB, or 64KB regions.

[0017] In accordance with the techniques described herein, an apparatus may include a tag check circuit that operates in response to a target address. The target address may identify a target memory location, which may be a location within the memory system to which access is desired, or otherwise a location within the memory system at which a tag check is performed (e.g., the target address may identify a memory location that a future memory access is expected to likely access; it is not necessary for the tag check to be performed simultaneously with the memory access itself). The memory system may include a main memory as well as a cache structure. In one example, the memory system includes a main memory, a level 1 instruction cache, a level 1 data cache, and a shared level 2 cache. It will be appreciated that other cache hierarchies are possible.

[0018] As noted above, a guard tag may be stored in association with a block of one or more memory locations. Thus, a memory location may be part of a block that has a guard tag, and the guard tag is used to constrain access to that block depending on whether the appropriate address tag for accessing that block is provided.

[0019] In some embodiments, blocks of memory locations with corresponding guard tags may each comprise a single memory location, where each individual memory location may have a different guard tag, thereby providing fine-granularity in setting the guard tags so that a wider range of memory errors can be detected.

[0020] In practice, however, the overhead of setting an individual guard tag for each addressed location may be too high, and it may be more efficient to associate each guard tag with a block of memory locations, in which case several adjacent memory locations may share the same guard tag, which may be sufficient to detect common forms of memory-related errors.

[0021] The guard tag associated with a given block of memory locations may be stored in any other memory location within the memory system. The specific manner in which the location of the guard tag within the memory system is selected may vary significantly from implementation to implementation or at run time. In some examples, the location storing the guard tag may be architecturally accessible by the processing circuitry; for example, the guard tag storage location may be a location mapped to the same part of the address space as the addressed location. In this case, the mapping between the addressed location itself and the address of the corresponding tag storage location may be fixed or hardwired, or may be variable, tracked, for example, in a tracking table or translation lookaside buffer maintained by the memory access circuitry. Alternatively, other implementations may store the guard tag associated with a given addressed location in a further storage location that is not architecturally accessible to the processing circuitry, for example, in additional storage provided within the microarchitecture that is not mapped to the address space addressable by instructions executed by the processing circuitry. In this case, the memory access circuitry may determine, based on the address of the addressed location, the specific internal address used to reference the corresponding tag storage location and trigger any additional memory accesses necessary to read the tag data from the tag storage location. Whether or not the tag storage location is architecturally accessible to the processing circuitry, the tag value may also be cached in a cache for faster access, either in the same cache used for data values ​​or in a dedicated tag cache.

[0022] In some cases, the guard tag may be relatively small, for example 4 or 8 bits, so that multiple guard tags, each associated with a different block of memory locations, can fit within the same memory location.

[0023] Address tags can be associated with target addresses in different ways. In some cases, the address tag can be specified separately from the target address, for example, using a separate register specified by the memory access instruction that triggers the memory access operation and a guard tag check. However, in other instances, the address tag can be determined as a function of one or more selected bits of the target address. That is, the address tag can include information derived from a portion of the target address itself. In many cases, an instruction set architecture may support addresses having a certain number of bits (e.g., 64 bits), but a given hardware device may not actually require so much memory capacity as to use all possible addresses that can be represented using that number of bits. For example, current trends in device usage still require addresses with a 2 64 It is not necessary to provide individual addressable locations. Thus, often some bits of a memory address may effectively be unused, either always having the same value or set as a sign extension of the most significant "real" address bits (thus the unused portion is set to all 0s or all 1s). Therefore, whenever an address is manipulated or moved between registers, the address tag can naturally be transported along with the address, so this unused portion can be reused to represent the address tag or a value from which the address tag can be derived, avoiding the need to access a separate register to obtain the address tag, and making it easier to keep track of the correspondence between addresses and corresponding address tags.

[0024] In embodiments in which a portion of the target address is used to determine the address tag, it should be noted that this address tag is different from the tag portion of the target address that the cache may use to determine whether information from the addressed location identified by the target address is stored in the cache. Many cache schemes may store the tag portion of the address of cached data in parallel with the data, such that when the cache is searched for a given address, a portion of the address may be compared to the tag stored in parallel with the cached data to determine whether the cached data actually corresponds to the requested address. However, in this case, the tag portion of the address that is compared with the tag in the cache is the portion of the address that actually identifies the specific addressed location for which data is requested; i.e., changing the cache tag portion of the address will naturally result in the address pointing to a different addressed location in the memory system. In contrast, when an address tag is used for tag-protected memory operations, the memory access circuitry may select the addressed location for which data is requested independently of the address tag. That is, even if the address tag has a different value, the addressed location referenced by the target address may still be the same, since the selection of the addressed location may depend only on other portions of the target address. This gives the compiler the freedom to set the address tag associated with a particular address to any value (e.g., the randomly selected value described above) to match the corresponding guard tag value assigned to the associated block of data in the memory system.

[0025] According to the techniques described herein, the device may also include a tag mapping circuit that stores mapping information indicating a mapping between guard tag values ​​and corresponding address tag values. This mapping information thus enables the tag mapping storage circuit to indicate which address tag values ​​will cause a match when performing a tag check for a particular guard tag value. In a typical tag-protected memory system, the tag check simply checks whether a provided address tag is the same as the guard tag. However, storing the mapping information in this manner can make the relationship between the guard tag values ​​and their corresponding address tag values ​​more complex, for example, the mapping may vary based on the thread from which the request originates.

[0026] The mapping information may include multiple fields in which remapped tag values ​​are stored for the values ​​of the guard tag and / or associated address tag. Alternatively or additionally, the mapping information may include some other form of relationship between tag values, such as a mathematical function that allows for deriving the remapped tag value from the value of the remapped tag. For example, the mapping information may include a mapping key value that is hashed with the input tag value of the remapped guard tag / address tag, and the hash of the input tag value and the mapping key value provides the remapped tag value used for tag checking. In either case, the mapping storage circuitry enables improved memory security, since an address tag used by a given thread to access a particular memory location may not result in a match when comparing the same memory location for the same address tag used by a different thread whose mapping information has been modified. Thus, malicious or careless attempts by one thread to access data belonging to another thread can be identified and, if necessary, the access can be prevented.

[0027] In accordance with the techniques herein, the tag checking circuitry is configured to remap at least one of the guard tag and the address tag based on mapping information stored by the tag mapping storage circuitry to generate a remapped tag for use in tag checking.

[0028] In some examples, the tag checking circuitry is configured to remap address tags but not guard tags. Such an approach may be faster than remapping guard tags and may allow memory accesses to fetch guard tags to be performed in parallel with the address tags being remapped. However, in other examples, remapping may be applied to guard tags but not address tags. By remapping guard tags and comparing the remapped guard tags with address tags, greater flexibility may be achieved regarding the mappings that can be used. For example, address tags and remapped guard tags may be longer than guard tags. Increasing the length of the remapped guard tags and address tags may increase the number of available tag values, thereby enabling further isolation of threads, as described below. In some examples, both guard tags and address tags may be remapped.

[0029] Upon remapping at least one of the guard tag and the address tag, the tag check circuitry may be configured to perform a tag check based on the remapped tag. In examples where only the guard tag and the address tag are remapped, this tag check may include determining whether the remapped tag and the non-remapped guard tag or address tag have the same value. In examples where both the address tag and the guard tag are remapped, the tag check may determine whether the two remapped tags have the same value. While the above examples describe detecting a match when the tags have the same value, other conditions for matching tag values ​​may be used, such as detecting a match when the address tag falls within a range of allowed values ​​indicated by the remapped guard tag, or detecting a match when one tag has a value derived from the other tag, such as by applying an offset to the tag value.

[0030] If the tag checking circuitry detects a mismatch in the tag check, this may indicate that a thread is attempting to improperly access data associated with another thread, or may otherwise indicate a memory error of the type listed above. Accordingly, the tag checking circuitry can perform an error response action in response to detecting a mismatch. In some examples, it may be desirable to prevent accesses that fail the tag check, and therefore the error response action includes denying access to the memory location specified by the target address. However, in some examples, access to the memory location specified by the target address may be permitted, and the fact that a mismatch was detected may be logged. This may be useful to indicate to programmer code acting as part of a process to identify malicious or malfunctioning code in a system that is not functioning properly or otherwise does not need to restrict access. This may improve performance, as the access may be allowed to proceed while the tag check is being performed.

[0031] In this way, by storing mapping information and basing tag checks on the remapped tags, the technique can effectively sandbox portions of code and implement memory protection in an efficient manner.

[0032] As described above, either address tags or guard tags can be remapped to generate remapped tags for use in tag checking. In some examples, both address tags and guard tags can be remapped to generate remapped tags that are compared to each other in tag checking. This can make it more difficult for an attacker to reverse engineer the mapping between guard tags and address tags by comparing pairs of address tags and guard tags that cause a match in tag checking.

[0033] In some examples, when a guard tag is remapped, the address tag is longer than the guard tag, and the remapped guard tag is longer than the guard tag. For example, a 4-bit guard tag may be stored in a memory system. If a 4-bit address tag is used, this provides 16 possible address tag values. However, if an 8-bit address tag is used for the address tag, there are 256 possible address tag values. The 4-bit guard tag may then be mapped to an 8-bit remapped guard tag for comparison with the 8-bit address tag. This approach may improve sandboxing between threads of the same process because different sets of non-overlapping address tags may be defined for different threads. For example, for a first thread, a first set of 16 address tag values ​​may be mapped to 16 guard tag values, and for a second thread, a second set of 16 different address tag values ​​may be mapped to 16 guard tag values. Thus, when an address tag associated with a first thread is used by a second thread, the mapping information for the second thread indicates that the address tag value does not map to any guard tag. Thus, tag checking may be more likely to detect and be able to handle such situations. This reduces the chance of finding a match when comparing address tags validly used by one thread to be used by another thread. In general, this approach may be able to increase memory security by providing greater isolation of different threads than is possible when address tags have the same number of bits as guard tags.

[0034] In this manner, the address tag and remapped guard tag may be longer than the guard tag, but in some instances of remapping the address tag, the guard tag and remapped address tag may be longer than the guard tag. Such an approach benefits from an increased number of possible tag values, but may require storing longer guard tags in the memory system. However, in some systems, the space available within the pointers for storing address tags may be limited, and therefore it may be desirable to store longer guard tags in the memory system and remap the address tag to the longer remapped address tag to benefit from a reduced likelihood of tags being inadvertently matched.

[0035] Thus, in general, when at least one of an address tag / guard tag is remapped to form a remapped tag, the remapped tag may be longer (have more bits) than the original address / guard tag being remapped.

[0036] In some examples, the tag check circuitry may be configured to perform tag checking in response to a memory access request. For example, the memory access request may be a load request requesting that data from a location associated with a target address be loaded into a register, or an instruction fetch request requesting that an instruction associated with the target address be fetched, or a store request requesting that data be written to a particular memory location identified by the target address. The memory access request may have one of a plurality of access types. For example, the memory access request may have one of a read access type, a write access type, and an execute access type, where these access types indicate the type of operation associated with the target address (a read access corresponds to a load request, a write access corresponds to a store request, and an execute access corresponds to an instruction fetch request). It will be understood that other systems may support other types of accesses and may use several possible sets of access types.

[0037] In some examples, for a given entry of mapping information providing a mapping between a given guard tag value and a given address tag value, the tag mapping information can limit which of multiple access types of a memory access request are permitted to access a memory location within a block associated with a guard tag having a given guard tag value when the address tag of the memory access request specifies the given address tag value. For example, an entry of mapping information can indicate that a block of memory locations associated with a particular guard tag is read-only. Thus, when the tag check circuit performs a tag check on a target address specifying a memory location within the block of memory locations, the tag check circuit can limit permitted access to read access even if the tag check based on the address tag and the guard tag detects a match. If the tag check circuit detects a match based on the tag value but the requested access type is not a read access indicated by the entry of mapping information as a permitted access type, the tag check circuit can determine that the access is not permitted.

[0038] By using the mapping information to limit the types of accesses that are allowed, the device can provide permission information at the granularity level of a block of memory locations for which separate guard tags are defined. In typical systems, permission information is defined only at the page level, with a set of permissions that apply to the entire page. This approach can therefore enable finer-grained permission to be implemented by setting different guard tag values ​​for different addresses within the same page and associating different permissions with those guard tag values, or by specifying different guard tag mappings / address tag mappings for different types of accesses (e.g., read / write / execute). In either case, the mapping information is used to limit what types of access requests are allowed to access the block of memory associated with a given guard tag value.

[0039] The mapping information exists in several forms. For example, the mapping information may include a mathematical relationship between address tag values ​​and guard tag values ​​such that the address tag value can be determined from the guard tag value, or vice versa. Such a mathematical relationship may be usable in both directions, both to determine the remapped tag value from the guard tag and / or address tag values, and similarly to determine the values ​​of the guard tag and / or address tag values ​​from the remapped tag values. Using the mathematical relationship in this manner allows tags to be remapped quickly and requires less storage space than other techniques. Alternatively, the mathematical relationship may be usable only in one direction to determine the remapped tag value, but may make it difficult or impossible to infer the address tag and / or guard tag values ​​from the remapped tag value, thereby preventing an attacker from reverse engineering a valid address tag even if they know the guard tag at a particular location.

[0040] In some examples, the mapping information specifies multiple remapped tag value fields storing remapped tag values ​​that can be looked up based on the values ​​of at least one of the guard tag and the address tag. In such examples, when remapping at least one of the address tag and the guard tag, the tag check circuit can be configured to select one of the multiple remapped fields based on the values ​​of at least one of the guard tag and the address tag. In this manner, the tag check circuit can determine the remapped tag to be used in the tag check based on the remapped tag value specified in the selected remapped tag value field. By storing the mapping information in this manner, the mapping information can easily associate any of the possible values ​​of the guard tag and / or the address tag with the remapped tag value by setting the remapped tag value field to a desired value. This provides flexibility in the mapping used between tag values ​​and allows tag values ​​to be easily updated. This approach can also allow the same address tag value to be mapped to two or more different guard tag values ​​to provide address tags that can be used to access more memory locations. Similarly, the same guard tag value may be mapped to two or more different address tag values ​​that may be used to enable access to a particular block of memory locations using two or more possible address tag values, or to provide different address tag values ​​for different types of access to the same memory location. Further information, such as permission information, may also be stored in association with each item of mapping information by providing a field that may be selected using the guard tag and / or address tag values ​​in a manner similar to the selection of the remapped tag values.

[0041] In addition to storing remapped tag values ​​in multiple remapped tag value fields of the mapping information, fields of the mapping information may be used to store permission information associated with the remapped tag values. Thus, each field may specify not only a remapped tag value to be used in the comparison, but also an indication of the type of memory access allowed. For example, for each item of the mapping information, one or more bits may be provided to indicate permission information. This allows the tag check circuit to ensure not only that an executing portion of code has access to a given block of memory locations, but also that the portion of code has sufficient access rights for the type of access being sought. For example, the tag check circuit may receive a write access request for a given location. The tag check circuit may detect a match when performing a tag comparison. However, the remapped tag value corresponding to the given location may indicate that only read and execute accesses are allowed to that memory location using that address tag. In response to detecting such a mismatch between the requested access type and the permission information, the tag check circuit may take an error response action. The error response action may be the same as or different from the error response action taken in response to detecting a mismatch in the tag comparison.

[0042] These techniques can be used to enforce write exclusivity, whereby memory locations are either write-accessible or execute-accessible, but memory locations that can be written to are not used for execution, and memory locations that store code that can be executed are not written to, thereby reducing the opportunity that an attacker can provide executable malicious code.

[0043] It will be appreciated that storing permission information in association with a remapped tag value is just one of several possible ways to restrict the type of memory access that is permitted. In some examples, the tag mapping storage circuitry is configured to store different sets of mapping information corresponding to different access types. For example, in a system utilizing read, write, and execute access types, the tag mapping storage may be configured to store a set of mapping information for each of the read, write, and execute access types. When performing a tag check, the tag check circuitry may be configured to select which set of mapping information to use to generate a remapped tag for use in the tag check based on the access type associated with the memory access request. That is, the tag check circuitry may select a set of mapping information corresponding to the type of access requested, such that, for example, when a read access is requested, the mapping information corresponding to the read access type is used for remapping. In this way, a different set of mapping information can be provided for each of several different access types, so that, for example, if an address tag valid for a read access to a given memory location is reused to attempt to write to the same memory location, different mapping information will be used to generate a remapped tag for use in the tag check, and the mapping information for the write access may therefore be such that a mismatch will be detected in the tag check. This means that separate read / write / execute permissions can effectively be defined for individual sub-portions of a page, which is not possible with permissions defined by the MMU using, for example, page tables.

[0044] The techniques described herein may be particularly useful for sandboxing different threads of the same process. A process running on a processor may have an associated set of page tables that allow virtual addresses used by the process to reference memory locations that are translated into physical addresses that can be used to access physical memory. These page tables may be used to provide isolation between different processes running on the processor. However, such an approach does not provide protection within a process that prevents threads of the process from accessing data associated with other threads of the same process.

[0045] Sandboxing or preventing threads of a process from accessing data of other threads of the same process that consequently share the same set of page tables may be desirable, for example, in the case of browser tabs. A browser may implement a single virtual machine, such as a JavaScript engine, that executes JavaScript code present in web pages loaded in different tabs of the browser. While it may be desirable to isolate code running in different browser tabs, using complete process isolation with a different set of page tables for each tab may be too resource intensive to implement for each tab. However, to provide memory protection between browser tabs in accordance with the techniques described herein, for example, each browser tab may be implemented within a thread, and each thread may be sandboxed.

[0046] According to some examples, the mapping information stored in the tag mapping storage circuitry is associated with a particular thread executable by the processing circuitry (e.g., a thread executing code from a single browser tab). The mapping information may indicate a mapping to use in response to a target address generated by the processing circuitry when executing the particular thread. Thus, the tag checking circuitry can ensure that it uses a set of mapping information associated with the executing thread to generate a remapped tag value for use in tag checking. By providing separate sets of mapping information for different threads, if a thread attempts to access a memory location it should not access using an address tag it uses for another location it can access, or if it attempts to reuse a target address and address tag combination from a different thread, this can be detected and an error response action can be taken.

[0047] Tabs in a browser are one example of when a process may have multiple threads, but it will be recognized that sandboxing between threads may be used for a range of possible purposes. Furthermore, some low-power or small-footprint devices may not need to implement any form of memory management, by using page tables and the techniques described herein to provide isolation between threads; such devices may be able to enforce finer-grained memory protection without the overhead of dealing with page tables.

[0048] In some examples, the tag mapping storage circuit may comprise storage circuitry that stores one set of mapping information at a time. For example, the tag mapping storage circuit may comprise registers that store mappings associated with threads currently executing on the processing circuit. When the processing circuit switches to execute a different thread, the device may cause the set of mapping information associated with the threads to be loaded into the registers to replace the mapping information associated with the thread that was no longer executing. By storing only one set of mapping information in the tag mapping storage circuit at a time, the tag mapping storage circuit may be simplified. Furthermore, because other information (such as register state, control state for controlling how to process the new thread, and a context identifier associated with the new thread) is typically loaded on a context switch, loading new mapping information back to the same may not cause significant performance issues when switching threads.

[0049] Alternatively, the tag mapping storage circuit may be configured to store multiple sets of mapping information, each set corresponding to a different thread. Thus, the tag check circuit may be configured to perform the tag check based on mapping information stored in one of multiple mapping registers in the tag mapping storage circuit associated with the thread that triggered the tag check. By storing mapping information in the tag mapping storage circuit for more than one thread, the device may more quickly transition between execution of different threads because it does not need to load a new set of mapping information on a context switch.

[0050] For example, a simultaneous-multi-threaded (SMT) processor may store mapping information for each thread in parallel with the architectural state stored for that thread. In an SMT processor, multiple threads can execute at once using instructions tagged with the thread identifier (ID) of the corresponding thread. An SMT core typically has multiple sets of registers to store the architectural state for multiple threads at once, and for each instruction, the appropriate set of registers is referenced based on the thread ID of that instruction. Thus, the pipeline of an SMT processor can interleave processing associated with multiple threads and can have instructions "in-flight" for multiple threads simultaneously. Thus, in addition to registers storing architectural state, SMT may also provide mapping registers for different threads supported in hardware. A tag check can then be performed based on the mapping information stored in a register selected using the thread ID of the instruction that triggers the tag check.

[0051] In some examples, the device provides the ability to update or generate mapping information. Such tag mapping configuration circuitry may be used to change some or all of the mappings between guard tag values ​​and / or address tag values ​​and remapped tag values, or may be used to generate an entirely new set of mappings. The tag mapping configuration circuitry can respond to several types of requests for a new or updated set of mapping information to generate or update the mapping information in a manner indicated by the request. The ISA defining the instructions supported by the processing circuitry may include instructions that allow a programmer to specify that mapping information should be generated or updated, or the request may be implemented as a microarchitectural feature to implement the programmer's intent specified at a higher level. In some examples, the ISA does not include dedicated instructions for setting mappings, but instead treats mapping registers as control registers that can be updated using set control register instructions that specify the values ​​to be written to the registers. In other examples, dedicated mapping configuration instructions may be supported that cause hardware to generate values ​​specified in the mapping information, without software having to provide the exact values ​​to be set in the mapping information as operands of the mapping configuration instructions. Examples of types of requests and responses for the tag mapping configuration circuitry are described below.

[0052] In some examples, the tag mapping configuration circuitry is configured to generate a new set of mapping information in response to a request for such a new mapping by “shuffling” available remapped tag values. That is, the tag mapping configuration circuitry can configure the tag mapping storage circuitry to indicate a new set of mapping information indicating that each value of the guard tag and / or address tag is associated with a different remapped tag value. By associating each value of the guard tag and / or address tag with a different remapped tag value, the chance of not detecting misuse of the address tag is reduced. In particular, this approach ensures that two values ​​of the guard tag and / or address tag are not mapped to the same remapped tag value. This, in turn, reduces the chance of a match being detected when a pointer is used to access an unintended region of memory. If two guard tag values ​​map to the same remapped tag value, for example if an address tag was effectively generated to access a block associated with a first of the guard tag values, a match may be detected when the address tag is used to access a block associated with a second of the guard tag values, even if accessing those locations triggers an error handling response to signal a memory usage error.

[0053] When updating the set of mapping information, it may be desirable to be able to specify one or more values ​​of the remapped tag that are not used. This may be the case when certain remapped tag values ​​are reserved for a particular purpose (e.g., because they are used in a previously allocated memory region where tag aliasing is not desired), and it is desirable that values ​​of at least one of the address tag and the guard tag not be mapped to those remapped tag values. This may be indicated by a tag mapping update request that specifies one or more excluded tag values ​​to be excluded from selection as remapped tag values. In response to this request, the tag mapping configuration circuitry may indicate a new set of mapping information indicating that each value of one of the guard tag and the address tag is associated with a remapped tag value other than the one or more excluded tag values. It will be appreciated that the new set of mapping information should be generated excluding certain tag values, and that if it is desirable for each tag value to be mapped to a different remapped tag value, more remapped tag values ​​may be available than the tag values ​​to be remapped, for example, by using longer remapped tags.

[0054] In some examples, the tag mapping configuration circuit responds to a request for a new mapping indicating that certain memory locations are not to be accessed regardless of the address tag provided. For example, it may be determined that a particular thread associated with a set of mapping information is not allowed to access certain memory locations regardless of the address tag provided in association with a request to access those memory locations. To implement this behavior, an apparatus may include tag mapping configuration circuitry configured to, in response to a tag mapping update request specifying one or more exclusion tag values, configure the tag mapping storage circuit to indicate a new set of mapping information indicating that memory access to a target address is not permitted when a tag check identifies that at least one of a guard tag and an address tag has one of one or more exclusion tag values. The mapping information may indicate that these memory locations are not to be accessed in some manner. For example, a set of mapping information may be configured such that one or more tag values ​​associated with prohibited memory locations do not have corresponding tag values ​​that cause a match in a tag check. This may be achieved by setting all fields in the mapping information to values ​​other than the exclusion tag values. Alternatively or additionally, the mapping information may include permission information indicating that no form of access to the specified memory locations is permitted when using that set of mapping information.

[0055] In some examples, the tag mapping configuration circuit provides the ability to “pin” one or more existing tag mappings when performing a tag mapping update. For example, it may be desirable to ensure that mappings that are still in use are maintained and not overwritten when updating other mappings in the same set of mapping information. Accordingly, the tag mapping configuration circuit may be configured to configure the tag mapping storage circuit to update tag mappings other than the one or more existing tag mappings in response to a tag mapping update request that specifies one or more existing tag mappings to be excluded from the update. Thus, an updated set of mapping information can be generated for storage in the tag mapping storage circuit while leaving the specified existing tag mappings unchanged. In some cases, when performing such an update, the tag mapping configuration circuit is configured to avoid mapping corresponding tag values ​​already associated with “pinned” tag values ​​to tag values ​​that are not marked as “pinned.” For example, if a particular guard tag value is “pinned,” in addition to not updating the mapping for the “pinned” guard tag value, the tag mapping configuration circuit may avoid associating any “unpinned” guard tag values ​​with address tag values ​​associated with the “pinned” guard tag value. It will be appreciated that this may be done in a similar manner as if the address tag value were "pinned."

[0056] In some examples, the device includes a tag mapping setting circuit configured to, in response to an all-match tag mapping update request, set the tag mapping storage circuit to indicate a new set of mapping information indicating that all guard tag values ​​should be mapped to the same address tag value. By doing so, a single address tag value can be used to access memory locations associated with any of the guard tags. In some cases, it may be beneficial to temporarily provide an all-match function so that tag checking can be guaranteed not to detect a mismatch when using a single address tag value to which all of the guard tag values ​​are mapped. This may be useful for providing support for legacy code that does not support the use of tags.

[0057] As described above, an error response action may be executed in response to detecting a mismatch in a tag check. Furthermore, an error response action (which may be the same error response action or a different error response action) may be executed in response to detecting an access attempt in which the requested access type is not indicated as permissible by the permission information. The error response action may include one or more of several possible actions. The error response action may include denying access to the memory location specified by the target address. Denying access to the requested memory location when the tag check fails may improve memory security. However, tag checks may be time-consuming to execute because they require fetching guard tags from memory, and delaying the actual memory access until the tag check passes may incur a performance cost that is unacceptable in some implementations. Because tag checks may not pose a significant security issue in themselves but may be used to identify memory errors in code that may present a risk for future exploitation by an attacker, it may be sufficient to simply provide an indication of a mismatch while still allowing the access to proceed. This may improve performance. Thus, the error response action may include placing an indication in a status register that the tag check detected a mismatch, logging an entry in an error report, or otherwise signaling a fault. The error response action may indicate that a mismatch was detected and the address of the location where the instruction that caused the mismatch is stored and / or the location to which access is sought. In some examples, the device is capable of operating in multiple modes, and different error response actions are performed in the different modes. For example, the device may be capable of operating in a non-precise mode in which the access is allowed to proceed despite the detected mismatch, and a precise mode in which access to the memory location specified by the target address is denied in response to detecting a mismatch.It will be appreciated that there are several possible error response actions that may be performed in response to detecting a mismatch, and that more than one such error response action may be performed in response to detecting a mismatch.

[0058] FIG. 1 schematically illustrates an example data processing apparatus 2. This is merely a high-level representation of a subset of the apparatus's components, and it will be understood that the apparatus may include many other components not shown. The apparatus 2 includes processing circuitry 4 for performing data processing in response to instructions decoded by an instruction decoder 6. The instruction decoder 6 decodes instructions fetched from an instruction cache 8 and generates control signals for controlling the processing circuitry 4 to perform the corresponding processing operations represented by the instructions. The processing circuitry 4 may include one or more execution units for performing operations on values ​​stored in registers 14 to generate result values ​​that are written back to the registers. For example, the execution units may include an arithmetic / logic unit (ALU) for performing arithmetic or logical operations, a floating-point unit for performing operations using floating-point operands, and / or a vector processing unit for performing vector operations on operands that include multiple independent data elements. The processing circuitry also includes a memory access unit (or load / store unit) 15 for controlling the transfer of data between the registers 14 and a memory system. In this example, the memory system includes an instruction cache 8, a level 1 data cache 16, a level 2 cache 17 shared between data and instructions, and a main memory 18. It will be understood that other cache hierarchies are possible and this is only one example. A memory management unit (MMU) 20 is provided to provide address translation functionality in support of memory accesses triggered by the load / store unit 15. The MMU has a translation lookaside buffer (TLB) 22 for caching a subset of entries from page tables stored in the memory systems 16, 17, 18.Each page table entry may provide an address translation mapping for the corresponding page of an address and may also specify access control parameters, such as access permissions specifying whether the page is a read-only area or readable and writable, or which privilege levels can access the page.

[0059] FIG. 2 illustrates an exemplary tag check based on comparing a guard tag with an address tag. The physical address space used to reference memory locations in a memory system can be logically divided into several blocks 30, each containing a certain number of addressable locations. For simplicity, in the example of FIG. 2, each block 30 contains four memory locations, although other block sizes may be used as well. Each block 30 is associated with a corresponding guard tag 32. The guard tags associated with a certain number of blocks 30 may be collected together and stored either in different architecturally accessible memory locations 34 within the same physical address space, or in additional storage locations provided in main memory 18 that are not architecturally accessible (not mapped to the same physical address space). The use of separate, non-architecturally accessible storage may be preferable in some cases to avoid running out of space in data caches 16, 17 for caching guard tag values, which may affect regular code performance and make coherency management more complex. For faster access than if the tags had to be accessed from main memory 18, the microarchitecture may provide an additional tag cache 19 (shown in FIG. 1) for caching tag values ​​to non-architecturally accessible storage. The specific mapping of which tag storage locations 34 correspond to each block 30 may be controlled by load / store unit 15 and may be hardwired or programmable. While FIG. 2 shows each tag 32 associated with a block of physical addresses, it is also possible to provide guard tags 32 associated with virtual memory locations in the virtual memory address space, although this may require some additional address translation for each memory access. Therefore, associating guard tags 32 with physical memory locations can improve performance. In general, exactly how guard tags 32 are associated with corresponding blocks 30 in the physical address space is a choice for a particular microarchitecture implementation.Generally, all that is required is the ability to access and compare the guard tag 32 associated with a given block of memory.

[0060] Thus, when a tag check is required, a comparison is performed based on the address tag 40 (associated with the target address 42, which identifies the addressed location 44 to be accessed) and the guard tag 32 associated with the block of memory locations 30 that contains the addressed location 44. For example, in FIG. 2, the target address 42 points to a particular location B1 in memory, marked 44 in the address space of FIG. 2. The comparison is therefore based on the guard tag B associated with the block of locations B that contains location B1, and the address tag 40 associated with the target address 42. The address tag 40 may be determined as a function of selected bits of the target address itself. In particular, the address tag may be determined from bits within a portion of the target address that are not used to indicate the particular memory location selected as the addressed location 44. For example, in some architectures, the most significant portion of the bits of the target address may always have a particular fixed value, such as sign extension (all 0s or all 1s), and therefore the address may be tagged with the address tag 40 by overwriting these unused bits with an arbitrary tag value. The particular tag value may be selected by the programmer, the compiler, or may be selected randomly. The address tag and guard tag 32 can be a relatively small number of bits, for example 4 bits, and therefore do not need to take up much space in memory and in the target address.

[0061] In response to a request to access a given memory location, a tag check may be performed to determine whether the access is permitted. In some implementations, tag checking may be performed for all memory accesses. However, it may be preferable to provide a configuration option for software to select whether to perform tag checking. In this case, if tag checking is enabled by configuration information stored in a control register, memory accesses may be treated as tag-protected memory accesses and tag checking may be performed on the target address of each memory access, but if tag checking is disabled by configuration information, memory accesses may be performed without tag checking. Also, some implementations may support the ability to define a subset of memory accesses as requiring tag checking and other memory accesses as not requiring tag checking (e.g., separate tag-check and no-check memory access instructions may be supported to indicate whether a memory access should be treated as a tag-protected memory access in which a tag check is performed on the target address if tag checking is enabled).

[0062] Additionally or alternatively, memory access circuitry 15 may support performing tag checks in response to dedicated tag check instructions that specify the target address for which tag checking is required, without triggering a memory access.

[0063] The memory access circuit 15 includes a tag check circuit 62 and a tag mapping storage circuit 64. The tag mapping storage circuit 64 is configured to store mapping information indicating a mapping between the values ​​of at least one of the guard tags and the address tags and the remapped tag values. The mapping information may provide a mapping between the guard tag values ​​and the remapped guard tag values, between the address tag values ​​and the remapped address tag values, or may provide mapping information for both the guard tags and the address tags. The tag check circuit 62 is communicatively coupled to the tag mapping storage circuit 64.

[0064] Thus, in response to a target address 42 having an associated address tag 40, using the mapping information, tag check circuit 62 remaps guard tag 32, address tag 40, or both to generate a remapped tag upon which the tag check is based. If one of guard tag 32 and address tag 40 is remapped to form a remapped tag, tag check circuit 62 compares the remapped tag with the one of guard tag 32 and address tag 40 that was not remapped to determine whether they match. If both guard tag 32 and address tag 40 are remapped to generate a remapped tag value, the two remapped tag values ​​are compared to determine whether they match. If tag check circuit 62 detects a mismatch in the tag check, tag check circuit 62 performs an error response action, such as outputting fault signal 60 (shown in FIG. 1). It will be appreciated that there are several possible error response actions that may be taken depending on the requirements of the system, such as updating a status register to indicate whether there was a match or not, or adding an entry to the error report indicating the address where the error was detected and / or the instruction address of the instruction that triggered the error.

[0065] 3 is a flow diagram illustrating a method for performing tag checking involving remapping address tags and / or guard tags. In step 102, a target address and an address tag are received. In some cases, the address tag may actually be derived from a subset of bits in the target address itself, while in other instances, it may be specified in a separate register. The target address may specify a memory location to which access is sought, where the memory location is part of a block of memory locations having an associated guard tag, which guard tag is identified in step 104. In step 106, the guard tag and / or address tag are remapped to generate a remapped tag that is used in a tag check performed in step 108. The tag check compares the remapped tag with the guard tag and / or address tag that was not remapped. As shown in step 110, if the tag check detects a mismatch, then in step 114, an error response action may be performed, such as placing an indication in a status register, recording an entry in an error report, signaling a fault, or denying access to the memory location identified by the target address. In step 112, access to the memory location can be granted in one of two ways, as indicated by the dotted lines in Figure 3. Access to the memory location can be granted regardless of the result of the tag check, and thus may even be granted before the tag check is performed. By doing this, performance may be improved because access can begin without having to wait for the guard tag to be returned from memory and for the tag check to be performed. Alternatively, access to the memory location may be granted only if a match is found in step 110. Thus, only accesses for which the appropriate address tag is provided may be allowed to proceed.Memory access circuitry 15 may be configured to perform only one of these techniques, or may be capable of operating in more than one mode and thus perform methods according to both variations when in different modes.

[0066] As described above, at least one of the guard tag and the address tag is remapped using mapping information stored in the tag mapping storage circuit 64. FIG. 4 illustrates an exemplary tag check for remapping a guard tag. FIG. 4 shows a target address 42 including an address tag 40 having a value of 0b1001. The target address 42 specifies a memory location 44 in memory 18 associated with a guard tag 32 having a value of 0b0011. In this example, the address tag and guard tag are both 4 bits in length, and therefore there are 16 possible values ​​for each of the address tag and guard tag. The tag mapping storage circuit 64 includes a mapping register 68 that stores mapping information. This mapping information is used to map the guard tag 32 to the remapped tag 52. In the example shown in FIG. 4, the mapping information includes multiple bit sets. Each bit set represents a field in the mapping information that specifies a remapped address tag value for a different guard tag value. An item of mapping information corresponding to the guard tag 32 is identified in the mapping register 68. 4, this corresponds to bits 12-15 of mapping register 68 where the remapped tag value is stored. A tag check can then be performed by comparing address tag 40 with remapped tag 52. In this case, remapped tag 52 has the same value of 1001 as the address tag value, so the tag check finds a match.

[0067] In the example shown in FIG. 4, the guard tag, address tag, and remapped tag 52 are all the same length. However, in some examples, the mapping information can map tags of different lengths to one another. FIG. 5 shows an exemplary tag check in which the remapped guard tag and address tag are longer than the guard tag. In this example, the address tag 40 is 8 bits long with a value of 0b10101001, and the guard tag is 4 bits long with a value of 0b0001. The mapping information stored in the mapping register 68 maps the 4-bit guard tag 32 to the 8-bit remapped tag 52 for use in the tag check. In this way, many of the benefits of having longer tag values, such as being able to allocate separate sets of address tags in the mapping information for different threads, can be achieved without using up more space in memory to store longer guard tags. In some architectures, the upper portion of the bits of the target address may always have a specific fixed value. This can occur because an instruction set architecture may support addresses with a certain number of bits (e.g., 64 bits), but a given hardware device may not actually require so much memory capacity to use all possible addresses that can be represented using that number of bits. For example, current trends in device usage still require addresses with 2 64It is not necessary to provide 10 individually addressable locations. Thus, often some bits of a memory address may be effectively unused. These bits may therefore be used to store an address tag or a value for deriving an address tag to avoid having to access a separate register to obtain the address tag. The number of unused bits may be sufficient so that address tags of 8 bits or more in length may be stored without affecting the length of the address or having to use a separate register to store the address tag. Utilizing longer address tags without using longer guard tags can improve memory security without requiring more space in memory to be devoted to storing guard tags or requiring extra storage for address tags.

[0068] FIG. 6 illustrates another exemplary tag check in which the remapped guard tag and address tag are longer than the guard tag. For simplicity, the target address and memory are not shown in the example of FIG. 6; only the tags and their comparison are illustrated. In this example, guard tag 32 is remapped to generate remapped tag 52, which is longer than guard tag 32 and the same length as address tag 40. Address tag 40 and remapped tag 52 are then compared in a tag check. In this example, because address tag 40 and remapped tag 52 have the same value, a match is detected in the tag check, and no error response action is performed. However, if a mismatch is detected, for example, because the value of remapped tag 52 and the value of address tag 40 are different, an error response action is performed.

[0069] In the examples shown in FIGS. 4-6, the guard tag is remapped and the remapped guard tag is compared to the address tag. This may provide greater flexibility in how the mapping can be constructed, for example, by facilitating the use of longer address tags. However, as shown in FIG. 7, the address tag 40 may instead be remapped based on mapping information stored in the tag mapping storage circuit 64 to generate a remapped address tag 52 for comparison with the guard tag 32. This allows the tag check to be performed more quickly. The guard tag 32 may need to be fetched from the tag cache 19, or may need to be fetched from the memory system if the guard tag is not found in the tag cache 19. Thus, by remapping the address tag 40, the remapping process can be performed at least partially in parallel with the fetching of the guard tag 32, thereby reducing the time it takes from receiving the target address to determining whether there is a match in the tag check. Although not shown, in some examples, both the guard tag and the address tag are remapped to generate two remapped tags that are compared to each other in the tag check.

[0070] FIG. 8 illustrates an exemplary tag check involving a permission check. In addition to checking the tag value, a permission check is performed to determine whether the type of access request that initiated the tag check is an allowed type of access. In the example of FIG. 8, address tag 40 is an 8-bit address tag that is compared with 8-bit remapped tag 52 based on 4-bit guard tag 32. In addition to storing mappings between guard tag values ​​and remapped tag values ​​for comparison with address tag values, tag mapping storage circuit 64 includes mapping registers 68 that store permission information for each mapping. As shown in FIG. 8, an item of mapping information associated with guard tag 32 stores a corresponding remapped tag 52 and permission information 54. In this example, three types of access are supported: read, write, and execute. The permission information indicates, for each item of mapping information, which of these types of accesses are allowed to occur. In other examples, different types of accesses and corresponding permissions may be supported. Additionally or alternatively, other information regarding the requested access may be provided in the mapping information, such as attributes indicating a cache policy applicable to the block of memory locations associated with the guard tag identified by the item of mapping information. In addition to checking whether the remapped tag value matches the address tag value, a permission check is performed to determine whether the requested access is permitted using the permission information stored in mapping register 68. If it is determined that the requested access is not permitted, an error response action can be taken, which may be the same as or a different error response action than that taken when a mismatch between tag values ​​is detected.

[0071] By providing permission information, the types of accesses allowed can be constrained. This can be used to ensure that a program that is expected to perform only read accesses to certain memory locations does not write code to or execute code from those locations, or to identify code that does so and may be faulty. Permission information can also be used to ensure write-execute exclusivity. It is often desirable for security purposes to ensure that code stored in a region of memory that can be written to cannot be executed to prevent malicious or accidental modification of code that is later executed by the processor. It will be appreciated that permission can be implemented at the granularity level of a block of memory locations, since different permissions can be associated with each block. This approach can therefore provide finer-grained permission control than any permission checks performed by an MMU based on page tables, where any permission information is applicable to the entire region of memory associated with each page table entry. Any permission checks based on tag mapping information can be considered an additional form of permission check performed in addition to the page table-based permission checks performed by an MMU (if tag mapping information-based permission checks are performed, this does not prevent MMU checks from also being performed).

[0072] 9 illustrates another exemplary tag check involving checking permission information stored with mapping information. In this example, memory access circuit 15 receives a read access request as indicated by access type 44. The access request specifies a memory location comprising a block of memory locations 30 associated with guard tag 32. Using the mapping information stored by tag mapping storage circuit 64, guard tag 32 is remapped to generate remapped tag 52. In this example, the tag mapping information specifies multiple remapped tag value fields comprised of address tag values ​​that match the associated guard tag values ​​and permission information. By structuring the mapping information in this manner, address tag values ​​and permission information can be easily associated with appropriate guard tag values, and this information can be easily updated or changed for individual items of mapping information.

[0073] To generate remapped tag 52, guard tag value 0b0100 can be looked up in the mapping information to identify that the corresponding address tag value is 0b10101001, and that the types of permitted access to the block of memory locations associated with guard tag 52 are read and write. A tag check then compares remapped tag 52 to address tag 40, and a permission check compares the permitted access types indicated by permission information 54 to requested access type 44. In this example, address tag 40 and remapped tag 52 match, and requested access type 44 is a permitted access type; therefore, no error response action is taken. If either or both of these checks detect a mismatch, error response action may be taken.

[0074] 8 and 9 show examples in which fields are used to store permission information for each item of mapping information. Thus, for the same set of mapping information, different items of mapping information (corresponding to different values ​​of one of the guard tag / address tags used to index the mapping information) may have different permissions. However, the permission information may be stored in several other ways. For example, a separate set of mapping information may be stored for each of multiple possible access types. This approach is illustrated in FIG. 10, which shows a tag mapping storage circuit 64 with a mapping register 68 for each of the read, write, and execute access types supported by the device. In response to an access request specifying an address tag 40 and an access type 44, the guard tag 32 is remapped based on the appropriate set of mapping information stored in the tag mapping storage circuit 64. In this case, the access request is a read access request, and therefore the guard tag 32 is remapped based on the set of mapping information stored in the mapping register 68 corresponding to the read access type. The set of mapping information for a read access type indicates that the remapped tag value for guard tag 32 is 0b1011, so remapped tag 52 has a value of 0b1011. This remapped tag value 52 is compared to address tag 40 in a tag check. Because the tag values ​​are the same, no mismatch is detected, and therefore, it is determined that the appropriate address tag has been provided to perform the requested type of access to the requested target location, and no error response action is taken. However, if the same address tag 40 with a value of 0b1011 is used to attempt and perform a write access, a different set of mapping information may be used to remap guard tag 32, resulting in a different remapped tag 52 that does not match address tag 40.10, if a write access is instead requested, a different mapping register 68 storing different mapping information is used, and the guard tag 32 is remapped to produce a remapped tag 52 having a value of 0b0011. Thus, the tag check detects a mismatch between the address tag 40 having a value of 0b1011 and the remapped tag 52 having a value of 0b0011, and an error response action is performed accordingly. In this manner, memory errors resulting from a valid address tag being reused for a different type of access than that intended can be identified, prevented, and / or logged.

[0075] In addition to, or instead of, providing a set of mapping information for each type of access, each set of mapping information may be associated with a particular thread executable by processing circuitry 4. FIG. 11 illustrates an exemplary tag check involved in selecting a mapping to use based on the thread being executed. In this example, when remapping guard tag 32, the set of mapping information to use is selected based on the thread being executed on processing circuitry 4. Tag mapping storage circuitry 64 is configured to store multiple sets of mapping information corresponding to different threads, and the thread ID 46 of the thread being executed on processing circuitry 4 is used to identify which set of mapping information to use. As shown in FIG. 11, thread ID 64 is 0x12A7, and therefore the set of mapping information associated with thread 0x12A7 is used to map guard tag 32 to a remapped tag 52 having a value of 0b1011. This remapped tag value 52 is compared to address tag 40 in a tag check. In this case, the tags have the same value, so no mismatch is detected and no error response is executed. However, if the same address tag 40 is used by another thread executing on processing circuit 4, such as a thread with a thread ID of 0x12A8, the mapping information associated with that thread ID is used to remap guard tag 32 to generate a remapped tag value of 0b0011. As a result, tag checking detects a mismatch between remapped tag 52 and address tag 40, and an error response action is performed. Thus, this technique can detect threads attempting to reuse address tags 40 that could validly have been created for use by a different thread, which can be useful for sandboxing threads from each other.

[0076] 11 , the tag mapping storage circuit 64 is configured to store multiple sets of mapping information in a bank of mapping registers 68. In this manner, mapping information corresponding to several threads can be stored in the tag mapping storage circuit 64 simultaneously. Alternatively, the tag mapping storage circuit 64 may be configured to store a limited number (e.g., one) of sets of mapping information at a time. When one set of mapping information is stored in the tag mapping storage circuit 64, the stored set of mapping information may be the set of mapping information corresponding to the thread currently executing on the processing circuit 4. When a context switch occurs that causes the processing circuit 4 to execute a different thread, the memory access circuit 15 may be configured to replace the mapping information stored in the tag mapping storage circuit 64 with the set of mapping information associated with the executing thread. This approach reduces the amount of storage required by the tag mapping storage circuit 64.

[0077] 12 schematically illustrates an apparatus including a tag check circuit 62, a tag mapping storage circuit 64, and a tag mapping configuration circuit 66. In this example, the tag mapping configuration circuit 66 is provided to operate in response to a request for a new or updated set of mapping information, to provide such a new or updated set of mapping information to the tag mapping storage circuit 64. Functionality may be provided to specify when and how the mapping information should be configured or updated. The tag mapping configuration circuit 66 may respond to multiple types of requests that specify how a new set of mapping information is generated. Examples of types of tag mapping configuration circuit 66 requests and corresponding behaviors that may be supported by the tag mapping configuration circuit 66 are described below with reference to FIGS. 13-16.

[0078] In the following examples, the term address tag value is used to refer to the value of an address tag that causes a match in a tag check when compared to a corresponding guard tag, which may be the same as the remapped tag value. In the following examples, the address tag values ​​are set such that each guard tag value is associated with a different address tag value, and tag mapping setting circuit 66 may support setting the guard tag values ​​such that each address tag value is associated with a different guard tag value.

[0079] FIG. 13 illustrates an example in which tag mapping configuration circuit 66 is configured to configure tag mappings in response to a request specifying that each guard tag value be associated with a different address tag value. Such a request is referred to as a shuffle request in FIG. 13. As can be seen from FIG. 13, the mapping generated by tag mapping configuration circuit 66 in response to such a shuffle request indicates that each address tag value is assigned to no more than one guard tag value. In this example, since the number of possible guard tag values ​​is the same as the number of possible address tag values, each address tag value is strictly assigned to one address tag value, although this is not generally the case when the address tag and guard tag may have different lengths. When generating new mappings, it may be desirable to have all of the guard tags map to different address tags to avoid a situation in which the same address tag value is associated with different guard tag values, because an address tag having one of these address tag values ​​may match a guard tag associated with the same address tag value even if the memory location is not a disallowed access. The selection of which address tag value is associated with each guard tag may be random. While FIG. 13 shows an example in which a 3-bit value is used for each of the guard tag value and the address tag value, it will be appreciated that these techniques are also applicable to tag values ​​of other lengths, including when the address tag has a different length than the guard tag.

[0080] FIG. 14 illustrates an example of tag mapping configuration in which certain address tag values ​​are excluded from selection. The tag mapping configuration circuit 66 is configured to operate in response to a request specifying one or more excluded tag values ​​to be excluded from selection. As shown in FIG. 14, this may be indicated by the use of an exclusion mask that includes a field for each possible address tag value to indicate whether the address tag value should be excluded from selection. In this example, a value of 1 indicates that the address tag value should be excluded from selection, although it will be understood that different mappings may be used. In response to the exclusion mask, the tag mapping configuration circuit is configured to generate a set of mapping information in which the excluded address tag values ​​are not assigned to guard tag values. In this example, 3-bit guard tag values ​​and 4-bit address tag values ​​are used. It will be understood that when certain values ​​are excluded from selection, such as through the use of an exclusion mask, if each guard tag value is assigned a different address tag value, more possible address tag values ​​than guard tag values ​​are required, and therefore a longer address tag is used. However, in some examples, reusing the same address tag value for different guard tag values ​​may be acceptable. Thus, in such examples, an exclusion mask may be used even if the address tag and guard tag have the same number of bits. While this increases the probability of detecting a false match in a tag check, it may nevertheless be useful to increase isolation between threads / sandboxes by providing a non-overlapping set of tag values ​​in the mapping information. Whether this approach is taken or a longer address tag is provided to ensure that each guard tag is assigned a different address tag value may be based on the relative priorities of sandboxing between threads of a process and detecting memory errors within a thread. In some examples, device 2 may be configured to support both approaches using software that can indicate the selected approach by setting configuration information in a control register to set the length of the remapped address tag to be used.In some implementations, updates to any control information used to control how tag mapping is performed may be restricted to software at or above a certain privilege level (e.g., restricted to operating system or hypervisor software, so that application-level code is not allowed to set control information).

[0081] FIG. 15 illustrates an example of a tag mapping update in which certain guard tag values ​​are excluded from the update. These guard tag values ​​are designated as “pinned” values ​​whose mappings should not change. As shown in FIG. 15, guard tag values ​​to be excluded from the update may be indicated using an update mask that includes a field for each possible guard tag value to indicate whether the guard tag value should be excluded. In the example of FIG. 15, a value of 1 indicates that the mapping should be excluded from the update, but it will be understood that other mappings may be used. The mapping information before and after the update is shown in FIG. 15 with an asterisk to identify the mappings designated by the update mask as being excluded from the update. It can be seen that these mappings are the same before and after the update. Other mappings have been updated by the tag mapping configuration circuit 66. It may be desirable to ensure certain mappings do not change when a set of mapping information is updated. By ensuring certain mappings are “pinned,” the tag mapping configuration circuit 66 can ensure that mappings for guard tags associated with blocks containing shared memory locations do not change, so that common address tags for different threads can be used to access those locations. The tag mapping configuration circuit 66 may also avoid assigning tag values ​​associated with "pinned" tag values ​​when performing updates, as can be seen in FIG. 15 because the address tag values ​​1001, 1110, and 0101 associated with the "pinned" guard tag values ​​010, 011, and 101 are not assigned to any of the other guard tag values.

[0082] FIG. 16 shows an example of a tag mapping configuration in which all guard tag values ​​are mapped to the same address tag value. This may be desirable to effectively disable the tag checking function, since a match is detected as long as the provided address tag has the same value as the address tag value to which all of the guard tag values ​​are mapped. This may be particularly advantageous when dealing with legacy code that does not support tag-protected accesses. In this case, all guard tag values ​​may be set to the default value of the address tag that may be provided. As explained above, in some architectures, the address tag may be determined from bits of the target address that would otherwise all be set to a given value. If a given value is not replaced in the target address by an address tag (such as in legacy code), these bits may nevertheless be interpreted as an address tag when performing tag checking, and by mapping all of the guard tag values ​​to their default values, all accesses may be permitted without having to provide a means to bypass tag checking entirely. As shown in FIG. 16, all of the guard tag values ​​are mapped to the address tag value 0b1111, but it will be understood that another value may be used instead.

[0083] FIG. 17 illustrates a simulator implementation that may be used. While the above-described embodiments implement the present invention in terms of apparatus and methods for operating specific processing hardware supporting the related art, it is also possible to provide an instruction execution environment according to the embodiments described herein implemented using a computer program. Such computer programs are often referred to as simulators, insofar as they provide a software-based implementation of a hardware architecture. Various simulator computer programs include emulators, virtual machines, models, and binary translators, including dynamic binary translators. Typically, a simulator implementation may run on a host processor 230, optionally running a host operating system 220 that supports the simulator program 210. In some configurations, there may be multiple layers of simulation between the hardware and the provided instruction execution environment, and / or there may be multiple different instruction execution environments provided on the same host processor. Historically, powerful processors have been required to provide simulator implementations that run at reasonable speeds, but such an approach may be justified in certain situations, such as when it is desirable to execute code native to another processor for compatibility or reuse reasons. For example, a simulator implementation may provide an instruction execution environment with additional features not supported by the host processor hardware, or may provide an instruction execution environment typically associated with a different hardware architecture. An overview of simulation is given in "Some Efficient Architecture Simulation Techniques," Robert Bedichek, Winter 1990 USENIX Conference, pp. 53-63.

[0084] While embodiments have been described above with reference to particular hardware configurations or features, equivalent functionality may be provided in the simulated embodiments through appropriate software configurations or features. For example, particular circuits may be implemented as computer program logic in the simulated embodiments. Similarly, memory hardware such as registers or caches may be implemented as software data structures in the simulated embodiments. In configurations where one or more of the hardware elements referenced in the foregoing embodiments reside in host hardware (e.g., host processor 230), some simulated embodiments may use the host hardware where appropriate.

[0085] Simulator program 210 may be stored on computer-readable storage medium 212 (which may be a non-transitory medium) and provides a program interface (instruction execution environment) for target code 200 (which may include applications, an operating system, and a hypervisor), which is the same as the interface of the hardware architecture modeled by simulator program 210. Thus, program instructions of target code 200 may be executed from within the instruction execution environment using simulator program 210, thereby enabling a host computer 230 that does not actually have the hardware features of device 2 described above to emulate those features. For example, simulator program 210 may include tag checking program logic 214 for identifying guard tags, performing tag checks, and, in response to detecting a mismatch in the tag check, performing error response actions in a manner corresponding to how analogous tag checking circuitry 62 of a hardware embodiment performs these functions. Simulator program 210 may also include tag mapping maintenance program logic 216 (similar to tag mapping storage circuit 64 described above) for maintaining mapping information indicating a mapping between guard tag values ​​and corresponding address tag values.

[0086] In this application, the term "configured to..." is used to mean that elements of an apparatus have a configuration that is capable of performing a defined operation. In this context, "configuration" refers to a way of arranging or interconnecting hardware or software. For example, an apparatus may have dedicated hardware that provides the defined operation, or a processor or other processing device may be programmed to perform the function. "Configured to" does not imply that the apparatus elements need to be modified in any way to provide the defined operation.

[0087] Although exemplary embodiments of the present invention are described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to these precise embodiments and that various changes and modifications can be made in these embodiments by those skilled in the art without departing from the scope and spirit of the invention as defined by the appended claims.

Claims

1. 1. An apparatus comprising: a tag check circuit responsive to the target address, identifying a guard tag stored in the memory system associated with a block of one or more memory locations, the block including the target memory location identified by the target address; performing a tag check based on the guard tag and an address tag associated with the target address; performing an error response action in response to detecting a mismatch in the tag check; a tag check circuit; a tag mapping storage circuit for storing mapping information indicating a mapping between guard tag values ​​and corresponding address tag values; Equipped with the tag check circuitry is configured to remap at least one of the guard tag and the address tag based on the mapping information stored by the tag mapping storage circuitry to generate a remapped tag for use in the tag check. Device.

2. the tag checking circuitry is configured to remap the address tag, and the remapped tag is a remapped address tag.

10. The apparatus of claim 1.

3. the tag checking circuitry is configured to remap the guard tag, the remapped tag being a remapped guard tag; 10. The apparatus of claim 1.

4. The apparatus of any one of claims 1 to 3, wherein the remapped tag is longer than the at least one of the address tag and the guard tag.

5. the tag check circuitry is configured to perform the tag check in response to a memory access request that specifies the target address, the memory access request having one of a plurality of access types; and wherein for a given item of mapping information providing a mapping between a given guard tag value and a given address tag value, the tag checking circuitry is configured to restrict which of the plurality of access types of memory access requests are permitted to access memory locations within a block associated with a guard tag having the given guard tag value when the address tag of the memory access request specifies the given address tag value. An apparatus according to any one of claims 1 to 4.

6. the mapping information specifies a plurality of remapped tag value fields; the tag check circuitry is configured to select one of the plurality of remapped tag value fields based on a value of the at least one of the guard tag and the address tag, and to determine the remapped tag based on a remapped tag value specified in the selected remapped tag value field. An apparatus according to any one of claims 1 to 5.

7. the tag check circuitry is configured to perform the tag check in response to a memory access request that specifies the target address, the memory access request having one of a plurality of access types; the tag check circuitry is configured to determine whether the one of the plurality of access types is permitted based on permission information specified in the selected remapped tag value field.

7. The apparatus of claim 6.

8. the tag check circuitry is configured to perform the tag check in response to a memory access request that specifies the target address, the memory access request having one of a plurality of access types; the tag mapping storage circuitry is configured to store different sets of mapping information corresponding to different access types; the tag check circuitry is configured to select, based on the one of the plurality of access types associated with the memory access request, which set of mapping information to use to generate the remapped tag for use in the tag check. An apparatus according to any one of claims 1 to 7.

9. the mapping information is associated with a particular thread executable by a processing circuit; the mapping information indicating a mapping to use in response to a target address generated by the processing circuitry when executing the particular thread. An apparatus according to any one of claims 1 to 8.

10. the apparatus further comprising: a tag mapping configuration circuit configured to configure, in response to a tag mapping update request, the tag mapping storage circuit to indicate a new set of mapping information indicating that each value of the at least one of the guard tag and the address tag is associated with a different remapped tag value; An apparatus according to any one of claims 1 to 9.

11. the apparatus comprises a tag mapping setting circuit configured to, in response to a tag mapping update request specifying one or more excluded tag values ​​to be excluded from selection as remapped tag values, set the tag mapping storage circuit to indicate a new set of mapping information indicating that each value of the one of the guard tag and the address tag is associated with a remapped tag value other than the one or more excluded tag values. An apparatus according to any one of claims 1 to 10.

12. the apparatus includes a tag mapping configuration circuit configured to configure the tag mapping storage circuit to update tag mappings other than the one or more existing tag mappings in response to a tag mapping update request specifying one or more existing tag mappings to be excluded from the update. An apparatus according to any one of claims 1 to 11.

13. The error response action is: placing an indication in a status register that said tag check detected a mismatch; logging the entry in an error report; Signaling a fault; and denying access to the memory location specified by the target address; The device according to any one of claims 1 to 12, comprising one of:

14. 1. A method comprising: The tag check circuit responds to the target address by identifying a guard tag stored in the memory system associated with a block of one or more memory locations, the block including the target memory location identified by the target address; performing a tag check based on the guard tag and an address tag associated with the target address; performing an error response action in response to detecting a mismatch in the tag check; Including, the method includes remapping, by the tag check circuitry, at least one of the guard tag and the address tag based on mapping information indicating a mapping between guard tag values ​​and corresponding address tag values ​​to generate a remapped tag for use in the tag check; method.

15. A computer program that causes a host data processing device to perform processing so as to provide an instruction execution environment, tag checking program logic responsive to the target address, identifying a guard tag stored in the memory system associated with a block of one or more memory locations, the block including the target memory location identified by the target address; performing a tag check based on the guard tag and an address tag associated with the target address; performing an error response action in response to detecting a mismatch in the tag check; tag checking program logic; tag mapping maintenance program logic that maintains mapping information indicating a mapping between guard tag values ​​and corresponding address tag values; Equipped with the tag checking program logic is configured to remap at least one of the guard tag and the address tag based on the mapping information maintained by the tag mapping maintenance program logic to generate a remapped tag for use in the tag checking. Computer program.

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