Ruthenium carbide for capacitor mold patterning of DRAM.

Abstract

A method of forming an electronic device and a film stack including depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and a patterned photoresist are formed, and the pattern of the patterned photoresist is transferred to the ruthenium carbide hard mask. A film stack including the ruthenium carbide hard mask on the capacitor mold is also described.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE

[0001] Embodiments of the present disclosure relate generally to integrated circuit manufacturing, and more particularly to film stacks and methods of forming film stacks for electronic devices using ruthenium carbide hard masks. [Background technology]

[0002]

[0002] Reliable fabrication of submicron features is one of the key requirements for very large scale integration (VLSI) and ultra-large scale integration (ULSI) of semiconductor devices. However, with the continued scaling of circuit technology, the size and pitch dimensions of circuit features, such as interconnects, place increasing demands on processing power. Various semiconductor components (interconnects, vias, capacitors, transistors, etc.) require precise placement of high aspect ratio features. Reliable formation of these components is essential for further improvements in devices and integration levels.

[0003]

[0003] Additionally, the electronic device and semiconductor industries continue to strive for higher production yields while improving the uniformity of layers deposited on substrates having ever-increasing surface areas. These same factors, combined with new materials, also result in higher integration of circuits per unit area on the substrate.

[0004] During the formation of many electronic devices, hard masks are used to protect portions of a substrate from removal. Hard masks are commonly used in patterning processes. Once patterning is complete, the hard mask is often removed, leaving behind the protected portions of the substrate. Removal of the hard mask material can be performed separately from other etching processes or can be performed in conjunction with other etching steps. The ability to remove hard mask material without affecting other surface features (also known as etch selectivity) is a useful feature.

[0005]

[0005] The development of hardmask materials with high etch selectivity is critical for patterning new generations of NAND and DRAM devices. For devices at each technology node, capacitor mold hardmask selectivity must be improved by 30% over previous nodes. Currently, boron-doped silicon is used for patterning DRAM capacitor molds for N to N+2 nodes.

[0006]

[0006] As proposed for the N+2 node, the dopant concentration is dominated by boron, and therefore, increasing the boron dopant concentration may not continue to sufficiently improve hardmask selectivity.

[0007]

[0007] Therefore, there is a continuing need in the art for capacitor mold hard masks with improved selectivity. Summary of the Invention

[0008] One or more embodiments of the present disclosure are directed to a method that includes depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate, forming a hard mask oxide on the ruthenium carbide layer, forming a patterned photoresist on the hard mask oxide, and transferring a pattern from the patterned photoresist to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask.

[0009]

[0009] A further embodiment of the present disclosure is directed to a method including forming a capacitor mold on a substrate. The capacitor mold includes a silicon oxide (SiO) layer and a silicon carbonitride (SiCN) or silicon nitride (SiN) layer on the silicon oxide layer. The silicon oxide (SiO) layer has a thickness ranging from 1 μm to 3 μm, and the SiCN or SiN layer has a thickness of up to 1000 Å. Optionally, one or more amorphous silicon or carbon films are deposited directly on the capacitor mold. A ruthenium carbide hard mask is deposited on the capacitor mold and, if present, on the optional amorphous silicon or carbon film. The ruthenium carbide hard mask contains ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen in the range of 5 atomic % to 15 atomic %. The combined thickness of the optional amorphous silicon or carbon film and the ruthenium carbide hard mask is in the range of 2500 Å to 3500 Å. A hard mask oxide is formed on the ruthenium carbide layer. An antireflective coating, including one or more of a dielectric antireflective coating (DARC) or an underlayer antireflective coating (BARC), is formed on the hard mask oxide. A patterned photoresist is formed on the antireflective coating. The pattern of the photoresist is transferred to the antireflective coating, hard mask oxide, and ruthenium carbide hard mask by exposing the substrate to an etchant plasma containing oxygen, chlorine, and carbonyl sulfide to form a patterned hard mask oxide, a patterned ruthenium carbide hard mask, and remove the antireflective coating. The chlorine content is in the range of 5% to 15% of the oxygen content on a molar basis, and the carbonyl sulfide content is in the range of 5% to 10% of the oxygen content on a molar basis. The remaining photoresist and antireflective coating are removed to leave a patterned hard mask oxide and a patterned ruthenium carbide hard mask. Optionally, the pattern of the patterned hard mask oxide and patterned ruthenium carbide hard mask is transferred to an optional amorphous silicon or carbon film.

[0010]

[0010] A further embodiment of the present disclosure is directed to a film stack comprising a capacitor mold, a ruthenium carbide hard mask on the capacitor mold, a hard mask oxide on the ruthenium carbide hard mask, and a patterned photoresist on the hard mask oxide.

[0011]

[0011] In order that the above-described features of the present disclosure may be understood in detail, the above-summarized disclosure will be more particularly described by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 illustrates a plasma process chamber for use with embodiments of the present disclosure. [Figure 2] 1A-D are process flow diagrams illustrating methods according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0013]

[0014] To facilitate understanding, wherever possible, the same reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0014]

[0015] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0015]

[0016] As used herein and in the appended claims, the term "substrate" refers to a surface, or a portion of a surface, upon which a process acts. Also, unless the context clearly indicates otherwise, those skilled in the art will understand that a reference to a substrate may refer to only a portion of a substrate. Furthermore, a reference to deposition on a substrate may refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0016]

[0017] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing may be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates.

[0017]

[0018] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates direct contact between elements, with no intervening elements.

[0018]

[0019] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0019]

[0020] Some embodiments of the present disclosure advantageously provide new hardmask materials with improved selectivity to boron-doped silicon. In some embodiments, ruthenium carbide films are used as hardmasks that are selective to adjacent hardmask oxides and / or capacitor mold components. Some embodiments provide ruthenium carbide hardmasks that can be ashed or etched from the substrate surface.

[0020]

[0021] 1 is a schematic diagram of an exemplary substrate processing system 132 that can be used for ruthenium carbide deposition or other processes in accordance with embodiments described herein. Examples of suitable processing chambers and tools include, but are not limited to, PRODUCER™ systems, such as the CENTURA™ system, which can use the DxZ™ process chamber, the PRECISION5000™ system, the PRODUCER SE™ process chamber, and the PRODUCER GT™ process chamber, all commercially available from Applied Materials, Inc. of Santa Clara, Calif. The processes described herein can also be performed on other substrate processing systems, including those from other manufacturers.

[0021]

[0022] The substrate processing system 132 shown in FIG. 1 includes a process chamber 100 coupled to a gas panel 130 and a controller 110. The process chamber 100 generally includes a top 124, side walls 101, and a bottom wall 122 that define an interior processing region 126. The interior processing region 126 of the chamber 100 is provided with a support pedestal 150. The pedestal 150 is supported by a stem 160 or pedestal support, which may typically be made of aluminum, ceramic, or other suitable materials. The pedestal 150 can be moved vertically within the chamber 100 using a displacement mechanism (not shown) or rotated about a central axis of the stem 160 using a suitable rotation mechanism (not shown).

[0022]

[0023] The illustrated pedestal 150 includes an embedded heating element 170 suitable for controlling the temperature of a substrate 190 supported on a surface 192 of the pedestal 150. The pedestal 150 can be resistively heated by applying an electric current from a power supply 106 to the heater element 170. The heater element 170 can be made of nickel-chromium wire enclosed in a nickel-iron-chromium alloy (e.g., INCOLOY®) sheathed tube. The current supplied by the power supply 106 is regulated by a controller 110 to control the heat generated by the heater element 170, thereby maintaining the substrate 190 and pedestal 150 at a substantially constant temperature during film deposition. The supplied electric current can be adjusted to selectively control the temperature of the pedestal 150 between about 100° C. and about 700° C.

[0023]

[0024] A temperature sensor 172, such as a thermocouple, may be embedded in the support pedestal 150 to monitor the temperature of the pedestal 150 in a conventional manner. The measured temperature is used by the controller 110 to control the power supplied to the heating element 170 to maintain the substrate at a desired temperature.

[0024]

[0025] A vacuum pump 102 is coupled to a port formed in the bottom of the chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure within the process chamber 100. The vacuum pump 102 also evacuates post-process gases and by-products from the chamber 100.

[0025]

[0026] The processing system 132 may further include additional equipment for controlling the chamber pressure, such as valves (e.g., throttle valves and isolation valves) positioned between the process chamber 100 and the vacuum pump 102 to control the chamber pressure.

[0026]

[0027] A showerhead 120 having a plurality of apertures 128 is positioned above the substrate support pedestal 150 at the top of the process chamber 100. The apertures 128 in the showerhead 120 are used to introduce process gases into the chamber 100. The apertures 128 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different process requirements. The showerhead 120 is connected to a gas panel 130 that can supply various gases to the interior processing region 126 during processing. A plasma is formed from the process gas mixture exiting the showerhead 120, facilitating thermal decomposition of the process gases, resulting in the deposition of material on the surface 191 of the substrate 190.

[0027]

[0028] The gas panel 130 can also be used to control and supply various vaporized liquid precursors. Although not shown, liquid precursors from a liquid precursor supply can be vaporized, for example, by a liquid injection vaporizer, and delivered to the process chamber 100 in the presence of a carrier gas. The carrier gas is typically an inert gas, such as nitrogen, or a noble gas, such as argon or helium. Alternatively, liquid precursors can be vaporized from ampoules by thermal and / or vacuum vaporization processes.

[0028]

[0029] The showerhead 120 and the substrate support pedestal 150 may form a pair of spaced-apart electrodes within the interior processing region 126. One or more RF power sources 140 supply a bias potential to the showerhead 120 through a matching network 138 to facilitate the generation of a plasma between the showerhead 120 and the pedestal 150. Alternatively, the RF power source 140 and the matching network 138 may be coupled to the showerhead 120, the substrate pedestal 150, or both the showerhead 120 and the substrate pedestal 150, or may be coupled to an antenna (not shown) located outside the chamber 100. In one embodiment, the RF power source 140 may provide from about 50 watts to about 10,000 watts at a frequency from about 50 kHz to about 100 MHz. In another embodiment, the RF power source 140 may provide from about 500 watts to about 1,800 watts at a frequency from about 50 kHz to about 13.6 MHz.

[0029]

[0030] The controller 110 includes a central processing unit (CPU) 112, memory 116, and support circuits 114 used to control process sequences and regulate gas flow from the gas panel 130. The CPU 112 may be any type of general-purpose computer processor that may be used in an industrial environment. Software routines may be stored in memory 116, such as random access memory, read-only memory, a floppy disk, or hard disk drive, or other form of digital storage. The support circuits 114 are conventionally coupled to the CPU 112 and may include cache, clock circuits, input / output systems, power supplies, etc. Bidirectional communication between the controller 110 and the various components of the processing system 132 is handled through a number of signal cables collectively referred to as a signal bus 118, such as those shown in FIG. 1 .

[0030]

[0031] 2A-2D, which illustrate an exemplary process for forming an electronic device using schematic cross-sectional views of the electronic device. The shading shown in the figures is used to illustrate different components and should not be considered to represent any particular material of construction unless specified.

[0031]

[0032] FIG. 2A illustrates an electronic device 200 having a capacitor mold 210 formed on a substrate 205. In some embodiments, the capacitor mold 210 comprises one or more of silicon oxide (SiO), silicon carbide (SiC), or silicon carbonitride (SiCN). As used herein and in the appended claims, unless otherwise specified, chemical formulas merely represent the elemental identity of a film and are not intended to be stoichiometric. For example, a SiO film contains silicon atoms and oxygen atoms. A typical silicon oxide film contains primarily silicon dioxide (SiO), which implies a specific stoichiometric relationship. In some embodiments, the elemental formula of a layer means that the layer contains, on an atomic basis, about 95% or more, 98% or more, 99% or more, or 99.5% or more of the recited element. Those skilled in the art will recognize that interlayer diffusion of atoms can unintentionally occur and affect the overall composition of the recited layer. Thus, for example, in a silicon oxide (SiO) layer, silicon atoms and oxygen atoms together account for 95% or more, 98% or more, 99% or more, or 99.5% or more of the total atoms in the layer, allowing for small amounts of contaminating atoms and interlayer diffused atoms. In other words, the layer "consists essentially of" the listed elements. "Consists essentially of" means that the listed elements account for 95% or more, 98% or more, 99% or more, or 99.5% or more on an atomic basis. The term "consists essentially of" can apply to any of the individual layers described herein and is not limited to the example of silicon oxide.

[0032]

[0033] In some embodiments, the capacitor mold 210 includes a silicon oxide (SiO) layer 212 and a second layer 214 including one or more of a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer. In some embodiments, the silicon oxide layer 212 has a thickness in the range of 0.5 μm to 5 μm, or in the range of 1 μm to 3 μm. In some embodiments, the silicon oxide layer 212 has a thickness of up to 3.5 μm.

[0033]

[0034] In some embodiments, second layer 214 comprises a silicon carbonitride (SiCN) layer. In some embodiments, second layer 214 comprises a silicon nitride (SiN) layer. Second layer 214, or the SiCN layer, or the SiN layer, has a thickness of up to 10,000 Å, or 5,000 Å, or 1,000 Å. In some embodiments, second layer 214 has a thickness in the range of 100 Å to 1,000 Å, or in the range of 500 Å to 900 Å.

[0034]

[0035] The silicon oxide layer 212 and the second layer 214 may be formed by any suitable technique known to those skilled in the art. For example, the layers may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or physical vapor deposition (PVD).

[0035]

[0036] In some embodiments, the substrate 205 and / or the capacitor mold 210 have a substantially planar surface. Alternatively, in some embodiments, the substrate 205 and / or the capacitor mold 210 have a surface with patterned structures, trenches, holes, or vias formed therein. While the substrate 205 is illustrated singly, those skilled in the art will understand that the substrate may include one or more layers of material used in forming semiconductor devices, such as metal contacts, trench isolation, gates, bit lines, or any other interconnect feature. The substrate 205 may comprise one or more metal layers, one or more dielectric materials, semiconductor materials, and combinations thereof used to fabricate semiconductor devices. For example, the substrate 205 may include an oxide material, a nitride material, a polysilicon material, etc., depending on the application. In one embodiment where a memory application is desired, the substrate 205 may include a silicon substrate material, an oxide material, and a nitride material, with or without polysilicon sandwiched therebetween.

[0036]

[0037] In some embodiments, substrate 205 comprises multiple alternating oxide and nitride materials (i.e., oxide-nitride-oxide (ONO)) deposited on a surface of a substrate (not shown). In various embodiments, substrate 205 may comprise multiple alternating oxide and nitride materials, one or more oxide or nitride materials, polysilicon or amorphous silicon materials, oxide alternating with amorphous silicon, oxide alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, or undoped amorphous silicon alternating with doped amorphous silicon. Substrate 205 may be any substrate or material surface on which film processing is performed. For example, the substrate 205 may be a material such as crystalline silicon, silicon oxide, silicon oxynitride, silicon nitride, strained silicon, silicon germanium, tungsten, titanium nitride, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, low-k dielectrics, and combinations thereof.

[0037]

[0038] 2B illustrates the electronic device 220 after forming an optional hard mask underlayer 222 on the capacitor mold 210. In some embodiments, the hard mask underlayer 222 comprises one or more of an amorphous silicon (a-Si) film or a carbon (C) film. In some embodiments, the hard mask underlayer 222 comprises an amorphous silicon film. In some embodiments, the hard mask underlayer 222 comprises a carbon film. In some embodiments, the hard mask underlayer 222 is formed directly on the capacitor mold 210 without an intervening layer.

[0038]

[0039] Optional seed layer 224 is shown formed on hard mask underlayer 222. In some embodiments, optional seed layer 224 is formed directly on hard mask underlayer 222. In some embodiments, optional seed layer 224 is formed directly on capacitor mold 210, and hard mask underlayer 222 is omitted. In one or more embodiments, optional seed layer 224 comprises boron. In some embodiments, optional seed layer 224 has a thickness up to 100 Å, or in a range of 10 Å to 100 Å, or in a range of 20 Å to 60 Å.

[0039]

[0040] A ruthenium carbide hard mask 226 is formed on the capacitor mold 210. In the illustrated embodiment, the ruthenium carbide hard mask 226 is formed directly on the optional seed layer 224 on the hard mask underlayer 222. In some embodiments, the optional hard mask underlayer 222 and optional seed layer 224 are omitted, and the ruthenium carbide hard mask 226 is formed directly on the capacitor mold 210. In some embodiments, the hard mask underlayer 222 is omitted, and the ruthenium carbide hard mask 226 is formed directly on the optional seed layer 224 that was formed on the capacitor mold 210.

[0040]

[0041] The ruthenium carbide hard mask 226 may be an amorphous, semi-crystalline, or crystalline material. The hard mask may also be referred to as a ruthenium-doped carbon film. However, those skilled in the art will recognize that the term ruthenium-doped carbon film is interchangeable with ruthenium carbide film and may depend on the level of crystallinity of the material.

[0041]

[0042] The ruthenium carbide hard mask 226 of some embodiments has a ruthenium composition in the range of 20 atomic % to 45 atomic % ruthenium. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes ruthenium in the range of greater than 0 atomic % to 50 atomic %, 5 atomic % to 50 atomic %, 10 atomic % to 45 atomic %, 20 atomic % to 45 atomic %, 25 atomic % to 40 atomic % ruthenium, or 30 atomic % to 35 atomic % ruthenium.

[0042]

[0043] In some embodiments, the ruthenium carbide hard mask 226 has a hydrogen composition in the range of 2 atomic % to 20 atomic % hydrogen. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes hydrogen in the range of 5 atomic % to 15 atomic % or hydrogen in the range of 8 atomic % to 12 atomic %. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes no more than 15 atomic % hydrogen, no more than 10 atomic % hydrogen, or no more than 5 atomic % hydrogen.

[0043]

[0044] In some embodiments, the ruthenium carbide hard mask 226 comprises ruthenium in the range of greater than 0 atomic % to 50 atomic % and hydrogen up to 15 atomic % with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask 226 comprises ruthenium in the range of 10 atomic % to 45 atomic % and hydrogen up to 10 atomic % with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask 226 comprises ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen up to 10 atomic % with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask 226 comprises ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen up to 15 ...%, up to 10 atomic %, or up to 5 atomic % with the remainder being carbon.

[0044]

[0045] In some embodiments, the ruthenium carbide hard mask 226 has a thickness in the range of 500 Å to 4000 Å, or in the range of 1000 Å to 4000 Å, or in the range of 1500 Å to 3500 Å. In some embodiments, the thickness of the ruthenium carbide hard mask 226 is in the range of 2500 Å to 3500 Å. In some embodiments, the optional hard mask underlayer 222 has a thickness in the range of 100 Å to 500 Å, and the ruthenium carbide hard mask 226 has a thickness in the range of 2500 Å to 3400 Å. In some embodiments, the combination of the optional hard mask underlayer 222 and the ruthenium carbide hard mask 226 has a thickness in the range of 2500 Å to 3500 Å. In some embodiments, the combination of the optional hard mask underlayer 222, optional seed layer 224, and ruthenium carbide hard mask 226 has a thickness in the range of 500 Å to 4000 Å.

[0045]

[0046] In the illustrated embodiment, a hardmask oxide 228 is formed on the ruthenium carbide hardmask 226. The hardmask oxide 228 may be any suitable material known to those skilled in the art that has etch selectivity to the ruthenium carbide hardmask 226. The hardmask oxide 228 in some embodiments has a thickness in the range of 500 Å to 1500 Å.

[0046]

[0047] In the illustrated embodiment, an advanced patterning film (APF) 230 is formed on the hard mask oxide 228. In some embodiments, the advanced patterning film 230 comprises a carbon film or a diamond-like carbon film. In some embodiments, the advanced patterning film 230 has a thickness ranging from 500 Å to 1500 Å. In some embodiments, the advanced patterning film 230 has a thickness of greater than 0 Å to less than or equal to 1500 Å, or 1000 Å.

[0047]

[0048] A dielectric antireflective coating (DARC) 232 is formed on the advanced patterning film 230. The DARC 232 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the dielectric antireflective coating 232 comprises silicon oxynitride (SiON). In some embodiments, the DARC 232 has a thickness ranging from 250 Å to 500 Å. In some embodiments, the DARC 232 has a thickness of greater than 0 Å to less than or equal to 500 Å.

[0048]

[0049] A bottom antireflective coating (BARC) 234 is formed on the DARC 232. The BARC 234 can be formed by any suitable technique known to those skilled in the art. In some embodiments, the BARC 234 has a thickness in the range of 100 Å to 500 Å.

[0049]

[0050] Photoresist 236 is formed on BARC 234. Photoresist 236 can be deposited by any suitable technique known to those skilled in the art. Photoresist 236 is patterned by any suitable technique (e.g., lithography) to form a patterned photoresist and expose top surfaces 235 of BARC 234. In some embodiments, photoresist 236 is an energy-sensitive resist material and can be patterned by exposing the energy-sensitive resist material to UV radiation through a patterning device, such as a mask (not shown), and then developing the energy-sensitive resist material with a suitable developer. After the energy-sensitive resist material is developed, a defined pattern of through openings 237 is present in photoresist 236.

[0050]

[0051] 2C illustrates electronic device 220 after the pattern in photoresist 236 has been transferred to antireflective coatings 232, 234, advanced patterning film 230, hardmask oxide 228, and ruthenium carbide hardmask 226. In some embodiments, transferring the pattern in photoresist 236 removes photoresist 236, BARC 234, DARC 232, and advanced patterning film 230, leaving behind patterned hardmask oxide 248 and patterned ruthenium carbide hardmask 246. In the illustrated embodiment, the pattern transfer also forms patterned hardmask underlayer 242 and patterned seed layer 244. In some embodiments, optional hardmask underlayer 222 and optional seed layer 224 are present and are not patterned with ruthenium carbide hardmask 226.

[0051]

[0052] In some embodiments, the pattern transfer is performed by exposing the substrate to an etchant plasma using the photoresist 236 as a mask. In some embodiments, the etchant plasma includes an oxygen (O2) content and a chlorine (Cl2) content. In some embodiments, the chlorine content of the etchant plasma ranges from 5% to 15% of the oxygen content on a molar basis. In some embodiments, the chlorine content of the etchant plasma is 15% or less, 10% or less, or 5% or less of the oxygen content on a molar basis.

[0052]

[0053] In some embodiments, the etchant plasma comprises carbonyl sulfide (COS), and the COS content in some embodiments ranges from 1% to 10% of the oxygen content on a molar basis.

[0053]

[0054] In some embodiments, the etchant plasma includes oxygen, chlorine, and carbonyl sulfide. The composition of the etchant plasma in some embodiments is 1% to 10% COS, 5% to 15% Cl, based on the amount of O on a molar basis.

[0054]

[0055] In some embodiments, the photoresist 236, the antireflective coatings 232, 234, and the advanced patterning film 230 are removed simultaneously with the pattern transfer. In some embodiments, one or more of the photoresist 236, the antireflective coatings 232, 234, or the advanced patterning film 230 remain after the pattern transfer and are removed in a separate process.

[0055]

[0056] 2D illustrates an embodiment of electronic device 240 after transferring a pattern to capacitor mold 210 to form electronic device 260 having patterned capacitor mold 262. Patterned capacitor mold 262 in the illustrated embodiment includes patterned silicon oxide layer 264 and patterned second layer 266.

[0056]

[0057] 2D illustrates the electronic device 240 after removal of the patterned hardmask oxide 248, the patterned ruthenium carbide hardmask 246, the patterned optional seed layer 244, and the patterned optional hardmask underlayer 242. The patterned hardmask oxide 248, the patterned ruthenium carbide hardmask 246, the patterned optional seed layer 244, and the patterned optional hardmask underlayer 242 can be removed simultaneously with the pattern transfer to the capacitor mold 210 or in one or more separate processes. In some embodiments, the patterned ruthenium carbide hardmask 246, the patterned optional seed layer 244, and the patterned optional hardmask underlayer 242 are removed using a plasma comprising oxygen and chlorine.

[0057]

[0058] Throughout this specification, references to "one embodiment," "a particular embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0058]

[0059] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate; forming a hard mask oxide on the ruthenium carbide layer; forming a patterned photoresist on the hard mask oxide; transferring a pattern of the patterned photoresist to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask; A method comprising:

2. 10. The method of claim 1, wherein the ruthenium carbide hard mask comprises ruthenium in the range of 20 atomic % to 45 atomic %.

3. 3. The method of claim 2, wherein the ruthenium carbide hard mask comprises 15 atomic % or less hydrogen.

4. 10. The method of claim 1, further comprising transferring a pattern of the patterned ruthenium carbide hard mask to the capacitor mold.

5. 5. The method of claim 4, further comprising etching the patterned ruthenium carbide hard mask from the capacitor mold.

6. 10. The method of claim 1, wherein transferring the pattern of the patterned photoresist to the ruthenium carbide hard mask comprises exposing the substrate to an etchant plasma comprising oxygen and chlorine.

7. 7. The method of claim 6, wherein the chlorine content is no more than 15% of the oxygen content on a molar basis.

8. The method of claim 7 , wherein the etchant plasma further comprises carbonyl sulfide.

9. 9. The method of claim 8, wherein the carbonyl sulfide content is less than or equal to 10% of the oxygen content on a molar basis.

10. 10. The method of claim 1, wherein the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

11. 10. The method of claim 1, further comprising forming one or more of a carbon film or an amorphous silicon film on the capacitor mold between the capacitor mold and the ruthenium carbide hard mask.

12. 12. The method of claim 11, wherein the combination of the carbon film, the amorphous silicon film, and the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

13. The method of claim 1 , wherein the capacitor mold comprises a silicon oxide (SiO 2 ) layer.

14. 14. The method of claim 13, wherein the capacitor mold further comprises a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide (SiO) layer.

15. 15. The method of claim 14, wherein the silicon oxide (SiO) layer has a thickness of up to 3 μm and the SiCN layer has a thickness of up to 1000 Å.

16. forming a capacitor mold on a substrate, the capacitor mold including a silicon oxide (SiO) layer and a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide (SiO) layer, the silicon oxide (SiO) layer having a thickness in the range of 1 μm to 3 μm, and the SiCN layer or the SiN layer having a thickness of up to 1000 Å; Optionally, depositing one or more of an amorphous silicon film or a carbon film directly onto the capacitor mold; depositing a ruthenium carbide hard mask on the capacitor mold and, if present, on the optional amorphous silicon or carbon film, the ruthenium carbide hard mask comprising ruthenium in the range of 20 atomic % to 45 atomic % and hydrogen in the range of 5 atomic % to 15 atomic %, and a combined thickness of the optional amorphous silicon or carbon film and the ruthenium carbide hard mask in the range of 2500 Å to 3500 Å; forming a hard mask oxide on the ruthenium carbide layer; forming an antireflective coating over the hard mask oxide, the antireflective coating comprising one or more of a dielectric antireflective coating (DARC) or a bottom antireflective coating (BARC); forming a patterned photoresist on the antireflective coating; transferring the pattern of the photoresist to the antireflective coating, the hardmask oxide, and the ruthenium carbide hardmask by exposing the substrate to an etchant plasma comprising oxygen, chlorine, and carbonyl sulfide to form a patterned hardmask oxide, a patterned ruthenium carbide hardmask, and to remove the antireflective coating, wherein the chlorine content is in the range of 5% to 15% of the oxygen content on a molar basis, and the carbonyl sulfide content is in the range of 5% to 10% of the oxygen content on a molar basis; removing the remaining photoresist and antireflective coating to leave a patterned hardmask oxide and a patterned ruthenium carbide hardmask; Optionally, transferring the pattern of the patterned hard mask oxide and the patterned ruthenium carbide hard mask to the optional amorphous silicon film or carbon film. A method comprising:

17. a capacitor mold; a ruthenium carbide hard mask on the capacitor mold; a hard mask oxide on the ruthenium carbide hard mask; a patterned photoresist on the hard mask oxide; A membrane stack comprising:

18. 20. The film stack of claim 17, wherein the ruthenium carbide hard mask comprises ruthenium in the range of 20 atomic % to 45 atomic % and up to 15 atomic % hydrogen, with the remainder being carbon.

19. 20. The film stack of claim 17, wherein the ruthenium carbide hard mask has a thickness in the range of 500 Å to 4000 Å.

20. 20. The film stack of claim 17, further comprising one or more of a carbon film or an amorphous silicon film on the capacitor mold and between the capacitor mold and the ruthenium carbide hard mask, wherein the combination of the carbon film, the amorphous silicon film, and the ruthenium carbide hard mask has a thickness in a range from 500 Å to 4000 Å.

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