Printed circuit board

Abstract

To provide a printed circuit board including a conductor pattern in which delamination hardly occurs when etching a seed metal layer for plating, and such a conductor pattern includes a plurality of fine patterns.SOLUTION: And a conductor pattern including a pattern metal layer disposed on the seed metal layer, wherein the seed metal layer includes a first metal layer including a first metal and a second metal layer disposed on the first metal layer, connected to the pattern metal layer, and including a second metal, and a thickness of the first metal layer is greater than a thickness of the second metal layer, the first metal may be any one selected from the group consisting of aluminum (Al), iridium (Ir), molybdenum (Mo), tungsten (W), cobalt (Co), nickel (Ni), and ruthenium (Ru).SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to printed circuit boards. [Background technology]

[0002] Demand for multi-chip packages, which mount multiple chips such as memory, CPUs, and GPUs on a substrate, is increasing. In particular, demand for package substrates for AI servers is skyrocketing. In response to this, the number of chip input / output ports is increasing, requiring high wiring density on substrates. Meanwhile, in order to form fine patterns, not only plating technology but also seed metal layer formation and removal technology is becoming increasingly important. Plating and patterning fine patterns on organic insulating layers is particularly challenging. For example, copper metal can generally be patterned through a wet etching process. To achieve a thick electroplated film, a sufficiently thick plating seed layer is required for stable plating. However, the thicker the seed layer, the longer the wet etching time required to etch and remove it. Increasing the seed layer etching time can result in undercutting as the seed layer is etched first, potentially causing delamination between the fine pattern and the organic insulating layer. Summary of the Invention [Problem to be solved by the invention]

[0003] Among the various objects of the present disclosure is to provide a printed circuit board including a conductor pattern that is less susceptible to delamination when etching a plating seed metal layer.

[0004] Another of the various objects of the present disclosure is to provide a printed circuit board in which such conductor pattern includes a plurality of fine patterns. [Means for solving the problem]

[0005] One of the various solutions proposed through the present disclosure is to form multiple metal layers in a conductor pattern including a seed metal layer and a pattern metal layer using a seed metal layer, and to form one of these metal layers thicker than the other metal layers using a metal with high electrical conductivity that is different from the metal mainly contained in the pattern metal layer.

[0006] For example, a printed circuit board according to one embodiment includes a conductor pattern including a seed metal layer and a patterned metal layer disposed on the seed metal layer, the seed metal layer including a first metal layer including a first metal, and a second metal layer disposed on the first metal layer and connected to the patterned metal layer, the first metal layer being thicker than the second metal layer, and the first metal may be any one selected from the group consisting of aluminum (Al), iridium (Ir), molybdenum (Mo), tungsten (W), cobalt (Co), nickel (Ni), and ruthenium (Ru).

[0007] For example, one example of a printed circuit board includes an insulating substrate, a seed metal layer disposed on the insulating substrate, and a conductor pattern including a patterned metal layer disposed on the seed metal layer, and the seed metal layer may have a layered structure in which a titanium (Ti) layer, a molybdenum (Mo) layer, and a copper (Cu) layer are stacked in this order. [Effects of the Invention]

[0008] Among the various advantages of the present disclosure, one advantage is that it is possible to provide a printed circuit board including a conductor pattern that is less likely to delaminate when etching a plating seed metal layer.

[0009] Another advantage of the present disclosure is that it provides a printed circuit board in which such a conductor pattern includes a plurality of fine patterns. [Brief explanation of the drawings]

[0010] [Figure 1]FIG. 1 is a block diagram illustrating an example of an electronic device system. [Figure 2] FIG. 1 is a perspective view schematically illustrating an example of an electronic device. [Figure 3] FIG. 1 is a cross-sectional view schematically illustrating an example of a printed circuit board. [Figure 4] 4 is a process diagram schematically illustrating an example of manufacturing the printed circuit board of FIG. 3. [Figure 5] FIG. 10 is a cross-sectional view schematically showing another example of a printed circuit board. [Figure 6] 6 is a process diagram schematically illustrating an example of manufacturing the printed circuit board of FIG. 5. FIG. [Figure 7] FIG. 1 is a cross-sectional view schematically illustrating an example of a semiconductor package. [Figure 8] FIG. 10 is a cross-sectional view schematically showing another example of a semiconductor package. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present disclosure will be described below with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be scaled (or highlighted or simplified) for clarity.

[0012] electronic equipment FIG. 1 is a block diagram illustrating an example of an electronic device system.

[0013] Referring to the drawing, an electronic device 1000 houses a main board 1010. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the main board 1010. These components are also coupled to other electronic components (described later) to form various signal lines 1090.

[0014] The chip-related components 1020 include, but are not limited to, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory; application processor chips such as central processors (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, encryption processors, microprocessors, and microcontrollers; and logic chips such as analog-to-digital converters and ASICs (application-specific ICs). Furthermore, these chip-related components 1020 can be combined with one another. The chip-related components 1020 can also be in the form of a package including the above-mentioned chips and electronic components.

[0015] The network-related components 1030 may include, but are not limited to, Wi-Fi (e.g., IEEE 802.11 family), WiMAX (e.g., IEEE 802.16 family), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated as such, as well as any of numerous other wireless or wired standards and protocols. The network-related components 1030 may also be combined with the chip-related components 1020.

[0016] The other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-firing ceramics (LTCC), electro-magnetic interference (EMI) filters, multi-layer ceramic capacitors (MLCC), etc. However, the other components 1040 may include, but are not limited to, passive elements in the form of chip components used for various other applications. The other components 1040 may also be combined with the chip-related components 1020 and / or the network-related components 1030.

[0017] Depending on the type of electronic device 1000, the electronic device 1000 may include other electronic components that may or may not be physically and / or electrically connected to the main board 1010. Examples of other electronic components include, but are not limited to, a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. Other electronic components may also include, but are not limited to, an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD), a digital versatile disk (DVD), and the like. In addition, other electronic components used for various purposes may also be included depending on the type of electronic device 1000.

[0018] The electronic device 1000 may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the electronic device 1000 is not limited to these, and may be any other electronic device that processes data.

[0019] FIG. 2 is a perspective view schematically illustrating an example of an electronic device.

[0020] Referring to the drawing, the electronic device may be, for example, a smartphone 1100. The smartphone 1100 houses a motherboard 1110, to which various components 1120 are physically and / or electrically connected. Furthermore, other components, such as a camera module 1130 and / or a speaker 1140, which may or may not be physically and / or electrically connected to the motherboard 1110, are housed inside the smartphone 1100. Some of the components 1120 may be the above-described chip-related components, such as, but not limited to, a component package 1121. The component package 1121 may be in the form of a printed circuit board on which electronic components, including active and / or passive components, are mounted on a surface. Alternatively, the component package 1121 may be in the form of a printed circuit board in which active and / or passive components are embedded. Meanwhile, the electronic device is not necessarily limited to the smartphone 1100, but may be other electronic devices as described above.

[0021] printed circuit board FIG. 3 is a cross-sectional view that schematically illustrates an example of a printed circuit board.

[0022] Referring to the drawing, a printed circuit board 100A according to an example includes an insulating substrate 110 and a plurality of conductor patterns 120A disposed on the insulating substrate 110. Each conductor pattern 120A may include seed metal layers 121, 122, and 123 and a pattern metal layer 124 disposed on the seed metal layers 121, 122, and 123. The seed metal layers 121, 122, and 123 may include a first metal layer 121 including a first metal, a second metal layer 122 including a second metal, and a third metal layer 123 including a third metal. The third metal layer 123, the first metal layer 121, and the second metal layer 122 may be stacked in this order in the thickness direction.

[0023] Meanwhile, the first metal may be different from the metal mainly contained in the patterned metal layer 124 but may have high electrical conductivity. For example, the first metal may have an electrical resistivity of 10×10 -8 The resistivity may be Ω*m or less, and more specifically, may be any one selected from the group consisting of aluminum (Al), iridium (Ir), molybdenum (Mo), tungsten (W), cobalt (Co), nickel (Ni), and ruthenium (Ru). The second metal may be the same as the metal primarily contained in the patterned metal layer 124 and may have a lower resistivity than the first metal. For example, the patterned metal layer 124 may include copper (Cu), and the second metal may be copper (Cu). The third metal may be a metal that has excellent adhesion to the insulating layer and has a higher resistivity than the first metal. For example, the third metal may be any one selected from the group consisting of chromium (Cr), tantalum (Ta), niobium (Nb), and titanium (Ti).

[0024] For example, among the seed metal layers 121, 122, and 123, the second metal layer 122 in contact with the patterned metal layer 124 may contain the same second metal, e.g., copper (Cu), as the metal primarily contained in the patterned metal layer 124, and may be a sputtered thin film formed by a sputtering process. In this case, nucleation on the surface can be facilitated when forming the patterned metal layer 124 using electrolytic plating, e.g., electrolytic copper, thereby facilitating plating. Furthermore, the second metal layer 122 may be formed thinner than the first metal layer 121, e.g., with a thickness of 1000 Å or less, or between 50 Å and 1000 Å. This can prevent undercut and delamination. On the other hand, if the thickness of the second metal layer 122 is less than 50 Å, island growth may occur, potentially resulting in adhesion problems during plating.

[0025] In addition, a first metal layer 121 may be disposed under the second metal layer 122. The first metal layer 121 may be different from the metal mainly contained in the pattern metal layer 124 or the second metal, for example, copper (Cu), but may have a resistivity of 10×10 -8 The first metal layer 121 may include a first metal having high electrical conductivity of Ω*m or less, such as aluminum (Al), iridium (Ir), molybdenum (Mo), tungsten (W), cobalt (Co), nickel (Ni), or ruthenium (Ru). In this case, the first metal layer 121 having high electrical conductivity can compensate for the conductivity of the entire seed layer due to a decrease in the thickness of the second metal layer 122, thereby enabling smoother plating. Meanwhile, the first metal layer 121 may also be a sputtered thin film formed by a sputtering process.

[0026] A third metal layer 123 may be disposed under the first metal layer 121 and may be in contact with at least one surface of the insulating substrate 110. The third metal layer 123 may have excellent adhesion to the insulating layer, a higher resistivity than the first metal, and a lower electrical conductivity than the first metal, such as chromium (Cr), tantalum (Ta), niobium (Nb), or titanium (Ti). The third metal layer 123 may be formed thinner than the first metal layer 121. In this case, adhesion between the insulating substrate 110 and the conductive pattern 120A may be improved. Furthermore, undercut and delamination may be prevented.

[0027] As a non-limiting example, the first metal layer 121 may be a molybdenum (Mo) layer, the second metal layer 122 may be a copper (Cu) layer, and the third metal layer 123 may be a titanium (Ti) layer, thereby allowing the seed metal layers 121, 122, and 123 to have a stacked structure in which a titanium (Ti) layer, a molybdenum (Mo) layer, and a copper (Cu) layer are stacked in this order, but is not limited to this.

[0028] On the other hand, the total conductance of the seed metal layers 121, 122, and 123 is 350×10 -2 Ω -1 In this case, plating may proceed more easily. Meanwhile, the total conductance may be the sum of the conductivities of the first to third metal layers 121, 122, and 123 included in the seed metal layers 121, 122, and 123. In addition, the conductance of each of the first to third metal layers 121, 122, and 123 may be a value obtained by dividing the thickness of each by the resistivity of each.

[0029] Meanwhile, the insulating substrate 110 may include an insulating material. The insulating material may include an organic insulating material and / or an inorganic insulating material. The organic insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide, or a material containing a resin together with an inorganic filler, an organic filler, and / or glass fiber (glass fiber, glass cloth, glass fabric). For example, the organic insulating material may be a non-photosensitive insulating material such as copper clad laminate (CCL), Ajinomoto build-up film (ABF), or prepreg (PPG), but is not limited thereto. Other polymer materials may also be used. The organic insulating material may also be a photosensitive insulating material such as a photoimageable dielectric (PID). The inorganic insulating material may be silicon (Si), glass, ceramic, etc., but is not limited thereto. Other inorganic materials may also be used.

[0030] Meanwhile, the plurality of conductor patterns 120A may be a plurality of adjacent fine patterns, in which the width of each of the fine patterns and the spacing between the fine patterns may be 2 μm or less, or 1 μm or less. For example, the plurality of conductor patterns 120A may be a plurality of fine patterns with a line / space of 2 μm / 2 μm or less, or 1 μm / 1 μm or less. Each aspect ratio of the fine patterns may be 1 or more. Even in this case, the configuration of the seed metal layers 121, 122, and 123 as described above allows for stable realization of the fine patterns. For example, undercut and delamination can be prevented, and plating can be performed smoothly. The number of conductor patterns 120A is not particularly limited. The above-described fine patterns may have a line shape and can be used as traces for signal transmission. Meanwhile, the conductor pattern 120A may further include a pad pattern or a plane pattern in addition to the line pattern, as necessary. The conductor pattern 120A may further include a power pattern and / or a ground pattern in addition to the signal pattern, as necessary.

[0031] FIG. 4 is a process diagram that schematically shows an example of the manufacturing process of the printed circuit board of FIG.

[0032] Referring to the drawing, seed metal layers 121, 122, and 123 are first formed on an insulating substrate 110. The seed metal layers 121, 122, and 123 may be formed, for example, by a sputtering process (e.g., DC sputtering), and a third metal layer 123 serving as a bonding layer, a first metal layer 121 serving as a compensation layer, and a second metal layer 122 serving as a seed layer may be formed in this order. Next, a photoresist mold 150 is formed on the second metal layer 122, and spaces for forming a fine circuit pattern are patterned using an exposure and development process, etc. Next, a patterned metal layer 124 is formed on the second metal layer 122 exposed through the openings in the photoresist mold 150 by electroplating, for example, copper electroplating. Next, the photoresist mold 150 is stripped and removed. Next, unnecessary areas of the second metal layer 122 are removed using wet etching, for example, an etching solution. Next, the first metal layer 121 and the third metal layer 123 in unnecessary regions are removed by dry etching, such as RIE (Reactive Ion Etching). Alternatively, they may be removed simultaneously. Through this process, a printed circuit board 100A according to an example having the above-described technical effects can be manufactured. The rest of the process is substantially the same as that described above, and therefore, redundant description will be omitted.

[0033] The technical effects of the printed circuit board 100A according to one example will be described in more detail below through experiments.

[0034] (Comparative Example) A titanium (Ti) layer and a copper (Cu) layer were deposited on the organic insulating layer using a sputtering process to thicknesses of approximately 500 Å and 2000 Å, respectively, to form a layered seed metal layer. Next, a photoresist mold was patterned on the seed metal layer, and copper (Cu) was electroplated to a thickness of 2 μm or more to form a patterned metal layer containing a fine circuit pattern with a line / space of 2 μm / 2 μm. Meanwhile, copper (Cu) has a specific resistance of 1.72 × 10 -8 Ω*m, and in the case of titanium (Ti), the resistivity is 42×10 -8 Ω*m, the total conductance of the seed metal layer is 1175×10-2 Ω -1 On the other hand, the copper (Cu) electroplating conditions were a copper sulfate aqueous plating solution, and the plating current density per unit area of ​​the substrate was 1 A / (dm 2 The test was performed under the condition of 1 ASD (Ampere per Square Decimator), which corresponds to a 1 μm / sq. decimeter (ASD) measurement. The sensed voltage was approximately 0.3 V. As mentioned above, the total conductance of the seed layer was reasonable, and copper (Cu) electroplating proceeded without any problems. After electroplating was completed, the photoresist mold was stripped and removed, and the seed metal layer was wet-etched to form a fine pattern. For example, using a copper (Cu) etchant, the thickness and width of the copper (Cu) plating layer of the fine pattern were reduced as the seed copper (Cu) layer was removed. In particular, undercutting occurred in the seed copper (Cu) layer during wet etching. Next, the seed titanium (Ti) layer was also removed using an etchant. When the seed titanium (Ti) layer was removed, severe undercutting occurred at the bottom of the fine pattern. When the line / space was 2 μm / 2 μm and the aspect ratio exceeded 1, severe delamination due to undercutting occurred.

[0035] Example 1 To address the issues in the comparative example, the seed metal layer was modified to a seed stacked structure that can mitigate undercut during seed etching. Specifically, a molybdenum (Mo) layer with good conductivity was introduced to reduce the thickness of the seed copper (Cu) layer. Specifically, a titanium (Ti), molybdenum (Mo), and copper (Cu) layer were deposited in this order on an organic insulating layer using a sputtering process to thicknesses of approximately 500 Å, 1500 Å, and 500 Å, respectively, to form a stacked seed metal layer. Next, a photoresist mold was patterned on the seed metal layer, and copper (Cu) was electroplated to a thickness of 2 μm or more to form a patterned metal layer with a fine circuit pattern with a line / space of 2 μm / 2 μm. Meanwhile, the thickness of the copper (Cu) layer was reduced to one-quarter of that of the comparative example, but the resistivity was reduced to 5.28 × 10 -8By adding a 1500Å thick molybdenum (Mo) layer, which is a compensation layer of about Ω*m, the total conductance of the seed metal layer is 587×10 -2 Ω -1 The copper (Cu) electroplating conditions were the same as those in the comparative example. Although the total conductance of the seed metal layer was reduced compared to the comparative example, copper (Cu) electroplating proceeded without any problems. After electroplating was completed, the photoresist mold was stripped and removed, and the seed metal layer was etched to form a fine pattern. For example, a copper (Cu) etchant was used to remove the seed copper (Cu) layer. The etching time was significantly shorter than in the comparative example, and the thickness and width of the copper (Cu) plating layer in the fine pattern were not significantly reduced. The titanium (Ti) layer, which serves as the bonding layer, and the molybdenum (Mo) layer, which serves as the compensation layer, were removed by dry etching rather than wet etching. For example, a gas etchant capable of etching the titanium (Ti) layer and the molybdenum (Mo) layer in one go was used, specifically, RIE. For RIE, a mixture of fluorine-based (CF4, CHF3, SF6, etc.) and chlorine-based (Cl2, BCl3, etc.) gases was used. In addition, argon gas was also used for plasma ion bombardment.In the final fine pattern after dry etching, almost no undercut due to a reduction in the thickness of the seed copper (Cu) layer was observed, and the fine pattern was formed without delamination.

[0036] Example 2 The seed metal layer was changed to confirm whether there would be any problems with electroplating even when the thickness of the seed copper (Cu) layer was further reduced compared to Example 1. That is, a titanium (Ti) layer, a molybdenum (Mo) layer, and a copper (Cu) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 500 Å, 1500 Å, and 300 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 470×10 -2 Ω -1The remaining experiments were carried out in the same way. Despite the reduction in the thickness of the seed copper (Cu) layer, plating proceeded normally, and similarly, in the final fine pattern, almost no undercut due to the reduction in the thickness of the seed copper (Cu) layer was observed, and the fine pattern was also formed without delamination.

[0037] Example 3 The seed metal layer was changed to confirm whether there would be any problems with electroplating even when the thickness of the seed copper (Cu) layer was further reduced compared to Example 2. That is, a titanium (Ti) layer, a molybdenum (Mo) layer, and a copper (Cu) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 500 Å, 1500 Å, and 100 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 354 × 10 -2 Ω -1 The remaining experiments were carried out in the same way. Despite the further reduction in the thickness of the seed copper (Cu) layer, plating proceeded normally, and similarly, in the final fine pattern, almost no undercut due to the reduction in the thickness of the seed copper (Cu) layer was observed, and the fine pattern was also formed without delamination.

[0038] (Reference example 1) In Example 1, the seed metal layer was changed to confirm that there would be no problems with electroplating when the seed copper (Cu) layer was replaced with a seed titanium (Ti) layer. That is, a titanium (Ti) layer, a molybdenum (Mo) layer, and a titanium (Ti) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 500 Å, 1500 Å, and 500 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 308×10 -2 Ω -1 The remaining experiments were carried out in the same way. Copper (Cu) was used as the electroplating material for forming the fine patterns, but using a titanium (Ti) seed layer instead of a copper (Cu) seed layer can be unfavorable for copper (Cu) nucleation, resulting in a lower total conductance. This can lead to plating defects.

[0039] FIG. 5 is a cross-sectional view schematically showing another example of a printed circuit board.

[0040] Referring to the drawings, a printed circuit board 100B according to another example includes an insulating substrate 110 and a plurality of conductor patterns 120B disposed on the insulating substrate 110. Each conductor pattern 120B may include seed metal layers 121 and 122 and a patterned metal layer 124 disposed on the seed metal layers 121 and 122. The seed metal layers 121 and 122 may include a first metal layer 121 including a first metal and a second metal layer 122 including a second metal. The first metal layer 121 and the second metal layer 122 may be stacked in this order in the thickness direction. For example, compared to the conductor pattern 120A of the printed circuit board 100A according to the example, the seed metal layers 121 and 122 of the conductor pattern 120B do not include a third metal layer. Even in this case, the above-described technical effects can be achieved. Other details are substantially the same as those described above, and therefore, redundant description will be omitted.

[0041] FIG. 6 is a process diagram that schematically shows an example of manufacturing the printed circuit board of FIG.

[0042] Referring to the drawing, first, seed metal layers 121 and 122 are formed on an insulating substrate 110. The seed metal layers 121 and 122 may be formed, for example, by a sputtering process (e.g., DC sputtering), with the first metal layer 121 serving as a compensation layer and the second metal layer 122 serving as a seed layer being formed in this order. Next, a photoresist mold 150 is formed on the second metal layer 122, and spaces for forming a fine circuit pattern are patterned using an exposure and development process, etc. Next, a patterned metal layer 124 is formed on the second metal layer 122 exposed through the openings in the photoresist mold 150 by electrolytic plating, for example, copper electroplating. Next, the photoresist mold 150 is stripped and removed. Next, unnecessary regions of the second metal layer 122 are removed by wet etching, for example, using an etchant. Next, unnecessary regions of the first metal layer 121 are removed by dry etching, for example, RIE (reactive ion etching), etc. By this process, a printed circuit board 100B according to another example having the above-described technical effects can be manufactured. The other details are substantially the same as those described above, and therefore, redundant explanations will be omitted.

[0043] The technical effects of the printed circuit board 100B according to another example will be described in more detail below through experiments.

[0044] Example 4 In Example 1, even when the titanium (Ti) bonding layer was removed from the seed metal layer and the seed metal layer was formed only with a molybdenum (Mo) compensation layer and a copper (Cu) seed layer, the seed metal layer was modified to confirm that there were no problems with plating and bonding. That is, a molybdenum (Mo) layer and a copper (Cu) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 1500 Å and 500 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 575×10 -2 Ω -1The remaining parts were subjected to the same experiment. When the titanium (Ti) layer, which is the bonding layer, was omitted, plating proceeded normally and the adhesion of the seed metal layer was reduced, but in the final fine pattern, almost no undercut due to a reduction in the thickness of the seed copper (Cu) layer was observed, and the fine pattern was formed with almost no delamination.

[0045] Example 5 The seed metal layer was changed to confirm whether there would be any problems with electroplating even when the thickness of the seed copper (Cu) layer was further reduced compared to Example 4. That is, a molybdenum (Mo) layer and a copper (Cu) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 1500 Å and 300 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 459 × 10 -2 Ω -1 The remaining experiments were carried out in the same way. When the thickness of the seed copper (Cu) layer was made thinner, plating proceeded normally, and although the adhesion of the seed metal layer decreased, almost no undercut due to the reduced thickness of the seed copper (Cu) layer was observed in the final fine pattern, and the fine pattern was formed with almost no delamination.

[0046] (Reference example 2) In Example 4, the seed metal layer was changed to confirm that there would be no problems with electroplating when the seed copper (Cu) layer was replaced with a seed titanium (Ti) layer. That is, a molybdenum (Mo) layer and a titanium (Ti) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 1500 Å and 500 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 296 × 10 -2 Ω -1 The remaining experiments were carried out in the same way. Copper (Cu) was used as the electroplating material for forming the fine patterns, but using a titanium (Ti) seed layer instead of a copper (Cu) seed layer can be unfavorable for copper (Cu) nucleation, resulting in a lower total conductance. This can lead to plating defects.

[0047] (Reference example 3) In Reference Example 2, the seed metal layer was changed to check whether problems would occur in electroplating if the thickness of the molybdenum (Mo) layer, which is the compensation layer, was increased. That is, a molybdenum (Mo) layer and a titanium (Ti) layer were deposited in this order on the organic insulating layer by a sputtering process to thicknesses of approximately 4000 Å and 500 Å, respectively, to form a seed metal layer with a stacked structure. In this case, the total conductance of the seed metal layer was 769×10 -2 Ω -1 The remaining experiments were carried out in the same way. Copper (Cu) was used as the electroplating material for forming the fine patterns, but using a titanium (Ti) seed layer instead of a copper (Cu) seed layer can be unfavorable for copper (Cu) nucleation. Therefore, plating defects may occur despite a high total conductance.

[0048] FIG. 7 is a cross-sectional view schematically showing an example of a semiconductor package.

[0049] Referring to the drawing, a semiconductor package 500 according to an example embodiment may include a package substrate 200 and first and second semiconductor chips 410 and 420 mounted on the package substrate 200. The package substrate 200 may include a bridge substrate 210 including fine wiring for interconnecting the first and second semiconductor chips 410 and 420. The bridge substrate 210 may include at least one of the printed circuit boards 100A and 100B described above as its internal structure. For example, the bridge substrate 210 may have a wiring structure including one or more insulating layers, one or more wiring layers disposed on or within the one or more insulating layers, and one or more via layers penetrating at least one of the one or more insulating layers. In this case, at least one of the one or more insulating layers may include the insulating substrate described above, and at least one of the one or more wiring layers may include the plurality of conductor patterns described above. The package substrate 200 may be a typical multilayer printed circuit board, and the specific structure thereof is not particularly limited. If necessary, at least one of the printed circuit boards 100A and 100B described above may be included as an internal structure of the package substrate 200. The first and second semiconductor chips 410 and 420 may be memory chips, application processor chips, and / or logic chips, respectively. The first and second semiconductor chips 410 and 420 may be the same type of chip or different types of chips. The other details are substantially the same as those described above, and redundant description will be omitted.

[0050] FIG. 8 is a cross-sectional view schematically showing another example of a semiconductor package.

[0051] Referring to the drawing, a semiconductor package 600 according to another example may include a package substrate 300 and first and second semiconductor chips 410 and 420 mounted on the package substrate 300. A fine wiring layer 310 including fine wiring for interconnecting the first and second semiconductor chips 410 and 420 may be disposed on the outermost surface of the package substrate 300. The fine wiring layer 310 may include at least one of the printed circuit boards 100A and 100B described above. For example, the fine wiring layer 310 may have a wiring structure including one or more insulating layers, one or more wiring layers disposed on or within the one or more insulating layers, and one or more via layers penetrating at least one of the one or more insulating layers. In this case, at least one of the one or more insulating layers may include the insulating substrate described above, and at least one of the one or more wiring layers may include the plurality of conductor patterns described above. The package substrate 300 may be a typical multilayer printed circuit board, and the specific structure thereof is not particularly limited. If necessary, at least one of the printed circuit boards 100A and 100B described above may be included as an internal structure of the package substrate 300. The first and second semiconductor chips 410 and 420 may be memory chips, application processor chips, and / or logic chips, respectively. The first and second semiconductor chips 410 and 420 may be the same type of chip or different types of chips. The other details are substantially the same as those described above, and redundant description will be omitted.

[0052] In the present disclosure, the resistivity of a metal can be, for example, the volume resistivity or bulk electrical resistivity of the metal.

[0053] In the present disclosure, the term "cover" may include not only completely covering but also at least partially covering, and may also include not only directly covering but also indirectly covering. Furthermore, the term "fill" may include not only completely filling but also at least partially filling, and may also include roughly filling. Furthermore, the term "surround" may include not only completely surrounding but also partially surrounding and roughly surrounding. Furthermore, "expose" may include not only completely exposing but also partially exposing, and may mean exposing a corresponding component from being embedded.

[0054] In this disclosure, "substantially" can be interpreted to include process errors, positional deviations, measurement errors, and the like that occur during the manufacturing process. For example, a substantially constant thickness can include not only a completely constant thickness, but also a roughly constant thickness. Furthermore, being substantially coplanar can include not only a completely coplanar thickness, but also a roughly coplanar thickness.

[0055] In the present disclosure, "on a cross section" can refer to the cross-sectional shape of an object when cut vertically or when viewed from the side, and "on a plane" can refer to the planar shape of an object when cut horizontally or when viewed from the top or bottom.

[0056] In this disclosure, for convenience, terms such as bottom, lower part, and bottom surface are used to refer to the downward direction based on the cross section of the drawing, and terms such as top, upper part, and top surface are used to refer to the opposite direction. However, this is a definition of directions for convenience of explanation, and the scope of the claims is not particularly limited by the description of these directions, and the concepts of top and bottom may change at any time.

[0057] In this disclosure, the term "connected" encompasses not only direct connection but also indirect connection via an adhesive layer or the like. Furthermore, the term "electrically connected" encompasses both physical connection and non-physical connection. Furthermore, terms such as "first" and "second" are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of the invention.

[0058] In the present disclosure, thickness, width, length, depth, line width, spacing, pitch, separation distance, surface roughness, etc. can be measured using a scanning microscope or optical microscope based on a cross section obtained by polishing or cutting a printed circuit board. The cut section can be a vertical or horizontal section, and each value can be measured based on the required cut section. For example, the width of the upper and / or lower ends of a via can be measured on a cross section cut along the central axis of the via. In this case, if the value is not constant, the value can be determined as the average of values ​​measured at any five points.

[0059] The term "one example" used in this disclosure does not mean the same embodiment as the other examples, but is provided to emphasize and describe the unique features that are different from each other. However, the above-described one example does not exclude being realized in combination with the features of another example. For example, even if a matter described in a particular example is not described in another example, it can be understood as being related to the other example unless there is a contrary or contradictory description with that matter in the other example.

[0060] The terms used in this disclosure are merely used to describe an example and are not intended to limit the disclosure. In this case, singular expressions include plural expressions unless the context clearly indicates otherwise. [Explanation of symbols]

[0061] 1000 electronic equipment 1010 mainboard 1020 Chip related parts 1030 Network related parts 1040 Other parts 1050 camera 1060 Antenna 1070 display 1080 battery 1090 signal line 1100 smartphones 1110 motherboard 1120 parts 1121 Parts Package 1130 Camera Module 1140 Speaker 100A, 100B printed circuit board 110 insulating substrate 120A, 120B conductor pattern 121, 122, 123 Seed metal layer 124 patterned metal layer 500, 600 semiconductor packages 410, 420 semiconductor chips 200, 300 package substrate 210 Bridge board 310 Fine wiring layer

Claims

1. a conductor pattern including a seed metal layer and a patterned metal layer disposed on the seed metal layer; the seed metal layer includes a first metal layer including a first metal, and a second metal layer disposed on the first metal layer and connected to the pattern metal layer, the second metal layer including a second metal; the first metal layer is thicker than the second metal layer; The first metal is any one selected from the group consisting of aluminum (Al), iridium (Ir), molybdenum (Mo), tungsten (W), cobalt (Co), nickel (Ni), and ruthenium (Ru).

2. The printed circuit board according to claim 1 , wherein the second metal has a lower resistivity than the first metal.

3. The printed circuit board of claim 2 , wherein the second metal is copper (Cu).

4. the first metal layer and the second metal layer are each a sputtered thin film; the first metal is molybdenum (Mo); The printed circuit board of claim 1 , wherein the second metal is copper (Cu).

5. the seed metal layer further includes a third metal layer including a third metal; the third metal layer, the first metal layer, and the second metal layer are stacked in this order based on the thickness direction, The printed circuit board of claim 1 , wherein the first metal layer has a greater thickness than the third metal layer.

6. The printed circuit board according to claim 5 , wherein the third metal has a higher resistivity than the first metal.

7. 7. The printed circuit board of claim 6, wherein the third metal is any one selected from the group consisting of chromium (Cr), tantalum (Ta), niobium (Nb), and titanium (Ti).

8. the first to third metal layers are each a sputtered thin film; the first metal is molybdenum (Mo); the second metal is copper (Cu); 6. The printed circuit board of claim 5, wherein the third metal is titanium (Ti).

9. the patterned metal layer has a thickness greater than that of the seed metal layer; The printed circuit board of claim 1 , wherein the patterned metal layer comprises the same metal as the second metal.

10. the patterned metal layer is an electroplated layer, The printed circuit board of claim 9 , wherein the patterned metal layer comprises copper (Cu).

11. The first metal has an electrical resistivity of 10×10 －８ Ω*m or less, the second metal layer has a thickness of 1000 Å or less; The total conductance of the seed metal layer is 350×10 －２ Ω －１ The printed circuit board according to claim 1 .

12. the conductor pattern includes a plurality of fine patterns adjacent to each other, The plurality of fine patterns each have a width of 2 μm or less, The plurality of fine patterns are spaced apart by 2 μm or less, The printed circuit board according to claim 1 , wherein each of the plurality of fine patterns has an aspect ratio of 1 or more.

13. further comprising an insulating substrate; The printed circuit board according to claim 1 , wherein the conductor pattern is in contact with at least one surface of the insulating substrate.

14. the printed circuit board has a multilayer wiring structure including one or more insulating layers, one or more wiring layers disposed on or within the one or more insulating layers, and one or more via layers penetrating at least one of the one or more insulating layers; At least one of the one or more insulating layers includes the insulating substrate; The printed circuit board according to claim 13 , wherein at least one of the one or more wiring layers includes the conductor pattern.

15. an insulating substrate; a conductor pattern including a seed metal layer disposed on the insulating substrate and a patterned metal layer disposed on the seed metal layer; The seed metal layer has a laminated structure in which a titanium (Ti) layer, a molybdenum (Mo) layer, and a copper (Cu) layer are laminated in this order.

16. the patterned metal layer comprises a copper (Cu) layer; The printed circuit board of claim 15 , wherein the copper (Cu) layers of the seed metal layer and the pattern metal layer contact each other.

17. the patterned metal layer has a thickness greater than that of the seed metal layer; The printed circuit board of claim 15 , wherein in the stacked structure of the seed metal layer, the molybdenum (Mo) layer is thicker than each of the titanium (Ti) layer and the copper (Cu) layer.

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