DC / DC circuit

Abstract

To improve the conversion efficiency.SOLUTION: A DC-DC circuit comprises: a capacitor net; a first coil; a second coil; and a smooth capacitor that is connected between the other end of the first coil and the other end of the second coil, and, a reference potential point. The capacitor net has a first state that a first capacitor is connected onto a wiring path between an input node to which an input voltage is applied and one end of the first coil by a plurality of switches and connects a second capacitor to between a connection point of the first capacitors on the wiring path and the reference potential point, and a second state that the second capacitor is connected to the one end of the second coil and the first capacitor is connected between the one end of the second capacitor and the reference potential point and between the other end of the second capacitor and the reference potential point.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a DC / DC circuit. [Background technology]

[0002] Conventionally, a step-down type DC / DC circuit using a coil, a capacitor, and a switch is known. This DC / DC circuit obtains the desired output voltage by changing the duty ratio of the input voltage applied to the coil through the switching operation of the switch.

[0003] However, when the output voltage is reduced relatively significantly relative to the input voltage, for example, when the relationship between the output voltage Vout and the input voltage Vin is set to Vout<0.1×Vin, the on-time of switching becomes extremely short, which results in an increase in switching loss and a deterioration in conversion efficiency.

[0004] Another method to improve conversion efficiency is to use a transformer to reduce the input voltage and then apply it to the coil, but this method has the disadvantage of requiring a transformer, which increases the volume of the DC-DC circuit. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 5059160 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the embodiments is to provide a DC-DC circuit that can improve conversion efficiency. [Means for solving the problem]

[0007] The DC-DC circuit of the embodiment includes a capacitor network including two or more first capacitors, one or more second capacitors, and a plurality of switches, and a power supply having one end connected to the capacitor network. , the other end is connected to the output node a first coil having one end connected to the capacitor network; , the other end is connected to the output node and a smoothing capacitor connected between the other end of the first coil and the other end of the second coil and a reference potential point, and the capacitor network has a first state in which the plurality of switches connect the first capacitor to a wiring path between an input node to which an input voltage is applied and one end of the first coil, and connect the second capacitor between a connection point between the first capacitors on the wiring path and the reference potential point, and a second state in which the second capacitor is connected to one end of the second coil, and connects the first capacitor between one end of the second capacitor and the reference potential point and between the other end of the second capacitor and the reference potential point, respectively. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing a DC / DC circuit according to a first embodiment of the present invention. [Figure 2] 4 is a timing chart for explaining control signals φ1, φ2, / φ1, and / φ2. [Figure 3] FIG. 4 is an explanatory diagram showing the connection relationship of the capacitor network Cn in each of Steps 1 to 4. [Figure 4] 4 is an explanatory diagram showing the connection relationship between each of the capacitors C1 to C3 of the capacitor network Cn and the coils L1, L2 in each of Steps 1 to 4, with the switch S omitted. FIG. [Figure 5] FIG. [Figure 6] 5A and 5B are explanatory diagrams for explaining outputs and effects in the present embodiment. [Figure 7] FIG. 4 is a circuit diagram showing a second embodiment of the present invention. [Figure 8] FIG. 10 is a circuit diagram showing a third embodiment of the present invention. [Figure 9] FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention. [Figure 10] 4 is a timing chart for explaining control signals φ1, φ2, / φ1, and / φ2. [Figure 11] 10 is an explanatory diagram showing the connection relationship between each of the capacitors C11 to C14 of the capacitor network Cn11 and the coils L1 and L2 in each of Steps 1 to 4, with the switch S omitted. FIG. [Figure 12] FIG. 10 is a circuit diagram showing a fifth embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] (First embodiment) 1 is a circuit diagram showing a DC-DC circuit according to a first embodiment of the present invention. This embodiment improves conversion efficiency by using a switched capacitor circuit made up of multiple capacitors.

[0011] As shown in Fig. 1, the DC-DC circuit 1 includes a capacitor network Cn including three capacitors C1, C2, and C3, two coils L1 and L2, and a capacitor Cs that configures a smoothing circuit together with the coils L1 and L2. The capacitor network Cn also includes switches S1p_1, S1p_2, and S1p_3 (hereinafter, referred to as switch S1p when not distinguished), switches S2p_1, S2p_2, and S2p_3 (hereinafter, referred to as switch S2p when not distinguished), and switches S1n and S2n for changing the connection relationship between the capacitors C1 to C3 and the coils L1 and L2. Hereinafter, the switches S1p, S2p, S1n, and S2n will be collectively referred to as switches S.

[0012] The switch S1p is turned on and off based on a control signal φ1, and the switch S2p is turned on and off based on a control signal φ2. The switch S1n is turned on and off based on a control signal / φ1 obtained by inverting the control signal φ1, and the switch S2n is turned on and off based on a control signal / φ2 obtained by inverting the control signal φ2. Note that various switches such as NMOS transistors, PMOS transistors, and GaN (gallium nitride) transistors can be used as the switches S.

[0013] The DC-DC converter 1 is controlled by a control circuit 2. The control circuit 2 may be configured by a processor using a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), or the like. The control circuit 2 may operate according to a program stored in a memory (not shown) to control each component, or may implement some or all of its functions using a hardware electronic circuit. The control circuit 2 generates control signals φ1, φ2, / φ1, / φ2 (hereinafter collectively referred to as the control signal φ) and supplies the generated control signals φ to each switch S to control the on / off of each switch S. An output voltage Vout is input to the control circuit 2. The control circuit 2 adjusts the duty ratio of the control signal φ so that the output voltage Vout becomes a desired voltage.

[0014] (Configuration of capacitor network Cn) Switches S1p_1, S2p_1, S1p_2, and S2p_2 are connected in series between a node (hereinafter referred to as node Nin) to which an input voltage Vin is supplied and a node (hereinafter referred to as node NL2) connected to one end of the coil L2. The connection point between the switch S1p_1 and the switch S2p_1 is referred to as node N1, the connection point between the switch S2p_1 and the switch S1p_2 is referred to as node N2, and the connection point between the switch S1p_2 and the switch S2p_2 is referred to as node N3.

[0015] The node N1 is connected to a node (hereinafter referred to as node NL1) connected to one end of the coil L1 via the capacitor C1 and the switch S2p_3. The node NL1 is connected to a reference potential point via the switch S1n. The connection point (hereinafter referred to as node N4) between the capacitor C1 and the switch S2p_3 is connected to a node N3 via the switch S1p_3, and the node N3 is connected to the node NL1 via the capacitor C3.

[0016] The node N2 is connected to a node NL2 via a capacitor C2, and the node NL2 is connected to a reference potential point via a switch S2n.

[0017] The other end of the coil L1 and the other end of the coil L2 are commonly connected to a node (hereinafter referred to as a node Nout) that outputs an output voltage Vout, and are also connected to a reference potential point via a capacitor Cs.

[0018] (Connection status at each step) FIG. 2 is a timing chart for explaining the control signals φ1, φ2, / φ1, and / φ2.

[0019] In the following explanation, it is assumed that switch S1p is turned on when the control signal φ1 is at a high level (hereinafter referred to as H level) and turned off when it is at a low level (hereinafter referred to as L level). Furthermore, switch S2p is turned on when the control signal φ2 is at a high level and turned off when it is at a low level. Furthermore, switch S1n is turned on when the control signal / φ1 is at a high level and turned off when it is at a low level. Furthermore, switch S2n is turned on when the control signal / φ2 is at a high level and turned off when it is at a low level.

[0020] In this embodiment, the control circuit 2 sets four steps (Step1 to Step4) using the control signal φ. St1 to St4 in FIG. 2 respectively indicate the four periods of Step1 to Step4. The control signal φ1 is at H level during period St1 and at L level during the other periods. The control signal / φ1 is at L level during period St1 and at H level during the other periods. The control signal φ2 is at H level during period St3 and at L level during the other periods. The control signal / φ2 is at L level during period St3 and at H level during the other periods. Note that the period St1 of Step1 and the period St3 of Step3 are 180 degrees out of phase with each other, and similarly the period St2 of Step2 and the period St4 of Step4 are 180 degrees out of phase with each other.

[0021] Therefore, during period St1 of Step 1, switches S1p and S2n are on and switches S2p ​​and S1n are off. During period St2 of Step 2, switches S1n and S2n are on and switches S1p and S2p are off. During period St3 of Step 3, switches S2p ​​and S1n are on and switches S1p and S2n are off. During period St4 of Step 4, switches S1n and S2n are on and switches S1p and S2p are off.

[0022] Fig. 3 is an explanatory diagram showing the connection relationship of the capacitor network Cn in each of Steps 1 to 4. In Fig. 3, thick lines indicate which switches S are in a connected state.

[0023] As shown in the upper left column of Fig. 3, in Step 1, switches S1p and S2n are turned on, and the connections shown by the thick lines are made. As shown in the upper right column of Fig. 3, in Step 2, switches S1n and S2n are turned on, and the connections shown by the thick lines are made. As shown in the lower left column of Fig. 3, in Step 3, switches S2p ​​and S1n are turned on, and the connections shown by the thick lines are made. As shown in the lower right column of Fig. 3, in Step 4, switches S1n and S2n are turned on, and the connections shown by the thick lines are made.

[0024] FIG. 4 is an explanatory diagram showing the connection relationship between the capacitors C1 to C3 of the capacitor network Cn and the coils L1 and L2 in each of Steps 1 to 4, with the switch S omitted.

[0025] In Step 1, as shown in the upper left column of Fig. 4, node Nin is connected to nodes N2 to N4 via capacitor C1, and is further connected to one end of coil L1 (node ​​NL1) via capacitor C3. That is, in the capacitor network Cn, odd-numbered capacitors C1 and C3 are connected in series between node Nin and node NL1. An even-numbered capacitor C2 is connected between nodes N2 to N4, which are the mutual junctions of capacitors C1 and C3, and the reference potential point. Note that node NL2 connected to coil L2 is also connected to the reference potential point.

[0026] In Step 2, as shown in the upper right column of FIG. 4, a node NL1 connected to one end of the coil L1 and a node NL2 connected to one end of the coil L2 are both connected to the reference potential point.

[0027] In Step 3, as shown in the lower right column of Figure 4, nodes N1 and N2 are connected to one end of coil L2 via capacitor C2 and nodes N3 and NL2. That is, in the capacitor network Cn, even-numbered capacitors C2 are connected in series between nodes N1 and N2 and node NL2. Odd-numbered capacitors C1 are connected between nodes N1 and N2 and the reference potential point, and odd-numbered capacitors C3 are connected between nodes N3 and NL2 and the reference potential point. Node NL1 connected to coil L1 is also connected to the reference potential point.

[0028] In Step 4, as shown in the lower left column of FIG. 4, a node NL1 connected to one end of the coil L1 and a node NL2 connected to one end of the coil L2 are both connected to the reference potential point.

[0029] (action) Next, the operation of the embodiment configured as above will be described with reference to Figures 5 and 6. Figure 5 is a circuit diagram showing a comparative example, and Figure 6 is an explanatory diagram for explaining the output and effects of this embodiment. In Figure 6, the arrows indicate the direction of current.

[0030] The comparative example in Figure 5 shows a typical DCDC circuit. In the DCDC circuit of the comparative example, a switch SW1 is provided between a power supply P and one end of a coil L, and one end of the coil L is connected to a reference potential point via a switch SW2. The other end of the coil L is connected to the reference potential point via a capacitor C. An output Vout is obtained from the other end of the coil L.

[0031] Switches SW1 and SW2 are alternately turned on and off. The voltage Vin generated in power supply P is intermittently applied to coil L by switch SW1. While SW1 is on, current flows from power supply P to the output terminal via switch SW1 and coil L. During this period, energy is stored in coil L. While SW1 is off, the back electromotive force of coil L causes current to flow from the reference potential point to the output terminal via coil L. The input voltage Vin is smoothed by coil L and capacitor C, and an output voltage Vout is obtained.

[0032] If Duty is the ratio of the ON period (duty ratio) in the switching cycle of the switch SW1, then Vout=Vin×Duty is established, i.e., Duty=Vout / Vin.

[0033] In Step 1 shown in the upper left column of Figure 6, an input voltage Vin from node Nin causes a current to flow from node Nin to coil L1 via capacitor network Cn. This causes energy to accumulate in coil L1. In Step 2, one end of coil L1 and one end of coil L2 are connected to the reference potential point. In Step 2, a back electromotive force generated in coils L1 and L2 causes a current to flow from the reference potential point to node Nout via coils L1 and L2.

[0034] In Step 3, the capacitor network Cn is connected to the coil L2, and a current flows through the coil L2 due to the charging voltage of the capacitor network Cn. This causes energy to be stored in the coil L2. In Step 4, one end of the coil L1 and one end of the coil L2 are connected to the reference potential point. In this case, a current flows from the reference potential point to the node Nout via the coils L1 and L2 due to the back electromotive force generated in the coils L1 and L2.

[0035] The control circuit 2 generates control signals φ1, φ2, / φ1, / φ2 to control each switch S, cyclically repeating Step 1, Step 2, Step 3, Step 4, Step 1, .... As a result, an output voltage Vout according to the input voltage Vin and the cycle of the switch S is obtained from the node Nout.

[0036] Now, in a steady state, the voltage at the connection point (nodes N2 to N4) between capacitors C1 and C3 is Va, and the voltage at one end of coil L1 is Vc. The terminal voltage of capacitor C1 is Vb, and the terminal voltage of capacitor C3 is Vd. In Step 1, an input voltage Vin is applied to node Nin, and capacitors C1, C2, and C3 of the capacitor network Cn are charged. In Step 3, current flows through coils L1 and L2 due to the charging voltage of capacitors C1 to C3. According to the law of conservation of charge, the following equations (1) to (3) hold for the capacitors C1 to C3. Vin-Va=Vb …(1) Va = Vb - Vd … (2) Va-Vc =Vd …(3) Now, if the period of Step 1 to Step 4 is 1, and the period of Step 1, that is, the period during which current flows through coils L1 and L2 due to input voltage Vin, is Duty, then the following equation (4) holds for coil L1 during the period of Step 1 and periods other than Step 1 according to the Volt-Second-Balance-Principle. Duty×(Vc-Vout)=(1-Duty)×Vout Duty × Vc = Vout … (4) The period of Step 3 is also assumed to have the same duty as the period of Step 1. According to the law of conservation of magnetic flux change rate for coil L2, the following equation (5) is established. Duty×(Vd-Vout)=(1-Duty)×Vout Duty × Vd = Vout … (5) From the above equations (4) and (5), the following equation (6) is obtained. Vc = Vd …(6) From the above equations (1) to (3) and (6), the following equation (7) is obtained. Vin = 5 × Vc …(7) From the above equations (4) and (7), the following equation (8) is obtained. Duty = 5 × (Vout / Vin) … (8) The above (8) shows that the duty cycle of this embodiment is five times longer than that of the comparative example. That is, in this embodiment, when the same relationship between the input voltage Vin and the output voltage Vout as in the comparative example is obtained, it is possible to make the switch on time five times longer than in the comparative example. Therefore, it is possible to reduce switching loss and obtain a highly efficient DC-DC circuit.

[0037] In actual use, the control circuit 2 may adjust the on-time (duty ratio) of the control signal φ so that the current output voltage Vout matches the target output voltage Vout.

[0038] 1, the node N4 is connected to the reference potential point via two switches S2p_3 and S1n. The node N4 is also connected to the node N2 via two switches S1p_3 and S1p_2. Therefore, it is possible to lower the withstand voltage of the switches S2p_3 and S1p_3 compared to when the node N4 is connected to the reference potential point or the node N2 by one switch.

[0039] In this embodiment, the input voltage is supplied to the coil via a capacitor network, which makes it possible to lengthen the switch on time required to obtain the required output, compared to when the input voltage is supplied to the coil via a switch. This reduces switching loss, resulting in a highly efficient DC-DC circuit.

[0040] (Second embodiment) Fig. 7 is a circuit diagram showing a second embodiment of the present invention, in which the same components as those in Fig. 1 are given the same reference numerals and their explanations will be omitted.

[0041] In this embodiment, a capacitor network Cn1 is employed, which differs from the capacitor network Cn in FIG. 1 in that switches S1p_4 and S2p_4 are added and the connection destinations of switches S1p_3 and S2p_3 are changed.

[0042] Switches S1p_1, S1p_2, S1p_3, and S1p_4 (hereinafter, when not distinguished, referred to as switches S1p) are turned on and off by a control signal φ1, and switches S2p_1, S2p_2, S2p_3, and S2p_4 (hereinafter, when not distinguished, referred to as switches S2p) are turned on and off by a control signal φ2. Furthermore, switches S1p, S2p, S1n, and S2n are collectively referred to as switches S. Various switches such as NMOS transistors, PMOS transistors, and GaN (gallium nitride) transistors can be used as switches S.

[0043] The node N4 is connected to the reference potential point via the switch S2p_3 and is also connected to the node N2 via the switch S1p_3. The node N2 is connected to the reference potential point via the capacitor C2 and the switch S1p_4. The connection point between the capacitor C2 and the switch S1p_4 (hereinafter referred to as node N5) is connected to the node N3 via the switch S2p_4.

[0044] In this embodiment, the control of each switch S by the control circuit 2 is the same as in the first embodiment. That is, the control circuit 2 controls each switch S by providing a control signal φ shown in FIG. 2 to each switch S to control it to be turned on or off. In Step 1, the switches S1p and S2n are turned on. In Step 2, the switches S1n and S2n are turned on. In Step 3, the switches S2p ​​and S1n are turned on. In Step 4, the switches S1n and S2n are turned on.

[0045] That is, in Step 1, node Nin is connected to nodes N2 to N4 via capacitor C1, and further connected to one end of coil L1 (node ​​NL1) via capacitor C3. That is, in the capacitor network Cn, odd-numbered capacitors C1 and C3 are connected in series between node Nin and node NL1. One end of even-numbered capacitor C2 is connected to node N2, which is the connection point between capacitors C1 and C3, and the other end of capacitor C2 is connected to the reference potential point via switch S1p_4. Note that node NL2 connected to coil L2 is also connected to the reference potential point. That is, the connection state is the same as that shown in the upper left column of FIG. 4.

[0046] In Step 2, node NL1 connected to one end of coil L1 and node NL2 connected to one end of coil L2 are both connected to the reference potential point, i.e., the same connection state as in the upper right column of FIG.

[0047] In Step 3, nodes N1 and N2 are connected to one end of coil L2 via capacitor C2 and nodes N5, N3, and NL2. That is, in the capacitor network Cn, an even-numbered capacitor C2 is connected in series between nodes N1 and N2 and node NL2. An odd-numbered capacitor C1 is connected between nodes N1 and N2 and the reference potential point, and an odd-numbered capacitor C3 is connected between nodes N2, N3, and NL2 and the reference potential point. Note that node NL1 connected to coil L1 is also connected to the reference potential point. That is, the connection state is the same as that shown in the lower right column of FIG. 4.

[0048] In Step 4, the node NL1 connected to one end of the coil L1 and the node NL2 connected to one end of the coil L2 are both connected to the reference potential point, i.e., the same connection state as in the lower left column of FIG.

[0049] That is, in this embodiment, Steps 1 to 4 are connected in the same manner as in the first embodiment. Therefore, in this embodiment, the relationship between the input voltage Vin and the output voltage Vout is given by the above equation (8). That is, compared to the comparative example, the on-time of the switch for obtaining the required output can be made longer. This makes it possible to reduce switching loss and obtain a highly efficient DC-DC circuit.

[0050] In this way, the same effects as those of the first embodiment can be obtained in this embodiment as well.

[0051] (Third embodiment) Fig. 8 is a circuit diagram showing a third embodiment of the present invention. In Fig. 8, the same components as those in Fig. 1 are given the same reference numerals and their explanations will be omitted.

[0052] In this embodiment, a capacitor network Cn2 is employed, which differs from the capacitor network Cn in FIG. 1 in that the node N4 and the node N3 are not connected by the switch S1p_3, but the node N4 and the node N2 are connected by the switch S1p_3, and the node N4 is not connected to the node NL1 via the switch S2p_3, but is connected to the reference potential point via the switch S2p_3.

[0053] In this embodiment, the control of each switch S by the control circuit 2 is the same as in the first embodiment. That is, the control circuit 2 controls each switch S by providing a control signal φ shown in FIG. 2 to each switch S to control it to be turned on or off. In Step 1, the switches S1p and S2n are turned on. In Step 2, the switches S1n and S2n are turned on. In Step 3, the switches S2p ​​and S1n are turned on. In Step 4, the switches S1n and S2n are turned on.

[0054] That is, in Step 1, node Nin is connected to nodes N2 to N4 via capacitor C1, and further connected to one end of coil L1 (node ​​NL1) via capacitor C3. That is, in the capacitor network Cn, odd-numbered capacitors C1 and C3 are connected in series between node Nin and node NL1. One end of even-numbered capacitor C2 is connected to nodes N2 to N4, which are the mutual connection points of capacitors C1 and C3, and the other end of capacitor C2 is connected to the reference potential point via switch S2n. Note that node NL2 connected to coil L2 is also connected to the reference potential point. That is, the connection state is the same as that shown in the upper left column of FIG. 4.

[0055] In Step 2, node NL1 connected to one end of coil L1 and node NL2 connected to one end of coil L2 are both connected to the reference potential point, i.e., the same connection state as in the upper right column of FIG.

[0056] In Step 3, nodes N1 and N2 are connected to one end of coil L2 via capacitor C2 and node NL2. That is, in the capacitor network Cn, even-numbered capacitors C2 are connected in series between nodes N1 and N2 and node NL2. Odd-numbered capacitors C1 are connected between nodes N1 and N2 and the reference potential point, and odd-numbered capacitors C3 are connected between nodes N3 and NL2 and the reference potential point. Note that node NL1 connected to coil L1 is also connected to the reference potential point. That is, the connection state is the same as that shown in the lower right column of FIG. 4.

[0057] In Step 4, the node NL1 connected to one end of the coil L1 and the node NL2 connected to one end of the coil L2 are both connected to the reference potential point, i.e., the same connection state as in the lower left column of FIG.

[0058] That is, in this embodiment, Steps 1 to 4 are connected in the same manner as in the first embodiment. Therefore, in this embodiment, the relationship between the input voltage Vin and the output voltage Vout is given by the above equation (8). That is, compared to the comparative example, the on-time of the switch for obtaining the required output can be made longer. This makes it possible to reduce switching loss and obtain a highly efficient DC-DC circuit.

[0059] In this way, the same effects as those of the first embodiment can be obtained in this embodiment as well.

[0060] (Fourth embodiment) Fig. 9 is a circuit diagram showing a fourth embodiment of the present invention. In Fig. 9, the same components as those in Fig. 1 are given the same reference numerals and their explanations will be omitted.

[0061] 9, the DC-DC circuit 10 includes a capacitor network Cn11 including four capacitors C11, C12, C13, and C14, two coils L1 and L2, and a capacitor Cs that configures a smoothing circuit together with the coils L1 and L2. The capacitor network Cn11 also includes switches S1p_11 to S1p_16 (hereinafter, referred to as switch S1p when not distinguished) for changing the connection relationship between the capacitors C11 to C14 and the coils L1 and L2, switches S2p_11 to S2p_16 (hereinafter, referred to as switch S2p when not distinguished), and switches S1n and S2n. Hereinafter, the switches S1p, S2p, S1n, and S2n will be collectively referred to as switches S.

[0062] The switch S1p is turned on and off based on a control signal φ1, and the switch S2p is turned on and off based on a control signal φ2. The switch S1n is turned on and off based on a control signal / φ1 obtained by inverting the control signal φ1, and the switch S2n is turned on and off based on a control signal / φ2 obtained by inverting the control signal φ2. Note that various switches such as NMOS transistors, PMOS transistors, and GaN (gallium nitride) transistors can be used as the switches S.

[0063] The DC-DC circuit 10 is controlled by a control circuit 2. The control circuit 2 generates a control signal φ and supplies the generated control signal φ to each switch S to control the on / off of each switch S.

[0064] Switches S1p_11, S2p_11, S1p_12, S2p_12, and S1p_13 are connected in series between a node Nin to which an input voltage Vin is supplied and a node (node ​​NL1) connected to one end of the coil L1. A connection point between the switch S1p_11 and the switch S2p_11 is referred to as a node N11, a connection point between the switch S2p_11 and the switch S1p_12 is referred to as a node N12, a connection point between the switch S1p_12 and the switch S2p_12 is referred to as a node N13, and a connection point between the switch S2p_12 and the switch S1p_13 is referred to as a node N14.

[0065] The node N11 is connected to a node N12 via a capacitor C11 and a switch S1p_14. A connection point between the capacitor C11 and the switch S1p_14 (hereinafter referred to as a node N15) is connected to a reference potential point via a switch S2p_14.

[0066] The node N12 is connected to a node N13 via a capacitor C12 and a switch S2p_15. A connection point between the capacitor C12 and the switch S2p_15 (hereinafter referred to as a node N16) is connected to a reference potential point via the switch S1p_15.

[0067] The node N13 is connected to a node N14 via a capacitor C13 and a switch S1p_16. The connection point between the capacitor C13 and the switch S1p_16 (hereinafter referred to as a node N17) is connected to a reference potential point via a switch S2p_16.

[0068] The node N14 is connected via a capacitor C14 to a node (node ​​NL2) connected to one end of the coil L2, and the node NL2 is connected to a reference potential point via a switch S2n.

[0069] The node NL1 is connected to a reference potential point via a switch S1n. The other end of the coil L1 and the other end of the coil L2 are commonly connected to a node (hereinafter referred to as a node Nout) that outputs an output voltage Vout, and are also connected to the reference potential point via a capacitor Cs.

[0070] (Connection status at each step) FIG. 10 is a timing chart for explaining the control signals φ1, φ2, / φ1, and / φ2.

[0071] In this embodiment as well, each switch S is turned on when the control signal φ is at H level and turned off when the control signal φ is at L level. Also in this embodiment as well, the control circuit 2 sets four steps (Step 1 to Step 4) using the control signal φ. St1 to St4 in FIG. 10 respectively indicate the four periods of Step 1 to Step 4. The control signal φ1 is at H level during period St1 and is at L level during the other periods. The control signal / φ1 is at L level during period St1 and is at H level during the other periods. The control signal φ2 is at H level during period St3 and is at L level during the other periods. The control signal / φ2 is at L level during period St3 and is at H level during the other periods.

[0072] Therefore, in this embodiment as well, during period St1 of Step 1, switches S1p and S2n are on and switches S2p ​​and S1n are off. During period St2 of Step 2, switches S1n and S2n are on and switches S1p and S2p are off. During period St3 of Step 3, switches S2p ​​and S1n are on and switches S1p and S2n are off. During period St4 of Step 4, switches S1n and S2n are on and switches S1p and S2p are off.

[0073] FIG. 11 is an explanatory diagram showing the connection relationship between the capacitors C11 to C14 of the capacitor network Cn11 and the coils L1 and L2 in each of Steps 1 to 4, with the switch S omitted.

[0074] In Step 1, switches S1p and S2n are turned on. As a result, node Nin is connected to capacitors C12 and C13 via nodes N12 and N13 from node N15 via capacitor C11. Capacitor C12 is connected to the reference potential via switch S1p_15. Capacitor C13 is connected to capacitor C14 via nodes N17 and N14 and to one end of coil L1 via node NL1. Capacitor C14 is connected to the reference potential via switch S2n. That is, as shown in the upper left column of FIG. 11, odd-numbered capacitors C11 and C13 are connected between node Nin and node NL1 connected to coil L1, and even-numbered capacitors C12 and C14 are connected between both ends of capacitor C13 and the reference potential.

[0075] In Step 2, the switches S1n and S2n are turned on, which connects the node NL1 connected to one end of the coil L1 and the node NL2 connected to one end of the coil L2 to the reference potential point, as shown in the upper right column of FIG.

[0076] In Step 3, switches S2p ​​and S1n are turned on. As a result, one end of capacitor C11 is connected to capacitor C12 via nodes N11 and N12. The other end of capacitor C11 is connected to the reference potential point via switch S2p_14. Capacitor C12 is connected to capacitor C13 via nodes N16 and N13, and capacitor C13 is connected to the reference potential point via switch S2p_16. Node N13 is connected to one end of capacitor C14 via node N14, and the other end of capacitor C14 is connected to one end of coil L2 via node NL2. One end of coil L1 is connected to the reference potential point via switch S1n. That is, as shown in the lower right column of FIG. 11, even-numbered capacitors C12 and C14 are connected between nodes N12 and N15 and node NL2 connected to coil L2, and capacitors C11 and C13 are connected between both ends of capacitor C12 and the reference potential point, respectively.

[0077] In Step 4, the switches S1n and S2n are turned on, which connects the node NL1 connected to one end of the coil L1 and the node NL2 connected to one end of the coil L2 to the reference potential point, as shown in the lower left column of FIG.

[0078] (action) Next, the operation of the embodiment configured as above will be described with reference to Fig. 11. In Fig. 11, the arrows indicate the direction of current.

[0079] The operation in each of Steps 1 to 4 is the same as in the first embodiment. In this embodiment, the on-time required to obtain the output voltage Vout for the input voltage Vin is different from that in the first embodiment. That is, if the cycle of Steps 1 to 4 is 1 and the period of Step 1, that is, the period during which current flows through the coils L1 and L2 due to the input voltage Vin, is Duty 2, Duty 2 is expressed by the following equation (9) using the input voltage Vin and the output voltage Vout. Duty2=8×(Vout / Vin) …(9) The above (8) shows that Duty 2 in this embodiment is six times longer than Duty 1 in the comparative example. That is, in this embodiment, when the same relationship between the input voltage Vin and the output voltage Vout as in the comparative example is obtained, it is possible to make the switch on time eight times longer than in the comparative example. Therefore, it is possible to reduce switching loss and obtain a highly efficient DC-DC circuit.

[0080] In this embodiment, two odd-numbered capacitors are connected between node Nin and node NL1 connected to coil L1, and two even-numbered capacitors are connected between this connection line and a reference potential point. This capacitor network allows the input voltage Vin to be stepped down and then applied to coil L1. This makes it possible to lengthen the switch on time required to obtain the required output, compared to when the input voltage is supplied to the coil via a switch. In this way, this embodiment can also achieve the same effects as the above-mentioned embodiments.

[0081] (Fifth embodiment) Fig. 12 is a circuit diagram showing a fifth embodiment of the present invention. In Fig. 12, the same components as those in Fig. 9 are given the same reference numerals and their explanations will be omitted.

[0082] As shown in FIG. 12, the DCDC circuit 20 differs from the DCDC circuit 10 of FIG. 9 in that the switches S1p_16 and S2p_16 are omitted, the node N15 is connected to the node NL1 via the switch S2p_14, the node N16 is connected to the node NL2 via the switch S1p_15, the node N16 is connected to the node N14 via the switch S2p_15, and the node N13 is connected to the node NL1 via the capacitor C13.

[0083] In Step 1, switches S1p and S2n are turned on. As a result, node Nin is connected to capacitors C12 and C13 via nodes N12 and N13 from node N15 via capacitor C11. Capacitor C12 is connected to the reference potential point via switches S1p_15 and S2n. Capacitor C13 is connected to capacitor C14 via nodes NL1 and N14 and to one end of coil L1 via node NL1. Capacitor C14 is connected to the reference potential point via switch S2n. That is, in Step 1, as shown in the upper left column of FIG. 11, odd-numbered capacitors C11 and C13 are connected between node Nin and node NL1 connected to coil L1, and even-numbered capacitors C12 and C14 are connected between both ends of capacitor C13 and the reference potential point, respectively.

[0084] In Step 2, the switches S1n and S2n are turned on, which connects the node NL1 connected to one end of the coil L1 and the node NL2 connected to one end of the coil L2 to the reference potential point, as shown in the upper right column of FIG.

[0085] In Step 3, switches S2p ​​and S1n are turned on. As a result, one end of capacitor C11 is connected to capacitor C12 via nodes N11 and N12. The other end of capacitor C11 is connected to the reference potential point via switches S2p_14 and S1n. Capacitor C12 is connected to one end of capacitor C13 via nodes N16, N14, and N13, and the other end of capacitor C13 is connected to the reference potential point via switch S1n. Furthermore, capacitor C13 is connected to capacitor C14 via nodes N13 and N14, and capacitor C14 is connected to one end of coil L2 via node NL2. Furthermore, one end of coil L1 is connected to the reference potential point via switch S1n. That is, as shown in the lower right column of Figure 11, even-numbered capacitors C12 and C14 are connected between nodes N12, N15 and node NL2 connected to coil L2, and capacitors C11 and C13 are connected between both ends of capacitor C12 and the reference potential point, respectively.

[0086] In Step 4, the switches S1n and S2n are turned on, which connects the node NL1 connected to one end of the coil L1 and the node NL2 connected to one end of the coil L2 to the reference potential point, as shown in the lower left column of FIG.

[0087] In this manner, in this embodiment, the connection state in each of Steps 1 to 4 is the same as that in Fig. 11. Therefore, in this embodiment as well, the same actions and effects as in the fourth embodiment are achieved.

[0088] The node N15 is connected to the reference potential point via two switches S2p_14 and S1n, and the withstand voltage of the switch S2p_14 can be reduced compared to the example of FIG.

[0089] The present invention is not limited to the above-described embodiments, and various modifications can be made in the implementation stage without departing from the spirit of the invention. Furthermore, the above-described embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining the disclosed multiple constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiments, if the problem described in the "Problem to be Solved by the Invention" section can be solved and the effect described in the "Effect of the Invention" section can be obtained, the configuration from which these constituent elements are deleted can be extracted as an invention. [Explanation of symbols]

[0090] 1...DCDC circuit, 2...control circuit, C1 to C3, Cs, C11 to C14...capacitors, Cn...capacitor network, L1, L2...coils, S, S1n, S1p, S2n, S2p...switches.

Claims

1. a capacitor network including two or more first capacitors, one or more second capacitors, and a plurality of switches; a first coil having one end connected to the capacitor network and the other end connected to an output node; a second coil having one end connected to the capacitor network and the other end connected to an output node; a smoothing capacitor connected between the other end of the first coil and the other end of the second coil and a reference potential point, the capacitor network has a first state in which the first capacitor is connected to a wiring path between an input node to which an input voltage is applied and one end of the first coil, and the second capacitor is connected between a connection point between the first capacitors on the wiring path and a reference potential point, by the plurality of switches; and a second state in which the second capacitor is connected to one end of the second coil, and the first capacitor is connected between one end of the second capacitor and the reference potential point and between the other end of the second capacitor and the reference potential point, respectively. DCDC circuit.

2. the capacitor network has a third state in which one end of the first coil and one end of the second coil are connected to a reference potential point by the plurality of switches; The DCDC circuit according to claim 1 .

3. the capacitor network is configured to cyclically repeat the first state, the third state, the first state, and the third state by the plurality of switches; The DCDC circuit according to claim 2 .

4. the capacitor network further connects the second capacitor between one end of the first coil and a reference potential point by the plurality of switches in the first state, and further connects the second capacitor between the second capacitor and the second coil in the second state. The DCDC circuit according to claim 1 .

5. the capacitor network has a third state in which one end of the first coil and one end of the second coil are connected to a reference potential point by the plurality of switches; the capacitor network is configured to cyclically repeat the first state, the third state, the first state, and the third state by the plurality of switches; The DCDC circuit according to claim 4 .

6. a capacitor network including first to third capacitors and first to eighth switches; a first coil having one end connected to the capacitor network and the other end connected to an output node; a second coil having one end connected to the capacitor network and the other end connected to an output node; a smoothing capacitor connected between the other end of the first coil and the other end of the second coil and a reference potential point, the capacitor network has a first state in which the first and third capacitors are connected to a wiring path between an input node to which an input voltage is applied and one end of the first coil by the first to eighth switches, and the second capacitor is connected between a connection point between the first capacitor and the third capacitor on the wiring path and a reference potential point, and a second state in which the second capacitor is connected to one end of the second coil, the first capacitor is connected between one end of the second capacitor and the reference potential point, and the third capacitor is connected between the other end of the second capacitor and the reference potential point. DCDC circuit.

7. the first to fourth switches are connected between an input node to which an input voltage is applied and a first node, between the first node and a second node, between the second node and a third node, and between the third node and one end of the second coil, respectively; the first capacitor is connected between the first node and a fourth node; the second capacitor is connected between the second node and one end of the second coil; the third capacitor is connected between the third node and one end of the first coil; the fifth switch connects the fourth node and the third node; the sixth switch connects the fourth node and one end of the first coil; the seventh switch connects the first coil and a reference potential point; the eighth switch connects the second coil and a reference potential point; the first, third, and fifth switches are turned on and off simultaneously, the second, fourth, and sixth switches are turned on and off simultaneously at timings different from those of the first, third, and fifth switches, and the seventh and eighth switches are turned on and off at timings different from each other; The DCDC circuit according to claim 6.

8. the capacitor network further comprises ninth and tenth switches; the first to fourth switches are connected between an input node to which an input voltage is applied and a first node, between the first node and a second node, between the second node and a third node, and between the third node and one end of the second coil, respectively; the first capacitor is connected between the first node and a fourth node; the second capacitor is connected between the second node and a fifth node; the third capacitor is connected between the third node and one end of the first coil; the fifth switch connects the fourth node and the second node; the sixth switch connects the fourth node and a reference potential point; the seventh switch connects the fifth node and a reference potential point; the eighth switch connects the fifth node and the third node; the ninth switch connects the first coil and a reference potential point; the tenth switch connects the second coil and a reference potential point; the first, third, fifth, and seventh switches are turned on and off simultaneously, the second, fourth, sixth, and eighth switches are turned on and off simultaneously at timings different from those of the first, third, fifth, and seventh switches, and the ninth and tenth switches are turned on and off at timings different from each other; The DCDC circuit according to claim 6.

9. the first to fourth switches are connected between an input node to which an input voltage is applied and a first node, between the first node and a second node, between the second node and a third node, and between the third node and one end of the second coil, respectively; the first capacitor is connected between the first node and a fourth node; the second capacitor is connected between the second node and one end of the second coil; the third capacitor is connected between the third node and one end of the first coil; the fifth switch connects the fourth node and the second node; the sixth switch connects the fourth node and a reference potential point; the seventh switch connects the first coil and a reference potential point; the eighth switch connects the second coil and a reference potential point; the first, third, and fifth switches are turned on and off simultaneously, the second, fourth, and sixth switches are turned on and off simultaneously at timings different from those of the first, third, and fifth switches, and the seventh and eighth switches are turned on and off at timings different from each other; The DCDC circuit according to claim 6.

10. a capacitor network including first to fourth capacitors and first to eleventh switches; a first coil having one end connected to the capacitor network and the other end connected to an output node; a second coil having one end connected to the capacitor network and the other end connected to an output node; a smoothing capacitor connected between the other end of the first coil and the other end of the second coil and a reference potential point, The capacitor network has a first state in which the first and third capacitors are connected on a wiring path between an input node to which an input voltage is applied and one end of the first coil by the first to eleventh switches, the second capacitor is connected between a connection point between the first capacitor and the third capacitor on the wiring path and a reference potential point, and the fourth capacitor is connected between one end of the second coil and the reference potential point, and a second state in which the fourth capacitor and the second capacitor are connected in series to one end of the second coil, the first capacitor is connected between one end of the second capacitor and the reference potential point, and the third capacitor is connected between the other end of the second capacitor and the reference potential point. DCDC circuit.

11. the first to fifth switches are connected between an input node to which an input voltage is applied and a first node, between the first node and a second node, between the second node and a third node, between the third node and a fourth node, and between the fourth node and one end of the first coil, respectively; the first capacitor is connected between the first node and a fifth node; the second capacitor is connected between the second node and a sixth node; the third capacitor is connected between the third node and one end of the first coil; the fourth capacitor is connected between the fourth node and one end of the second coil; the sixth switch connects the fifth node and one end of the first coil; the seventh switch connects the fifth node and the third node; the eighth switch connects the sixth node and the fourth node; the ninth switch connects the sixth node and one end of the second coil; the tenth switch connects the first coil and a reference potential point; the eleventh switch connects the second coil and a reference potential point; the first, third, fifth, seventh, and ninth switches are turned on and off simultaneously, the second, fourth, sixth, and eighth switches are turned on and off simultaneously at timings different from those of the first, third, fifth, seventh, and ninth switches, and the tenth and eleventh switches are turned on and off at timings different from each other; The DCDC circuit according to claim 10.

12. the capacitor network further comprises twelfth and thirteenth switches; the first to fifth switches are connected between an input node to which an input voltage is applied and a first node, between the first node and a second node, between the second node and a third node, between the third node and a fourth node, and between the third node and one end of the first coil, respectively; the first capacitor is connected between the first node and a fifth node; the second capacitor is connected between the second node and a sixth node; the third capacitor is connected between the third node and a seventh node; the fourth capacitor is connected between the fourth node and one end of the second coil; the sixth switch connects the fifth node and a reference potential point; the seventh switch connects the fifth node and the second node; the eighth switch connects the sixth node and the third node; the ninth switch connects the sixth node and the reference potential point; the tenth switch connects the seventh node and a reference potential point; the eleventh switch connects the seventh node and the fourth node; the twelfth switch connects the first coil and a reference potential point; the thirteenth switch connects the second coil and a reference potential point; the first, third, fifth, seventh, ninth, and eleventh switches are turned on and off simultaneously, the second, fourth, sixth, eighth, and tenth switches are turned on and off simultaneously at timings different from those of the first, third, fifth, seventh, nineth, and eleventh switches, and the tenth and eleventh switches are turned on and off at timings different from each other; The DCDC circuit according to claim 10.

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