Multilayer electronic component and its manufacturing method

Abstract

To provide a laminated electronic component.SOLUTION: A laminated electronic component includes a main body including a dielectric layer and internal electrodes arranged alternately with the dielectric layer, and an external electrode placed in the main body and connected to the internal electrode, and a composite layer containing Sn and Ni is arranged at the interface between the internal electrode and the dielectric layer, and the internal electrode includes an interface portion adjacent to the composite layer, and a central portion arranged between the interface portions, and the interface portion contains a ceramic additive.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a multilayer electronic component and a method for manufacturing the same. [Background technology]

[0002] Multi-layered ceramic capacitors (MLCCs), a type of multilayer electronic component, are chip-type capacitors that are mounted on printed circuit boards of various electronic products, such as visual devices like liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, smartphones, and mobile phones, and serve to charge and discharge electricity.

[0003] Such multilayer ceramic capacitors have the advantages of being small in size yet having high capacitance and being easy to mount, and therefore can be used as components in various electronic devices. In recent years, with the miniaturization of electronic device components, there has been an increasing demand for miniaturized and high-capacity multilayer ceramic capacitors.

[0004] In order to reduce the size and increase the capacitance of multilayer ceramic capacitors, a technology is needed that can reduce the thickness of the internal electrodes and dielectric layers.

[0005] However, as the internal electrodes and dielectric layers are made thinner, the interconnectivity of the internal electrodes may be reduced and the smoothness may be reduced, which may result in a decrease in reliability. Summary of the Invention [Problem to be solved by the invention]

[0006] One of the various objects of the present invention is to improve the reliability of multilayer electronic components.

[0007] One of the various objects of the present invention is to improve the electrode connectivity of the internal electrodes.

[0008] One of the various objects of the present invention is to increase the smoothness of the internal electrodes.

[0009] One of the various objects of the present invention is to provide a highly reliable, compact, and high-capacity laminated electronic component.

[0010] However, the scope of the present invention is not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Means for solving the problem]

[0011] A multilayer electronic component according to one embodiment of the present invention includes a main body including dielectric layers and internal electrodes alternately arranged with the dielectric layers, and external electrodes arranged on the main body and connected to the internal electrodes, wherein a composite layer containing Sn and Ni is arranged at an interface between the internal electrode and the dielectric layer, and the internal electrode includes an interface portion adjacent to the composite layer and a central portion arranged between the interface portions, and the interface portion contains a ceramic additive.

[0012] A method for manufacturing a multilayer electronic component according to another embodiment of the present invention includes the steps of: preparing ceramic green sheets; applying an internal electrode paste onto the ceramic green sheets to form an internal electrode pattern; stacking the ceramic green sheets on which the internal electrode pattern is formed to form a laminate; primarily calcining the laminate; secondary calcining the primarily calcined laminate; firing the secondary calcined laminate to form a body including dielectric layers and internal electrodes; and forming external electrodes on the body, wherein the internal electrode paste includes Sn powder, a ceramic additive, and a conductive powder, and the conductive powder has a core-shell structure, the core includes Ni, and the shell includes Ni, S, and O. [Effects of the Invention]

[0013] One of the various effects of the present invention is that it improves the reliability of multilayer electronic components.

[0014] One of the various effects of the present invention is that the shrinkage of the internal electrodes in the thickness direction is maximized and the shrinkage in the length and width directions is suppressed, thereby improving the connectivity and smoothness of the internal electrodes while making them thinner.

[0015] However, the various beneficial advantages and effects of the present invention are not limited to the above, and can be more easily understood in the course of describing specific embodiments of the present invention. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic perspective view of a multilayer electronic component according to an embodiment of the present invention; [Figure 2] 2 is a schematic cross-sectional view taken along line II' of FIG. 1. [Figure 3] 2 is a schematic cross-sectional view taken along line II-II' in FIG. 1. [Figure 4] 1 is an exploded perspective view showing a main body in which dielectric layers and internal electrodes are stacked according to an embodiment of the present invention; [Figure 5] FIG. 3 is an enlarged view of the P1 region in FIG. 2. [Figure 6] FIG. 6 is an enlarged view of the P2 region in FIG. 5. [Figure 7] (a) is a diagram for explaining the wettability of Sn and Ni, and (b) is a diagram for explaining the wettability of Sn and BaTiO3. [Figure 8] 10A to 10C are diagrams illustrating a method for manufacturing a multilayer electronic component according to another embodiment of the present invention. [Figure 9] 10A to 10C are diagrams illustrating a method for manufacturing a multilayer electronic component according to another embodiment of the present invention. [Figure 10] 10A to 10C are diagrams illustrating a method for manufacturing a multilayer electronic component according to another embodiment of the present invention. [Figure 11]10A to 10C are diagrams illustrating a method for manufacturing a multilayer electronic component according to another embodiment of the present invention. [Figure 12] FIG. 1 is a diagram showing an image scan of a cross section of a comparative example using a scanning electron microscope (SEM). [Figure 13] FIG. 1 is an image scanned of a cross section of an example of the invention using a scanning electron microscope (SEM). [Figure 14] This is an enlarged view of the interface between the internal electrode and the dielectric layer in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for clearer explanation.

[0018] In order to clearly explain the present invention, parts not relevant to the description are omitted in the drawings, and the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of explanation, and the present invention is not necessarily limited to those shown in the drawings. Furthermore, components that have the same function within the same concept will be described using the same reference numerals. Furthermore, throughout the specification, the term "comprises" a certain component does not mean to exclude other components, but means that other components may be further included, unless otherwise specified.

[0019] In the drawings, the first direction can be defined as the stacking direction or thickness (T) direction, the second direction as the length (L) direction, and the third direction as the width (W) direction.

[0020] [Multilayer electronic components] FIG. 1 is a schematic perspective view of a multilayer electronic component according to one embodiment of the present invention, FIG. 2 is a schematic cross-sectional view taken along line I-I' in FIG. 1, FIG. 3 is a schematic cross-sectional view taken along line II-II' in FIG. 1, FIG. 4 is an exploded perspective view of a main body in which dielectric layers and internal electrodes are laminated according to one embodiment of the present invention, FIG. 5 is an enlarged view of area P1 in FIG. 2, and FIG. 6 is an enlarged view of area P2 in FIG. 5.

[0021] A multilayer electronic component according to one embodiment of the present invention will be described in detail below with reference to FIGS.

[0022] A multilayer electronic component 100 according to one embodiment of the present invention is a multilayer electronic component including a main body 110 including dielectric layers 111 and internal electrodes 121, 122 arranged alternately with the dielectric layers, and external electrodes 131, 132 arranged on the main body and connected to the internal electrodes, wherein a composite layer CL containing Sn and Ni is arranged at the interface between the internal electrode and the dielectric layer, and the internal electrodes 121, 122 include an interface portion IP adjacent to the composite layer CL and a central portion CP arranged between the interface portions, and the interface portion IP contains a ceramic additive 23.

[0023] The body 110 is formed by alternately laminating dielectric layers 111 and internal electrodes 121 and 122 .

[0024] The specific shape of the body 110 is not particularly limited, but as shown, the body 110 may have a hexahedral shape or a shape similar thereto. Due to shrinkage of the ceramic powder contained in the body 110 during the firing process, the body 110 may have a substantially hexahedral shape, although not a hexahedral shape with perfectly straight lines.

[0025] The main body 110 may have first and second surfaces 1, 2 facing each other in a first direction, third and fourth surfaces 3, 4 connected to the first and second surfaces 1, 2 and facing each other in a second direction, and fifth and sixth surfaces 5, 6 connected to the first and second surfaces 1, 2 and also connected to the third and fourth surfaces 3, 4 and facing each other in the third direction.

[0026] The plurality of dielectric layers 111 constituting the body 110 are in a fired state, and the boundaries between adjacent dielectric layers 111 may be integrated to such an extent that they are difficult to identify without using a scanning electron microscope (SEM).

[0027] According to an embodiment of the present invention, the raw material for forming the dielectric layer 111 is not particularly limited as long as it can provide sufficient capacitance. For example, a barium titanate-based material, a lead complex perovskite-based material, or a strontium titanate-based material can be used. The barium titanate-based material can include a BaTiO3-based ceramic powder, and examples of the ceramic powder include BaTiO3, BaTiO3 partially solid-dissolved with Ca (calcium), Zr (zirconium), etc. 1-x Ca x )TiO3, Ba(Ti 1-y Ca y )O3, (Ba 1-x Ca x )(Ti 1-y Zr y )O3, or Ba(Ti 1-y Zr y )O3, etc.

[0028] The material for forming the dielectric layer 111 may be a powder of barium titanate (BaTiO3) or the like to which various ceramic additives, organic solvents, binders, dispersants, etc. may be added depending on the purpose of the present invention.

[0029] On the other hand, the thickness td of the dielectric layer 111 does not need to be particularly limited.

[0030] However, in general, when the dielectric layer is formed thinly, with a thickness of less than 0.6 μm, and particularly when the thickness of the dielectric layer is 0.41 μm or less, there is a risk of the reliability decreasing.

[0031] As described below, according to one embodiment of the present invention, by maximizing the shrinkage of the internal electrodes in the thickness direction, the internal electrodes can be made thinner while improving their connectivity and smoothness, thereby effectively improving reliability even when the dielectric layer is very thin. As a result, sufficient reliability can be ensured even when the dielectric layer is 0.41 μm or less in thickness.

[0032] Therefore, when the thickness of the dielectric layer 111 is 0.41 μm or less, the effect of improving reliability according to the present invention can be more significant.

[0033] The thickness td of the dielectric layer 111 may refer to the average thickness of the dielectric layer 111 disposed between the first internal electrode 121 and the second internal electrode 122.

[0034] The average thickness of the dielectric layer 111 can be measured by image scanning a cross section of the body 110 in the length and thickness direction (LT) using a scanning electron microscope (SEM).

[0035] For example, in an arbitrary dielectric layer extracted from an image obtained by scanning a cross section of the body 110 in the length and thickness direction (LT) cut at the center of the width direction using a scanning electron microscope (SEM), the thickness can be measured at 30 points equally spaced along the length, and the average value can be calculated.

[0036] The thickness measured at the 30 equally spaced points may be measured at a capacitance forming portion A, which means a region where the first and second internal electrodes 121 and 122 overlap each other.

[0037] The main body 110 is arranged inside the main body 110 and includes a first internal electrode 121 and a second internal electrode 122 arranged opposite each other with a dielectric layer 111 sandwiched therebetween, and may include a capacitance forming portion A in which capacitance is formed, and cover portions 112 and 113 formed on the upper and lower parts of the capacitance forming portion A.

[0038] The capacitance forming portion A is a portion that contributes to forming the capacitance of the capacitor, and can be formed by repeatedly laminating a plurality of first and second internal electrodes 121 and 122 with the dielectric layer 111 sandwiched therebetween.

[0039] The upper cover part 112 and the lower cover part 113 may be formed by stacking a single dielectric layer or two or more dielectric layers in the thickness direction on the upper and lower surfaces of the capacitance forming part A, respectively, and basically serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0040] The upper cover part 112 and the lower cover part 113 do not include an internal electrode and may include the same material as the dielectric layer 111 .

[0041] That is, the upper cover part 112 and the lower cover part 113 may include a ceramic material, for example, a barium titanate (BaTiO3) based ceramic material.

[0042] On the other hand, there is no need to particularly limit the thickness of the cover portions 112 and 113. However, in order to more easily achieve a smaller size and higher capacity of the multilayer electronic component, the thickness tp of the cover portions 112 and 113 can be 20 μm or less.

[0043] In addition, margin portions 114 and 115 may be arranged on the side surfaces of the capacitance forming portion A.

[0044] The margin portions 114, 115 may include a margin portion 114 disposed on the sixth surface 6 of the body 110 and a margin portion 115 disposed on the fifth surface 5. That is, the margin portions 114, 115 may be disposed on both side surfaces of the ceramic body 110 in the width direction.

[0045] The margin portions 114, 115 may refer to the regions between both ends of the first and second internal electrodes 121, 122 and the boundary surface of the body 110 in a cross section of the body 110 cut in the width-thickness (WT) direction, as shown in FIG. 3.

[0046] The margins 114 and 115 essentially serve to prevent damage to the internal electrodes due to physical or chemical stress.

[0047] The margin portions 114 and 115 can be formed by applying a conductive paste to the ceramic green sheet except for the areas where the margin portions are to be formed, thereby forming internal electrodes.

[0048] In addition, in order to reduce the steps caused by the internal electrodes 121, 122, margin portions 114, 115 may be formed by cutting the internal electrodes after lamination so that they are exposed on the fifth and sixth surfaces 5, 6 of the main body, and then laminating a single dielectric layer or two or more dielectric layers in the width direction on both sides of the capacitance forming portion A.

[0049] The internal electrodes 121 , 122 may be arranged alternately with the dielectric layers 111 .

[0050] The internal electrodes 121, 122 may include first and second internal electrodes 121, 122. The first and second internal electrodes 121, 122 are alternately arranged to face each other across the dielectric layer 111 constituting the body 110, and may be exposed to third and fourth surfaces 3, 4 of the body 110, respectively.

[0051] Referring to FIG. 2, the first internal electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second internal electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4.

[0052] In this case, the first and second internal electrodes 121 and 122 may be electrically isolated from each other by the dielectric layer 111 disposed therebetween.

[0053] Referring to FIG. 4, the body 110 can be formed by alternately stacking ceramic green sheets on which the first internal electrodes 121 are printed and ceramic green sheets on which the second internal electrodes 122 are printed, and then firing the stacked ceramic green sheets.

[0054] Referring to FIG. 6, a composite layer CL containing Sn and Ni is disposed at the interface between the internal electrodes 121, 122 and the dielectric layer 111, and the internal electrodes 121, 122 include an interface portion IP adjacent to the composite layer CL and a central portion CP disposed between the interface portions, and the interface portion IP may contain a ceramic additive 23.

[0055] A common conventional method for thinning the internal electrodes 121 and 122 is to print a thin layer of conductive paste to form the internal electrodes and then bake it. However, this method has the problem that shrinkage occurs in all directions during baking, which can cause the electrodes to break and reduce the smoothness of the internal electrodes.

[0056] In the present invention, by controlling the shrinkage behavior during sintering, it is possible to improve the connectivity and smoothness of the internal electrodes while making the internal electrodes thinner.

[0057] Normally, during sintering, shrinkage of 15 to 25% occurs in all directions, including the first, second, and third directions. However, in the present invention, the shrinkage of the internal electrodes in the first direction (thickness direction) during sintering is maximized, and the shrinkage in the second and third directions (length and width directions) is suppressed, thereby making it possible to improve the connectivity and smoothness of the internal electrodes while making them thinner.

[0058] 7(a) is a diagram illustrating the wettability of Sn and Ni, and FIG. 7(b) is a diagram illustrating the wettability of Sn and BaTiO3. Referring to FIG. 7, it can be seen that Sn and Ni have high wettability with a contact angle (θ1) of 90 degrees or less, and Sn and BaTiO3 have low wettability with a contact angle (θ2) of more than 90 degrees. The composite layer CL containing Sn and Ni has low wettability with the ceramic additive 23, and therefore acts as a barrier that prevents the ceramic additive 23 from migrating to the dielectric layer 111, allowing the ceramic additive 23 to be trapped at the interface IP.

[0059] The ceramic additive 23 is trapped in the interface IP, suppressing sintering shrinkage in the lateral direction, and the center CP is constrained by the interface IP, causing concentrated shrinkage in the thickness direction. This allows the internal electrodes to be made thinner while improving their connectivity and smoothness.

[0060] In one embodiment, the interface portion IP may be a region from the interface between the composite layer CL and the internal electrodes 121 and 122 to a depth of 1 / 3 of the thickness of the internal electrodes.

[0061] That is, when the internal electrode is divided into three equal parts in the first direction, the central portion CP may be disposed between the interface portions IP.

[0062] On the other hand, the interface portion IP can contain the ceramic additive 23 in an amount of 5 to 15% by area.

[0063] If the ceramic additive 23 is less than 5% by area in the interface IP, the effect of the ceramic additive 23 in suppressing sintering shrinkage in the transverse direction is insufficient, and if it exceeds 15% by area, the content of the ceramic additive is too high, which is actually disadvantageous in thinning the internal electrodes.

[0064] The area % of the ceramic additive contained in the interface portion IP may be determined by measuring the area occupied by the ceramic additive in a region up to a depth of 1 / 3 of the thickness of the internal electrodes in any five internal electrodes extracted from an image obtained by scanning a cross section in the first and second directions (length and thickness directions) cut at the center of the third direction (width direction) of the main body 110 using a scanning electron microscope (SEM), and calculating the average value.

[0065] The central portion CP may also contain a ceramic additive, but may contain less ceramic additive than the interface portion IP. Alternatively, the central portion CP may not contain any ceramic additive.

[0066] As a specific example, the area % of the ceramic additive in the central portion CP can be half or less of the area % of the ceramic additive 23 in the interface portion IP. Also, the area % of the ceramic additive in the central portion CP can be less than 5 area %.

[0067] In one embodiment, the Sn concentration of the composite layer CL can be five times or more the Sn concentration of the central portion CP.

[0068] This is because if the Sn concentration in the composite layer CL is less than five times the Sn concentration in the central portion CP, the effect of trapping the ceramic additive 23 in the interface portion IP may be insufficient.

[0069] The ratio of the Sn concentration in the composite layer CL to the Sn concentration in the central portion CP can be determined by performing an EDS (Energy Disperse X-ray Spectrometer) line scan analysis along the thickness direction of any five internal electrodes extracted from an image obtained by scanning a cross section in the first and second directions (length and thickness directions) cut at the central portion of the third direction (width direction) of the main body 110 using a scanning electron microscope (SEM), measuring the ratio of the Sn concentration at the center in the thickness direction to the Sn concentration in the composite layer CL, and calculating the average value.

[0070] In one embodiment, the composite layer CL may contain the Sn and Ni in the form of Ni3Sn.

[0071] The Ni3Sn contained in the composite layer CL can be confirmed by analyzing the interface between the internal electrodes 121, 122 and the dielectric layer 111 using a Selected Area Diffraction Pattern (SAD).

[0072] In one embodiment, the ceramic additive 23 included in the interface IP can be BaTiO3.

[0073] This is because BaTiO3 has high wettability with Sn, and therefore the composite layer CL containing Ni and Sn can have a more pronounced effect of suppressing the ceramic additive 23 from migrating to the dielectric layer 111.

[0074] In one embodiment, the internal electrodes 121 and 122 may contain Ni as a main component. Sn contained in the internal electrodes 121 and 122 liquefies at 232°C or higher and migrates to the interface to form intermetallic compounds with Ni. In addition, the internal electrodes 121 and 122 may contain Ni as a main component and one or more of copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0075] In one embodiment, the thickness of the composite layer CL may be 10 to 30 nm.

[0076] If the thickness of the composite layer CL is less than 10 nm, it does not function as a barrier sufficiently, and if it exceeds 30 nm, delamination may occur due to early shrinkage during sintering.

[0077] On the other hand, the thickness te of the internal electrodes 121 and 122 does not need to be particularly limited.

[0078] However, in general, when the internal electrodes 121 and 122 are formed thinly with a thickness of less than 0.6 μm, particularly when the thickness of the internal electrodes 121 and 122 is 0.41 μm or less, the connectivity and smoothness of the internal electrodes may be reduced.

[0079] As described above, according to one embodiment of the present invention, by maximizing the shrinkage of the internal electrodes in the thickness direction, the internal electrodes can be made thinner while improving the connectivity and smoothness of the internal electrodes. Therefore, even when the thickness of the internal electrodes 121 and 122 is 0.41 μm or less, excellent connectivity and smoothness of the internal electrodes can be ensured.

[0080] Therefore, when the thickness of the internal electrodes 121, 122 is 0.41 μm or less, the effect of the present invention becomes more pronounced, and the miniaturization and high capacitance of the capacitor component can be more easily achieved.

[0081] The thickness te of the internal electrodes 121 and 122 may refer to the average thickness of the internal electrodes 121 and 122.

[0082] The average thickness of the internal electrodes 121 and 122 can be measured by image scanning a cross section of the body 110 in the length and thickness direction (LT) using a scanning electron microscope (SEM).

[0083] For example, the thickness of any first and second internal electrodes 121, 122 extracted from an image obtained by scanning a cross section of the main body 110 in the first and second directions (length and thickness directions) cut at the center of the third direction (width direction) using a scanning electron microscope (SEM) can be measured at 30 equally spaced points in the length direction, and the average value can be calculated.

[0084] In one embodiment, the internal electrodes 121 and 122 may have an internal electrode connectivity of 85% or more.

[0085] The connectivity of the internal electrodes may be defined as the ratio of the length of the portion where the internal electrodes are actually formed to the total length of the internal electrodes.

[0086] For example, as shown in FIG. 5, if the total length of the internal electrode 121 measured at any one point is defined as b, and the lengths of the portions where the electrodes are actually formed are defined as e1, e2, e3, and e4, respectively, the connectivity of the internal electrodes can be expressed as e / b, which is the sum of the lengths of the portions where the electrodes are actually formed (e=e1+e2+e3+e4) divided by the total length of the electrode, b.

[0087] If the connectivity of the internal electrodes is less than 85%, it may be difficult to ensure sufficient capacitance.

[0088] According to one embodiment of the present invention, the shrinkage of the internal electrodes in the thickness direction is maximized, thereby improving the connectivity of the internal electrodes while making the internal electrodes thinner, thereby ensuring the connectivity of the internal electrodes to be 85% or more.

[0089] There is no need to particularly limit the upper limit of the connectivity of the internal electrodes, but in consideration of the manufacturing process, the upper limit may be 97%.

[0090] The outer electrodes 131 and 132 are disposed on the body 110 and connected to the inner electrodes 121 and 122 .

[0091] As shown in FIG. 2, the first and second external electrodes 131 and 132 may be disposed on the third and fourth surfaces 3 and 4 of the body 110, respectively, and connected to the first and second internal electrodes 121 and 122, respectively.

[0092] In this embodiment, the multilayer electronic component 100 has two external electrodes 131 and 132, but the number and shape of the external electrodes 131 and 132 may vary depending on the shape of the internal electrodes 121 and 122 and other purposes.

[0093] Meanwhile, the external electrodes 131 and 132 may be formed using any material that has electrical conductivity, such as a metal, and the specific material may be determined taking into consideration electrical properties, structural stability, etc., and may further have a multi-layer structure.

[0094] For example, the external electrodes 131 and 132 may include electrode layers 131a and 132a disposed on the main body 110 and plating layers 131b and 132b formed on the electrode layers 131a and 132a.

[0095] As a more specific example of the electrode layers 131a and 132a, the electrode layers 131a and 132a may be fired electrodes containing a conductive metal and glass, or may be resin-based electrodes containing a conductive metal and resin.

[0096] The electrode layers 131a and 132a may be formed by sequentially forming a fired electrode and a resin-based electrode on the main body, and may be formed by transferring a sheet containing a conductive metal onto the main body, or by transferring a sheet containing a conductive metal onto a fired electrode.

[0097] The conductive metal contained in the electrode layers 131a and 132a may be, but is not limited to, a material with excellent electrical conductivity. For example, the conductive metal may be one or more of nickel (Ni), copper (Cu), and alloys thereof.

[0098] The plating layers 131b and 132b serve to improve mounting characteristics. The type of the plating layers 131b and 132b is not particularly limited, and may be a plating layer containing one or more of Ni, Sn, Pd, and alloys thereof, and may be formed of multiple layers.

[0099] As a more specific example of the plating layers 131b, 132b, the plating layers 131b, 132b may be Ni plating layers or Sn plating layers, and may have a form in which a Ni plating layer and a Sn plating layer are formed in this order on the electrode layers 131a, 132a, or a form in which a Sn plating layer, a Ni plating layer, and a Sn plating layer are formed in this order. Also, the plating layers 131b, 132b may include multiple Ni plating layers and / or multiple Sn plating layers.

[0100] The size of the multilayer electronic component 100 does not need to be particularly limited.

[0101] However, in order to achieve both miniaturization and high capacity, it is necessary to reduce the thickness of the dielectric layers and internal electrodes and increase the number of layers. Therefore, the reliability improvement effect of the present invention can be more pronounced in multilayer electronic components 100 having a size of 0402 (length x width, 0.4 mm x 0.2 mm) or less.

[0102] Therefore, taking into consideration manufacturing errors, the size of the external electrodes, etc., the reliability improvement effect of the present invention can be more significant when the length of the multilayer electronic component 100 is 0.44 mm or less and the width is 0.22 mm or less. Here, the length of the multilayer electronic component 100 may refer to the size of the multilayer electronic component 100 in the second direction, and the width of the multilayer electronic component 100 may refer to the size of the multilayer electronic component 100 in the third direction.

[0103] [Manufacturing method for multilayer electronic components] 8 to 11 are diagrams illustrating a method for manufacturing a multilayer electronic component according to another embodiment of the present invention.

[0104] A method for manufacturing a multilayer electronic component according to another embodiment of the present invention will now be described with reference to FIGS.

[0105] A method for manufacturing a multilayer electronic component according to another embodiment of the present invention includes the steps of: preparing ceramic green sheets; applying an internal electrode paste onto the ceramic green sheets to form an internal electrode pattern; stacking the ceramic green sheets on which the internal electrode pattern is formed to form a laminate; primarily calcining the laminate; secondary calcining the primarily calcined laminate; firing the secondary calcined laminate to form a body including dielectric layers and internal electrodes; and forming external electrodes on the body, wherein the internal electrode paste includes Sn powder 22, a ceramic additive 23, and a conductive powder 21, and the conductive powder has a core 21a-shell 21b structure, the core 21a includes Ni, and the shell 21b includes Ni, S, and O.

[0106] <Preparing ceramic green sheets> First, a ceramic green sheet for forming the dielectric layer 111 is prepared.

[0107] The ceramic green sheet is used to form the dielectric layer 111 of the body 110. The ceramic powder 11, a polymer, and a solvent are mixed to prepare a slurry, which can then be formed into a sheet having a predetermined thickness using a method such as a doctor blade.

[0108] <Step of forming internal electrode pattern> Then, a conductive paste for internal electrodes is printed to a predetermined thickness on at least one surface of each of the ceramic green sheets to form internal electrodes. The conductive paste for internal electrodes can be printed by screen printing, gravure printing, or the like.

[0109] The internal electrode paste includes Sn powder, a ceramic additive, and a conductive powder, and the conductive powder has a core-shell structure, the core including Ni, and the shell including Ni, S, and O. By forming the internal electrodes using this internal electrode paste, shrinkage of the internal electrodes in the first direction (thickness direction) during sintering is maximized and shrinkage in the second and third directions (length and width directions) is suppressed, thereby improving the connectivity and smoothness of the internal electrodes while making the internal electrodes thinner. In addition, the internal electrode structure of the multilayer electronic component according to the above-mentioned embodiment of the present invention can be more easily realized.

[0110] 8 shows that a conductive paste for internal electrodes containing Sn powder 22, a ceramic additive 23, and conductive powder 21 is printed on a ceramic green sheet containing ceramic powder 11. The conductive powder 21 has a core 21a-shell 21b structure, with the core 21a containing Ni and the shell 21b containing Ni, S, and O.

[0111] The Ni, S, and O contained in the shell 21b can play a role in delaying the contraction of Ni at low temperatures.

[0112] If the shell has a Ni-O structure that does not contain S, the O on the surface reacts with C in the early stage of the secondary calcination to generate CO, CO2, etc., which are then volatilized, making it difficult to delay the shrinkage of Ni.

[0113] In contrast, when the shell 21b contains Ni, S, and O as in the present invention, S and O are strongly bonded, allowing the retention of an oxide film at the beginning of secondary calcination, thereby delaying Ni contraction. In addition, by delaying necking between Ni particles 21a, it can provide a path for the ceramic additive 23 to move to the interface of the internal electrode.

[0114] In one embodiment, the conductive powder may have an average size of less than 100 nm.

[0115] To form thin internal electrodes, it is advantageous to use fine conductive powder. With typical fine conductive powders, the sintering shrinkage start temperature is lower, but the difference in sintering start temperature between the powder and the dielectric layer becomes large, which can lead to defects such as delamination.

[0116] However, according to the present invention, Ni, S, and O contained in the shell 21b of the conductive powder 21 can play a role in delaying the contraction of Ni at low temperatures, thereby suppressing defects such as delamination even when using fine powder of less than 100 nm.

[0117] In one embodiment, in the core-shell structure, the shell 21b may contain 1000 to 2000 ppm of S.

[0118] The finer the conductive powder, the higher the S content required to achieve sufficient shrinkage retardation. When conductive powder with an average particle size of 100 nm or less is coated with 1000 ppm or more of S, sufficient shrinkage retardation effect can be achieved. When S exceeds 2000 ppm, there is no significant difference in terms of shrinkage retardation effect.

[0119] In one embodiment, Ni—O may be disposed on the surface of the shell 21 b. When the nano-sized metal powder is exposed to the air, it reacts with oxygen to cause an exothermic reaction, but Ni—O may be disposed on the surface of the shell 21 b to prevent this.

[0120] In one embodiment, the amount of Sn powder 22 may be 0.3 to 1.0 wt% relative to 100 wt% of the conductive powder 21. If the amount of Sn powder 22 is less than 0.3 wt%, it is insufficient to form a composite layer CL of 10 nm or more, and if it exceeds 1.0 wt%, the composite layer CL is formed to an excessive thickness of 30 nm or more, which may promote sintering shrinkage and cause delamination defects.

[0121] In one embodiment, the ceramic additive 23 may be 5 to 20 wt% relative to 100 wt% of the conductive powder 21. When a conductive powder with an average particle size of 100 nm or less is used as the main material for the internal electrodes 121, 122, 5 wt% or more of the additive is required relative to 100 wt% of the conductive powder. As the average particle size becomes smaller, a higher content of the ceramic additive is required to suppress sintering shrinkage. If the proportion of the ceramic additive exceeds 20 wt% relative to 100 wt% of the conductive powder, it is disadvantageous in thinning the internal electrodes.

[0122] In one embodiment, the ceramic additive 23 can be BaTiO3.

[0123] This is because BaTiO3 has high wettability with Sn, and therefore the composite layer CL containing Ni and Sn can have a more pronounced effect of suppressing the ceramic additive 23 from migrating to the ceramic green sheet.

[0124] <Laminate formation stage> The ceramic green sheets on which the internal electrode patterns are formed are stacked to form a laminate, which can be pressure-bonded by applying pressure in the stacking direction (first direction).

[0125] In this case, the laminate can be cut into chips in regions corresponding to the main body of one multilayer electronic component, and can be cut so that one end of the internal electrode patterns is alternately exposed through both end surfaces in the second direction.

[0126] <Primary calcination stage> Thereafter, the laminate may be subjected to primary calcination.

[0127] Referring to FIG. 9, during the primary calcination step, Sn powder 22, which has a low melting point, moves in a liquid form to the interface with the ceramic sheet, and since Sn has low wettability with the ceramic powder 11, it is arranged at the interface as a layer 22'.

[0128] In one embodiment, the primary calcination step may be performed at a temperature of 250 to 350°C in a moderate reducing atmosphere. The Sn powder may be in a liquid state within this temperature range, and since Sn has high oxidation reactivity, heat treatment in a moderate reducing atmosphere may prevent oxidation of Sn.

[0129] In this case, the medium reducing atmosphere for preventing oxidation of Sn may be a gas atmosphere in which nitrogen (N2) gas and 0.2 to 1.0 vol. % of hydrogen (H2) gas are mixed.

[0130] <Secondary calcination stage> Thereafter, the primary calcined laminate may be subjected to a secondary calcination step.

[0131] When the shell 21b of the conductive powder 21 contains Ni, S, and O, S and O are strongly bonded to each other, allowing an oxide film to be formed at the beginning of the secondary calcination, thereby delaying the shrinkage of Ni. In addition, by delaying necking between Ni particles 21a, the shell 21b can provide a path for the ceramic additive 23 to move to the interface of the internal electrode.

[0132] Figure 10 is a schematic diagram showing the state after secondary calcination is completed. Referring to Figure 10, the Sn layer and Ni particles react at the interface with the ceramic sheet to form a composite layer CL containing Sn and Ni, and the ceramic additive 23 migrates to the interface with the composite layer CL. The composite layer CL containing Sn and Ni has low wettability with the ceramic additive, so it acts as a barrier that prevents the ceramic additive 23 from migrating toward the ceramic green sheet, allowing the ceramic additive 23 to be trapped at the interface.

[0133] In one embodiment, the secondary calcination step may be performed at 600 to 900° C. In this temperature range, the formation of the composite layer CL containing Sn and Ni and the migration of the ceramic additive 23 may be facilitated.

[0134] <Sintering stage> The secondary calcined laminate can then be sintered to form a body including the dielectric layers and internal electrodes.

[0135] 11, the ceramic additive 23 is trapped in the interface portion IP, suppressing sintering shrinkage in the lateral direction, while the central portion CP is constrained by the interface portion IP, causing concentrated shrinkage in the thickness direction. This allows the internal electrodes to be made thinner while improving their connectivity and smoothness. Then, the ceramic powder 11 is sintered to form the dielectric layer 111.

[0136] In one embodiment, the sintering process may be performed in a reducing atmosphere. The sintering process may be performed by controlling the temperature rise rate, which may be, but is not limited to, 30°C / 60s to 50°C / 60s at a temperature of 700°C or less, and the sintering temperature may be 900 to 1300°C.

[0137] <External electrode formation stage> Thereafter, a step of forming an external electrode on the body may be performed.

[0138] In this case, first and second external electrodes 131 and 132 may be formed to cover the exposed portions of the first and second internal electrodes 121 and 122 exposed at both end surfaces in the second direction of the body 110 and to be electrically connected to the first and second internal electrodes.

[0139] Furthermore, the surfaces of the first and second external electrodes 131, 132 may be plated with nickel, tin, palladium, or the like, if necessary.

[0140] [(Example)] The sample chips of the invention and comparative examples were fabricated by laminating ceramic green sheets printed with conductive paste for internal electrodes to form a laminate, followed by primary calcination, secondary calcination, and sintering processes to form external electrodes. The conditions other than the conductive paste for internal electrodes were the same for the invention and comparative examples.

[0141] In the comparative example, a conductive paste for internal electrodes containing Ni powder with an average size of 60 nm and BaTiO3 powder with an average size of 10 nm as a ceramic additive was used.

[0142] In the example of the present invention, a conductive paste for internal electrodes was used, which contained a conductive powder with a core-shell structure in which the core contained Ni and the shell contained Ni, S, and O, a ceramic additive, and Sn powder. The average size of the conductive powder was 60 nm, the average size of the ceramic additive was 10 nm, and the average size of the Sn powder was 60 nm. 1 wt% of the Sn powder was added to 100 wt% of the conductive powder. The ceramic additive was BaTiO3.

[0143] Comparing Figure 12 (Comparative Example) and Figure 13 (Example of the Invention), which are image scans of cross sections cut in the first and second directions at the center of the third direction of the sample chip using a scanning electron microscope (SEM), it can be seen that the smoothness of the internal electrodes in the Example of the Invention is significantly improved compared to the Comparative Example.

[0144] In addition, the length of the portion where the internal electrodes were actually formed was measured relative to the total length of all internal electrodes in the above cross-sectional image, and the electrode connectivity of each internal electrode was calculated.The average value was then calculated, and it was confirmed that the connectivity of the internal electrodes in the example of the invention was 93%, and the connectivity of the internal electrodes in the comparative example was 84%, which was a 9% improvement in the connectivity of the internal electrodes.

[0145] Furthermore, the average thickness of the internal electrodes of the invention example was reduced by 5.8% compared to the comparative example.

[0146] Referring to Figure 14, which is an enlarged view of the interface between the internal electrode and the dielectric layer in Figure 13, it can be seen that a composite layer containing Ni and Sn is disposed at the interface between the dielectric layer and the internal electrode, and that the co-material is trapped at the interface of the internal electrode.

[0147] Table 1 below shows the area occupied by the ceramic additive in the region (interface) up to a depth of 1 / 3 of the thickness of the internal electrode for any five internal electrodes extracted from an image scanned with a scanning electron microscope (SEM) of a cross section in the first and second directions (length and thickness directions) cut at the center of the third direction (width direction) of the main body of an example of the invention, and lists each value and its average value.

[0148] [Table 1]

[0149] As can be seen from Table 1 above, in the invention example, the interface IP can contain 5 to 15 area % of the ceramic additive 23.

[0150] Table 2 below shows the results of EDS (Energy Disperse X-ray Spectrometer) line scan analysis performed along the thickness direction of the internal electrodes on five randomly selected internal electrodes extracted from an image obtained by scanning a cross section of the body of an example of the invention in the first and second directions (length and thickness directions) cut at the center of the third direction (width direction) of the body, and measuring the Sn concentration at the center of the thickness direction and the ratio of the Sn concentration in the composite layer CL, and listing the respective values ​​and their average values.

[0151] [Table 2]

[0152] Referring to Table 2 above, it can be seen that the Sn concentration in the composite layer CL is five times or more higher than the Sn concentration in the central portion CP.

[0153] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments and the accompanying drawings, but is limited only by the appended claims. Therefore, various substitutions, modifications, and alterations can be made by those skilled in the art without departing from the technical spirit of the present invention as set forth in the claims, and these also fall within the scope of the present invention. [Explanation of symbols]

[0154] 100 Multilayer electronic components 110 Main Unit 111 Dielectric layer 112, 113 Cover 114, 115 Margin 121, 122 Internal electrode 131, 132 External electrode 131a Electrode layer 132b plating layer

Claims

1. a body including dielectric layers and internal electrodes alternating with the dielectric layers; an external electrode disposed on the main body and connected to the internal electrode, a composite layer containing Sn and Ni is disposed at the interface between the internal electrode and the dielectric layer; the internal electrode has an interface portion adjacent to the composite layer and a central portion disposed between the interface portions, the interface portion including a ceramic additive at an interface with the composite layer; The central portion does not contain a ceramic additive, or the area percentage of the ceramic additive in the central portion is lower than the area percentage of the ceramic additive in the interface portion.

2. 2. The multilayer electronic component according to claim 1, wherein the interface portion is a region extending from the interface between the composite layer and the internal electrode to a depth of one-third of the thickness of the internal electrode.

3. 3. The multilayer electronic component according to claim 2, wherein the interface portion contains the ceramic additive in an amount of 5 to 15% by area.

4. 4. The multilayer electronic component according to claim 2, wherein the area percentage of the ceramic additive in the central portion is equal to or less than half the area percentage of the ceramic additive in the interface portion.

5. 5. The multilayer electronic component according to claim 1, wherein the Sn concentration in the composite layer is at least five times the Sn concentration in the central portion.

6. The composite layer is made of Sn and Ni. ３ The multilayer electronic component according to claim 1 , wherein the metal is in the form of Sn.

7. The ceramic additive is BaTiO ３ The multilayer electronic component according to claim 1 , wherein

8. The multilayer electronic component according to claim 1 , wherein the internal electrodes contain Ni as a main component.

9. 9. The multilayer electronic component according to claim 1, wherein the composite layer has an average thickness of 10 to 30 nm.

10. 10. The multilayer electronic component according to claim 1, wherein the internal electrodes have an average thickness of 0.41 μm or less.

11. The multilayer electronic component according to claim 1 , wherein the internal electrodes have a connectivity of 85% or more.

12. providing a ceramic green sheet; applying an internal electrode paste onto the ceramic green sheet to form an internal electrode pattern; forming a laminate by stacking the ceramic green sheets on which the internal electrode patterns are formed; a step of primarily calcining the laminate; Secondary calcination of the primary calcined laminate; firing the secondary calcined laminate to form a body including dielectric layers and internal electrodes; forming external electrodes on the main body, The internal electrode paste includes Sn powder, a ceramic additive, and a conductive powder, The conductive powder has a core-shell structure, the core contains Ni, and the shell contains Ni, S, and O.

13. The method for producing a multilayer electronic component according to claim 12, wherein the conductive powder has an average size of less than 100 nm.

14. The method for producing a multilayer electronic component according to claim 12 or 13, wherein the shell contains 1000 to 2000 ppm of S.

15. The method for producing a multilayer electronic component according to claim 12 , wherein NiO is disposed on a surface of the shell.

16. 16. The method for producing a multilayer electronic component according to claim 12, wherein the Sn powder is 0.3 to 1.0 wt % relative to 100 wt % of the conductive powder.

17. 17. The method for producing a multilayer electronic component according to claim 12, wherein the ceramic additive is contained in an amount of 5 to 20 wt % relative to 100 wt % of the conductive powder.

18. The ceramic additive is BaTiO ３ The method for producing a multilayer electronic component according to any one of claims 12 to 17, wherein

19. The method for manufacturing a multilayer electronic component according to any one of claims 12 to 18, wherein the primary calcination is carried out at a temperature of 250 to 350°C in a moderate reducing atmosphere.

20. The medium reducing atmosphere is nitrogen (N ２ ) gas and 0.2 to 1.0 vol. % hydrogen (H ２ 20. The method for producing a multilayer electronic component according to claim 19, wherein the gas atmosphere is a mixture of a gas containing a gas containing a metal oxide and a gas containing a metal oxide.

21. The method for manufacturing a multilayer electronic component according to any one of claims 12 to 20, wherein the secondary calcination is performed at 600 to 900°C.

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