Electrical device and semiconductor device including same

Abstract

To provide an electric device and a semiconductor device including the same.SOLUTION: An electric device includes a lower electrode, an upper electrode, which is disposed apart from the lower electrode, and a dielectric layer being disposed between the lower electrode and the upper electrode and including a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer. The third metal oxide layer is disposed between the first metal oxide layer and the second metal oxide layer, and contains boron (B) and one or two or more metal elements selected from a group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be). The third metal oxide layer contains boron (B) less than aluminum (Al), magnesium (Mg), silicon (Si), and / or beryllium (Be) metal element.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an electric device and a semiconductor device including the same. [Background technology]

[0002] As electronic devices are downscaled, the space occupied by electrical devices within the electronic devices is also reduced. This requires that the size of electrical devices such as capacitors be reduced, as well as the thickness of the capacitor dielectric layer. However, in such cases, a large leakage current occurs through the capacitor's dielectric layer, making it difficult to operate the device. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide an electric device having a high electric capacity and a low leakage current value, and a semiconductor device including the same. The present invention also provides an electrical device having a dielectric layer comprising three or more metal oxide layers. The present invention also provides an electrical device having a dielectric layer comprising a metal oxide layer containing three or more metal elements. [Means for solving the problem]

[0004] An electrical device according to one embodiment may include a lower electrode, an upper electrode spaced apart from the lower electrode, and a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer.

[0005] The first metal oxide layer and the second metal oxide layer each independently have a dielectric constant of 20 or greater and 70 or less.

[0006] The third metal oxide layer is disposed between the first metal oxide layer and the second metal oxide layer, and contains one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), and boron (B).

[0007] The first metal oxide layer, the third metal oxide layer, and the second metal oxide layer may be sequentially disposed in the thickness direction of the dielectric layer.

[0008] The third metal oxide layer has a boron (B) content that is less than or equal to the content of aluminum (Al), magnesium (Mg), silicon (Si), and / or beryllium (Be) metal elements.

[0009] The third metal oxide layer may further contain one or more metal elements selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu.

[0010] The third metal oxide layer is AB a C 1-a O. A is one or more selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu, B is boron (B), C is one or more selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), and a is greater than 0.00 and equal to or less than 0.50.

[0011] The first metal oxide layer is disposed adjacent to the bottom electrode, and the thickness of the first metal oxide layer is also greater than or equal to 40% of the total thickness of the dielectric layer.

[0012] The ratio of the thickness of the third metal oxide layer to the thickness of the first metal oxide layer is also equal to or greater than 0.3 and less than 1.0.

[0013] An electrical device according to another embodiment may include a lower electrode, an upper electrode spaced apart from the lower electrode, and a dielectric layer disposed between the lower electrode and the upper electrode and including three or more metal elements.

[0014] The dielectric layer may include a first metal element selected from the group consisting of one or more of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu, a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), and boron (B).

[0015] The content of boron (B) in the dielectric layer is less than or equal to the content of the second metallic element. The content of boron (B) is more than 0.0 at% and less than 3.0 at% relative to the total metal elements in the dielectric layer. The content of the first metal element is more than 92 at% and less than 100 at% relative to the total metal elements in the dielectric layer. The content of the second metal element is more than 0.0 at% and less than 5.0 at% relative to the total metal elements in the dielectric layer.

[0016] The boron (B) may have a concentration gradient in the thickness direction of the dielectric layer. The dielectric layer has, in the thickness direction, a lower surface facing the lower electrode, an inner region located on the lower surface, and an upper surface located on the inner region and facing the upper electrode, in that order, with the boron content in the inner region being higher than the boron content in the lower surface, the upper surface, or both. The boron (B) has a maximum concentration at a position 40% to 90% of the dielectric layer thickness away from the lower electrode.

[0017] The electrical device according to the embodiment has a resistance of 1.0×10 when a voltage of 1.0 V is applied. -4 A / cm 2 The following leakage current values ​​are shown: [Effects of the Invention]

[0018] According to an embodiment of the present invention, an electrical device having high capacitance and excellent leakage current blocking / reducing properties and a semiconductor device including the same can be provided, which realizes improved integration and contributes to the miniaturization of electronic devices. [Brief explanation of the drawings]

[0019] [Figure 1] 1 is a schematic diagram of an electrical device according to an embodiment. [Figure 2] 1 is a schematic diagram of an electrical device according to an embodiment. [Figure 3] 1 is a schematic diagram of an electrical device according to an embodiment. [Figure 4] 1 is a schematic diagram of a semiconductor device according to an embodiment; [Figure 5] FIG. 1 is a layout diagram of a semiconductor device according to an embodiment. [Figure 6] 6 is a cross-sectional view of the semiconductor device taken along line AA' in FIG. 5. [Figure 7] 6 is a cross-sectional view of the semiconductor device taken along line AA' in FIG. 5. [Figure 8] 1 is a conceptual diagram illustrating a device architecture applied to an electronic device according to an embodiment; [Figure 9] 1 is a conceptual diagram illustrating a device architecture applied to an electronic device according to an embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0020] The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the technical concept. The terms "upper" and "above" include not only those directly above / below / left / right in contact, but also those directly above / below / left / right in non-contact.

[0021] The singular includes the plural unless the context clearly dictates otherwise. It should be understood that the terms "comprise" or "have" and the like indicate the presence of a feature, number, step, operation, component, part, ingredient, material, or combination thereof stated in the specification, unless specifically stated to the contrary, but do not preclude the presence or possible addition of one or more other features, numbers, steps, operations, components, parts, ingredients, materials, or combinations thereof.

[0022] Terms such as "first," "second," and "third" are used to describe various components, but are used only to distinguish one component from another, and do not limit the order or type of the components. Furthermore, terms such as "unit," "means," "module," and "section" refer to a comprehensive structural unit that processes a certain function or operation, and may be realized by hardware or software, or by a combination of hardware and software.

[0023] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Hereinafter, the same reference numerals in the drawings refer to the same elements, and the size of each element (such as width and thickness of a region) in the drawings may be exaggerated for clarity and convenience. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0024] According to one aspect, an electric device having low leakage current and high capacitance can be provided. The electric device is also a capacitor.

[0025] 1 is a schematic diagram of a capacitor according to an embodiment. Referring to FIG. 1, the capacitor 1 may include a lower electrode 100, an upper electrode 200 spaced apart from the lower electrode 100, and a dielectric layer 300 disposed between the lower electrode 100 and the upper electrode 200.

[0026] The lower electrode 100 may be disposed on a substrate (not shown). The substrate may be part of a structure supporting the capacitor or part of a device connected to the capacitor. The substrate may include a semiconductor material pattern, an insulating material pattern, and / or a conductive material pattern. The substrate may include, for example, the substrate 11′, gate stack 12, interlayer insulating layer 15, contact structure 20′, and / or bit line structure 13 shown in FIGS. 6 and 7 (described below). The substrate may also include a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc., and / or an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0027] The upper electrode 200 may be disposed opposite the lower electrode 100 at a distance. The lower electrode 100 and / or the upper electrode 200 may each independently include a metal, a metal nitride, a metal oxide, or a combination thereof. Specifically, the lower electrode 100 and / or the upper electrode 200 may each independently include a metal such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), or the like. ), and / or conductive metal oxides such as platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenium oxide (SrRuO3), barium strontium ruthenium oxide ((Ba,Sr)RuO3), calcium ruthenium oxide (CaRuO3), lanthanum strontium cobalt oxide ((La,Sr)CoO3).

[0028] For example, the bottom electrode 100 and / or the top electrode 200 may each independently include a metal nitride represented as M-M'-N, where M is a metal element, M' is an element different from M, and N is nitrogen. Such a metal nitride may include an M-N metal nitride doped with element M'. M is Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, One or more elements selected from Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. M' is H, Li, Be, B, N, O, Na, Mg, Al, Si, P, S, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, As, Se, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs , Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. In the metal nitride MM'N, when the composition ratio of M, M', and N is x:y:z, 0≦x≦2, 0≦y≦2, 0 <z≦4でもあり、xとyのうち、1つは、0ではない。

[0029] The bottom electrode 100 and / or the top electrode 200 may each independently be a single material layer or a laminated structure of multiple material layers. For example, the bottom electrode 100 and / or the top electrode 200 may each independently be a single layer of titanium nitride (TiN) or a single layer of niobium nitride (NbN). Alternatively, the bottom electrode 100 and / or the top electrode 200 may have a laminated structure including a first electrode layer containing titanium nitride (TiN) and a second electrode layer containing niobium nitride (NbN).

[0030] The dielectric layer 300 includes a first metal oxide layer 310, a second metal oxide layer 330, and a third metal oxide layer 320. The first metal oxide layer 310 may be disposed adjacent to the lower electrode 100, the second metal oxide layer 330 may be disposed facing the first metal oxide layer 310 at a distance, and the third metal oxide layer 320 may be disposed between the first metal oxide layer 310 and the second metal oxide layer 330. That is, the first metal oxide layer 310, the third metal oxide layer 320, and the second metal oxide layer 330 may be sequentially disposed in the thickness direction of the dielectric layer 300.

[0031] The first metal oxide layer 310 and / or the second metal oxide layer 330 have a high dielectric constant. For example, the first metal oxide layer 310 and / or the second metal oxide layer 330 each independently have a dielectric constant of 20 or more and 70 or less. For example, the first metal oxide layer 310 and / or the second metal oxide layer 330 each independently may contain one or more metals selected from Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu. Specifically, the first metal oxide layer 310 and / or the second metal oxide layer 330 may each independently include hafnium oxide (HfO2), hafnium silicate (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicate (ZrSiO4), tantalum pentoxide (Ta2O5), titanium oxide (TiO2), strontium titanate (SrTiO3), yttrium oxide (YO3), aluminum oxide (Al2O3), cerium oxide (CeO2), lead scandium tantalate (PbScTaO3), lead zinc niobate (PbZnNbO3), or the like. Additionally, the first metal oxide layer 310 and / or the second metal oxide layer 330 may each independently include a metal nitride oxide such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), or yttrium oxynitride (YON), a silicate such as ZrSiON, HfSiON, YSiON, or LaSiON, or an aluminate such as ZrAlON or HfAlON.

[0032] The third metal oxide layer 320 contains one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), and may further contain boron (B). The third metal oxide layer 320 also serves as a leakage current reduction layer that reduces or blocks leakage current flowing within the capacitor 1. For example, a capacitor that does not contain the third metal oxide layer 320 and only includes the first metal oxide layer 310 and / or the second metal oxide layer 330 will experience excessive leakage current flow within the capacitor, making it difficult to operate. On the other hand, if a metal oxide layer containing one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), but not boron (B), is included between the first metal oxide layer 310 and the second metal oxide layer 330, the leakage current within the capacitor will be reduced, but the capacitance of the capacitor will be low. On the other hand, when a metal oxide layer containing boron (B) along with one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be) is included between the first metal oxide layer 310 and the second metal oxide layer 330, the leakage current in the capacitor is also reduced, and at the same time the capacitance of the capacitor is maintained or the decrease is reduced.

[0033] The third metal oxide layer 320 may further contain one or more metal elements selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu.

[0034] The third metal oxide layer 320 has a boron (B) content that is less than or equal to the content of one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be). For example, the boron (B) content in the third metal oxide layer 320 is 0.95 or less, 0.90 or less, 0.80 or less, 0.75 or less, 0.70 or less, 0.01 or more, 0.05 or more, 0.10 or more, 0.15 or more, 0.20 or more, 0.25 or more, or 0.30 or more relative to the content of one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be).

[0035] The third metal oxide layer 320 is AB a C 1-aThe third metal oxide layer 320 may include a metal oxide represented by the formula: O. A is one or more metal elements selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu. B is boron (B). C is one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be). The ratio (a) of boron (B) to C is greater than 0.00, 0.10 or more, 0.15 or more, 0.20 or more, 0.50 or less, or 0.45 or less. The A metal element, C metal element, and / or boron (B) in the third metal oxide layer 320 may be included in an appropriate amount depending on the desired dielectric constant of the dielectric layer, the leakage current value of the capacitor, and the like. For example, the content of boron (B) in the third metal oxide layer 320 is greater than 0.0 at%, 0.3 at% or more, 0.5 at% or more, 0.7 at% or more, 1.0 at% or more, 10.0 at% or less, 7.0 at% or less, 5.0 at% or less, 4.0 at% or less, 3.0 at% or less, 2.5 at% or less, 2.0 at% or less, or 1.5 at% or less relative to the total content of metal elements in the third metal oxide layer 320. The content of the metal element A in the third metal oxide layer 320 is 80 at% or more, 85 at% or more, 90 at% or more, but less than 100 at%, 98 at% or less, or 96 at% or less relative to the total content of metal elements in the third metal oxide layer 320. The content of boron (B) in the third metal oxide layer 320 is more than 0.0 at%, 0.5 at% or more, 1.0 at% or more, 1.5 at% or more, 2.0 at% or more, 10.0 at% or less, 7.0 at% or less, 5.0 at% or less, 4.0 at% or less, 3.0 at% or less, 2.5 at% or less, or 2.0 at% or less, relative to the total content of metal elements in the third metal oxide layer 320. a C 1-a In a metal oxide represented by O, the element ratio between metal element A, boron (B), and metal element C is determined by the content of each metal element in the third metal oxide, and the content of oxygen (O) element can be determined by the content and stoichiometry of metal elements A, C, and boron (B).

[0036] The thickness of the dielectric layer 300 is 20 Å or more and 100 Å or less. Specifically, the dielectric layer 300 may have a thickness of 25 Å or more, 30 Å or more, 35 Å or more, 90 Å or less, 80 Å or less, 70 Å or less, or 60 Å or less.

[0037] The first metal oxide layer 310 is disposed adjacent to the lower electrode 100 and may have a thickness of 40% or more of the total thickness of the dielectric layer 300. Specifically, the thickness of the first metal oxide layer 310 is 45% or more, 50% or more, 55% or more, 60% or more, 65% or more, 90% or less, 85% or less, 80% or less, or 75% or less of the total thickness of the dielectric layer 300. For example, the thickness of the first metal oxide layer 310 is 10 Å or more, 15 Å or more, 20 Å or more, 50 Å or less, 45 Å or less, 40 Å or less, or 35 Å or less.

[0038] The thickness of the second metal oxide layer 330 is 10 Å or more, 15 Å or more, 20 Å or more, 50 Å or less, 45 Å or less, 40 Å or less, or 35 Å or less.

[0039] The thickness of the third metal oxide layer 320 is 5 Å or more, 10 Å or more, 15 Å or more, 20 Å or more, 50 Å or less, 45 Å or less, 40 Å or less, or 35 Å or less. The thickness of the third metal oxide layer 320 is 0.1 or more, 0.2 or more, 0.3 or more, but less than 1.0, 0.9 or less, 0.8 or less, 0.7 or less, or 0.5 or less than the thickness of the first metal oxide layer 310.

[0040] Meanwhile, the boundaries between the first metal oxide layer 310, the second metal oxide layer 330, and the third metal oxide layer 320 are unclear. Specifically, the boundaries between the first metal oxide layer 310 and the third metal oxide layer 320, the second metal oxide layer 330 and the third metal oxide layer 320, or all of them are unclear. For example, if the first metal oxide layer 310, the second metal oxide layer 330, and the third metal oxide layer 320 are manufactured with similar compositions or are thin, the boundaries between adjacent layers are not clearly defined due to material diffusion between them.

[0041] The dielectric layer 300 may further include a fourth metal oxide layer (not shown) containing one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be). The fourth metal oxide layer may be free of boron (B) or may contain a lower amount of boron (B) than the third metal oxide layer 320. The fourth metal oxide layer may be disposed between the upper electrode 200 and the second metal oxide layer 330. The thickness of the fourth metal oxide layer may be 5 Å or more, 10 Å or more, 15 Å or more, 20 Å or more, 50 Å or less, 45 Å or less, 40 Å or less, or 35 Å or less.

[0042] The capacitor 1 may further include an interface layer (not shown) between the lower electrode 100 and the dielectric layer 300 and / or between the upper electrode 200 and the dielectric layer 300. The interface layer can act as a barrier layer that prevents the diffusion and / or migration of impurities between the lower electrode 100 and the dielectric layer 300 and / or between the upper electrode 200 and the dielectric layer 300. For example, the interface layer can prevent some atoms (e.g., nitrogen atoms) contained in the upper / lower electrodes 100, 200 from penetrating into the dielectric layer 300 and prevent some atoms (e.g., oxygen atoms) contained in the dielectric layer 300 from diffusing into the upper / lower electrodes 100, 200. The interface layer may include a conductive transition metal oxide, such as a metal oxide such as titanium oxide, tantalum oxide, niobium oxide, molybdenum oxide, or iridium oxide, or a metal oxynitride such as titanium oxynitride (TiON), tantalum oxynitride (TaON), niobium oxynitride (NbON), or molybdenum oxynitride (MoON). Specifically, the interface layer may include an oxide of a metal included in the lower electrode 100 and / or upper electrode 200. For example, the lower electrode 100 may include a metal nitride represented by MM'N, and the interface layer between the lower electrode 100 and the dielectric layer 300 may include a metal oxynitride represented by MM'N. The interface layer is formed to a thickness that does not allow it to function as a dielectric layer, and may have a thickness of, for example, about 1 Å to 10 Å.

[0043] A capacitor according to another embodiment may include a dielectric layer including a first metal element selected from the group consisting of one or more of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu, a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), and boron (B). FIG. 2 is a schematic diagram of such a capacitor. Referring to FIG. 2, the capacitor 2 includes a lower electrode 100, an upper electrode 200 spaced apart from the lower electrode 100, and a dielectric layer 301 disposed between the lower electrode 100 and the upper electrode 200. The dielectric layer 301 may include the first metal element, the second metal element, and boron (B), where the content of boron (B) is less than or equal to the content of the second metal element.

[0044] The first metal element, the second metal element, and / or boron (B) may be included in the dielectric layer 301 in an appropriate content depending on the desired dielectric constant of the dielectric layer, the leakage current value of the capacitor, etc. For example, the content of boron (B) in the dielectric layer 301 may be greater than 0.0 at% or greater than 0.2 at% or greater, greater than 0.3 at% or greater, greater than 0.5 at% or greater, less than 3.0 at% or less, less than 2.5 at% or less, less than 2.0 at% or less, or less than 1.5 at% relative to the total metal element content in the dielectric layer 301. In addition, the content of the first metal element in the dielectric layer 301 may be greater than 92 at% or greater, greater than 94 at% or greater, greater than 95 at% or greater, less than 100 at%, less than 98 at% or less, or less than 96 at% relative to the total metal element content in the dielectric layer. The content of the second metal element in the dielectric layer 301 is greater than 0.0 at%, 0.3 at% or more, 0.5 at% or more, 1.0 at% or more, 1.5 at% or more, 2.0 at% or more, 5.0 at% or less, 4.5 at% or less, 4.0 at% or less, 3.5 at% or less, 3.0 at% or less, or 1.5 at% or less, relative to the total metal elements in the dielectric layer. The dielectric layer 301 may include a metal oxide of the first metal element, a metal oxide of the second metal element, and / or boron oxide. For example, the dielectric layer 301 may include a metal oxide of AB a C 1-aO. A is a first metal element, B is boron (B), and C is a second metal element. a is greater than 0.00, 0.10 or greater, 0.15 or greater, or 0.20 or greater, and is 0.50 or less, or 0.45 or less. AB a C 1-a The dielectric layer 301 is a metal oxide represented by O, and the element ratio between the first metal element (A), boron (B), and the second metal element (C) is determined by the content of each metal element in the dielectric layer 301, and the content of oxygen (O) element can be determined by the content and stoichiometry of the first metal element (A), the second metal element (C), and boron (B).

[0045] Meanwhile, boron (B) may have a concentration gradient in the thickness direction of the dielectric layer 301. Specifically, the dielectric layer 301 has a lower surface 311 facing the lower electrode 100, an inner region 321 located on the lower surface 311, and an upper surface 331 located on the inner region 321 and facing the upper electrode 200, in that order in the thickness direction, and the boron content in the inner region 321 may be higher than the boron content in the lower surface 311 and / or the upper surface 331. As another example, as shown in FIG. 3, the dielectric layer 302 has a lower region 312 and an upper region 332 of a certain thickness above and below the inner region 322, and the boron content in the inner region 322 may be higher than the boron content in the lower region 312 and / or the upper region 332. For example, the boron content in the inner regions 321, 322 may be 5 times or more, 10 times or more, 15 times or more, 20 times or more, 50 times or more, or 100 times or more greater than the boron content in the lower surface / lower regions 311, 312, the upper surface / upper regions 331, 332, or all of them. Also, boron (B) may have a maximum concentration (content) at a position 40% or more of the thickness of the dielectric layers 301, 302 away from the lower electrode 100. The position where boron (B) has a maximum concentration (content) may be, for example, 45% or more, 50% or more, 55% or more, 60% or more, 90% or less, 85% or less, 80% or less, or 75% or less of the thickness of the dielectric layers 301, 302 away from the lower electrode 100.

[0046] The lower electrode 100, the upper electrode 200, the interface layer (not shown), etc. are the same as those described above, and the dielectric layers 301 and 302 may refer to the dielectric layer 300 described above.

[0047] The above-described capacitors 1, 2, and 3 can have a low leakage current value. Specifically, when a voltage of 1.0 V is applied to the capacitors 1, 2, and 3, the leakage current is 1.0×10 -4 A / cm 2 Below, 5.0 x 10 -5 A / cm 2 or less, or 1.0×10 -5 A / cm 2 The following leakage current values ​​can be shown:

[0048] An electric device (capacitor) according to an embodiment may be fabricated by forming a lower electrode 100 on a substrate, forming a dielectric layer 300 including metal oxide layers 310, 320, and 330 having a desired composition and thickness on the lower electrode 100, and then forming an upper electrode 200 thereon. The lower electrode 100, the dielectric layer 300, and the upper electrode 200 may be formed by methods known in the art. For example, they may each be independently formed by a deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. Among these, the atomic layer deposition (ALD) method has the advantage of forming a layer that is uniform at the atomic level and can be performed at a relatively low temperature.

[0049] Specifically, the lower electrode 100, the dielectric layer 300, and the upper electrode 200 may each be independently formed by repeating a deposition cycle consisting of supplying a metal precursor, purging the metal precursor, supplying a reactive gas (e.g., a nitriding agent or an oxygen source), and purging the reactive gas one or more times.

[0050] For example, the lower electrode 100 and / or upper electrode 200 including a metal nitride can be fabricated by supplying a metal precursor and a nitriding agent onto a substrate or a dielectric layer and reacting them at an appropriate temperature. The process temperature is appropriately adjusted depending on the thermal stability of the metal precursor and / or the nitriding agent, and can be between 100°C and 700°C.

[0051] The metal precursor is MR x Or, M'R x M or M' is as described above, and R is C1-C 10 Alkyl group, C2-C 10 Alkenyl group, carbonyl group (C=O), halide, C6-C 10 Aryl group, C6-C 10 Cycloalkyl groups, C6-C 10 Cycloalkenyl group, (C=O)R (where R is hydrogen or C1-C 10 alkyl group), C1-C 10 Alkoxy group, C1-C 10 Amidinate, C1-C 10 Alkylamides, C1-C 10 alkylimides, -N(Q)(Q'), where Q and Q' are independently C1-C 10 alkyl group or hydrogen), Q(C=O)CN (Q is hydrogen or C1-C 10 alkyl group) and C1-C 10 There may be one or two β-diketonates, and x may be greater than 0 and equal to or less than 6.

[0052] The metal precursor is MH y or M'H y M and M' are as defined above, and H may include one or more of F, Cl, Br, and I. y is greater than 0 and equal to or less than 6.

[0053] The nitriding agent may include NH3, N2H2, N3H, and / or N2H4 as a reactive gas containing nitrogen element.

[0054] After being delivered to the substrate or dielectric layer 300, unreacted metal precursors, reactive gases (e.g., nitriding agents), and / or their by-products may be removed by purging, which may utilize inert gases such as Ar, He, Ne, and / or N gas.

[0055] After the formation of the lower electrode 100, an interfacial layer (not shown) may be formed on the lower electrode 100, or after the formation of the dielectric layer 300, on the dielectric layer 300. The interfacial layer may be formed by providing precursors and / or sources of the elements constituting the interfacial layer on the lower electrode 100 or on the dielectric layer 300. Alternatively, the interfacial layer may be formed by providing an oxygen source to the lower electrode 100 to oxidize a portion of the surface of the lower electrode 100.

[0056] The dielectric layers 300, 301, and 302 may be fabricated to have a desired composition, concentration, and / or thickness by providing a first metal precursor, a second metal precursor, a boron precursor, and an oxygen source on the lower electrode 100 and adjusting the order, time, amount, etc. of the supply of the first metal precursor, the second metal precursor, the boron precursor, and the oxygen source. For example, the dielectric layers 300, 301, and 302 may be fabricated by providing a first metal precursor (e.g., a zirconium precursor) and an oxygen source on the lower electrode to form a first metal oxide layer 310, providing a first metal precursor (e.g., a zirconium precursor), a second metal precursor (e.g., an aluminum precursor), a boron precursor, and an oxygen source on the first metal oxide layer 310 to form a third metal oxide layer 320, and providing a first metal precursor (e.g., a zirconium precursor) and an oxygen source on the third metal oxide layer 320 to form a second metal oxide layer 330. The first metal precursor, the second metal precursor, the boron precursor, and / or the oxygen source are simultaneously or intermittently / alternately provided onto the lower electrode 100. For example, two or more of the first metal precursor, the second metal precursor, the boron precursor, and the oxygen source may be simultaneously provided onto the lower electrode 100 through two or more injection ports, or the first metal precursor, the second metal precursor, the boron precursor, and the oxygen source may be sequentially provided onto the lower electrode 100, respectively.

[0057] The dielectric layers 300, 301, and 302 may have varying compositions, concentrations, and / or thicknesses of metal elements therein due to material diffusion. For example, the third metal oxide layer 320 may further include one or more metal elements selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu due to material diffusion from the adjacent first metal oxide layer 310 and / or second metal oxide layer 330, and may also have different contents, concentrations, and / or positions within the dielectric layers of aluminum (Al), magnesium (Mg), silicon (Si), beryllium (Be), and / or boron (B).

[0058] The metal precursors, such as the first metal precursor, the second metal precursor, and the boron precursor, each independently comprise an AR x , C.R. x , or BR x A is the first metal element, C is the second metal element, B is boron, and R is C1-C 10 Alkyl group, C2-C 10 Alkenyl group, carbonyl group (C=O), halide, C6-C 10 Aryl group, C6-C 10 Cycloalkyl groups, C6-C 10 Cycloalkenyl group, (C=O)R (where R is hydrogen or C1-C 10 alkyl group), C1-C 10 Alkoxy group, C1-C 10 Amidinate, C1-C 10 Alkylamides, C1-C 10 alkylimides, -N(Q)(Q'), where Q and Q' are independently C1-C 10 alkyl group or hydrogen), Q(C=O)CN (Q is hydrogen or C1-C 10 alkyl group) and C1-C 10 There may be one or two β-diketonates, and x may be greater than 0 and equal to or less than 6.

[0059] Examples of oxygen sources include O3, H2O, O2, N2O, O2, and / or plasma. The dielectric layers 300, 301, and 302 or the metal oxide layers 310, 320, and 330 are subjected to a heat treatment. Specifically, the heat treatment is performed after the dielectric layers 300, 301 and / or the upper electrode 200 are formed. As another example, the heat treatment is performed after the first metal oxide layer 310, the third metal oxide layer 320, and / or the second metal oxide layer 330 are formed. During the heat treatment, metal elements in the dielectric layers 300, 301, and 302 undergo material diffusion, and some or all of the metal oxide in the dielectric layers 300, 301, and 302 or the metal oxide layers 310, 320, and 330 are crystallized or the crystal grain size increases.

[0060] The heat treatment may be performed at a temperature of, but is not limited to, 400° C. to 1100° C. The heat treatment may be performed for, but is not limited to, 1 nanosecond or more, 1 microsecond or more, 0.001 seconds or more, 0.01 seconds or more, 0.05 seconds or more, 0.1 seconds or more, 0.5 seconds or more, 1 second or more, 3 seconds or more, 5 seconds or more, 10 minutes or less, 5 minutes or less, 1 minute or less, or 30 seconds or less.

[0061] According to another aspect, a semiconductor device may be provided. The semiconductor device may have memory characteristics, such as a DRAM. The semiconductor device may also have a configuration in which a field-effect transistor and a capacitor are electrically connected, and the capacitor may be one of the aforementioned electrical devices.

[0062] 4 is a schematic diagram showing a semiconductor device (a connection structure between a capacitor and a field effect transistor) according to one embodiment. Referring to FIG. 4, the semiconductor device D1 has a structure in which the capacitor 1 including the dielectric layer 300 and the field effect transistor 10 are electrically connected by a contact 20. For example, one of the electrodes 100, 200 of the capacitor 1 and one of the source and drain 11a, 11b of the field effect transistor 10 may be electrically connected by the contact 20. While FIG. 4 illustrates an example of the semiconductor device D1 including the capacitor 1 of FIG. 1, the semiconductor device D1 may also include the capacitors 2, 3 of FIG. 2 or FIG. 3.

[0063] The field-effect transistor 10 may include a substrate 11 and a gate electrode 12b disposed opposite the channel 11c, and may further include a gate insulating layer 12a between the substrate 11 and the gate electrode 12b.

[0064] The substrate 11 may include a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and may be modified into various forms such as silicon on insulator (SOI).

[0065] The substrate 11 may include a source 11a, a drain 11b, and a channel 11c electrically connected to the source 11a and the drain 11b. The source 11a may be electrically connected to or in contact with one end of the channel 11c, and the drain 11b may be electrically connected to or in contact with the other end of the channel 11c. That is, the channel 11c may be defined as a substrate region between the source 11a and the drain 11b in the substrate 11.

[0066] The source 11a, the drain 11b, and the channel 11c are formed by independently implanting impurities into different regions of the substrate 11, and in this case, the source 11a, the channel 11c, and the drain 11b may contain the substrate material as a base material.

[0067] Additionally, the source 11a and the drain 11b are formed of a conductive material, and may each independently include, for example, a metal, a metal compound, or a conductive polymer.

[0068] The channel 11c may also be realized by a separate material layer (thin film) (not shown). In this case, for example, the channel 11c may include not only semiconductor materials such as Si, Ge, SiGe, and III-V semiconductors, but also oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional materials (2D materials), quantum dots (QDs), and / or organic semiconductors. For example, the oxide semiconductor may include InGaZnO, the two-dimensional material may include transition metal dichalcogenides (TMDs) or graphene, and the quantum dots may include colloidal quantum dots or nanocrystal structures.

[0069] The gate electrode 12b may be disposed on the substrate 11, spaced apart from the substrate 11, and facing the channel 11c. The gate electrode 12b has a conductivity of 1 Mohm / square or less. The gate electrode 12b may include a metal, a metal nitride, a metal carbide, and / or polysilicon. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and / or tantalum (Ta), and the metal nitride film may include a titanium nitride film (TiN film) and / or a tantalum nitride film (TaN film). The metal carbide may also be a metal carbide doped (or containing) with aluminum and / or silicon, and may include, for example, TiAlC, TaAlC, TiSiC, or TaSiC. The gate electrode 12b may have a structure in which multiple materials are stacked, for example, a stacked structure of a metal nitride layer / metal layer such as TiN / Al, or a stacked structure of a metal nitride layer / metal carbide layer / metal layer such as TiN / TiAlC / W. The gate electrode 12b may include titanium nitride (TiN) or molybdenum (Mo), and the above examples may be used in various modified forms.

[0070] A gate insulating layer 12a may be further disposed between the substrate 11 and the gate electrode 12b. The gate insulating layer 12a may include a paraelectric material or a high-dielectric material and may have a dielectric constant of 20 to 70. The gate insulating layer 12a may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc., or may include a two-dimensional insulator such as h-BN (hexagonal boron nitride). For example, the gate insulating layer 12a includes silicon oxide (SiO2), silicon nitride (SiNx), or the like, and may further include hafnium oxide (HfO2), hafnium silicate (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminate (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicate (ZrSiO4), tantalum pentoxide (Ta2O5), titanium oxide (TiO2), strontium titanate (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalate (PbSc 0.5 Ta 0.5 The gate insulating layer 12a may include a metal nitride oxide such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), or yttrium oxynitride (YON), a silicate such as ZrSiON, HfSiON, YSiON, or LaSiON, or an aluminate such as ZrAlON or HfAlON. The gate insulating layer 12a may also include the dielectric layers 300, 301, and 302 described above. The gate insulating layer 12a can form a gate stack like the gate electrode 12b.

[0071] Contact 20 may comprise any suitable conductive material, such as tungsten, copper, aluminum, polysilicon, or the like.

[0072] The arrangement of the capacitor 1 and the field effect transistor 10 can be modified in various ways. For example, the capacitor 1 can be disposed on the substrate 11 and embedded in the substrate 11.

[0073] While FIG. 4 illustrates a semiconductor device 1 having one capacitor 1 and one field effect transistor 10, a semiconductor device D10 may have a structure in which a plurality of capacitors and a plurality of field effect transistors are repeatedly arranged, as shown in FIG. 5. Referring to FIG. 5, the semiconductor device D10 may further include a substrate 11' including a source, a drain, and a channel, a field effect transistor including a gate stack 12, a contact structure 20' disposed on the substrate 11' so as not to overlap with the gate stack 12, and a capacitor 1' disposed on the contact structure 20', and may further include a bit line structure 13 electrically connecting the plurality of field effect transistors. While FIG. 5 illustrates a semiconductor device D10 in which the contact structures 20' and the capacitors 1' are repeatedly arranged along the X and Y directions, the present invention is not limited thereto. For example, the contact structures 20' may be arranged along the X and Y directions, and the capacitors 1' may be arranged in a hexagonal shape, such as a honeycomb structure.

[0074] FIG. 6 is an example cross-sectional view of the semiconductor device D10 of FIG. 5 taken along line A-A'. Referring to FIG. 6, the substrate 11' may have a shallow trench isolation (STI) structure including an isolation layer 14. The isolation layer 14 may be a single layer of one insulating film or a multi-layer structure of two or more insulating films. The isolation layer 14 may include an isolation trench 14T in the substrate 11', and the isolation trench 14T may be filled with an insulating material. Examples of insulating materials include, but are not limited to, fluoride silicate glass (FSG), undoped silicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethylorthosilicate (PE-TEOS), and / or tonosilazene (TOSZ).

[0075] The substrate 11′ may further include an active region AC defined by an isolation layer 14 and gate line trenches 12T arranged parallel to the top surface of the substrate 11′ and extending along the X direction. The active region AC may have a relatively long island shape having a short axis and a long axis. The long axis of the active region AC may be aligned along the D3 direction parallel to the top surface of the substrate 11′, as exemplarily illustrated in FIG. 5 . The gate line trenches 12T may be arranged to intersect with the active region AC at a predetermined depth from the top surface of the substrate 11′ or within the active region AC. The gate line trenches 12T may also be arranged within isolation trenches 14T, and the gate line trenches 12T within the isolation trenches 14T may have a lower bottom surface than the gate line trenches 12T in the active region AC.

[0076] The first source / drain 11'ab and the second source / drain 11''ab may be disposed in upper portions of the active region AC located on both sides of the gate line trench 12T.

[0077] A gate stack 12 may be disposed within the gate line trench 12T. Specifically, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be sequentially disposed within the gate line trench 12T. The gate insulating layer 12a and the gate electrode 12b refer to the above-described contents, and the gate capping layer 12c may include silicon oxide, silicon oxynitride, and / or silicon nitride. The gate capping layer 12c may be disposed on the gate electrode 12b to fill the remaining portion of the gate line trench 12T.

[0078] In addition, bit line structures 13 may be disposed on the first source / drains 11′ab. The bit line structures 13 may be disposed parallel to the top surface of the substrate 11′ and extend along the Y direction. The bit line structures 13 are electrically connected to the first source / drains 11′ab and may include bit line contacts 13a, bit lines 13b, and a bit line capping layer 13c, which are sequentially disposed on the substrate. For example, the bit line contacts 13a may include polysilicon, the bit lines 13b may include a metal material, and the bit line capping layer 13c may include an insulating material such as silicon nitride or silicon oxynitride. Although FIG. 6 illustrates the bit line contacts 13a as having a bottom surface flush with the top surface of the substrate 11′, the bit line contacts 13a may extend from the top surface of the substrate 11′ to within a recess (not shown) formed to a predetermined depth, and the bottom surface of the bit line contacts 13a may be lower than the top surface of the substrate 11′.

[0079] Optionally, the bit line structure 13 may include a bit line interlayer (not shown) between the bit line contact 13a and the bit line 13b. The bit line interlayer may include a metal silicide, such as tungsten silicide, and / or a metal nitride, such as tungsten nitride. Also, bit line spacers (not shown) may be further formed on sidewalls of the bit line structure 13. The bit line spacers may have a single-layer structure or a multi-layer structure and may include an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride. Also, the bit line spacers may further include air spaces (not shown).

[0080] The contact structure 20' may be disposed on the second source / drain 11''ab. The contact structure 20' and the bit line structure 13 may be disposed on different source / drains on the substrate. The contact structure 20' may have a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source / drain 11''ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the side and bottom of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metal material, and the barrier layer may include a conductive metal nitride.

[0081] The capacitor 1′ may be electrically connected to the contact structure 20′ and disposed on the substrate 11′. Specifically, the capacitor 1′ may include a lower electrode 100 electrically connected to the contact structure 20′, a dielectric layer 300 disposed on the lower electrode 100, and an upper electrode 200 disposed on the dielectric layer 300. The dielectric layer 300 may be disposed on the lower electrode 100 so as to be parallel to a surface of the lower electrode 100.

[0082] An interlayer insulating layer 15 may be further disposed between the capacitor 1′ and the substrate 11′. The interlayer insulating layer 15 may be disposed in a space between the capacitor 1′ and the substrate 11′ where no other structures are disposed. Specifically, the interlayer insulating layer 15 may be disposed to cover wiring and / or electrode structures, such as the bit line structure 13, the contact structure 20′, and the gate stack 12, on the substrate 11′. For example, the interlayer insulating layer 15 surrounds the walls of the contact structure 20′. The interlayer insulating layer 15 may include a first interlayer insulating layer 15a surrounding the bit line contact 13a and a second interlayer insulating layer 15b covering the side and / or top surfaces of the bit line 13b and the bit line capping layer 13c.

[0083] The lower electrode 100 of the capacitor 1′ may be disposed on the interlayer insulating layer 15, specifically, on the second interlayer insulating layer 15b. When multiple capacitors 1′ are disposed, the bottom surfaces of the multiple lower electrodes 100 may be separated by an etching stop layer 16. That is, the etching stop layer 16 may include an opening 16T, and the bottom surfaces of the lower electrodes 100 of the capacitor 1′ may be disposed within the opening 16T.

[0084] The lower electrode 100 has a bottomed cylindrical or cup shape as shown in Fig. 6. As another example, the lower electrode 100 may have a pillar shape such as a cylindrical, rectangular, or polygonal prism extending along the vertical direction (Z direction) as shown in Fig. 7.

[0085] In addition, the capacitor 1 ′ may further include a support (not shown) for preventing the lower electrode 100 from tilting or falling, and the support may be disposed on a sidewall of the lower electrode 100 .

[0086] The semiconductor devices D20 and D30 may be manufactured based on a conventional method known in the art. Specifically, the semiconductor devices D20 and D30 may be manufactured by the following steps i) to xvi).

[0087] i) forming an isolation trench 14T in the substrate 11′ and forming an isolation film 14 in the isolation trench 14T (defining an active region AC of the substrate 11′ by the isolation film 14 and / or the isolation trench 14T); ii) filling the inside of the isolation trench 14T with an insulating material; iii) implanting impurity ions into the substrate 11′ to form first source / drains 11′ab and second source / drains 11″ab in the upper region of the active region AC; iv) forming a gate line trench 12T in the substrate 11′; v) forming a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c inside the gate line trench 12T; vi) forming a first interlayer insulating layer 15a on the substrate 11′ and forming openings (not shown) exposing the top surfaces of the first source / drains 11′ab; vii) forming a bit line structure 13 electrically connected to the first source / drain 11'ab on the opening of vi); viii) forming a second interlayer insulating layer 15b covering the top and side surfaces of the bit line structure 13; ix) forming openings (not shown) in the first and second interlayer insulating layers 15a and 15b to expose the top surfaces of the second source / drains 11''ab; x) forming a contact structure 20' on the opening of ix) to be electrically connected to the second source / drain 11''ab; xi) forming an etching stop layer 16 and a mold layer (not shown) on the second interlayer insulating layer 15b and the contact structure 20′; xii) forming an opening (not shown) in the etching stop layer 16 and the mold layer (not shown) to expose the top surface of the contact structure 20′; xiii) forming a lower electrode 100 to cover the inner wall of the opening (to cover the bottom and side surfaces); xiv) Removing the mold layer (not shown) xv) forming a dielectric layer 300 on the lower electrode 100; and xvi) forming the top electrode 200 on the dielectric layer 300;

[0088] The types and / or order of the above-described steps are not limited and may be adjusted, omitted, or added as appropriate. Furthermore, deposition processes, patterning processes, etching processes, and the like known in the art are used to form components in each step. For example, an etch-back process may be applied when forming the electrodes. In step v), the gate electrode 12b may be formed by forming a conductive layer on the gate insulating layer 12a and then removing a predetermined height of the upper portion of the conductive layer through an etch-back process. In step xiii), the lower electrode 100 may be formed by forming an electrode to cover the upper surface of the mold layer and the bottom and side surfaces of the opening, and then removing a portion of the electrode on the upper surface of the mold layer through an etch-back process, thereby fabricating a structure having a plurality of lower electrodes 100. As another example, a planarization process may be applied. For example, in step v), the gate capping layer 12c may be formed by filling the remaining portion of the gate line trench 12T with an insulating material and then planarizing the insulating material until the upper surface of the substrate 11′ is exposed.

[0089] The electric devices and semiconductor devices may be applied to various electronic devices. Specifically, the electric devices and / or semiconductor devices may be applied as logic elements or memory elements in various electronic devices. Specifically, the electric devices and semiconductor devices may be used for arithmetic operations, program execution, and temporary data storage in electronic devices such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices. The electric devices and semiconductor devices according to the embodiments are useful for electronic devices in which large amounts of data are transmitted continuously.

[0090] 8 and 9 are conceptual diagrams that schematically illustrate electronic element architectures that can be applied to electronic devices according to embodiments.

[0091] 8, an electronic device architecture 1000 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, the ALU 1020, and the control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1000 may be implemented as a single chip including the memory unit 1010, the ALU 1020, and the control unit 1030. Specifically, the memory unit 1010, the ALU 1020, and the control unit 1030 may be interconnected on-chip by metal lines and communicate directly with each other. The memory unit 1010, the ALU 1020, and the control unit 1030 may also be monolithically integrated on a single substrate to form a single chip. An input / output device 2000 may be connected to the electronic device architecture (chip) 1000. The memory unit 1010 may include both a main memory and a cache memory. Such an electronic device architecture (chip) 1000 may also be an on-chip memory processing unit.

[0092] The memory unit 1010, the ALU 1020, and / or the control unit 1030 may each independently include the electrical devices described above. Referring to Figure 9, a cache memory 1510, an ALU 1520, and a control unit 1530 constitute a central processing unit (CPU) 1500, and the cache memory 1510 is made up of static random access memory (SRAM). A main memory 1600 and an auxiliary storage 1700 are provided separately from the CPU 1500. The main memory 1600 may also be dynamic random access memory (DRAM) and may include the electrical devices described above.

[0093] In some cases, the electronic device architecture may be implemented in a form in which a computing unit device and a memory unit device are adjacent to each other on a single chip without the division of sub-units.

[0094] The technical contents of the electrical device will be described in more detail below through the following embodiments, which are merely for illustrative purposes and are not intended to limit the scope of the invention.

[0095] Example 1 The bottom electrode was formed by DC sputtering or ALD. A dielectric layer was formed on the lower electrode using atomic layer deposition (ALD). Specifically, a first metal oxide layer containing zirconium oxide (ZrO2) was formed, followed by a third metal oxide layer containing zirconium (Zr), aluminum (Al), and boron (B) on the first metal oxide layer, and then a second metal oxide layer containing zirconium oxide (ZrO2) was formed on the third metal oxide layer. As a result, the dielectric layer has a concentration gradient in which the boron content in the inner region is greater than the boron content at the upper and lower surfaces. In addition, the amounts of zirconium (Zr) precursor, aluminum (Al) precursor, and boron (B) precursor were adjusted during the formation of the third metal oxide layer so that the content ratio of boron (B) element to aluminum (Al) element in the third metal oxide layer was 1.0, the content ratio of boron (B) element to all metal elements in the third metal oxide layer was 5.0 at%, or the content ratio of boron (B) element to all metal elements in the dielectric layer was 2.0 at%.

[0096] The top electrode was formed on the dielectric layer via DC sputtering or ALD. The layers and electrodes thus formed were subjected to rapid thermal annealing (RTA) at temperatures of 400°C to 1000°C to fabricate a capacitor.

[0097] Examples 2 and 3 A capacitor was manufactured in the same manner as in Example 1, except that the amounts of zirconium (Zr) precursor, aluminum (Al) precursor, and boron (B) precursor were varied during the formation of the third metal oxide layer to adjust the content ratio between metal elements in the third metal oxide layer or the content ratio between metal elements in the dielectric.

[0098] Comparative Example 1 A capacitor was manufactured in the same manner as in Example 1, except that a boron (B) precursor was not used when forming the third metal oxide layer, and a third metal oxide layer containing zirconium (Zr) and aluminum (Al) was formed.

[0099] Comparative Example 2 A capacitor was manufactured in the same manner as in Example 1, except that the third metal oxide layer was formed without using an aluminum (Al) precursor, and instead a third metal oxide layer containing zirconium (Zr) and boron (B) was formed. Electrical Characterization 1 A voltage of 1.0 V was applied to the capacitors manufactured by the methods of Examples 1 to 3 and Comparative Examples 1 and 2 to measure the capacitance. The capacitance of each capacitor was normalized based on the capacitance of the capacitor of Comparative Example 1, and the capacitance is shown in Table 1.

[0100] Furthermore, a voltage of 1.0 V was applied to the capacitors of Examples 1 to 3 and Comparative Examples 1 and 2 to measure the leakage current values, and the results are shown in Table 1.

[0101] Referring to Table 1, the capacitors of Examples 1 to 3, which contain aluminum (Al) and boron (B) in the dielectric layer, exhibited a capacitance 15% or more higher than that of the capacitor of Comparative Example 1, which does not contain boron (B). In addition, the capacitors of Examples 1 to 3 exhibited a capacitance of 1.0×10 -5 A / cm 2 The capacitor of Comparative Example 2 exhibited a leakage current value of 1.0×10 -4 A / cm 2That is, it was confirmed that the capacitors of Examples 1 to 3 had high capacitance and low leakage current at the same time.

[0102] [Table 1]

[0103] Examples 4 and 5 Capacitors were fabricated in the same manner as in Example 1, except that the thicknesses of the first and second metal oxide layers were adjusted so that the third metal oxide layer was positioned at a distance of 40% or more of the dielectric layer thickness from the lower electrode (Example 4) or less than 40% of the dielectric layer thickness from the lower electrode (Example 5). As a result, the dielectric layer of Example 4 had a maximum concentration of boron (B) at a position 40% or more of the dielectric layer thickness from the lower electrode, and the dielectric layer of Example 5 had a maximum concentration of boron (B) at a position less than 40% of the dielectric layer thickness from the lower electrode.

[0104] Electrical Characterization 2 A voltage of 1.0 V was applied to the capacitors of Examples 4 and 5, and the capacitance and leakage current value at the time of application of 1.0 V were measured and shown in Table 2. The capacitance was normalized based on the capacitance of the capacitor of Example 4.

[0105] Referring to Table 2, the capacitors of Examples 4 and 5 both had low leakage current values, but the capacitor of Example 5, in which the third metal oxide layer was disposed at a position less than 40% of the total thickness of the dielectric layer away from the lower electrode, exhibited a lower capacitance than Example 4.

[0106] [Table 2]

[0107] According to the above exemplary embodiments, an electrical device having high capacitance and excellent leakage current blocking / reducing properties and a semiconductor device including the same can be provided. Such an electrical device can realize an improved integration density and contribute to the miniaturization of electronic devices.

[0108] Although the embodiments have been described in detail above, the scope of the invention is not limited to these examples, and various modifications and improvements made by those skilled in the art using the basic concepts defined in the claims also fall within the scope of the invention. [Explanation of symbols]

[0109] 1, 2, 3 Capacitor 10 Field-effect transistor 11 Circuit Board 11a Source 11b Drain 11c channel 12a Gate insulating layer 12b gate electrode 20 Contacts 100 Lower electrode 200 Upper electrode 300 Dielectric Layer 301, 302 Dielectric layers 310 First metal oxide layer 311 Lower surface 312 Lower area 320 Third metal oxide layer 321, 322 internal area 330 Second metal oxide layer 331 Upper surface 332 Upper area

Claims

1. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal oxide layer and a second metal oxide layer having a dielectric constant of 20 or more and 70 or less; a third metal oxide layer disposed between the first metal oxide layer and the second metal oxide layer, the third metal oxide layer containing boron (B) and one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), the third metal oxide layer comprises a metal oxide represented by ABaCl-aO; A is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; B is boron (B), C is at least one selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); a is more than 0.00 and not more than 0.

50.

2. The electrical device of claim 1 , wherein the first metal oxide layer, the third metal oxide layer, and the second metal oxide layer are sequentially disposed in a thickness direction of the dielectric layer.

3. 3. The electrical device according to claim 1, wherein the first metal oxide layer and the second metal oxide layer each independently contain an oxide of one or more metal elements selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu.

4. 4. The electrical device according to claim 1, wherein the content of boron (B) is less than or equal to the content of the metal element.

5. 5. The electrical device according to claim 1, wherein the third metal oxide layer further contains one or more metal elements selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu.

6. the first metal oxide layer is disposed adjacent to a bottom electrode; 6. The electrical device of claim 1, wherein the thickness of the first metal oxide layer is 40% or more of the total thickness of the dielectric layer.

7. 7. The electrical device according to claim 1, wherein the first metal oxide layer has a thickness of 10 Å to 50 Å.

8. 8. The electrical device according to claim 1, wherein the second metal oxide layer has a thickness of 10 Å to 50 Å.

9. 9. The electrical device according to claim 1, wherein the third metal oxide layer has a thickness of 5 Å to 50 Å.

10. 10. The electrical device according to claim 1, wherein a ratio of a thickness of the third metal oxide layer to a thickness of the first metal oxide layer is equal to or greater than 0.3 and less than 1.

0.

11. 11. The electrical device of claim 1, wherein the dielectric layer has a thickness of 25 Å to 100 Å.

12. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal oxide layer and a second metal oxide layer having a dielectric constant of 20 or more and 70 or less; a third metal oxide layer disposed between the first metal oxide layer and the second metal oxide layer, the third metal oxide layer containing boron (B) and one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be), The dielectric layer is An electrical device comprising a fourth metal oxide layer disposed between the upper electrode and the second metal oxide layer, the fourth metal oxide layer containing one or more metal elements selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be).

13. 13. The electrical device of claim 12, wherein the fourth metal oxide layer is free of boron (B) or contains a boron (B) content that is less than the boron content of the third metal oxide layer.

14. 13. The electrical device of claim 12, wherein the fourth metal oxide layer has a thickness of at least 5 Å and at most 50 Å.

15. 14. The electrical device according to claim 1, wherein the leakage current value is 1.0×10 −4 A / cm 2 or less when a voltage of 1.0 V is applied.

16. A semiconductor device in which a field effect transistor and a capacitor are electrically connected, A semiconductor device, wherein the capacitor comprises the electrical device according to claim 1 .

17. The field effect transistor is 17. The semiconductor device of claim 16, comprising: a semiconductor layer including a source and a drain; a dielectric layer disposed on the semiconductor layer; and a gate electrode disposed on the dielectric layer.

18. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal element, which is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); boron (B), The content of the boron (B) is less than or equal to the content of the second metal element, The content of the boron (B) is more than 0.0 at % and 3.0 at % or less relative to the total metal elements of the dielectric layer.

19. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal element, which is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); boron (B), The content of the boron (B) is less than or equal to the content of the second metal element, The content of the first metal element is 92 at % or more and less than 100 at % relative to the total metal elements of the dielectric layer.

20. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal element, which is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); boron (B), The content of the boron (B) is less than or equal to the content of the second metal element, The content of the second metal element is more than 0.0 at % and not more than 5.0 at % relative to the total metal elements in the dielectric layer.

21. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal element, which is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); boron (B), The content of the boron (B) is less than or equal to the content of the second metal element, The dielectric layer comprises a metal oxide represented by ABaCl-aO, A is a first metal element, B is boron (B), C is a second metal element, and a is more than 0.00 and 0.50 or less.

22. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal element, which is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); boron (B), The content of the boron (B) is less than or equal to the content of the second metal element, The electrical device, wherein the boron (B) has a concentration gradient in the thickness direction of the dielectric layer.

23. the dielectric layer has, in order in a thickness direction, a lower surface facing the lower electrode, an inner region located on the lower surface, and an upper surface located on the inner region and facing the upper electrode; 23. The electrical device of claim 22, wherein the boron content in the interior region is greater than the boron content at the bottom surface, the top surface, or both.

24. 24. The electrical device of claim 22 or 23, wherein the boron (B) has a maximum concentration at a position 40% or more of the dielectric layer thickness away from the bottom electrode.

25. 25. The electrical device of claim 18, wherein the dielectric layer has a thickness of 20 Å or more and 100 Å or less.

26. A lower electrode; an upper electrode disposed at a distance from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode; The dielectric layer is a first metal element, which is at least one selected from the group consisting of Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, Pb, Zn, and Lu; a second metal element selected from the group consisting of aluminum (Al), magnesium (Mg), silicon (Si), and beryllium (Be); boron (B), The content of the boron (B) is less than or equal to the content of the second metal element, An electrical device having a leakage current value of 1.0×10 −4 A / cm 2 or less when a voltage of 1.0 V is applied.

27. A semiconductor device in which a field effect transistor and a capacitor are electrically connected, 27. A semiconductor device, wherein the capacitor comprises the electrical device according to claim 18.

28. The field effect transistor is 28. The semiconductor device of claim 27, comprising: a semiconductor layer including a source and a drain; a dielectric layer disposed on the semiconductor layer; and a gate electrode disposed on the dielectric layer.

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