MEMORY DEVICE, METHOD OF OPERATION THEREOF, AND MEMORY SYSTEM

Abstract

In an example of the present disclosure, a memory device, a method of operating the same, and a memory system are provided. The memory device includes a memory cell array and peripheral circuits coupled to the memory cell array. The method of operating the memory device includes receiving a first instruction instructing to write dummy data to a specified location within the memory cell array, generating dummy data to be written in response to the first instruction, and writing the dummy data to be written to the specified location.

Description

[Technical Field]

[0001] Examples of the present disclosure relate to the field of semiconductor technology, and in particular to memory devices and methods of operating same, and memory systems. [Background technology]

[0002] The memory device and its system serve as storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) type memory has become the mainstream product in the market due to its high storage density, controllable production cost, favorable programming and erasing speed, and retention characteristics. Summary of the Invention [Problem to be solved by the invention]

[0003] However, as people's demands for storage devices increase, there is a great deal of room for improvement in memory devices and their systems. [Means for solving the problem]

[0004] Examples of the present disclosure provide memory devices, methods of operating the same, and memory systems.

[0005] In a first aspect, an example of the present disclosure provides a memory device, comprising: a memory cell array; and peripheral circuitry coupled to the memory cell array; The peripheral circuitry is receiving a first instruction instructing to write dummy data to a specified location in the memory cell array; generating dummy data to be written in response to the first command; It is configured to write the dummy data to be written at the specified location.

[0006] In one example, the first instruction comprises a set feature command, or the first instruction includes a first flag set on a reserved field of a write command.

[0007] In one example, when the first instruction is configured by a set feature command, the command in which the first instruction is placed does not include dummy data to be written; When the first instruction includes a first flag set on a reserved field of the write command, the peripheral circuit is configured to respond to the first instruction by not receiving data information included in the write command but directly generating dummy data to be written.

[0008] In one example, the peripheral circuitry includes: Randomly generate dummy data to be written, or or It is configured to generate dummy data to be written in accordance with data stored in locations adjacent to the specified location in combination with a preset algorithm.

[0009] In one example, the preset algorithm relates to coupling effects between memory cells in a memory cell array.

[0010] In one example, the memory cell array comprises a plurality of memory blocks, each of which comprises a plurality of valid memory pages and a plurality of dummy memory pages; The specified location is At least one of the plurality of memory blocks, at least one valid memory page in an erased state in one of the memory blocks; and At least one of the dummy memory pages in one of the memory blocks Contains one of the following:

[0011] In one example, the specified location includes at least one valid memory page in one of the memory blocks in an erased state, and memory pages adjacent to the specified location are in a programmed state.

[0012] In one example, the peripheral circuitry includes: receiving a second instruction indicating to perform a read operation on data in the memory cell array; Further configured to return the data to be read in response to the second instruction, and when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes dummy data.

[0013] In one example, the peripheral circuitry includes: Writes the dummy data that should be written to the specified location, then saves the specified location, Before returning the data to be read, check whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored; The device is further configured to determine that the data to be read includes dummy data when the address corresponding to the data to be read is within an address range corresponding to the stored specified location.

[0014] On the other hand, an example of the present disclosure provides a memory system, which includes: one or more memory devices as described in the previous examples of this disclosure; and a memory controller coupled to the memory device and configured to control the memory device.

[0015] In one example, the memory system includes a solid state disk.

[0016] In yet another aspect, an example of the present disclosure provides a memory system, comprising: at least one memory device; and a memory controller coupled to the memory device and configured to control the memory device; The memory device comprises a memory cell array and peripheral circuits coupled to the memory cell array; the memory controller is configured to send a first command, the first command including a first instruction and a plurality of address instructions, the first instruction instructing to write dummy data to specified locations corresponding to the plurality of address instructions; The peripheral circuitry within the memory device is configured to receive a first command, generate dummy data to be written in response to the first command, and write the dummy data to be written to specified locations corresponding to the plurality of address instructions.

[0017] In one example, the memory controller is configured to send a second command, the second command including a second instruction, the second instruction directing performing a read operation on data in the memory cell array; the peripheral circuit is configured to receive a second command and, in response to the second command, return the data to be read, wherein when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes dummy data; The memory controller is further configured to receive the returned data to be read, and when the returned data frame includes a second flag, to stop receiving the remaining data frames or not perform a decoding operation on the returned data to be read.

[0018] In one example, the memory controller is configured to send a second command, the second command including a second instruction, the second instruction directing performing a read operation on data in the memory cell array; the peripheral circuit is configured to receive a second command and, in response to the second command, return data to be read, the data to be read including dummy data; The memory controller is further configured to receive the returned data to be read, and to discard the data to be read when decoding of the returned data to be read fails.

[0019] In yet another aspect, an example of the present disclosure provides a method of operating a memory device, comprising: receiving a first instruction to write dummy data to specified locations in a memory cell array of a memory device; generating dummy data to be written in response to a first command; and writing the dummy data to be written in the specified location.

[0020] In one example, the first instruction comprises a set feature command, or the first instruction includes a first flag set on a reserved field of a write command.

[0021] In one example, when the first instruction is configured by a set feature command, the command in which the first instruction is placed does not include dummy data to be written; When the first instruction includes a first flag set on a reserved field of the write command, in response to the first instruction, the device does not receive data information included in the write command but directly generates dummy data to be written.

[0022] In one example, generating dummy data to be written includes: Randomly generate dummy data to be written, or or This involves generating dummy data to be written in accordance with data stored in locations adjacent to the specified location in combination with a preset algorithm.

[0023] In one example, the method comprises: receiving a second instruction instructing to perform a read operation on data in the memory cell array; and returning the data to be read in response to the second command, wherein when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes dummy data.

[0024] In one example, the method comprises: writing dummy data to be written to the specified location and then saving the specified location; Before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored; and determining that the data to be read includes dummy data when the address corresponding to the data to be read is within the address range corresponding to the stored specified location.

[0025] In an example of the present disclosure, a memory device, an operating method thereof, and a memory system are proposed. The operating method of the memory device includes receiving a first instruction instructing writing dummy data to a specified location in a memory cell array of the memory device, generating the dummy data to be written in response to the first instruction, and writing the dummy data to be written to the specified location. After receiving the dummy data embedded in the specified location, the memory device in the example of the present disclosure generates the dummy data based on its own characteristics and stores the dummy data in the specified location. In this way, the memory device generates the dummy data according to its own characteristics instead of the memory controller transmitting the dummy data to the memory device, thereby saving the time required to transmit the dummy data, shortening the time required to embed the dummy data, and improving the throughput of the memory system. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a schematic diagram of an exemplary system including a memory system according to an example of the present disclosure. [Figure 2a] 1 is a schematic diagram of an exemplary memory card including a memory system according to an example of the present disclosure. [Figure 2b] FIG. 1 is a schematic diagram of an exemplary solid-state drive including a memory system according to an example of the present disclosure. [Figure 3a] 1 is a schematic diagram of a distribution of memory cells in a 3D NAND memory according to an example of the present disclosure. [Figure 3b] FIG. 1 is a schematic diagram of an exemplary memory device including peripheral circuitry according to an example of the present disclosure. [Figure 4] 1 is a schematic cross-sectional view of a memory cell array including a NAND memory according to an example of the present disclosure. [Figure 5] 1 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an example of the present disclosure. [Figure 6] FIG. 1 is a schematic diagram of an exemplary memory system including a memory controller and a memory device according to an example of the present disclosure. [Figure 7] 1 is a schematic flowchart of implementing a method of operating a memory device according to an example of the present disclosure. [Figure 8] FIG. 10 is a schematic diagram of a write command when a memory device performs a write operation according to an example of the present disclosure. [Figure 9] FIG. 2 is a schematic diagram of address information of a write command corresponding to a triple-level cell (TLC) according to an example of the present disclosure. [Figure 10] 1 is a schematic diagram of a read command when a memory device performs a read operation according to an example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0027] Examples of the present disclosure are described in more detail below with reference to the accompanying drawings. While examples of the present disclosure are illustrated in the drawings, it should be understood that the present disclosure may be implemented in a variety of ways and should not be limited to the Detailed Description set forth herein. Rather, these examples are provided so that the disclosure may be more fully understood and the scope of the disclosure may be fully conveyed to those skilled in the art.

[0028] In the following description, numerous specific details are provided to provide a more complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other instances, some technical features well known in the art are not described to avoid confusion with the present disclosure, that is, not all features of the actual examples are described herein, and well-known functions and structures are not described in detail.

[0029] In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

[0030] When an element or layer is referred to as being "on," "adjacent," "connected," or "coupled" to another element or layer, it will be understood that this may be directly on, adjacent to, connected to, or coupled to the other element or layer, or that there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected," or "directly coupled" to another element or layer, there are no intervening elements or layers. Terms such as first, second, third, etc. may be used to describe at least one of various elements, components, regions, layers, or sections, but it will be understood that these elements, components, regions, layers, or sections should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section described below could be represented as a second element, component, region, layer, or section without departing from the teachings of the present disclosure. When a second element, component, region, layer, or section is described, this does not indicate that the first element, component, region, layer, or section is present in the present disclosure.

[0031] Spatial terms such as "below," "lower," "below," "below," "above," "above" and the like may be used herein for convenience to describe the relationship between one element or feature and another element or feature shown in the figures. It will be understood that spatial relationship terms are used in addition to the orientation depicted in the figures and include different orientations of the device in operation. For example, if a device in the figures were turned over, an element or feature described as being "below" or "below" or "below" another element or feature would then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "below" can include both an above and below orientation. The device may be oriented in some other way (rotated 90 degrees or at some other orientation), and the spatial descriptors used herein may be interpreted accordingly.

[0032] The terms used herein are intended to describe particular examples only and should not be construed as limitations on the present disclosure. As used herein, the singular forms "a," "an," and "said / the" (the singular articles "a," "an," and "said / the") are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the phrases "comprising" or "comprising," when used herein, identify the presence of at least one of the stated features, integers, operations, elements, or components, but do not exclude the presence or addition of at least one of one or more other features, integers, operations, elements, components, or groups. As used herein, the phrase "at least one of" includes any and all combinations of the associated listed items.

[0033] In order to facilitate a more detailed understanding of the characteristics and technical contents of examples of the present disclosure, examples of the present disclosure are described in detail below in conjunction with the accompanying drawings, which are provided for reference and explanation only and are not intended to limit the examples of the present disclosure.

[0034] The memory devices in the examples of the present disclosure include, but are not limited to, 3D NAND type memories, and for ease of understanding, 3D NAND type memories are used as an example for illustration purposes.

[0035] FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1 , the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to transmit or receive data from the memory device 104.

[0036] According to some examples, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some examples, the memory controller 106 is designed to operate in low-load environments, such as with Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some examples, the memory controller 106 is designed to operate in high-load environments with solid-state disks (SSDs) or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and enterprise storage arrays.

[0037] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some examples, the memory controller 106 is further configured to process error correction codes (ECC) on data read from or written to the memory device 104. Any other suitable functions may also be performed by the memory controller 106, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with external devices through at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, and the like.

[0038] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices and included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged in different types of end electronic products. In one example, as shown in FIG. 2a, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a SmartMedia (SM) card, a Memory Stick, a MultiMediaCard (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can further include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 of FIG. 1). In another example, as shown in FIG. 2b, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 may further include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG. 1 ). In some examples, the SSD 206 has at least one of a storage capacity or an operating speed greater than that of the memory card 202.

[0039] FIG. 3A is a schematic diagram of a memory cell array of a 3D NAND memory. As shown in FIG. 3A, the memory cell array of the 3D NAND memory consists of several rows of memory cells arranged parallel to and staggered with respect to a gate insulating structure. The memory cell rows are separated by a gate insulating structure and a top selective gate insulating structure, and each memory cell row includes a plurality of memory cells. The gate insulating structure may include a first gate insulating structure and a second gate insulating structure. The first gate insulating structure divides the memory cell array into a plurality of memory blocks. The plurality of second gate insulating structures can divide the memory blocks into a plurality of memory fingers. The top selective gate insulating structure disposed in the middle of each memory finger can divide the memory finger into two parts, thereby dividing the memory finger into two memory strings. The memory block shown in FIG. 3A includes six memory strings. In practical applications, the number of memory strings in a memory block is not limited to this.

[0040] In some examples, each memory block may be coupled to multiple word lines, with multiple memory cells coupled to each individually controlled word line forming a memory page, and a page as referred to herein is a physical page. For example, all memory cells coupled to one word line in each memory string in FIG. 3a form one page.

[0041] 3a is merely an example and is not used to limit the number of memory cell rows included in one memory finger of the 3D NAND memory in the present disclosure. In actual applications, the number of memory cell rows included in one memory finger may be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0042] FIG. 3b is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be an example of the memory device 104 in FIG. 1. The memory device 300 may include a memory cell array 301 and peripheral circuits 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as an example of a three-dimensional NAND-type memory cell array, in which the memory cells 306 are NAND-type memory cells provided in the form of an array of memory strings 308, each extending vertically above a substrate (not shown). In some examples, each memory string 308 includes multiple memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, depending on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be either a floating-gate memory cell including a floating-gate transistor or a charge-trapping memory cell including a charge-trapping transistor.

[0043] In some examples, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some examples, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, an MLC can store two bits per cell (also called a double-level cell), three bits per cell (also called a triple-level cell (TLC)), four bits per cell (also called a quad-level cell (QLC)), five bits per cell (also called a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value being used for the erased state.

[0044] As shown in FIG. 3b, each memory string 308 includes a bottom selective transistor 310 (also called a source side selective transistor and including a source selective gate BSG) on its source side and a top selective transistor 312 (also called a drain side selective transistor and including a drain selective gate TSG) on its drain side. The source selective transistor BSG 310 and the drain selective transistor TSG 312 can be configured to activate a selected memory string 308 during read and program operations. In some examples, the sources of memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314, e.g., a common SL. In other words, according to some examples, all memory strings 308 in the same memory block 304 have an array common source (ACS). The TSG 312 of each memory string 308 is coupled to a respective bit line 316, to which data can be read and written via an output bus (not shown), according to some examples. In some examples, each memory string 308 is configured to be selected or deselected by at least one of applying a select voltage (e.g., above the threshold voltage of the transistor comprising the TSG 312) or a deselect voltage (e.g., 0V) to the respective TSG 312 through one or more TSG lines 313, or applying a select voltage (e.g., above the threshold voltage of the transistor comprising the BSG 310) or a deselect voltage (e.g., 0V) to the respective BSG 310 through one or more BSG lines 315.

[0045] As shown in FIG. 3b, a NAND memory string 308 may be organized into multiple memory blocks 304, each of which may have a common source line 314, for example, coupled to ground. In some examples, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 in the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, the source line 314 coupled to the selected memory block 304, as well as unselected memory blocks 304 in the same plane as the selected memory block 304, may be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20 V or greater). It will be understood that in some examples, erase operations may be performed at a half-memory block level, a quarter-memory block level, or a level having any suitable number of memory blocks or any suitable fraction of a memory block. Memory cells 306 of adjacent memory strings 308 may be coupled through word lines 318 that select which rows of memory cells 306 are affected by read and program operations. In some examples, referring to FIG. 3a above, multiple memory cells are isolated by a top selective gate insulating structure and a gate insulating structure. The multiple memory cells between the top selective gate insulating structure and the gate insulating structure are arranged into multiple memory cell rows, with each memory cell row being parallel to the gate insulating structure and the top selective gate insulating structure. Memory cells in a string that share the same word line form physical pages 320, and each physical page 320 can be mapped to at least one logical page based on the storage mode (e.g., SLC or MLC as described above) of the corresponding memory cell 306. A logical page can constitute a basic data unit for program and read operations.

[0046] Referring to Figures 3a and 3b, it can be seen that each memory cell 306 of the plurality of memory cells is coupled to a respective word line 318, and each memory string 308 is coupled to a respective bit line 316 via a respective selective transistor (such as a top selective transistor (TSG) 312).

[0047] 4 shows a schematic cross-sectional view of an exemplary memory cell array 301 including a memory string 308 exemplified by a NAND, according to an embodiment of the present disclosure. As shown in FIG. 4, the NAND memory cell array 301 may include a stacked structure 410 including multiple gate layers 411 and multiple insulating layers 412 stacked in alternating order, and a channel structure vertically penetrating the gate layers 411 and insulating layers 412. The channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with multiple gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and insulating layers 412 may be stacked alternately, with two adjacent gate layers 411 separated by the insulating layer 412.

[0048] The constituent material of the gate layer 411 may include a conductive material. The conductive material may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some examples, each gate layer 411 may include a metal layer, such as a tungsten layer. In some examples, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 on top of the stacked structure 410 may extend laterally as a top selective gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a bottom selective gate line, and the gate layer 411 extending laterally between the top selective gate line and the bottom selective gate line may be used as a word line layer.

[0049] In some examples, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0050] In some examples, the memory string 308 includes a channel structure extending vertically through the stack structure 410. In some examples, the channel structure includes a channel hole filled with a semiconductor material (e.g., as a semiconductor channel) and a dielectric material (e.g., as a memory film). In some examples, the semiconductor channel includes silicon, e.g., polysilicon. In some examples, the memory film is a composite dielectric layer including a tunnel layer, a storage layer (also referred to as a "charge trap / storage layer"), and a blocking layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some examples, the semiconductor channel, tunnel layer, storage layer, and blocking layer are radially arranged in this order from the center of the pillar toward the outer surface of the pillar. The tunnel layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0051] Referring again to FIG. 3b, peripheral circuitry 302 may be coupled to memory cell array 301 through bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target memory cell 306 through bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. Peripheral circuitry 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 5 illustrates some exemplary peripheral circuits, where peripheral circuitry 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an I / F interface 516, and a data bus 518. It will be appreciated that in some examples, additional peripheral circuitry not shown in FIG. 5 may be included as well.

[0052] The page buffer / sense amplifier 504 may be configured to read data from and program (write) data into the memory cell array 301 according to control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 may store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 may perform a program verify operation to confirm that data has been properly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 may sense low-power signals from the bit lines 316 representing data bits stored in the memory cells 306 and amplify small voltage swings to recognizable logic levels in a read operation. The column decoder / bit line driver 506 may be controlled by the control logic 512 and configured to select one or more memory strings 308 by applying bit line voltages generated from a voltage generator 510.

[0053] The row decoder / word line driver 508 may be controlled by the control logic 512 and configured to select / deselect memory blocks 304 of the memory cell array 301 and select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 may be further configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some examples, the row decoder / word line driver 508 may also select / deselect and drive the BSG lines 315 and TSG lines 313 as well. As described in more detail below, the row decoder / word line driver 508 is configured to perform program operations on memory cells 306 coupled to selected word lines 318. The voltage generator 510 may be controlled by the control logic 512 and configured to generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0054] The control logic 512 may be coupled to the other portions of the peripheral circuits described above and configured to control the operation of the other portions of the peripheral circuits. The registers 514 may be coupled to the control logic 512 and may include a status register, a command register, and an address register that store status information, command operation codes (OP codes), and command addresses for controlling the operation of the peripheral circuits. The interface 516 may be coupled to the control logic 512 and may operate as a control buffer that buffers and relays control commands received from a host (not shown) to the control logic 512 and buffers and relays status information received from the control logic 512 to the host. The interface 516 may further be coupled to the column decoder / bit line driver 506 via a data bus 518 and may operate as a data I / O interface and data buffer that buffers and relays data to and from the memory cell array 301.

[0055] It should be understood that in the process of writing data, multiple operations are required, and both the performance of writing data and the correctness of data are important characteristics of a memory system. Therefore, high requirements are imposed on the process of writing data. In the existing process of writing data, some special processing may be performed to ensure the stability of data. For example, an operation of filling dummy data in a memory cell array may be performed. The dummy data here may be any random data. The dummy data is not intended to be read, but it plays a specific role, such as mitigating the coupling effect of a memory page without data written to an adjacent memory page with data written, thereby better retaining data in the written memory cell.

[0056] The memory system may include a memory controller and a memory device. The memory device may include a memory cell array and peripheral circuits. The memory cell array may include multiple memory blocks, and each memory block may include multiple memory pages. During the process of writing data, some memory blocks in the memory device may not have data completely written to them. The physical characteristics of the memory system require that, when the power is turned off (or shut down) or under certain conditions, a dummy data filling operation needs to be performed on the memory blocks that have not been completely written to ensure the stability of the written data. In some examples, a method of filling dummy data includes: a memory controller sending a special command to the memory device, the special command indicating that some memory pages in the memory device should be filled with dummy data; sending corresponding dummy data to be written to the memory device; and, after the memory device receives the special command and the dummy data to be written, filling the received dummy data into the memory pages that need to be filled with dummy data. However, the above-mentioned process of filling dummy data is time-consuming, and the content of the filled dummy data is data that users do not care much about.

[0057] Based on one or more of the above problems, examples of the present disclosure propose a memory device, an operating method thereof, and a memory system. Referring to FIGS. 1 and 6, a memory system 102 includes at least one memory device 104 and a memory controller 106 coupled to the memory device and configured to control the memory device. The memory controller 106 can access or control the memory device 104 according to specific timing rules. The memory controller 106 enables a host 108 (a device accessing the memory device) to use storage resources on the memory device 104 according to its own requirements via address signals (address information / address instructions, ADDR), data signals (data instructions, DATA), control signals (control instructions, CTRL), and various command signals (CMD). The memory device 104, as referred to herein, includes a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. Referring to FIG. 7, a method of operating the memory device includes the following operations. ACT S701: A first command instructing to write dummy data to a specified location in the memory cell array 301 is received. Operation S702: In response to the first command, generate dummy data to be written. Operation S703: The dummy data to be written is written to the designated location.

[0058] The memory cell array 301 may include multiple memory planes, each of which may include multiple memory blocks, and each of which may include multiple memory pages. A memory page is the smallest unit for read and write (i.e., program) operations, and a memory block is the smallest unit for erase operations. In some examples, each memory block may include multiple valid memory pages and multiple dummy memory pages. The aforementioned memory pages may be understood to refer to valid memory pages and dummy memory pages herein. A valid memory page is a memory page included in an area corresponding to a word line (WL) or a channel hole (CH) and configured to store user data (actual data), with a storage channel structure formed within the storage channel hole. A dummy memory page is a memory page included in an area corresponding to a dummy word line (DWL) or a dummy channel hole (DCH). The dummy memory page is configured for special functions such as support, fault repair, bad block handling, and the like, and is not configured to store actual data. Here, a dummy channel structure is formed within the dummy channel hole. The valid memory pages and the dummy memory pages may be arranged spaced apart or adjacently, and it should be understood that the valid memory pages and the dummy memory pages are all physical memory pages.

[0059] The peripheral circuitry 302 may include at least one of any suitable digital, analog, or mixed-signal circuitry configured to facilitate various operations of the memory device, such as reading, writing, erasing, and the like. For example, the peripheral circuitry may include control logic (such as a control circuit or controller), data buffers, decoders (decoders may also be referred to as decoders), drivers, read and write circuits, etc. When the control logic receives commands and address data for read and write operations, the decoder can apply corresponding voltages from the drivers to corresponding bit lines and word lines based on the addresses decoded under the control logic, thereby realizing data reading and writing, and data interaction with the outside world through the data buffer.

[0060] 5, more specifically, the I / F interface 516 is used to receive a first instruction and transmit the first instruction to the control logic 512. The control logic 512 is used to generate dummy data according to the first instruction, and the page buffer / sense amplifier 504, the column decoder / bit line driver 506, the row decoder / word line driver 508, the voltage generator 510, and the control logic 512 are used to collectively write the dummy data.

[0061] In operation S701, a first command is received.

[0062] In some examples, when there is a memory block in the memory cell array that is not completely filled, the memory controller or host transmits a first command to instruct the memory device to fill a specified location with dummy data. Here, the first command may include a first command CMD and a plurality of address commands ADDR. Here, the memory device 104 is used to receive the first command, and the first command CMD is used to instruct the memory device 104 to write the dummy data to a specified location in the memory cell array 301. For example, referring to FIG. 8 , it can be seen that the plurality of address commands ADDR includes a 4-bit row address (R1, R2, R3, R4) that is the address of the specified location in the memory cell array 301. In some examples, the first command is configured by a set feature command or the first command includes a first flag set on a reserved field of a write command.

[0063] In some specific examples, the first instruction is configured by a set feature command. Here, it is assumed that the memory device supports the set feature command, and the set feature command may also be supported by the memory controller or the host. Under this assumption, the first instruction may be directly configured by the set feature command. The set feature command allows a user-defined protocol, such as the first instruction, to be directly edited to realize communication regarding the first instruction between the memory device and the memory controller or the host. Note that when the first instruction is configured by the set feature command, the command in which the first instruction is placed does not include dummy data to be written, but includes a page program command, i.e., a dummy data write command and an address of the dummy data to be written. In one example, the first command of the dummy data write command in the ONFI protocol is an 81h command.

[0064] In some specific examples, the first instruction includes a first flag set on a reserved field of the write command. That is, in some examples, the first instruction may be embedded in a normal write command of the memory device. The normal write command may include a first part and a second part, where the first part includes an address instruction (address information) and the second part includes data information. In examples of the present disclosure, the first instruction includes a first flag set on a reserved field of the write command, that is, the first instruction is embedded in the reserved field of the write command (hereinafter, this type of write command is referred to as a special write command for short). For example, referring to FIG. 9, FIG. 9 shows a schematic diagram of address information of a write command corresponding to a triple-level cell (TLC). The write command includes six sets of address information (first, second, third, fourth, fifth, sixth), and the sixth set (sixth) of address information is set with a plurality of reserved addresses (a plurality of LOWs shown in dotted boxes in FIG. 9), and the reserved field of the write command may be any one of the plurality of reserved addresses in the sixth set (sixth) of address information. In other words, any one of the plurality of reserved addresses shown in the dotted boxes in FIG. 9 may be used to set the first flag.

[0065] When the first instruction includes a first flag set on a reserved field of the write command, the peripheral circuit responds to the first instruction by directly generating dummy data to be written without receiving data information included in the write command. Because the memory device does not receive data information, the memory controller or host may randomly generate invalid data information to meet the format requirements of the write command when generating the corresponding special write command. Furthermore, when sending these special write commands, the memory controller or host may transmit only an address instruction without transmitting data information. In this way, the memory device can receive only address information through the first instruction without receiving data information.

[0066] In some other examples, the first instruction may further be configured with a vendor command. Here, a vendor-specific command is a command that is not generally available but is used only for a specific agreed-upon vendor, such as a manufacturer. The vendor-specific command is available only if the user is an agreed-upon vendor. When configured with the vendor command, the protocol on the memory device side and the memory controller side needs to be updated, i.e., the protocol needs to be agreed upon again between the two sides. Similarly, the command in which the first instruction is placed does not need to include data information.

[0067] In some examples, the memory controller or host does not generate the dummy data when sending the initial command to write the dummy data to a specified location in the memory cell array.

[0068] Here, the designated location may include any location within the memory cell array of the memory device to which data has not been written. In some examples, the designated location may be: At least one of the plurality of memory blocks, at least one valid memory page in an erased state in one of the memory blocks; and At least one of the dummy memory pages in one of the memory blocks Contains one of the following:

[0069] In some examples, the specified location may include at least one of multiple memory blocks. When a specific memory block or blocks (i.e., blank memory blocks) in the memory cell array does not have data stored therein and some special test operation, such as checking whether the programming count and erase count are normal or checking the erase time, needs to be performed, data needs to be written to these memory blocks, but the written data itself is not of interest. At this time, dummy data can be written into these memory blocks to achieve the purpose of quick testing. In some examples, the specified location may include at least one valid memory page in an erased state in one of the memory blocks, and memory pages adjacent to the specified location are in a programmed state. When some memory pages in a memory block are written with data, i.e., some of the memory pages are in a programmed state, and the remaining memory pages are not written with data, it can be understood that another part of the memory pages is in an erased state. The level of a memory page in an erased state is different from that of a memory page in a programmed state, and electrons in a memory page in a programmed state adjacent to a memory page in an erased state are shifted, i.e., an electron coupling effect occurs. As a result, data retention in the memory page in a programmed state is reduced. Based on this, when some memory pages in a memory block are written with data, dummy data can be stored in one or more memory pages to which data has not been written that are adjacent to the memory pages to which data has been written, thereby reducing the electronic coupling effect of the memory pages in the programmed state.

[0070] In some examples, the specified location may include all remaining valid memory pages in an erased state in one of the memory blocks. It can be understood that a memory block is the smallest execution unit for an erase operation. In the process of performing an erase operation on a memory block, not only are memory pages in the erased memory block to which data has been written erased, but also valid memory pages in the memory block to which no data has been written, i.e., in an erased state, are erased. As a result, valid memory pages in an erased state may be over-erased, which may cause problems such as memory cell leakage current. At this time, writing dummy data to all remaining valid memory pages in an erased state in the memory block can reduce the probability of over-erasing and improve the performance of the memory device. In some examples, as described above, multiple memory pages in a memory block are divided into valid memory pages and dummy memory pages, where the valid memory pages are configured to store data and the dummy memory pages are configured for special functions such as support, fault repair, bad block handling, etc. It can be understood that when a dummy memory page is set adjacent to a valid data memory page, the above-mentioned electronic coupling effect may also exist between the dummy memory page and the valid data memory page, and the above-mentioned over-erase problem exists even when there is no data stored in the dummy memory page, i.e., when the dummy memory page is in an erased state. In this case, storing dummy data in the dummy memory page can reduce the electronic offset of the valid memory page adjacent to the dummy memory page and alleviate the over-erase problem, thereby improving the performance of the memory device.

[0071] In operation S702, the memory device autonomously generates dummy data to be written in response to the first command.

[0072] In some examples, generating dummy data to be written includes: This includes randomly generating dummy data to be written, or generating dummy data to be written in accordance with data stored in locations adjacent to the specified location in combination with a preset algorithm.

[0073] It is understood that the user does not care much about the content of the dummy data, and the dummy data does not need to be read and reused later. Based on this, the dummy data can be randomly generated by the memory device according to its own characteristics, or can be calculated according to its own actual requirements.

[0074] In some particular examples, the randomly generated dummy data may be all "0's", or all "1's", or a random combination of "1's" and "0's".

[0075] In some other specific examples, to reduce the electronic coupling effect between adjacent memory pages, a set of dummy data may be calculated based on data of memory pages in a programmed state and in combination with a preset algorithm, where the adjacent memory pages may be memory pages to which data is written and adjacent memory pages to which data is not written. The preset algorithm relates to the coupling effect between memory cells in a memory cell array.

[0076] It can be understood that when the stored data corresponding to a memory cell of a particular memory page includes a "1" or a "0", electrons are located in different layers of the channel structure. At this time, when an adjacent memory page is in an erased state, the positions of the electrons are fixed, and the electrons at the fixed positions have different coupling effects with adjacent electrons in different layers. At this time, dummy data that minimizes the coupling effect is derived from the data in the memory page to which data is written, thereby obtaining more accurate dummy data to be written, thereby more accurately reducing the electronic coupling effect between adjacent memory pages and improving data stability.

[0077] In operation S703, the generated dummy data to be written is written to the specified location.

[0078] Note that the generated dummy data to be written also first goes into the page buffer and then is written from the page buffer to the designated location of the memory cell.

[0079] Based on this, after receiving a first instruction instructing to fill a specified location with dummy data, the memory device in the above example of the present disclosure generates dummy data according to its own characteristics and stores the dummy data in the specified location. In this way, on the one hand, the memory device generates dummy data according to its own characteristics instead of the memory controller transmitting dummy data to the memory device. Therefore, the transmission time of the dummy data can be saved, the time for filling the dummy data can be shortened, and the throughput of the memory system can be improved. On the other hand, storing the dummy data in the specified location can reduce the coupling effect between memory pages in the memory device to which data is written and memory pages to which data is not written, and the stability of the written data can be improved.

[0080] In actual operation, some application scenarios require that data in a memory cell array be read. For example, after a memory device encounters an abnormal power failure, all data currently stored in the memory device are read, and based on the read result, a decision is made after the abnormal power failure and a data recovery strategy is determined. In the following, we will introduce how to deal with the situation where dummy data already stored in the memory device is read in these scenarios.

[0081] In some examples, the method includes receiving a second instruction directing a read operation to be performed on data in the memory cell array; and returning the data to be read in response to the second command, wherein when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes dummy data.

[0082] The second command received by the memory device is a read command, and the second command includes address information for performing a read operation. For example, referring to FIG. 10, the read command shown in FIG. 10 includes a data bus DQ[7:0], a cycle type of the read operation (Cycle Type), column address information (C1, C2), row address information (R1, R2, R3, R4), and a waiting time (tWB, tR, tRR) after sending the read command. The memory device reads memory pages corresponding to the column address information (C1, C2) and row address information (R1, R2, R3, R4) according to the instructions of the second command, and after reading the data of the corresponding memory pages, returns the read data to the memory controller or the host. The memory controller or the host can determine whether the read data includes dummy data according to the returned data.

[0083] In some examples, when the data to be read includes dummy data, a second flag is set on a reserved field of the frame header of the returned data frame. After receiving the returned data to be read, the memory controller or host determines whether to decode the returned data to be read according to whether the second flag is present in the returned data frame. When the second flag is present in the returned data frame, this indicates that the returned data to be read includes dummy data. At this time, the memory controller or host stops receiving the remaining data frames or does not perform a decoding operation on the returned data to be read. When the second flag is not present in the returned data frame, this indicates that the returned data to be read does not include dummy data. At this time, the memory controller or host continues receiving the remaining data frames and performs a decoding operation on the returned data to be read.

[0084] It should be noted that there are two situations for the returned data. One is a situation where there is no dummy data in the returned data (all of the data is real data), and at this time the memory controller performs normal operation. The other is a situation where there is dummy data in the returned data, and at this time two methods can be used to distinguish the dummy data. The first situation is a situation where the returned dummy data has a corresponding flag, such as the second flag described above, and the dummy data can be selected using the flag. The second situation is a situation where the returned dummy data does not have any flag, and at this time, considering that the dummy data is generated by the memory device according to its own characteristics, its address is not stored in the logical-physical mapping table (LTP). At this time, the real data can be selected according to the logical-physical mapping table, and the remaining data is dummy data.

[0085] It should also be noted that when dummy data is written to a memory device, the dummy data is not encoded like normal data. Based on this, the write duration of the dummy data is shorter than the write duration of normal valid data. However, when decoding the dummy data, there will be a decoding failure. Since users do not care about the dummy data, the dummy data can be discarded directly.

[0086] In some examples, the method further includes writing the dummy data to be written to the specified location, then saving the specified location; checking whether an address corresponding to the data to be read is within an address range corresponding to the saved specified location before returning the data to be read; and determining that the data to be read includes dummy data when the address corresponding to the data to be read is within an address range corresponding to the saved specified location.

[0087] That is, after writing dummy data to a specified location in the memory cell array of the memory device, the memory device saves an address corresponding to the specified location. After reading the address of the data to be read in the memory cell array in accordance with the instructions of the second instruction, the memory device checks whether the address corresponding to the data to be read is within the address range corresponding to the stored specified location. If the address corresponding to the data to be read is within the address range corresponding to the stored specified location, this indicates that the data to be read contains dummy data. At this time, a second flag can be set on a reserved field in the frame header of the returned data frame. If the address corresponding to the data to be read is not within the address range corresponding to the stored specified location, this indicates that the data to be read does not contain dummy data, and at this time, the second flag can be not set on the reserved field in the frame header of the returned data frame. In this manner, a criterion for whether dummy data is included in the returned data can be provided.

[0088] Meanwhile, an example of the present disclosure further provides a memory device, comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array; The peripheral circuitry is receiving a first instruction instructing to write dummy data to a specified location in the memory cell array; generating dummy data to be written in response to the first command; It is configured to write the dummy data to be written at the specified location.

[0089] In some examples, the first instruction comprises a set feature command, or the first instruction includes a first flag set on a reserved field of a write command.

[0090] In some examples, when the first instruction is configured by a set feature command, the command in which the first instruction is placed does not include dummy data to be written; When the first instruction includes a first flag set on a reserved field of the write command, the peripheral circuit is configured to respond to the first instruction by not receiving data information included in the write command but directly generating dummy data to be written.

[0091] In some examples, the peripheral circuitry includes: Randomly generate dummy data to be written, or or It is configured to generate dummy data to be written in accordance with data stored in locations adjacent to the specified location in combination with a preset algorithm.

[0092] In some examples, the preset algorithms relate to coupling effects between memory cells in a memory cell array.

[0093] In some examples, the memory cell array comprises a plurality of memory blocks, each of the memory blocks comprising a plurality of valid memory pages and a plurality of dummy memory pages; The specified location is At least one of the plurality of memory blocks, at least one valid memory page in an erased state in one of the memory blocks; and At least one of the dummy memory pages in one of the memory blocks Contains one of the following:

[0094] In some examples, the specified location includes at least one of the valid memory pages in one of the memory blocks in an erased state, and memory pages adjacent to the specified location are in a programmed state.

[0095] In some examples, the peripheral circuitry includes: receiving a second instruction instructing to perform a read operation on data in the memory cell array; Further configured to return the data to be read in response to the second instruction, and when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes dummy data.

[0096] In some examples, the peripheral circuitry includes: Writes the dummy data that should be written to the specified location, then saves the specified location, Before returning the data to be read, check whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored; The device is further configured to determine that the data to be read includes dummy data when the address corresponding to the data to be read is within an address range corresponding to the stored specified location.

[0097] In some examples, the memory device includes a NAND type memory.

[0098] It should be noted that the above hardware parts and the general operating principles of the memory device may be understood in accordance with the above-mentioned Figures 3a to 5, and the above-mentioned method of processing dummy data by the memory device may refer to what has been described above with respect to the above-mentioned method of processing dummy data in the operating method of the memory device.

[0099] In yet another aspect, examples of the present disclosure further disclose a memory system, the memory system including one or more memory devices as described in the previous examples of the present disclosure; and a memory controller coupled to the memory device and configured to control the memory device to perform read, write, and erase operations. Here, the memory controller and the memory device may be coupled in any suitable manner. In the example of the present disclosure, the memory device may be a semiconductor memory that stores data in a non-volatile manner, such as a NAND-type memory. The memory system is connected to a host, which may be an electronic device such as a personal computer or a mobile terminal.

[0100] In some examples, the memory system includes a Universal Flash Storage (UFS) device or a solid state disk.

[0101] In yet another aspect, examples of the present disclosure further disclose a memory system, comprising: at least one memory device; and a memory controller coupled to the memory device and configured to control the memory device; The memory device comprises a memory cell array and peripheral circuits coupled to the memory cell array; the memory controller is configured to send a first command, the first command including a first instruction and a plurality of address instructions, the first instruction instructing to write dummy data to specified locations corresponding to the plurality of address instructions; The peripheral circuitry within the memory device is configured to receive a first command, generate dummy data to be written in response to the first command, and write the dummy data to be written to specified locations corresponding to the plurality of address instructions.

[0102] Here, in this example, the first command is issued by the memory controller.

[0103] In some examples, the memory controller is configured to send a second command, the second command including a second instruction, the second instruction directing performing a read operation on data in the memory cell array; the peripheral circuit is configured to receive a second command and, in response to the second command, return the data to be read, wherein when the data to be read includes dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes dummy data; The memory controller is further configured to receive the returned data to be read, and when the returned data frame includes a second flag, stop receiving the remaining data frames or not perform a decoding operation on the returned data to be read.

[0104] Here, in this example, the second command is issued by the memory controller.

[0105] In some examples, the memory controller is configured to send a second command, the second command including a second instruction, the second instruction directing performing a read operation on data in the memory cell array; the peripheral circuit is configured to receive a second command and, in response to the second command, return data to be read, the data to be read including dummy data; The memory controller is further configured to receive the returned data to be read, and to discard the data to be read when decoding of the returned data to be read fails.

[0106] Examples of the present disclosure provide a storage medium having executable instructions stored thereon, which, when executed by a memory controller, may implement the operations of any one of the methods described in the preceding examples.

[0107] In the examples of the present disclosure, the storage medium may be a NAND-type memory in a memory device, and the executable instructions may be stored in the NAND-type memory, which may be firmware in the above examples. In this manner, the memory controller may execute the executable instructions in the storage medium, thereby implementing operations in any one of the methods in the foregoing examples.

[0108] It should be understood that throughout this specification, when a reference is made to "some examples" or "one example," this means that a particular feature, structure, or characteristic associated with the example is included in at least one example of the present disclosure. Thus, the appearance of the phrase "in some examples" or "in one example" in various places throughout this specification does not necessarily all refer to the same example. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. It should be understood that in the various examples of the present disclosure, the serial numbers of the processes described above do not imply an order of execution, and that the order of execution of the processes should be determined by the functionality and inherent logic of the exemplary processes of the examples of the present disclosure, rather than limiting them. The serial numbers of the above-mentioned examples of the present disclosure are for illustrative purposes only and do not represent advantages or disadvantages of the examples.

[0109] The above is merely a preferred example of the present disclosure and does not limit the patent scope of the present disclosure. Under the inventive concept of the present disclosure, any equivalent structural transformation made by using the contents of the present disclosure and the accompanying drawings, or any direct or indirect application in any other related technical field, falls within the patent protection scope of the present disclosure. [Explanation of symbols]

[0110] 100 systems 102 Memory System 104 Memory Devices 106 Memory Controller 108 Host 202 Memory Card 204 memory card connector 206 SSD 208 SSD connector 300 memory devices 301 Memory Cell Array 302 Peripheral Circuit 304 memory blocks 306 memory cells 308 Memory String 310 Bottom Selective Transistor 312 Top Selective Transistor 313 TSG Line 314 Source Line (SL) 315 BSG line 316 bit lines 318 Word Line 320 physical pages 401 Substrate 410 Laminated structure 411 Gate Layer 412 Insulating layer 504 Page Buffer / Sense Amplifier 506 Column Decoder / Bit Line Driver 508 Row Decoder / Word Line Driver 510 Voltage Generator 512 Control Logic 514 registers 516 I / F interface 518 Data Bus

Claims

1. 1. A memory device comprising: a memory cell array; a peripheral circuit coupled to the memory cell array, the peripheral circuit comprising: receiving a first command instructing to write dummy data to a specified location in the memory cell array; generating the dummy data to be written in response to the first command; writing the dummy data to be written at the specified location; receiving a second command instructing to perform a read operation on data in the memory cell array; configured to return the data to be read in response to the second command; When the data to be read includes the dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes the dummy data. Memory device.

2. the first instruction consists of a set feature command, or 10. The memory device of claim 1, wherein the first instruction includes a first flag set on a reserved field of a write command.

3. When the first instruction is configured by the set feature command, the command in which the first instruction is placed does not include the dummy data to be written; When the first instruction includes the first flag set on the reserved field of the write command, the peripheral circuit 3. The memory device of claim 2, configured to, in response to the first instruction, not receive data information included in the write command, but directly generate the dummy data to be written.

4. The peripheral circuit includes: Randomly generating the dummy data to be written; or 10. The memory device of claim 1, configured to generate the dummy data to be written according to data stored at locations adjacent to the specified location in combination with a preset algorithm.

5. The memory device of claim 4 , wherein the preset algorithm relates to coupling effects between memory cells in the memory cell array.

6. the memory cell array comprises a plurality of memory blocks, each of the memory blocks comprising a plurality of valid memory pages and a plurality of dummy memory pages; The specified location is at least one of the plurality of memory blocks; at least one of the valid memory pages in an erased state in one of the memory blocks; or At least one of the dummy memory pages in one of the memory blocks 10. The memory device of claim 1, comprising one or more of:

7. The specified location is 7. The memory device of claim 6, wherein at least one of the valid memory pages in one of the memory blocks is in an erased state and a memory page adjacent to the specified location is in a programmed state.

8. The peripheral circuitry comprises: After writing the dummy data to be written in the specified location, save the specified location; before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored; 2. The memory device of claim 1, further configured to determine that the data to be read includes the dummy data when the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored.

9. 10. The memory device of claim 1, comprising a 3D NAND memory.

10. 1. A memory system comprising: at least one memory device, a memory cell array; at least one memory device comprising: peripheral circuitry coupled to the memory cell array; a memory controller coupled to the memory device and configured to control the memory device; The memory controller configured to send a first command, the first command including a first instruction and a plurality of address instructions, the first instruction instructing to write dummy data to designated locations corresponding to the plurality of address instructions; The peripheral circuitry in the memory device includes: receiving the first command; generating the dummy data to be written in response to the first command; writing the dummy data to be written at the specified locations corresponding to the plurality of address instructions; receiving the second instruction instructing to perform a read operation on data in the memory cell array; configured to return the data to be read in response to the second command; When the data to be read includes the dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes the dummy data. Memory system.

11. The memory controller configured to send a second command, the second command including a second instruction, the second instruction directing a read operation to be performed on data in the memory cell array; Receive the returned data to be read; 11. The memory system of claim 10, further configured to: stop receiving remaining data frames or not perform a decoding operation on the returned data to be read when the returned data frame includes the second flag.

12. The memory controller configured to send a second command, the second command including a second instruction, the second instruction directing a read operation to be performed on data in the memory cell array; The peripheral circuit includes: receiving the second instruction; configured to return the data to be read in response to the second command; the data to be read includes the dummy data; The memory controller Receive the returned data to be read; 11. The memory system of claim 10, further configured to discard the data to be read when decoding of the returned data to be read fails.

13. The memory system of claim 10 including a solid state disk.

14. 1. A method of operating a memory device, comprising: receiving a first instruction to write dummy data to specified locations in a memory cell array of the memory device; generating the dummy data to be written in response to the first command; writing the dummy data to be written in the specified location; receiving a second command instructing to perform a read operation on data in the memory cell array; and returning the data to be read in response to the second command; When the data to be read includes the dummy data, a second flag is set on a reserved field of a frame header of the returned data frame, the second flag indicating that the read data includes the dummy data. method.

15. the first instruction consists of a set feature command, or 15. The method of claim 14, wherein the first instruction includes a first flag set on a reserved field of a write command.

16. When the first instruction is configured by the set feature command, the command in which the first instruction is placed does not include the dummy data to be written; 16. The method of claim 15, wherein, when the first instruction includes the first flag set on the reserved field of the write command, in response to the first instruction, the method does not receive data information included in the write command and directly generates the dummy data to be written.

17. The step of generating the dummy data to be written comprises: randomly generating the dummy data to be written; or 17. The method of claim 16, further comprising generating the dummy data to be written in accordance with data stored in locations adjacent to the specified location in combination with a preset algorithm.

18. The method of claim 17, further comprising: writing the dummy data to be written to the specified location, and then saving the specified location; before returning the data to be read, checking whether the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored; and determining that the data to be read includes the dummy data when the address corresponding to the data to be read is within the address range corresponding to the specified location where it is stored.

19. A memory device as described in claim 1, wherein when the data to be read does not include the dummy data, the second flag is not set on the reserved field of the frame header of the returned data frame.

20. The method described in claim 15, wherein when the data to be read does not include the dummy data, the second flag is not set on the reserved field of the frame header of the returned data frame.

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