Substrate processing apparatus, substrate processing method, and storage medium

Abstract

To increase the throughput of a substrate processing device with the suppression of an exclusive floor area.SOLUTION: The substrate processing device includes: one processing block and another processing block provided on either of the right and left sides of a carrier loading unit of a carrier block in a plan view; a substrate transfer region which includes a first transfer mechanism provided on the carrier block; a loading unit lamination having, in a longitudinal direction, an overlaid configuration of a first loading unit, a second loading unit and a third loading unit, on which a substrate is delivered respectively by the first transfer mechanism, a main transfer mechanism of the one processing block and a main transfer mechanism of the other processing block, and provided on one of the front and the rear sides relative to the first transfer mechanism in a plan view; and a second transfer mechanism for substrate transfer between the first loading unit and the second loading unit and between the first loading unit and the third loading unit, respectively, which is provided in the transfer region to sandwich the lamination from the front and back in a plan view together with the first transfer mechanism.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a substrate processing apparatus, a substrate processing method, and a storage medium. [Background technology]

[0002] In the manufacturing process of semiconductor devices, semiconductor wafers (hereinafter referred to as wafers) are transported between various processing modules in a substrate processing apparatus to undergo processes such as liquid processing and heat treatment. Wafers are transported to the substrate processing apparatus by a carrier. Patent Document 1 discloses a substrate processing apparatus equipped with a carrier block that transfers wafers to and from the carrier. This carrier block is provided with two transport mechanisms that sandwich a stack consisting of multiple substrate mounting sections, and each transport mechanism includes a holder for transferring wafers between the mounting sections and a holder for transferring wafers to and from the carrier. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-69916 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a technique that can increase the throughput of a substrate processing apparatus while reducing the floor space required. [Means for solving the problem]

[0005] The substrate processing apparatus according to the present disclosure includes a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed; a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view; a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block; a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view; a first transport mechanism for transferring the substrate to and from the carrier; a stack of platform parts, which are configured such that a first platform part, a second platform part, and a third platform part to which the substrates are transferred by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, are stacked one on top of the other in the vertical direction, and which are provided in the transport region in a plan view; a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers; Equipped with 、 In a plan view, a direction in which the stack of the carriers on the placement section is located relative to a position where the first transport mechanism is provided in the carrier block differs by 90° from a direction in which the carrier placement section is located relative to a position where the first transport mechanism is provided; Of the first transport mechanism and the second transport mechanism, only the first transport mechanism delivers the substrate to and from the carrier. Another substrate processing apparatus according to the present disclosure includes: a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed; a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view; a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block; a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view; a first transport mechanism for transferring the substrate to and from the carrier; a stack of platform parts, which are configured such that a first platform part, a second platform part, and a third platform part to which the substrates are transferred by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, are stacked one on top of the other in the vertical direction, and which are provided in the transport region in a plan view; a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers; Equipped with a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided on one of the front and rear sides of the second transfer mechanism; If the processing module of the one processing block and the processing module of the other processing block are referred to as a first processing module and a second processing module, respectively, the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module that supplies a coating liquid to the substrate to form a coating film; the fourth processing module is a hydrophobic processing module that performs a gas processing on the substrate to hydrophobize the substrate before the supply of the coating liquid; An airflow forming mechanism is provided in the transfer region to form an airflow from the other of the front and rear sides toward the fourth processing module and an airflow from the first processing block and the other processing block toward the transfer region. [Effects of the Invention]

[0006] The present disclosure can increase the throughput of a substrate processing apparatus while reducing the floor space required. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a cross-sectional plan view of a coating and developing apparatus according to an embodiment of a substrate processing apparatus of the present disclosure. [Figure 2] FIG. 2 is a vertical sectional front view of the coating and developing apparatus. [Figure 3] FIG. 2 is a vertical sectional front view of the coating and developing apparatus. [Figure 4] FIG. 2 is a left side view of the coating and developing apparatus. [Figure 5] FIG. 2 is a vertical sectional side view of the coating and developing apparatus. [Figure 6] 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. [Figure 7] 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. [Figure 8] 5A to 5C are explanatory views showing the operation of a transport mechanism provided in the coating and developing apparatus. [Figure 9] FIG. 2 is a schematic view of a transport path in the coating and developing apparatus. [Figure 10] FIG. 2 is a schematic view of a transport path in the coating and developing apparatus. [Figure 11] 3 is a schematic view showing an air flow formed in the coating and developing apparatus. FIG. [Figure 12] FIG. 2 is a schematic diagram showing a wafer transport path in the substrate processing apparatus. DETAILED DESCRIPTION OF THE INVENTION

[0008] A coating and developing apparatus 1 according to one embodiment of a substrate processing apparatus of the present disclosure will be described with reference to the cross-sectional plan view of FIG. 1 and the longitudinal front views of FIG. 2 and FIG. 3. FIGS. 2 and 3 show cross sections at different positions of the apparatus. The coating and developing apparatus 1 includes a carrier block D1, a first processing block D2, a second processing block D3, and an interface block D4, which are arranged in this order in a horizontal linear fashion, with adjacent blocks connected to each other. These blocks (carrier block, first and second processing blocks, and interface block) D1 to D4 are each partitioned by a housing, and a transport area for wafers W, i.e., substrates, is formed inside each housing.

[0009] In the following explanation, the arrangement direction of these blocks D1 to D4 will be referred to as the left-right direction, with the carrier block D1 side being the left side and the interface block D4 being the right side. Furthermore, in terms of the front-to-rear direction of the device, when looking at the carrier block D1 from the left, the front will be referred to as the front and the back will be referred to as the rear. The interface block D4, which serves as a relay block, is connected to the exposure machine 20 from the right side.

[0010] Before describing each of the blocks D1 to D4 in detail, we will describe the general configuration of the coating and developing apparatus 1. A wafer W is transported to the coating and developing apparatus 1 while being stored in a carrier C called, for example, a FOUP (Front Opening Unify Pod). The coating and developing apparatus 1 forms a coating film by supplying various coating liquids, including resist, to the wafer W, and develops the resist film exposed by an exposure machine 20.

[0011] The first processing block (left processing block) D2 and the second processing block (right processing block) D3 are each partitioned vertically into two. The lower and upper sides of the partitioned first processing block D2 are referred to as the first lower processing block D21 and the first upper processing block D22, respectively. The lower and upper sides of the partitioned second processing block D3 are referred to as the second lower processing block D31 and the second upper processing block D32, respectively. Therefore, the first lower processing block D21 and the first upper processing block D22 are stacked on top of each other, and the second lower processing block D31 and the second upper processing block D32 are stacked on top of each other. The first lower processing block D21 and the first upper processing block D22 are adjacent to each other, and the second lower processing block D31 and the second upper processing block D32 are adjacent to each other.

[0012] Each of these processing blocks (D21, D22, D31, D32) includes the above-mentioned processing modules and a transfer mechanism (main transfer mechanism) capable of transferring wafers to and from the processing modules. Furthermore, the first upper processing block D22 and the second upper processing block D32 are each provided with a transfer mechanism separate from the transfer mechanism for transferring wafers to and from the processing modules. Hereinafter, this separate transfer mechanism will be referred to as a shuttle. This shuttle is a bypass transfer mechanism that transfers wafers W toward downstream blocks without passing through the processing modules, and the first upper processing block D22 and the second upper processing block D32 in which this shuttle is provided are bypass transfer path forming blocks.

[0013] The first lower processing block D21 and the second lower processing block D31 form an outbound route for transporting wafers W from the carrier block D1 to the interface block D4. The first upper processing block D22 and the second upper processing block D32 form a return route for transporting wafers W that have been exposed in the exposure machine 20 from the interface block D4 to the carrier block D1, and the same types of processing modules are provided in both blocks so that the same processing can be performed. On the return route, wafers W are transported to a processing module by a transfer mechanism in one of the first upper processing block D22 and the second upper processing block D32 and processed therein, and then transported by a shuttle in the other block.

[0014] The first lower processing block D21 and the second lower processing block D31 that make up the outbound path may be collectively referred to as the lower processing block G1, and the first upper processing block D22 and the second upper processing block D32 that make up the return path may be collectively referred to as the upper processing block G2. As described above, the lower processing block G1 and the upper processing block G2 are vertically stacked one on top of the other. By providing the shuttle as described above, the wafer W is transported in the upper processing block G2 via one of two transport paths. A module is a location other than the transport mechanism (including the shuttle) where the wafer W is placed, i.e., a wafer W placement section. A module that processes a wafer W is referred to as a processing module as described above, but this processing also includes acquiring images for inspection.

[0015] The carrier block D1 will be described below with reference to the side view of Figure 4. Carriers C are carried in and out of the carrier block D1 by a carrier transport mechanism (external transport mechanism) (not shown) provided in the clean room where the coating and developing apparatus 1 is installed. The carrier block D1 is a block that carries wafers W in and out of the carriers C and also transfers wafers W to and from the upper processing block G2 and the lower processing block G1.

[0016] The aforementioned housing constituting carrier block D1 is designated 11. Housing 11 is formed in a rectangular shape, and its lower side protrudes to the left to form support base 12. Furthermore, on the left side surface of housing 11 above support base 12, two points spaced apart from each other in the vertical direction protrude to the left to form support bases 13 and 14. The lower support base and the upper support base are designated 13 and 14, respectively.

[0017] Each of the support bases 12 to 14 can accommodate, for example, four carriers C at intervals in the front-to-rear direction, and each of the support bases 12 to 14 has a stage for placing the carriers C thereon, and the stages are arranged, for example, in a 3 x 4 matrix when viewed from the left. The left end of the support base 12 protrudes further left than the support bases 13 and 14, and the stage of the support base 12 is provided on the right side of the support base 12, below the support bases 13 and 14. The interior of the support base 12 is used as an area for storing bottles containing processing liquid for liquid processing in the first processing block D2 and the second processing block D3, as described above.

[0018] Carriers C can be transferred between the stages by a carrier transfer mechanism 21, which will be described later. Regarding these stages, the two front stages of each of the support bases 13 and 14 are configured as movable stages 15 on which carriers C are placed to load and unload wafers W into and from the apparatus. Therefore, a total of four movable stages 15 are arranged in a 2 × 2 matrix when viewed from the left. The movable stages 15 move between a load position on the right side for loading and unloading wafers W and an unload position on the left side for transferring carriers C to and from the carrier transfer mechanism 21. In this example, the movable stage 15 of the support base 12 is used as a stage on which carriers C are placed to load unprocessed wafers W into the apparatus, while the movable stage 15 of the support base 13 is used as a stage on which carriers C are placed to store processed wafers W in the apparatus.

[0019] Regarding the other stages, the two rear stages of the support bases 13 and 14 and the two stages of the support base 14 are configured as temporary placement stages 16. The other two stages of the support base 14 are configured as a carry-in stage 17 and an unloading stage 18. For example, the stage on the rear end side and the stage on the front end side of the support base 14 are the carry-in stage 17 and the unloading stage 18, respectively. These carry-in stage 17 and unloading stage 18 are stages on which the carriers C are placed so that the external transport mechanism described above can carry the carriers C into and out of the coating and developing apparatus 1, respectively.

[0020] The carrier C is transferred in the following order: carry-in stage 17 → movable stage 15 of support base 12 → movable stage 15 of support base 13 → carry-out stage 18. When transferring the carrier C between stages in this way, if the destination stage is not available (if it is occupied by another carrier C), the carrier C is placed on the temporary placement stage 16 and waits until the destination stage becomes available.

[0021] A carrier transfer mechanism 21 is provided above the left side of the support base 12. The carrier transfer mechanism 21 includes an articulated arm 22 that can hold a held portion provided on the upper part of the carrier C, and a movement mechanism 23 that can move the articulated arm 22 up and down and back and forth, and can transfer the carrier C between stages as described above.

[0022] Four transfer openings 24 for loading and unloading wafers W are formed in the left wall of the housing 11, and are arranged in a 2 × 2 matrix to match the arrangement of the movable stages 15. A door 25 is provided at each transfer opening 24. The door 25 is capable of holding the lid of the carrier C on the movable stage 15 at the load position, and can move while holding the lid to open and close the transfer opening 24.

[0023] The transfer opening 24 faces a transfer area 31 for wafers W formed within the housing 11. In plan view, the transfer area 31 is formed in a linear shape that is long from front to back, and is provided between the movable stage 15, which serves as a carrier placement unit, and the first processing block G2. A transfer mechanism 32 is provided on the front side (the other side) of the transfer area 31. The transfer mechanism 32 includes a base that is movable back and forth, vertically movable, and rotatable about a vertical axis, and a wafer W holder that can move forward and backward on the base. The transfer mechanism 32, which is the first transfer mechanism, can access the carrier C on the movable stage 15 at the load position described above, and the module stack T1 and pre-processing inspection module 41, which will be described later, to transfer the wafers W.

[0024] A pre-processing inspection module 41, which is a third processing module, is provided in the carrier block D1, and this pre-processing inspection module 41 images the surface of the wafer W before processing by the coating and developing apparatus 1. Image data obtained by this imaging is sent to the control unit 10, which will be described later, and the presence or absence of an abnormality in the wafer W is determined based on the image data by the control unit 10. The pre-processing inspection module 41 has a housing in the shape of a rectangular parallelepiped that is elongated from side to side, and the right side is located in the center of the front and rear of the transfer region 31, and the left side penetrates the left wall of the housing 11 and protrudes outside the housing 11.

[0025] The housing of the pre-processing inspection module 41 contains a stage 42 that can move left and right within the module, a half mirror 43 provided above the path of movement of the stage 42, an illumination unit 44 that irradiates light downward via the half mirror 43, and a camera 45 provided to the left of the half mirror 43 (see FIG. 3). A wafer W is delivered to the stage 42 located on the right side of the housing by the transport mechanism 32. As the stage 42 to which the wafer W has been delivered moves to the left side of the housing and passes below the half mirror 43, light is emitted from the illumination unit 44 and an image of the wafer W reflected on the half mirror 43 is captured by the camera 45, thereby acquiring the image data.

[0026] 1, a second transfer mechanism, that is, a transfer mechanism 33, is provided in the transfer region 31 so as to be located, in a plan view, behind the pre-processing inspection module 41. The transfer mechanism 33 includes a base that can be raised and lowered and rotated about a vertical axis, and a wafer W holder that can move forward and backward on the base, and can deliver the wafer W to and from a shuttle TRS12 of the module stack T1 and the first upper processing block D22, which will be described later.

[0027] Next, the module stack T1 will be described. This module stack T1 is configured by vertically stacking transfer modules TRS, on which wafers W are temporarily placed, and temperature adjustment modules SCPL, and is provided in the front-to-rear center of the transfer region 31. Therefore, in a plan view, the module stack T1 is located behind the transfer mechanism 32, sandwiched between the transfer mechanisms 32 and 33, and overlaps the right side of the pre-processing inspection module 41. Therefore, in a plan view, the pre-processing inspection module 41 is configured to extend leftward from a position overlapping the stack T1. Furthermore, with regard to the stages for the carrier C described above, the two vertical rows of stages on the front side, including the moving stage 15, are located forward of the module stack T1. Of the two vertical rows of stages on the rear side, one row is located to the left of the module stack T1, and the other row is located rearward of the module stack T1.

[0028] The transfer module TRS has, for example, multiple pins arranged horizontally, and the wafer W is transferred to and from these pins by the lifting and lowering operation of the transfer mechanism. The SCPL has, for example, a configuration in which a refrigerant flow path is connected to a plate on which the wafer W is placed, thereby cooling the temporarily placed wafer W, and the wafer W is transferred to and from the plate by the lifting and lowering operation of the transfer mechanism. SCPLs are also provided in blocks other than the carrier block D1, and the SCPLs in blocks other than D1 have the same configuration as, for example, the SCPL in carrier block D1. TRSs are also provided in blocks other than D1. These TRSs have the same configuration as the TRS in carrier block D1, except for the TRS for a shuttle that transfers wafer W to and from the shuttle, which will be described later.

[0029] Hereinafter, in order to distinguish the SCPL and TRS at each location, which are temporary placement modules, numbers are added after the SCPL and TRS. For example, multiple TRS and SCPL are stacked at each location. That is, multiple TRS and SCPLs with the same number are provided, but for convenience of illustration, only one is shown. Note that in this specification, a stack of modules refers to modules that are stacked in a plan view, and the modules may be separated from each other or may be in contact with each other.

[0030] Some of the modules constituting the module stack T1 are located below the pre-processing inspection module 41, and others are located above the pre-processing inspection module 41. For example, from bottom to top, the modules are arranged in the order TRS1, TRS2, SCPL1, TRS3, and SCPL2, with the pre-processing inspection module 41 located between SCPL1 and TRS3 (see FIG. 3). For example, TRS1, TRS2, and SCPL1 are located at the height of the first lower processing block D21, and TRS3 and SCPL2 are located at the height of the first upper processing block D22. The transfer mechanism 33 can access each module constituting the module stack T1, and the transfer mechanism 32 can access TRS1 and TRS2. Regarding the transfer of wafers W to and from carriers C and between modules in the module stack T1, the transfer mechanism 32 is dedicated to transfers to and from carriers C, and the transfer mechanism 33 is dedicated to transfers between modules in the module stack T1.

[0031] TRS1 and TRS2 are used to transfer wafers W between the transfer mechanisms 32 and 33, and both serve as first receivers used to transfer wafers W to and from carriers C. SCPL1 is used to transfer wafers W between the first lower processing block D21 and the carrier block D1. Therefore, the second receiver, SCPL1, is also accessible by a transfer mechanism 6A of the first lower processing block D21, which will be described later. Furthermore, TRS3 is a third receiver, TRS3, is used to transfer wafers W between the first upper processing block D22 and the carrier block D1. Therefore, the transfer mechanism 6B of the first upper processing block D22, which will be described later, is also accessible to TRS3. SCPL2 is a module used to adjust the temperature of wafers W before they undergo development processing in the first upper processing block D22, and is accessed by the transfer mechanism 6B.

[0032] A hydrophobization treatment module 30, which is a fourth treatment module that supplies a treatment gas to the wafer W to perform a hydrophobization treatment before a coating film is formed, is provided on the rear side (either the front or rear) of the transfer mechanism 33. For example, a plurality of hydrophobization treatment modules 30 are stacked at the height of the second upper treatment block D22, and the transfer mechanism 33 transfers the wafer W to and from the hydrophobization treatment module 30. The hydrophobization treatment module 30 includes a hot plate on which the wafer W is placed, similar to the hot plate 55 provided in the heating module 54 described below, and a cover that can be raised and lowered to cover the hot plate. A treatment gas is supplied into an enclosed space formed above the hot plate by the cover, thereby performing a hydrophobization treatment on the wafer W.

[0033] Next, the first processing block D2 will be described with reference to the longitudinal side view of Figure 5. The front side of the first processing block D2 is vertically partitioned to form eight levels, which are numbered E1 to E8 from bottom to top. The lower levels E1 to E4 are included in the first lower processing block D21, and the upper levels E5 to E8 are included in the first upper processing block D22. Each level forms an area where a liquid processing module can be installed.

[0034] First, the first upper processing block D22 will be described. Each of the stories E5 to E8 is provided with a developing module 51 as a liquid processing module. The developing module 51 includes two cups 52 arranged side by side and each containing a wafer W, and a nozzle (not shown). The developing module 51 supplies the developing liquid from the bottle to the surface of the wafer W by a pump (not shown), thereby processing the wafer W.

[0035] A transfer region 53 for wafers W is provided behind stories E5 to E8 and extends linearly in a plan view from the left end to the right end of the upper processing block D22. Therefore, the extension direction of the transfer region 53 is perpendicular to the extension direction of the transfer region 31 of the carrier block D1. The transfer region 53 extends from the height of story E5 to the height of story E8. In other words, the transfer region 53 is not divided into stories E5 to E8.

[0036] The processing modules are stacked, for example, in seven stages in the vertical direction behind the transport area 53, with two stacks of processing modules arranged side by side. That is, the stacks of processing modules and the cups 52 are each arranged along the extension direction of the transport area 53.

[0037] The stack of processing modules arranged side by side as described above is referred to as the rear processing unit 50. The processing modules constituting this rear processing unit 50 include multiple heating modules 54 and multiple post-processing inspection modules 57. The heating module 54 is a module that performs post-exposure bake (PEB) and includes a hot plate 55 on which a wafer W is placed and heated, and a cooling plate 56 that adjusts the temperature of the wafer W. The cooling plate 56 is movable between a front position where the wafer W is transferred by the lifting and lowering operation of a transfer mechanism 6B (described later) and a rear position where it overlaps with the hot plate 55. The lifting and lowering operation of pins (not shown) provided on the hot plate 55 cooperates with the movement of the cooling plate 56 to transfer the wafer W between the hot plate 55 and the cooling plate 56.

[0038] The post-processing inspection module 57 has the same configuration as the pre-processing inspection module 41, and is arranged so that the movement direction of the wafer W during imaging is the front-to-rear direction. The post-processing inspection module 57 acquires image data of the surface of the wafer W that has been processed by the coating and developing apparatus 1, more specifically, the surface of the wafer W on which a resist pattern has been formed by development, and transmits the image data to the control unit 10.

[0039] The transfer area 53, which is the main transfer path, is provided with the transfer mechanism 6B, which is the main transfer mechanism described above, and the transfer mechanism 6B includes a base 61 that is movable left and right, vertically movable, and rotatable about a vertical axis, and a holder 62 for the wafer W that can move forward and backward on the base 61. Note that each of the transfer mechanisms other than the shuttle in the coating and developing apparatus 1, including this transfer mechanism 6B, is provided with two holders, which can move forward and backward independently of each other on the base.

[0040] A moving mechanism 63 for moving the base 61 of the transfer mechanism 6B laterally is provided below the rear processing unit 50, and a flat space 71A is formed between the moving mechanism 63 and the rear processing unit 50 (see FIG. 5). The space 71A extends from the left end to the right end of the first upper processing block D22. A shuttle and the TRS12 and TRS14 for the shuttle are installed in the space 71A, which will be described in detail later. The transfer mechanism 6B can transfer wafers W to and from each processing module in the first upper processing block D22, the TRS3 and SCPL2 of the carrier block D1, and the TRS14 for the shuttle. In other words, the transfer mechanism 6B is shared by each liquid processing module provided on multiple stacked levels and each processing module constituting the rear processing unit 50.

[0041] Next, the first lower processing block D21 will be described. The first lower processing block D21 has a configuration generally similar to the first upper processing block D22 already described, and the following description will focus on the differences from the first upper processing block D22. No processing modules are provided on level E1, and anti-reflective coating formation modules 47 are provided on levels E2 to E4 as liquid processing modules. The anti-reflective coating formation module 47, which is the first processing module and also a coating film formation module, has a configuration similar to the developing module 51, which is the second processing module, except that it supplies a coating liquid for forming an anti-reflective coating from a nozzle instead of a developing liquid.

[0042] The rear processing section 50 is composed of heating modules 54. However, unlike the heating modules 54 in the first upper processing block D22, the heating modules 54 in the first lower processing block D21 and the second lower processing block D32 (described later) are designed to remove solvent from the coating film. The main transport mechanism in the transfer region 53 is shown as transfer mechanism 6A and has the same configuration as the previously described transfer mechanism 6B. The transfer mechanism 6A delivers wafers W to and from each processing module in the first lower processing block D21, the SCPL1 in the module stack T1, and the module stack T2 (described later). The first lower processing block D21 does not have a shuttle or a TRS for the shuttle.

[0043] The first processing block D2 is provided with a module stack T2 (see FIGS. 1 and 3). This module stack T2 is located to the right of the transfer region 53 of the first lower processing block D21 and to the right of the transfer region of the second upper processing block D22, and is composed of SCPLs. The SCPL in the first lower processing block D21 is designated SCPL3, and the SCPL in the first upper processing block D22 is designated SCPL4. The module stack T2 is located so that its right end slightly extends into the second processing block D3. SCPL3 is used to adjust the temperature of wafers W before processing in a resist film formation module in the second lower processing block D22 (described below), and SCPL4 is used to adjust the temperature of wafers W before processing in a developing module 51 in the second upper processing block D22 (described below).

[0044] Regarding the layout of the modules in the first upper processing block D22 and the first lower processing block D21, the rear-side processing section 50 and the cups 52 of the liquid processing modules are located to the left of the module stack T2 to enable transfer by the transport mechanisms 6A and 6B. The layout of the liquid processing modules and rear-side processing section 50 is common to the first and second lower processing blocks D21 and D31 and the first and second upper processing blocks D22 and D32. Therefore, in the second lower processing block D31 and second upper processing block D32 described below, the rear-side processing section 50 and the cups 52 of the liquid processing modules are also located away from the right end of the block.

[0045] Next, we will explain the second processing block D3. The second processing block D3 has a configuration similar to that of the first processing block D2, except that it does not have the module stack T2. The following explanation focuses on the differences between the first processing block D2 and the second processing block D3. First, we will explain the second upper processing block D32. The main transfer mechanism in the second upper processing block D32 is designated 6D. A space 71B similar to the space 71A in the first upper processing block D22 is formed between the transfer mechanism 63 that moves the transfer mechanism 6D and the rear processing unit 50. The space 71B is located at the same height as the space 71A and is connected to the space 71A. A shuttle and shuttle TRS11 and TRS13 are installed in the space 71B, which will be described later. The transfer mechanism 6D transfers wafers W to and from each processing module in the upper processing block D22, the module stack T3 in the interface block D4 (described later), and the shuttle TRS11.

[0046] Next, the second lower processing block D31 will be described. Resist film forming modules 49 are provided on stories E2 to E4. The resist film forming modules 49 have the same configuration as the developing modules 51, except that the processing liquid supplied to the wafers W is resist instead of a developer. The rear processing unit 50 has the same configuration as the rear processing unit 50 of the first lower processing block D21. The main transport mechanism in the second lower processing block D31 is a transport mechanism 6C. The transport mechanism 6C delivers wafers W to and from each processing module in the lower processing block D21 and the module stack T3 in the interface block D4.

[0047] The following describes the interface block D4. The interface block D4 has a module stack T3 in the center between the front and rear. This module stack T3 is composed of stacked modules TRS5 to TRS7 and a temperature adjustment module ICPL. In addition to these modules, a buffer module for temporarily waiting a wafer W may also be provided, but this will not be described here. The ICPL is a module to which the wafer W is transferred immediately before exposure. It is provided at the bottom of the module stack T3 and adjusts the temperature of the placed wafer W in the same way as the SCPL. TRS5 and TRS6 are provided at the height of the lower processing block G1, and TRS7 is provided at the height of the upper processing block G2. Transfer mechanisms 36, 37, and 38 are provided at the front, rear, and right of the module stack T3, respectively.

[0048] The transfer mechanisms 36 and 37 are configured similarly to the transfer mechanism 33, and are capable of transferring wafers W between the modules constituting the module stack T3. The transfer mechanism 36 is also capable of transferring wafers W to a back surface cleaning module 65, which will be described later, and the transfer mechanism 37 is also capable of transferring wafers W to a shuttle TRS 13 and a post-exposure cleaning module 66, which will be described later. The transfer mechanism 38 is configured similarly to the transfer mechanism 32, and transfers wafers W between the ICPL, TRS 6, and exposure machine 20.

[0049] Further, a plurality of back surface cleaning modules 65 are stacked and provided in front of the transfer mechanism 36. The back surface cleaning module 65 has a configuration similar to that of the developing module 51, except that instead of being provided with a nozzle for supplying a developing solution to the front surface of the wafer W, a nozzle for supplying a cleaning solution to the back surface of the wafer W is provided, and that the back surface cleaning module 65 has one cup 52. A plurality of post-exposure cleaning modules 66 are stacked and provided behind the transfer mechanism 37. The post-exposure cleaning module 66 has a configuration similar to that of the developing module 51, except that instead of being provided with a developing solution to the front surface of the wafer W, a cleaning solution is provided to the front surface of the wafer W, and that the back surface cleaning module 65 has one cup 52.

[0050] Next, the shuttles provided in the first upper processing block D22 and the second upper processing block D32 will be described as 7A and 7B, respectively. The shuttle 7A includes a moving mechanism 72A, a moving body 73A, and a support 74A. The moving mechanism 72A is configured as an elongated member extending laterally and is provided to fit within the space 71A of the first upper processing block D22 described above. The moving body 73A is connected to the front side of the moving mechanism 72A and extends laterally. The support 74A is connected to the front side of the moving body 73A and is formed in the shape of a rectangular parallelepiped that is elongated laterally. The wafer W is supported on the support 74A and transported horizontally and linearly in the left-right direction.

[0051] The moving mechanism 72A allows the moving body 73A to move left and right relative to the moving mechanism 72A. The support 74A moves left and right relative to the moving body 73A in response to the movement of the moving body 73A relative to the moving mechanism 72A (see FIGS. 6 to 8). The moving body 73A moves between a right position where its right end is located to the right of the right end of the moving mechanism 72A (toward the interface block D4) and a left position where its left end is located to the left of the left end of the moving mechanism 72A (toward the carrier block D1). When the moving body 73A is located in the right position, the right end of the support 74A is located to the right of the right end of the moving body 73A (the state shown in FIG. 6). The position of the support 74A in this state is referred to as the right transfer position. When the moving body 73A is located in the left position, the left end of the support 74A is located to the left of the left end of the moving body 73A (the state shown in FIG. 8). The position of the support 74A in this state is referred to as the left transfer position.

[0052] The shuttle 7A transports a wafer W from a TRS 11 provided in the second upper processing block D32 to a TRS 12 (fourth receiving portion) provided in the first upper processing block D22. The TRS 11 includes a support plate 75 serving as a receiving portion main body formed to form a recess with an open left side in a plan view, three pins 76 protruding upward from the support plate 75, and an elevator mechanism (not shown) for raising and lowering the support plate 75. The TRS 11 is located, for example, at the left end of the second upper processing block D32. The elevator mechanism may be an actuator such as a cylinder or a motor, and is connected to the back side (lower side) of each support plate 75 and positioned so as not to interfere with the movement trajectories of the movable bodies 73A and the supports 74A. As the support plate 75 rises and falls, the pins 76 move between an elevated position and a lowered position to support the underside of the wafer W. In plan view, the right end of support 74A at the right transfer position is contained in the recess formed by support plate 75, and wafer W can be transferred between support 74A and TRS11 by raising and lowering pins 76.

[0053] The TRS12 has the same configuration as the TRS11, except that the support plate 75 is formed to form a recess that is open on the right side in a plan view. The left end of the support 74A in the left transfer position is fitted into the recess formed by the support plate 75 in a plan view, allowing the transfer of wafers W between the support 74A and the TRS12. The TRS12 is provided at the left end of the first upper processing block D22 so that the wafers W can be transferred between the support 74A and the transfer mechanism 33 of the carrier block D1. As described above, the transfer of a substrate (wafer W) supported by the support 74 is performed by changing the relative left-right positions of multiple components, such as the movable body 73A and the support 74A, that are provided in the front-rear direction. By transferring the substrate in this manner, the TRS11 and TRS12, which are positioned to the left and right of the support 74A, are less likely to interfere with the movable body 73A, making it possible to arrange the pins 76 in three or more positions that can easily support the substrate.

[0054] Shuttle 7B, which is the second bypass transport mechanism, is located at a different height from shuttle 7A, for example, lower than shuttle 7A. Shuttle 7B is configured similarly to shuttle 7A, and the reference numerals for the components of shuttle 7B, such as the moving mechanism, moving body, and support, are denoted by adding a B instead of an A after the numeral to distinguish them from the components of shuttle 7A. Specifically, for example, the moving mechanism of shuttle 7B is denoted as 72B. This moving mechanism 72B is provided to fit within space 71B of the second upper processing block D32.

[0055] Shuttle 7B transports wafers W from TRS13 in second upper processing block D32 to TRS14 in first upper processing block D22. TRS13 has a similar configuration to TRS11 and is located at the right end of second upper processing block D32 so that wafers W can be transferred to and from interface block D4. TRS14 has a similar configuration to TRS12 and is located to the left of module stack T2 and to the right of TRS12 so that wafers W can be transferred to and from transfer mechanism 6B.

[0056] As described above, shuttle 7B is provided below shuttle 7A, and therefore the height at which the second bypass substrate mounting portions TRS13 and TRS14 are located is lower than the height at which the first bypass substrate mounting portions TRS11 and TRS12 are located. In other words, as shown in Fig. 2, the set of shuttle 7A, TRS11, and TRS12 and the set of shuttle 7B, TRS13, and TRS14 are provided at positions offset from each other in the longitudinal direction (vertical direction).

[0057] The transfer path (first bypass transfer path) for wafer W by shuttle 7A and the transfer path (second bypass transfer path) for wafer W by shuttle 7B are designated 77A and 77B, respectively. The transfer paths 77A and 77B are located at the same front-to-rear positions. In correspondence with the positions of TRS11 to TRS14, the transfer path 77A projects toward the second upper processing block D22, and the transfer path 77B projects toward the first upper processing block D22. This protrusion allows the right side of the transfer path 77A and the left side of the transfer path 77B to overlap in a plan view. The transfer paths 77A and 77B may be located, for example, away from the heating plate 55 of the heating module 54 and overlap the standby position of the cooling plate 56 in a plan view. By positioning the transfer paths relatively far from the heating plate 55, the effects of heat on the transferred wafer W can be more reliably reduced.

[0058] The transfer of the wafer W by the shuttle 7A will be described in sequence with reference to FIGS. 6 to 8. The transfer mechanism 6D in the second upper processing block D32 transfers the wafer W, which has been processed in each processing module in the second upper processing block D32, onto the pins 76 in the raised position of the TRS 11. The pins 76 move to their lowered positions, and the wafer W is transferred to the support 74A in the right transfer position described above (FIG. 6). While the movable body 73A and the support 74A each move to the left, the pins 76 of the TRS 11 return to their raised positions (FIG. 7).

[0059] When support 74A moves to the left transfer position described above, pins 76 of TRS12, which were in the lowered position, move to the raised position to support wafer W (FIG. 8). When support 74A moves toward the right transfer position, pins 76 return to the lowered position. Subsequently, transfer mechanism 33 of carrier block D1 receives wafer W. In this manner, shuttle 7A transfers wafer W toward carrier block D1, which is a downstream block. Shuttles 7B, TRS13, and TRS14 operate in the same manner as shuttles 7A, TRS11, and TRS12, respectively, and wafer W is transferred from TRS13 to TRS14. In other words, shuttle 7B transfers wafer W toward first upper processing block D22, which is a downstream block.

[0060] The coating and developing apparatus 1 also includes a control unit 10 (see FIG. 1). The control unit 10 is configured with a computer and includes a program, a memory, and a CPU. The program incorporates a group of steps that enable a series of operations in the coating and developing apparatus 1 to be performed. The program causes the control unit 10 to output control signals to each part of the coating and developing apparatus 1, thereby controlling the operation of each part. Specifically, the control unit 10 controls the operations of the transfer mechanisms 6A-6D, shuttles 7A and 7B, and each processing module. This allows the transfer of wafers W, the processing of wafers W, and the determination of abnormalities in wafers W, as described below. The above program is stored on a storage medium such as a compact disc, hard disk, or DVD, and is installed in the control unit 10.

[0061] Next, the processing and transport path of the wafer W in the coating and developing apparatus 1 will be described with reference to Figures 9 and 10, which respectively show the outward and return paths mentioned above. In Figures 9 and 10, the transport mechanisms used for transporting the wafer W between modules are shown on or near some of the arrows indicating the transport of the wafer W between modules.

[0062] First, the wafer W is carried out by the transfer mechanism 32 from the carrier C placed on the moving stage 15 of the support table 12. Then, the wafer W is carried by the transfer mechanism 32 to the pre-processing inspection module 41, where image data is acquired and the presence or absence of an abnormality is determined.

[0063] The wafer W is then transferred to TRS1 by transfer mechanism 32. After that, the wafer W is transferred by transfer mechanism 33 to hydrophobization treatment module 30 and then to SCPL1, and then loaded into first lower processing block D21 by transfer mechanism 6A, and transferred in the order of anti-reflection film forming module 47 and heating module 54, where an anti-reflection film is formed. The wafer W is then transferred to SCPL4 of module stack T2, and transferred by transfer mechanism 6C in the order of resist film forming module 49 and then to heating module 54, where a resist film is formed. The wafer W is then transferred to TRS5 of module stack T3.

[0064] Thereafter, the wafer W is transported by the front transfer mechanism 36 through the back surface cleaning module 65 and ICPL, and then by the transfer mechanism 38 to the exposure machine 20, where the resist film on the front surface of the wafer W is exposed according to a predetermined pattern. After exposure, the wafer W is transported by the transfer mechanism 38 to the TRS 6, and then transported by the rear transfer mechanism 37 to the post-exposure cleaning module 66.

[0065] The subsequent transfer path of the wafer W is divided into a path (referred to as the first path) in which the wafer W is processed in the first upper processing block D22, and a path (referred to as the second path) in which the wafer W is processed in the second upper processing block D32, as described above. Regarding the second path, the transfer mechanism 37 transfers the wafer W to the TRS7 of the module stack T3, and the transfer mechanism 6D takes the wafer W into the second upper processing block D32. The wafer W is then transferred in the order of the heating module 54, SCPL3, developing module 51, and post-processing inspection module 57. After a resist pattern is formed, image data is acquired and the presence or absence of anomalies is determined.

[0066] 6 to 8, the wafer W is then transferred in the order of transfer mechanism 6D → TRS11 → shuttle 7A → TRS12, and then transfer mechanism 33 of carrier block D1 receives the wafer W and transfers it to TRS2. In this manner, the wafer W is transferred toward the downstream block by transfer mechanism 6D, one of transfer mechanisms 6B and 6D that are the main transfer mechanisms of first upper processing block D22 and second upper processing block D22, which are bypass transfer path forming blocks, and shuttle 7A. The wafer W is then stored in carrier C on moving stage 15 of support table 13 by transfer mechanism 32.

[0067] Regarding the first path, the wafer W is transferred in the order of transfer mechanism 37 → TRS13 → shuttle 7B → TRS14 → transfer mechanism 6B, and then loaded into the first upper processing block D22. The wafer W is then transferred by transfer mechanism 6B in the order of heating module 54 → SCPL2 → developing module 51 → post-processing inspection module 57, and after undergoing processing similar to that of the wafer W on the second path, is transferred to TRS3 in carrier block D1. In this manner, the wafer W is transferred toward downstream blocks by transfer mechanisms 6B and 6D, which are the main transfer mechanisms of the first and second upper processing blocks D22 and D22, which are bypass transfer path forming blocks, and shuttle 7B. The wafer W is then transferred to TRS2 by transfer mechanism 33, and then transferred to carrier C on moving stage 15 of support table 13 by transfer mechanism 32, similar to the wafer W on the second path.

[0068] As described above, the carrier block D1 in the coating and developing apparatus 1 is provided with a module stack T1 including TRSs and SCPLs for transferring wafers W to and from the carrier C, the lower processing block (first processing block) G1, and the upper processing block (second processing block) G2. The coating and developing apparatus 1 is also provided with transfer mechanisms 32 and 33, with the transfer mechanism 32 responsible for transferring wafers W to and from the carrier C and the transfer mechanism 33 responsible for transferring wafers W between modules in the module stack T1. By dividing the roles of the transfer mechanism 32 and the transfer mechanism 33, the transfer mechanism 32 can quickly transfer wafers W into and out of the carrier C. Meanwhile, processing modules are stacked in the processing blocks D21, D22, D31, and D32 that make up the lower processing block G1 and the upper processing block G2, to which wafers W are transferred via the transfer mechanism 33, and wafers W can be processed in each processing module. Therefore, the coating and developing apparatus 1 can achieve high throughput. Furthermore, the transfer area 31 facing the transfer port 24 through which the wafer W is delivered to the carrier C extends in the front-to-rear direction, and the transfer mechanisms 32 and 33 are provided in the front and rear of the module stack T1 in this transfer area 31, respectively, so that the left-to-right width of the carrier block D1 can be made relatively small. Therefore, the coating and developing apparatus 1 can reduce its footprint (occupied floor area).

[0069] A pre-processing inspection module 41 is provided on the carrier block D1. The right end of this pre-processing inspection module 41 overlaps the module stack T1 and penetrates the side wall of the housing 11, so that the left end thereof protrudes from the transport area 31. In other words, the pre-processing inspection module 41 is arranged by utilizing the space formed in the center of the front and rear of the transport area 31 by arranging the module stack T1 and the space outside the housing 11 where the carrier C is transferred. In other words, the pre-processing inspection module 41 is installed in the carrier block D1, while preventing an increase in the footprint of the carrier block D1.

[0070] Furthermore, a hydrophobic treatment module 30 is disposed as a treatment module behind the transfer mechanism 33 and is accessible by the transfer mechanism 33. This arrangement of the hydrophobic treatment module 30 also prevents the left and right width of the coating and developing apparatus 1 from increasing. The transfer mechanism 33 delivers and receives wafers W to the hydrophobic treatment module 30, and the transfer mechanism 32 delivers and receives wafers W to the pre-treatment inspection module 41. This prevents uneven load distribution between the transfer mechanisms 32 and 33, and prevents a decrease in throughput due to the provision of these treatment modules. However, the transfer mechanism 33 may be configured to deliver wafers W to the pre-treatment inspection module 41.

[0071] Furthermore, when providing multiple movable stages 15 on which carriers C are placed for loading and unloading wafers W, they are provided in multiple tiers on the front side of the module stack T1. By arranging the movable stages 15 so that they are concentrated on the front side of the module stack T1 in this manner, it is possible to install the necessary number of movable stages 15 to ensure sufficient throughput, while also allowing the central portion of the transfer region 31 from front to back to be used as an installation area for the module stack T1 and pre-processing inspection module 41. Furthermore, by arranging the module stack T1 in this manner, it is possible to arrange the transfer mechanism 33 behind it. Therefore, as described above, providing each movable stage 15 on the front side of the module stack T1 and at different heights from each other contributes to increasing throughput while reducing the footprint of the apparatus.

[0072] Incidentally, by providing the temporary placement stage 16, which is a temporary placement section for carriers, unnecessary carriers C can be retracted from the movable stage 15, thereby enabling efficient loading and unloading of wafers W into and from the carriers C. In the carrier block D1, the temporary placement stage 16 is provided at the same position as the module stack T1 in the front-to-rear direction and at a position rearward of the module stack T1. In other words, by providing the movable stage 15 in the layout described above, the temporary placement stage 16 is provided in an empty space that is not accessed by the transfer mechanism 32. In other words, the temporary placement stage 16 is arranged in a layout that prevents the carrier block D1 from becoming larger.

[0073] Furthermore, the coating and developing apparatus 1 is provided with shuttles 7A and 7B, which transport wafers W toward the carrier block D1. As a result, a wafer W to be processed in one of the first upper processing block D22 and the second upper processing block D32 is transported toward the carrier block D1 so as to bypass the processing modules in the other block. This reduces the load on the transfer mechanism 6B of the first upper processing block D22 and the transfer mechanism 6D of the second upper processing block D32 (more specifically, the number of transfer processes required within the block). As a result, the throughput of the coating and developing apparatus 1 can be further improved.

[0074] Incidentally, air flow generating units (not shown) are provided above the housing 11 of the carrier block D1, above the housings of the first and second processing blocks D2 and D3, and above the housing of the interface block D4. Each air flow generating unit takes in air from outside the coating and developing apparatus 1 and supplies it to the wafer W transport path in the block in which the air flow generating unit is provided, thereby forming an air flow. In Figure 11, the air flow generating units of the carrier block D1 and the second processing block D22 are indicated as 81 and 82, respectively. For ease of illustration, these air flow generating units 81 and 82 are shown at positions distant from the carrier block D1 and the first processing block D2, respectively.

[0075] The airflow forming unit 82 supplies air via a duct (not shown) to filters provided in the ceiling of each transport area 53 of the first lower processing block D21 and the first upper processing block D22 that make up the first processing block D2. The air supplied from the filters flows downward through the transport area 53 and is exhausted from exhaust ports (not shown) provided on the lower side of the first lower processing block D21 and the first upper processing block D22 (not shown).

[0076] 11, for example, in the carrier block D1, a vertically long filter 83 is provided at the end on the front side of the transport region 31. Air supplied from the airflow creating unit 81 to the filter 83 is supplied from the filter 83 toward the rear of the transport region 31. An exhaust hole 84 is opened, for example, at the bottom of the block behind the module stack T1, and the air supplied from the filter 83 is exhausted from the exhaust hole 84.

[0077] By adjusting the balance between the air supply and exhaust rates in each block, the first lower processing block D21 and the first upper processing block D22 are set to a state in which the pressure is higher than that of the transfer region 31. As a result, a portion of the air supplied to the transfer region 53 as described above flows into the transfer region 31 and is exhausted through the exhaust hole 84. In FIG. 11, the airflows formed in the transfer regions 31 and 53 are indicated by arrows. The airflows formed in this manner more reliably prevent the processing gas used in the hydrophobization processing module 30 from flowing into the transfer region 31. If the processing gas were to flow into the development module 51 via the transfer region 31 and react with the developer, this could cause development defects. However, the formation of the airflows described above prevents such defects from occurring. In other words, the formation of the airflows prevents a decrease in the yield of products manufactured from wafers W. The filter 83 and the airflow generating units 81 and 82 form an airflow generating mechanism.

[0078] Incidentally, a post-processing inspection module 57 may be provided in place of the pre-processing inspection module 41 described above. In this case, the outbound route described in FIG. 9 may be a route that does not involve transport to the inspection module. Specifically, the wafer W may be transported in the order of carrier C → transfer mechanism 32 → TRS1 → transfer mechanism 33 → SCPL1 and then loaded into the first lower processing block D21. The return route described in FIG. 10 may be a route that passes through the post-processing inspection module 57 provided in the carrier block D1 in this manner. Specifically, the wafer W that has been processed and transferred to TRS2 of the carrier block D1 may be transported by the transfer mechanism 32 to the post-processing inspection module 57 and then returned to the carrier C.

[0079] When the post-processing inspection module 57 is arranged in the carrier block D1 in this manner, the pre-processing inspection module 41 may be provided as, for example, a processing module constituting the rear-side processing section 50 of the first lower processing block D21. Note that the carrier block D1 may be configured without either the pre-processing inspection module 41 or the post-processing inspection module 57, and in this case, the wafers W may be transferred between the transfer mechanisms 32 and 33 by using the modules of the module stack T1 as needed.

[0080] In the above transfer example, the moving stage 15 (loader) on which the carrier C is placed to unload the wafer W is different from the moving stage 15 (unloader) on which the carrier C is placed to load the wafer W. However, one moving stage 15 may serve as both a loader and an unloader. The above transfer mechanism 32 is configured to be shared by four moving stages 15, which has the advantage of making it easy to switch the use of the moving stages 15 in this way.

[0081] In the coating and developing apparatus 1, the upper processing block G2 may serve as the outbound route for wafers W, and the lower processing block G1 may serve as the return route for wafers W. Specifically, for example, without forming an anti-reflective coating within the apparatus, resist film forming modules 49 may be installed as liquid processing modules in the first upper processing block D22 and the second upper processing block D32. Furthermore, developing modules 51 may be installed as liquid processing modules in the first lower processing block D21 and the second lower processing block D31. Wafers W may be transported between blocks along a transfer path reverse to the previously described transfer path, whereby resist film formation, exposure, and development are performed in that order to form a resist pattern. Therefore, the shuttle is not limited to forming a return path, and the carrier block D1 is not limited to being configured to transfer wafers W to the shuttle TRS on the return path. Shuttles may also be installed in the first lower processing block D21 and the second lower processing block D31. For example, the liquid processing modules of the first lower processing block D21 and the second lower processing block D31 can both be resist film forming modules 49, and the apparatus can be configured so that a wafer W is processed in the resist film forming module 49 of either block using a shuttle.

[0082] Furthermore, the liquid processing performed by the apparatus is not limited to the above examples, and may include forming an insulating film by applying a chemical liquid, forming a protective film to protect the surface of a resist film by applying a chemical liquid, and applying an adhesive to bond wafers W together. Also, a cleaning process may be performed in which a cleaning liquid is supplied to the front or back surface of the wafer W. Therefore, the substrate processing apparatus of the present technology is not limited to a coating and developing apparatus.

[0083] Furthermore, the lower processing block G1 and the upper processing block G2 do not have to be connected to each other by the interface block D4. A description will be given with reference to the schematic diagram of the substrate processing apparatus 8 in Figure 12. Assume that module stack T1 includes TRS21 to TRS23. TRS21 is used for delivery to and from carrier C, and wafers W are transported between carrier C and TRS21 by transfer mechanism 32. TRS22 and TRS23 are used for delivery to and from the lower processing block G1 and upper processing block G2, and wafers W are transported between TRS21 and TRS22 and between TRS21 and TRS23 by transfer mechanism 33, respectively. Wafers W are loaded from carrier C via TRS21 to TRS22, and from TRS23 to the lower processing block G1 and upper processing block G2, respectively, and are returned to carrier C via TRS22, TRS23, and TRS21 after processing. In other words, the apparatus may be configured so that the wafer W is processed in only one of the lower processing block G1 and the upper processing block G2 and then returned to the carrier C.

[0084] Furthermore, each of the lower processing block G1 and the upper processing block G2 is not limited to being composed of two processing blocks arranged side by side, but may be composed of a single processing block.Furthermore, each of the lower processing block G1 and the upper processing block G2 may be composed of three or more processing blocks arranged side by side, and wafers W may be transferred between the side by side processing blocks.

[0085] In each processing block, the liquid processing module is located at the front and the processing module constituting rear processing section 50 is located at the rear, but this layout may be reversed. Also, in carrier block D1, the layout of transport mechanisms 32, 33 and each stage for carrier C may be reversed. Also, the arrangement of carrier block D1 and other blocks may be reversed left to right.

[0086] In addition, instead of the hydrophobic treatment module 30, other modules such as a post-treatment inspection module 57 may be provided in the carrier block D1, and transported by the transfer mechanism 33. However, the hydrophobic treatment module 30 does not need to move the mounting portion (hot plate) on which the wafer W is placed laterally when performing treatment. In other words, when providing a treatment module behind the transfer mechanism 33, providing a treatment module that performs treatment without moving the mounting portion for the wafer W laterally is preferable in order to prevent an increase in the size of the carrier block D1 and, ultimately, the size of the substrate processing apparatus. Note that the order of the TRS and SCPL that make up the module stack T1 may be changed in height or stacked in a different order as long as the wafer W can be transported within the apparatus.

[0087] The hydrophobic treatment module 30 may be arranged so as to overlap the TRS and SCPL that make up the module stack T1. However, by arranging multiple TRS and SCPL in the module stack T1 and loading wafers W on them, the transfer of wafers W between the carrier block D1 and the first processing block D2 and between the carrier C and the carrier block D1 can be performed quickly. Therefore, as described above, the hydrophobic treatment module 30 is preferably arranged on the rear side of the transfer region 31. Furthermore, in the coating and developing apparatus 1, after the transfer mechanism 32 transfers the wafer W to the pre-processing inspection module 41, the transfer mechanism 33 may receive the wafer W from the inspection module 41, transfer it to the SCPL1, and then take the wafer W into the lower processing block D21. In other words, the transfer of wafers W between the transfer mechanisms 32 and 33 does not necessarily have to be performed using the temporary storage module.

[0088] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects, and various omissions, substitutions, modifications, and combinations may be made to the above-described embodiments without departing from the scope and spirit of the appended claims. [Explanation of symbols]

[0089] C Carrier D2 First processing block D21 First lower processing block D22 First upper processing block 15 Moving Stage TRS Handover Module T1 Module Stack W wafer 31 Transport area 32, 33 Conveying mechanism 6A, 6B, 6C, 6D Conveyor mechanism

Claims

1. a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed; a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view; a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block; a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view; a first transport mechanism for transferring the substrate to and from the carrier; a stack of platform units, each of which receives and delivers the substrate by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, and which are vertically stacked one on top of the other, and which are provided in the transport region in a plan view; a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers; Equipped with In a plan view, a direction in which the stack of the carriers on the placement unit is located relative to a position where the first transport mechanism is provided in the carrier block differs by 90° from a direction in which the carrier placement unit is located relative to a position where the first transport mechanism is provided; The substrate processing apparatus, wherein only the first transport mechanism of the first transport mechanism and the second transport mechanism transfers the substrate to and from the carrier.

2. A substrate processing apparatus as described in claim 1, wherein, when viewed from the front, the area in which the carrier loading section is provided and the position in which the second transport mechanism is provided are aligned on the left and right, separated only by the side wall that faces the outside of the carrier block among the side walls that constitute the carrier block.

3. If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module, 3. The substrate processing apparatus according to claim 1, further comprising a third processing module, to which the substrate is transferred by the first transport mechanism or the second transport mechanism, provided at a position overlapping the stack in a plan view.

4. 4. The substrate processing apparatus according to claim 3, wherein the third processing module is an inspection module for inspecting the substrate.

5. The substrate processing apparatus according to claim 4 , wherein the inspection module extends to the other of the left and right sides from a position overlapping the stack in a plan view, and is provided so as to protrude outside a housing that forms the transfer area.

6. 6. The substrate processing apparatus according to claim 4, wherein the substrate is transported to the inspection module before being transported to the first processing block and the second processing block.

7. a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided on one of the front and rear sides of the second transfer mechanism; 7. The substrate processing apparatus according to claim 3, wherein the substrate is transferred to the third processing module by the first transfer mechanism.

8. a carrier block including a carrier placement portion on which a carrier for storing a substrate is placed; a processing block including a plurality of processing modules stacked on top of each other, each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate, the processing block being provided on either the left or right side of the carrier placement unit in a plan view; a plurality of processing modules each configured to process the substrate and stacked on top of one another; and a main transport mechanism shared by the plurality of processing modules and configured to transport the substrate, the other processing block being vertically overlapped with the first processing block; a transport region for the substrate provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view; a first transport mechanism for transferring the substrate to and from the carrier; a stack of platform units, each of which receives and delivers the substrate by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, and which are vertically stacked one on top of the other, and which are provided in the transport region in a plan view; a second transport mechanism provided in the transport region in a plan view for transporting the substrate between the first and second receivers and between the first and third receivers; Equipped with a fourth processing module to which the substrate is transferred by the second transfer mechanism is provided on one of the front and rear sides of the second transfer mechanism; If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module, the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module that supplies a coating liquid to the substrate to form a coating film; the fourth processing module is a hydrophobic processing module that performs a gas processing on the substrate to hydrophobize the substrate before the supply of the coating liquid; a substrate processing apparatus provided with an airflow forming mechanism for forming an airflow from the other of the front and rear sides in the transfer region toward the fourth processing module and an airflow from the first processing block and the other processing block toward the transfer region;

9. The substrate processing apparatus according to claim 7 , wherein a plurality of the carrier placement sections are provided at different heights on the other side of the stack.

10. On the other side of the conveying area, a temporary carrier placement section for temporarily placing the carrier, the temporary placement section being provided at the same position as the stack body in the front and rear or on one side of the stack body in the front and rear; The substrate processing apparatus according to claim 9 , further comprising: a carrier transfer mechanism that transfers the carrier between the temporary placement unit and the carrier placement unit.

11. 11. The substrate processing apparatus according to claim 1, wherein the first transport mechanism does not transfer the substrate to or from the second platform and the third platform.

12. The substrate processing apparatus according to claim 1 , wherein the second transport mechanism does not transfer the substrate to or from the carrier.

13. an inspection module for inspecting the substrate is provided in the carrier block; 13. The substrate processing apparatus according to claim 1, wherein only the first transport mechanism of the first and second transport mechanisms transfers the substrate to and from the inspection module.

14. a step of placing a carrier for storing substrates on a carrier placement portion provided in a carrier block; a process of transporting the substrate in one processing block provided on either the left or right side of the carrier mounting part in a plan view, the processing block including a plurality of processing modules stacked on top of each other and each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate; a step of transporting the substrate in another processing block that is vertically overlapped with the one processing block, the processing block including a plurality of processing modules that are stacked on top of each other and that process the substrate, and a main transport mechanism that is shared by the plurality of processing modules and transports the substrate; transporting the substrate in a substrate transport region provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view; transferring the substrate to the carrier by a first transport mechanism; transferring the substrate to a first platform, a second platform, and a third platform which are stacked one on top of the other in the vertical direction and which, in a plan view, constitute a stack of platform parts provided in the transport region, by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, respectively; transporting the substrate between the first and second receivers and between the first and third receivers by a second transport mechanism provided in the transport region in a plan view; Equipped with In a plan view, a direction in which the stack of the carriers on the placement unit is located relative to a position where the first transport mechanism is provided in the carrier block differs by 90° from a direction in which the carrier placement unit is located relative to a position where the first transport mechanism is provided; A substrate processing method, wherein only the first transport mechanism of the first and second transport mechanisms transfers the substrate to and from the carrier.

15. a step of placing a carrier for storing substrates on a carrier placement portion provided in a carrier block; a process of transporting the substrate in one processing block provided on either the left or right side of the carrier mounting part in a plan view, the processing block including a plurality of processing modules stacked on top of each other and each processing the substrate, and a main transport mechanism shared by the plurality of processing modules and transporting the substrate; a step of transporting the substrate in another processing block that is vertically overlapped with the one processing block, the processing block including a plurality of processing modules that are stacked on top of each other and that process the substrate, and a main transport mechanism that is shared by the plurality of processing modules and transports the substrate; transporting the substrate in a substrate transport region provided in the carrier block so as to be interposed between the carrier placement part, the first processing block, and the second processing block in a plan view; transferring the substrate to the carrier by a first transport mechanism; transferring the substrate to a first platform, a second platform, and a third platform which are stacked one on top of the other in the vertical direction and which, in a plan view, constitute a stack of platform parts provided in the transport region, by the first transport mechanism, the main transport mechanism of the one processing block, and the main transport mechanism of the other processing block, respectively; transporting the substrate between the first and second receivers and between the first and third receivers by a second transport mechanism provided in the transport region in a plan view; transferring the substrate to a fourth processing module provided on one of the front and rear sides of the second transfer mechanism by the second transfer mechanism; Equipped with If the processing module of the one processing block and the processing module of the other processing block are respectively referred to as a first processing module and a second processing module, the plurality of first processing modules or the plurality of second processing modules includes a coating film forming module; a step of supplying a coating liquid to the substrate in the coating film forming module to form a coating film; a step of hydrophobizing the substrate by gas treatment before supplying the coating liquid in a hydrophobic treatment module that is the fourth treatment module; forming an air flow from the other of the front and rear sides of the transport region toward the fourth processing module and an air flow from the first processing block and the other processing block toward the transport region by an air flow forming mechanism; A substrate processing method comprising:

16. A storage medium for storing a computer program used in a substrate processing apparatus, 16. A storage medium, wherein the computer program is a set of steps for executing the substrate processing method according to claim 14 or 15.

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