Artificial neural networks with reference arrays for IV gradient construction.

Abstract

Numerous embodiments of an artificial neural network comprising a plurality of reference arrays used to construct a vector x matrix multiplication array are disclosed. In one embodiment, a system comprises a vector x matrix multiplication array in an artificial neural network and a plurality of reference arrays characterized by different IV curves, one or more of the plurality of reference arrays being used to generate input voltages to the vector x matrix multiplication array during operation.

Description

[Technical Field]

[0001] (Priority Claim) Related applications claim priority to U.S. Provisional Patent Application No. 63 / 328,543, filed April 7, 2022, entitled "Artificial Neural Network Comprising Monte Carlo Reference Array for IV Slope Configuration," and U.S. Patent Application No. 17 / 848,381, filed June 23, 2022, entitled "Artificial Neural Network Comprising Reference Array for IV Slope Configuration."

[0002] FIELD OF THE INVENTION Numerous embodiments of an artificial neural network with a reference array used for IV gradient configuration in the main array are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that can depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons and an output layer of neurons that provide the neural network's output. Neurons at each level make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency, compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, the synapses of most CMOS implementations are too large given the large number of neurons and synapses.

[0006] Applicant previously disclosed in U.S. Patent Application Publication No. 2017 / 0337466 A1, which is incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to the number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight value to generate the first plurality of outputs. <Nonvolatile memory cell>

[0007] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are accomplished by electrons flowing from the source region 14 toward the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is essentially analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable and making memory arrays ideal for storage and for fine-tuning adjustments to the synaptic weights of neural networks. <Neural network using nonvolatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplications, determines a single output value, which is applied by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then fed to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing operational amplifiers 38 and the activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that a system may alternatively include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., memory cells 310 of VMM array 900, may be configured to optionally operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (sub-threshold region) as follows: Ids=Io×e (Vg-Vth) / nVt =w×Io×e (Vg) / nVt , In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, k is Boltzmann's constant, T is the temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n×Vt×log[Ids / wp×Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector x matrix multiplier VMM array with current inputs, the output current is: Iout=wa×Io×e (Vg) / nVt , i.e. Iout=(wa / wp)×Iin=W×Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth=Vth0+gamma(SQRT|Vsb-2×φF)-SQRT|2×φF|) where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2×beta×(Vgs-Vth) 2 , beta=u×Cox×Wt / L W ∝ (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, memory array 1003 stores weights in each memory cell that are used by VMM array 1000. Second, memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic circuitry and is also power efficient. Here, voltage inputs are applied to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current on each of the bit lines BL0-BLN performs the function of summing the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each of the multiplexers 1212 includes a respective multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on the respective bit lines (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, in which the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current on each bit line performs the function of summing all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 performs one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (causing the wrong value to be stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells; of the first non-volatile reference memory cell Reference Array 130 1 and, and a second reference array 1302 of non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400 except that VMM array 1300 implements bidirectional tuning, so that each individual cell can be fully erased, partially programmed, or partially erased as needed to reach a desired amount of charge on its floating gate through the use of individual EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited to the memory cells 210 shown in FIG. 2 and that is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2200, the input INPUT 0., ... , INPUT N are the bit lines BL0, ..., BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are the bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suited for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUTM are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predetermined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] Figure 14 shows an example LSTM 1400. LSTM 1400 in this example includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives input vector x0 and generates output vector h0 and cell state vector c0. Cell 1402 receives input vector x1, output vector (hidden state) h0 from cell 1401, and cell state c0 from cell 1401, and generates output vector h1 and cell state vector c1. Cell 1403 receives input vector x2, output vector (hidden state) h1 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells can be used; an LSTM with four cells is just an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows LSTM cell 1600, an example implementation of LSTM cell 1500. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. VMM arrays, therefore, prove particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508 and adder device 1509 are implemented in digital or analog fashion. Activation function block 1602 can be implemented in digital or analog fashion.

[0072] An alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an adder device 1708 for adding two vectors, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from sigmoid function block 1702, a register 1704 for storing the value f(t) × c(t−1) when that value is output from multiplier device 1703 via multiplexer 1710, a register 1705 for storing the value i(t) × u(t) when that value is output from multiplier device 1703 via multiplexer 1710, a register 1706 for storing the value o(t) × ĉ(t) when that value is output from multiplier device 1703 via multiplexer 1710, and a multiplexer 1709.

[0073] While LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 1600, so LSTM cell 1700 requires less space than LSTM 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the example described below reduces the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are gating mechanisms within recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 shows an exemplary GRU 1800. GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0077] FIG. 19 shows an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate the output.

[0078] FIG. 20 shows GRU cell 2000, which is an example of an implementation of GRU cell 1900. For the convenience of the reader, the same numbering scheme as GRU cell 1900 is used in GRU cell 2000. As can be seen from FIG. 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems. Multiplier devices 1904, 1905, and 1906, adder device 1907, and complementary device 1908 are implemented in a digital or analog manner. Activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an adder device 2105 for adding the two vectors, a complement device 2109 for subtracting an input from one to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) as it is output from multiplier device 2103 via multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) as it is output from multiplier device 2103 via multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) as it is output from multiplier device 2103 via multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires one-third the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] For each memory cell in the VMM array, each weight W can be provided by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to provide the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to provide the weight W as the average of the two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that provide a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 3101 and 3102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of every pair of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other examples, the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another example: In a VMM system 3210, positive weights W+ are provided in a first array 3211 and negative weights W− are provided in a second array 3212 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 3213.

[0086] Figure 33 shows VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). VMM system 3300 includes array 3301 and array 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connecting to memory cells that provide a negative weight W-. W- lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The outputs on the W+ and W- lines from each array 3301, 3302 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 3301 and 3302 may be further combined via adder circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adder circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system can be erased or programmed to hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate. For example, each floating gate can hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] To ensure the accuracy of a VMM system, it is important to compensate for natural variations that occur. For example, IV slope may vary within the same memory array due to natural process variations and may change as the operating temperature changes. IV slope refers to the relationship between the current drawn by a memory cell when a voltage is applied to its terminals, such as its control gate terminal. It is desirable to be able to compensate for such changes to the IV slope of some or all of the memory array. Summary of the Invention

[0089] A number of examples are described for providing a neural network system with multiple reference arrays containing a range of intentional variations so that an appropriate portion of the reference array that closely approximates the operational array can be selected for operation.

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[0139] [Brief explanation of the drawings]

[0140] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7] FIG. 1 is a block diagram illustrating a VMM system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 9] 1 shows another example of a VMM system. [Figure 10] 1 shows another example of a VMM system. [Figure 11] 1 shows another example of a VMM system. [Figure 12] 1 shows another example of a VMM system. [Figure 13] 1 shows another example of a VMM system. [Figure 14] 1 shows a prior art long-term memory system. [Figure 15] An exemplary cell for use in a long-term memory system is shown. [Figure 16] 16 illustrates an exemplary implementation of the cell of FIG. 15. [Figure 17] 16 illustrates another exemplary embodiment of the cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an exemplary implementation of the cell of FIG. 19. [Figure 21] 20 illustrates another exemplary embodiment of the cell of FIG. 19. [Figure 22] 1 shows another example of a VMM system. [Figure 23] 1 shows another example of a VMM system. [Figure 24] 1 shows another example of a VMM system. [Figure 25] 1 shows another example of a VMM system. [Figure 26] 1 shows another example of a VMM system. [Figure 27] 1 shows another example of a VMM system. [Figure 28] 1 shows another example of a VMM system. [Figure 29] 1 shows another example of a VMM system. [Figure 30] 1 shows another example of a VMM system. [Figure 31] 1 shows another example of a VMM system. [Figure 32] 1 shows another example of a VMM system. [Figure 33] 1 shows another example of a VMM system. [Figure 34] An example of a VMM system is shown. [Figure 35] Shows examples of the VMM array and the reference array. [Figure 36] Shows examples of the VMM array and the reference array. [Figure 37] Shows examples of the VMM array and the reference array. [Figure 38] Shows an example of the reference array. [Figure 39] Shows an example of the reference array. [Figure 40A] Shows the physical layout of the analog array and the embedded reference array. [Figure 40B] Shows the physical layout of the analog array and the embedded reference array. [Figure 41] Shows the reference array selection method. [Figure 42A] Shows examples of data of cells having different I-V gradients. [Figure 42B] Shows examples of data of cells having different I-V gradients. [Figure 43] Shows an example of the physical layout of the memory cell. [Figure 44] Shows an example of the calibration circuit. [Figure 45] Shows the row DAC bias generator. [Figure 46] Shows the row DAC bias generator. [Figure 47] Shows an exemplary global row DAC decoder. [Figure 48] Shows an exemplary global row DAC decoder. [Figure 49] Shows an exemplary layout of the reference array. [Figure 50] Shows an exemplary layout of the reference array. [Figure 51] Shows an exemplary layout of the reference array. [[ID=�8]]

Mode for Carrying Out the Invention

[0141] <Structure of the VMM System> 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high-voltage decoder 3403, a column decoder 3404, a bit line driver 3405, input circuits 3406, output circuits 3407, control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high-voltage generation block 3410, which includes a charge pump 3411, a charge pump regulator 3412, and a high-voltage level generator 3413. The VMM system 3400 further includes a (program / erase or weight adjustment) algorithm controller 3414, analog circuitry 3415, a control engine 3416 (which may include specialized functions such as, but not limited to, arithmetic functions, startup functions, embedded microcontroller logic, etc.), and test control logic 3417.

[0142] The input circuit 3406 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of a normalization, a linear or nonlinear up / downscaling function, or an arithmetic function. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as a ReLU or a sigmoid.

[0143] The output circuit 3407 may include circuits such as an ADC (analog to digital converter, for converting the analog output of the neuron into digital bits), an AAC (analog to analog converter, such as a current-to-voltage converter or a logarithmic converter), an APC (analog to pulse converter, analog to time modulated pulse converter), or any other type of converter. The output circuit 3407 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement one or more of statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of the neuron output. The output circuit 3407 may implement temperature compensation functions for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant or to increase the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same.

[0144] 35 and 36 show an example of a reference array embedded in the same physical array as the VMM array.

[0145] 35 shows a physical array 3500. Physical array 3500 optionally includes an array of non-volatile memory cells, which may optionally include stacked gate flash memory cells or split gate flash memory cells.

[0146] Physical array 3500 is divided into two types of arrays: VMM array 3401 (as in FIG. 34) and reference array 3501. Reference array 3501 includes multiple reference arrays, as shown in FIGS. 38 and 39. In one embodiment, VMM array 3401 and reference array 3501 share the same bit lines. In another embodiment, VMM array 3401 and reference array 3501 use separate sets of bit lines, and the two sets of bit lines are separated. An exemplary physical layout is shown in FIGS. 40A and 40B.

[0147] 36 shows physical array 3600 divided into two arrays: VMM array 3401 and reference array 3501. In one embodiment, VMM array 3401 and reference array 3501 share one or more sets of horizontal lines, such as word lines, control gate lines, and erase lines. In another embodiment, VMM array 3401 and reference array 3501 do not share any sets of horizontal lines.

[0148] 37 shows an embodiment in which reference array 3501 and VMM array 3401 are located in separate physical arrays. For example, there may be substrate separation or active diffusion separation between the two arrays. Physical array 3701 includes VMM array 3401, and physical array 3702 includes reference array 3501. VMM array 3401 and reference array 3501 do not share any bit lines, word lines, control gate lines, or erase lines.

[0149] FIG. 38 shows an exemplary Reference Array3501, where reference array 3501 includes multiple reference arrays, such as reference arrays 3801-0, 3801-1, ..., 3801-(n-1), and 3801-n. Thus, reference array 3501 includes n+1 different reference arrays. The different reference arrays can have different characteristics that cause each reference array to be characterized by a different IV curve than the other reference arrays. For example, each reference array can differ in one or more of the following dimensions: (1) the width of the control gate lines of the transistors in each reference array, (2) the width of the word lines of the transistors in each reference array, (3) the width of the floating gates of the transistors in each reference array, (4) the overall width of the non-volatile memory cells in each reference array, (5) the spacing of shallow trench isolation (STI) in each reference array, or (6) other features. Additionally, the reference arrays may each differ in one or more device implant conditions or doping characteristics (such as, but not limited to, well implant conditions, source implant conditions, drain implant conditions, etc.).

[0150] FIG. 39 shows another example of reference array 3501. Here, reference array 3501 includes multiple reference arrays, such as reference arrays 3901-0, 3901-1, ..., 3901-(n-1), and 3901-n, and 3901-0, 3902-1, ..., 3902-(n-1), and 3902-n. Thus, reference array 3501 includes 2×(n+1) different reference arrays. As in FIG. 38, the different reference arrays can have different characteristics that cause each reference array to be characterized by a different IV curve from the other reference arrays. For example, each reference array can differ in one or more of the following dimensions: control gate width, word line width, floating gate width, total non-volatile memory cell width within the array, STI spacing, and device implant conditions, without limitation.

[0151] FIG. 40A shows the physical layout of the VMM array and reference array. VMM system 4001 includes VMM array 4002 and array 4004. Exemplary bit line BL0 is coupled to VMM array 4002, and exemplary bit line BLR0 is coupled to reference array 4004. Bit line BL0 coupled to VMM array 4002 may be referred to as VMM array bit line BL0, and for example, uses metal layers M1-M4 within VMM array 4002, with metal layers M2-M4 also connecting to peripheral circuits (such as column decoders), while bit line BLR0 coupled to reference array 4004 may be referred to as reference array bit line BLR0, and for example, uses only metal layer M1. VMM array 4002 and reference array 4004 are part of the same physical array 4003. Physical array 4003 includes substrate 4005 and diffusion layer 4006, both of which are shared by VMM array 4002 and reference array 4004. Physical array 4003 is electrically partitioned by using separate metal interconnects for VMM array 4002 and reference array 4004. For example, as can be seen, metal bit line BL0 of the VMM array and metal bit line BLR0 of the reference array both use metal layer M1, but are separated from each other. Using the same physical array 4003 for both VMM array 4002 and reference array 4004 reduces any physical impact from process uniformity and area overhead that would result from using separate physical arrays.

[0152] Figure 40B shows another embodiment of the physical layout of the VMM array and reference array, which is similar to Figure 40A except that in this VMM system 4051, the diffusion layer 4056 for the VMM array 4052 and the diffusion layer 4057 for the reference array 4004 are separated.

[0153] FIG. 41 illustrates a reference array selection method 4100 performed to calibrate a VMM system. Method 4100 can be performed during a manufacturing or test process, or can be performed during real-time operation of the VMM system. In step 4101, multiple reference arrays are selected as candidates for the calibration process. For example, multiple reference arrays are selected as candidates to adjust the IV (current-voltage) slope of the VMM array. In step 4102, a metric is determined for each of the multiple reference arrays. The metric may be, for example, a target circuit performance metric or a target neural network performance metric. In step 4103, a reference array within the multiple reference arrays that results in a metric closest to the target value is identified. In step 4104, the reference array identified in step 4103 is used to calibrate the VMM array.

[0154] Figure 42A shows data captured from a memory array having different physical characteristics. Figure 42B shows data captured from a memory array having different electrical characteristics (such as due to well implants). As can be seen, the IV slope of the memory cells can differ based on physical or electrical variations between the memory cells.

[0155] 43 shows one example of a physical layout of reference memory cells 4300 in reference array 3501, it can be understood that the control gate width, word line width, floating gate width, overall width, and STI spacing dimensions can vary based on the manufacturing process and layout used. These are examples of the characteristics discussed above with reference to FIGS. 38 and 39 and can vary from reference array to reference array.

[0156] 44-48 provide an example of how a reference array 3501 can be used to calibrate a VMM array 3401.

[0157] FIG. 44 shows an exemplary row bias calibration circuit 4400 including a current digital-to-analog converter (DAC) 4401, an operational amplifier 4402, and a reference memory cell 4403. The reference memory cell 4403 may be a reference cell in the reference arrays of FIGS. 35-39. The row bias calibration circuit 4400 provides a reference CG bias. The CG bias may then be applied directly to a CG terminal in the VMM array to provide a bias voltage for those cells, or the CG bias may be used in a larger system, such as row DAC bias generator 4500 in FIG. 45, row DAC bias generator 4600 in FIG. 46, input block 4700 in FIG. 47, or input block 4800 in FIG. 48, to generate a bias voltage that may be applied to a CG terminal or other terminal in the VMM array to provide a bias voltage for those cells.

[0158] Reference memory cell 4403 may specifically be from the reference array selected in step 4103 of method 4100 of Figure 41. The input, DIN[0:n], selects the current generated by current DAC 4401. The generated current is the target current that a memory cell in VMM array 3401 would ideally generate for the stored weight corresponding to the value of DIN[0:n]. For example, if DIN is an 8-bit value, there are 256 possible values ​​of DIN and 256 respective current levels that would ideally be generated during a read operation to a memory cell in VMM array 3401 storing a weight corresponding to that value.

[0159] Op-amp 4402 outputs a voltage CGbias on terminal CG of reference memory cell 4403. Based on the inherent properties of op-amps, op-amp 4402 adjusts this output voltage until the voltage on its inverting input terminal equals the voltage VREF (which may be any reference value, such as 0.5 V) on its non-inverting input terminal. The output voltage of op-amp 4402 can be sampled and applied to the control gate terminals of memory cells in VMM array 3401 as a bias voltage, or alternatively as an analog input to the array. Alternatively, CGbias can be used in systems such as row DAC bias generator 4500 of FIG. 45, row DAC bias generator 4600 of FIG. 46, input block 4700 of FIG. 47, or input block 4800 of FIG. 48.

[0160] Reference cell 4403 may be a single cell or may include multiple cells. For example, multiple reference cells may be used to achieve an averaging effect or to reflect the weight distribution of a layer of a neural network. For example, in an attempt to approximate a typical weight distribution in a VMM array in an artificial neural network, multiple reference cells may be selected so that 50% of the reference cells reflect low weight values, 20% of the reference cells reflect medium weight values, and 30% of the reference cells reflect high weight values.

[0161] Or, for example, different instantiations of row bias calibration circuit 4400 can be used to generate different CGbias levels, such as high, medium, and low CGbias levels. For example, a low CGbias level (VREFL) can be generated using several reference cells (e.g., 1 cell, 2 cells, ..., 32 cells), each with a target current of 3 nA (generated by the current digital-to-analog converter 4401) representing the first level of the 32 levels of the memory cell for a 5-bit cell; a high CGbias level (VREFH) can be generated using several reference cells (e.g., 1 cell, 2 cells, ..., 32 cells), each with a target current of 96 nA representing the 32nd level of the 32 levels of the memory cell for a 5-bit cell; and a medium CGbias level (VREFM) can be generated using several reference cells (e.g., 1 cell, 2 cells, ..., 32 cells), each with a target current of 48 nA representing the 16th level of the 32 levels of the memory cell for a 5-bit cell. In this manner, three instances of the row bias calibration circuit 4400 can be used to generate the high voltage VREFH, the medium voltage VREFM, and the low voltage VREFL.

[0162] In the case of a serial DAC input (such as an input comprising a sequence of one digital input bit applied simultaneously, with a corresponding digital output being shifted and added for each binary input bit position) or a timed input (pulse width modulated input or pulse count input), the CG bias voltage applied to the VMM array can be supplied by the row bias calibration circuit 4400 of FIG. 44.

[0163] FIG. 45 shows a row DAC bias generator 4500 comprising a voltage ladder 4501, a mapping block 4502, and an output buffer 4503. The voltage ladder 4501 generates multiple voltage levels (L, ..., L), each of which supplies a voltage to the VMM array to operate the VMM array in either linear mode or sub-threshold mode, depending on the selected voltage mode (linear or sub-threshold). For sub-threshold operation, for example, the voltage ladder 4501 may have 8-14 bits of resolution. Control logic (not shown) controls the row DAC bias generator 4500 (by providing control signals to multiplexers, enabling various blocks using enable signals such as EN, and performing other control functions).

[0164] Mapping block 4502 converts the levels from voltage ladder 4501 into respective analog outputs, such as voltages representing an 8-bit output, and the output of mapping block 4502 is fed to output buffer 4503 .

[0165] The output of output buffer 4503 is shown as DAC_OUT 4590 and is then applied as a bias voltage (e.g., on the CG terminal) to a row of memory cells in the VMM array to modify the IV slope of those cells. Local trimming of each level (represented by trim blocks L0_trm, ..., Ln_trm) is provided in mapping block 4502, at least when the array is operating in the sub-threshold region. By applying this bias voltage, for example, to the control gate lines of a row of memory cells, a non-linear IV slope for the memory cells in the VMM array is achieved over a temperature range in the sub-threshold region. It can be seen that DAC_Out 4590 is generated using multiple reference arrays (e.g., one reference array for generating VREFH and another reference array for generating VREFL).

[0166] Voltage ladder 4501 receives a high reference voltage VREFH (such as VREFH generated by an instantiation of row bias calibration circuit 4400 in FIG. 44 described above) and a low reference voltage VREFL (such as VREFL generated by an instantiation of row bias calibration circuit 4400 in FIG. 44 described above). VREFH corresponds to the highest value that can be stored in a cell in the VMM array, and VREFL corresponds to the lowest value that can be stored in a cell in the VMM array. Voltage ladder 4501 comprises a plurality of resistors used to generate a voltage range between VREFL and VREFH, optionally according to a linear or logarithmic function. For example, the top node of the top resistor in the voltage ladder has voltage VREFH, and the bottom of the resistor has a lower voltage due to the voltage drop across the top resistor. The bottom node of the bottom resistor has voltage VREFL. The voltage ladder thereby generates multiple voltage levels (L0, ..., Lk) (for example, k may be 4095) that are required when it is desired to supply voltages to the VMM array to operate the non-volatile memory cells of the VMM array in linear or sub-threshold mode.

[0167] Mapping block 4502 receives digital input DIN[n:0] and uses it to select one of m+1 (where (m+1)=2^(n+1)) analog voltages via sub-blocks 4563 within mapping block 4502. For example, if (n+1)=8, then (m+1)=256. Mapping block 4502 includes (m+1) trim blocks 4562 and (m+1) multiplexers 4563. Mapping block 4502 converts k+1 voltage levels from DAC 4501 to respective analog outputs corresponding to DIN[n:0]. This is achieved using local trimming for each level (represented by trim blocks L0_trm, ..., Lm_trm), which may be useful, for example, when the nonvolatile memory cells in the array are operating in the sub-threshold region. This is desirable to achieve an optimal IV slope over temperature for the nonvolatile memory cells in the VMM array in the sub-threshold or linear region.

[0168] By adjusting the reference voltages VREFL and VREFH, the k+1 level is also adjusted in a similar manner. This may be done, for example, to match the output range of this input block to the input range of the memory cells. This may also be done for temperature compensation by adjusting the reference levels VREFL and VREFH (e.g., shifting them lower when the temperature is high and shifting them higher when the temperature is low) to achieve a desired range of gate bias for the memory cells, which may be required due to temperature changes. Further individual level adjustments and temperature compensation may be performed by level trimming circuits in mapping block 4502, for example, to maximize the accuracy of the neural network.

[0169] FIG. 46 shows row DAC bias generator 4600. Row DAC bias generator 4600 is similar to row DAC bias generator 4500, except that it uses voltage ladder 4601 instead of voltage ladder 4501. Voltage ladder 4601 is similar to voltage ladder 4501, but adds an intermediate reference level VREFM (such as VREFM generated by the instantiation of row bias calibration circuit 4400 of FIG. 44 described above). The adjustment and temperature behavior of the VREFM reference level is controlled similarly to that of the VREFH and VREFL reference levels. It includes an additional buffer 4603 to apply the intermediate reference level to the resistor ladder to further adjust the IV slope match between GDAC5480 and the input of the memory array. While voltage ladder 4601 uses three voltage reference levels (VREFH, VREFM, and VREFL), it will be understood that other numbers of voltage reference levels can be used instead.

[0170] The reference voltage is generated from the CGbias output of the instantiation of row bias calibration circuit 4400 of Figure 44 using reference memory cells 4403 from n+1 reference arrays 3801 or 3901. Row DAC bias generator 4600 provides the bias voltage (DAC_OUT 4602) that is applied to the rows of the VMM array.

[0171] FIG. 47 illustrates an exemplary input block 4700 used to provide input to a VMM array, such as VMM array 3401 of FIG. Input block 4700 includes a global digital-to-analog converter (DAC) 4701, address row decoders 4702-0 to 4702-n, each corresponding to one of the rows numbered 0 to n in the VMM array, row registers 4703-0 to 4703-n, each corresponding to one of the rows numbered 0 to n in the VMM array, digital comparator blocks 4704-0 to 4704-n, each corresponding to one of the rows numbered 0 to n in the VMM array, row sample-and-hold (S / H) buffers 4705-0 to 4705-n, each corresponding to one of the rows numbered 0 to n in the VMM array, output signals 4706-0 to 4706-n, each corresponding to one of the rows numbered 0 to n in the VMM array, and a counter 4707.

[0172] The global DAC 4701 may optionally comprise the row DAC bias generator 4500 of FIG. 45 or the row DAC bias generator 4600 of FIG. 46, with the reference voltage levels VREFH, VREFL, and optionally VREFM provided by an instantiation of the row bias calibration circuit 4400 of FIG. 44.

[0173] Each set of row registers 4703, digital comparators 4704, and row sample and hold buffers 4705 for a particular row can be considered a local digital-to-analog converter for that particular row, and the voltage source for that local digital-to-analog converter is provided by a global DAC 4701, as described below.

[0174] Address row decoders 4702-0 through 4702-n receive a row address ADD[n:0] and an enable signal EN. The output of each address row decoder, denoted ENROW, where ADD[n:0] is the address of that particular row, is high when EN is asserted. Row registers 4703-0 through 4703-n are loaded with the respective digital input bits DINx (where x is the number of bits, such as 8 or 16) for that particular row, where the load operation is triggered by a clock signal CLK and DINx is the activation input for that particular row, performing a vector x multiplication matrix operation. When the output of a particular address row decoder 4702 is high, the associated row register 4703 is enabled and outputs its digital bit DINx. A counter 4707, when enabled by a signal EN, counts pulses in another clock signal CLKB. The output of the counter 4707 is a count value. Digital comparator blocks 4704-0 through 4704-n compare the activation value DINx stored in each of the respective row registers 4703 with the count value. If the count value matches the value stored in a particular row register 4702, the respective digital comparator block 4704 enables the corresponding row S / H buffer 4705, which samples and holds the analog output value from the global DAC 4701. The global DAC 4701 performs a digital-to-analog conversion on the count value (which also matches DINx in the row register 4703 for that row). Each row S / H buffer 4705 outputs the held analog value as an output signal 4706. For example, if x=8 and DINx is an 8-bit input (meaning there are 256 different values ​​for DINx), the counter 4707 counts up to 256 and then resets. In doing so, it covers all possible values ​​of DINx, and each row S / H buffer 4705 is loaded with its associated DINx value.

[0175] The output signals 4706 may be applied to the control gate lines or word lines, for example, during a programming or read operation on a particular row, or during a neural read operation in which all rows are read. During a neural read, all S / H buffers 4705 are enabled to drive the array input terminals via their respective output signals 4706, resulting in bit line currents being output by the VMM array, which are then processed by output circuits such as ITV (current-to-voltage converter) circuits and ADC (analog-to-digital converter) circuits.

[0176] Each respective output signal 4706 may be applied to a respective control gate line or word line, for example, during a programming or read operation on that particular row.

[0177] In another embodiment, row sample and hold buffer 4704 may be shared by multiple rows in a time division multiplexed manner.

[0178] Figure 48 shows an exemplary input block 4800 used to provide inputs to a VMM array, such as VMM array 3401 of Figure 34. Input block 4800 is similar to input block 4400 of Figure 44, but provides multiple outputs from a global digital-to-analog converter for neural read operations. Input block 4800 includes a global digital-to-analog converter 4801, address row decoders 4802-0 to 4802-n, each corresponding to a respective one of the rows numbered 0 to n, row registers 4803-0 to 4803-n, each corresponding to a respective one of the rows numbered 0 to n, digital comparators 4804 to 4804-n, each corresponding to a respective one of the rows numbered 0 to n, row sample and hold buffers 4805-0 to 4805-n, each corresponding to a respective one of the rows numbered 0 to n, and output signals 4806-0 to 4806-n, each corresponding to a respective one of the rows numbered 0 to n.

[0179] The global DAC 4801 may optionally comprise the row DAC bias generator 4500 of FIG. 45 or the row DAC bias generator 4600 of FIG. 46, with reference voltage levels VREFH, VREFL, and optionally VREFM provided by an instantiation of the row bias calibration circuit 4400 of FIG. 44.

[0180] Address row decoders 4802-0 through 4802-n receive a row address ADD[n:0] and an enable signal EN. The output of each address row decoder 4802, designated ENROW, is high when ADD[n:0] is the address for that particular row and EN is asserted. Row registers 4803-0 through 4803-n are loaded with respective digital input bits DINx (where x is the number of bits, such as 8 or 16), where loading is triggered by the clock signal CLK for that particular row and DINx is the activation input for that particular row. When the output ENROW of a particular address row decoder 4802 is high, the associated row register 4803 is enabled and outputs its digital bit DINx. A counter 4807, when enabled by the signal EN, counts pulses in another clock signal CLKB. The output of the counter 4807 is a count value. Digital comparator blocks 4804-0 through 4804-n compare the activation value DINx stored in each of the respective row registers 4803 with the count value. If the count value matches the value stored in a particular row register 4802, the respective digital comparator block 4804 enables the corresponding row S / H buffer 4805 to sample and hold the analog output value from the GDAC 4801. As shown, there are two vertical analog output lines from the GDAC 4801. For example, for an 8-bit GDAC 4801, one line can carry output analog levels from 0 to 127 (corresponding to 00000000 to 01111111), and the other line can carry output analog levels from 128 to 255 (corresponding to 10000000 to 11111111). Both lines can operate simultaneously to reduce the row DAC sampling time from 256 (DAC) clocks to 128 (DAC) clocks. Each row S / H buffer 4805 receives only one of the outputs from GDAC 4801. The output signal 4806 may be applied to a control gate line or word line, for example, during a programming operation on that particular row.

[0181] Optionally, the global digital-to-analog converter 4801 may comprise a first global DAC for odd rows and a second global DAC for even rows.

[0182] FIG. 49 shows an exemplary layout of reference array 3501. Reference array 3501 includes reference arrays 4901-0, 4901-1, 4901-2, and 4901-3, which are coupled to respective shared bit lines in the same metal layer, such as metal layer M1. Each reference array 4901 can provide a CG reference bias, for example, but not limited to, a low level (VREFL), a medium level (VREFM), or a high level (VREFH), as described above in connection with FIGS. 44-46. When a particular bit line is used for one reference array, cells in other reference arrays connected to that bit line are deeply programmed so that they do not conduct any current and are essentially disabled. In this way, each bit line can be effectively dedicated for use by only one of the reference arrays.

[0183] 50 shows an example layout of reference array 3501. Reference array 3501 includes reference arrays 5001-0, 5001-1, 5001-2, and 5001-3, which are coupled to respective bit lines in different metal layers, such as metal layers M4, M3, M2, and M1, respectively. Each reference array 4901 provides a CG reference bias, for example, but not limited to, a low level (VREFL), a mid-level (VREFM), or a high level (VREFH), as described above in connection with FIGS.

[0184] FIG. 51 shows an example layout of reference array 3501. Reference array 3501 includes reference arrays 5101-0, 5101-1, 5101-2, and 5101-3, each coupled to a bit line in the same metal layer, such as metal layer M1. Each reference array 4901 provides a CG reference bias, for example, but not limited to, a low level (VREFL), a medium level (VREFM), or a high level (VREFH), as described above in connection with FIGS. 44-46. Here, each bit line is electrically coupled to only one of the reference arrays and is electrically isolated from the other reference arrays.

[0185] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: Vector x matrix multiplication arrays in artificial neural networks; a plurality of reference arrays characterized by different I-V curves, one or more of the plurality of reference arrays being used during operation to generate input voltages to the vector x matrix multiplication array.

2. The system of claim 1 , comprising a control circuit that provides a target current through the one or more reference cells of the plurality of reference arrays to generate the input voltage.

3. The system of claim 1 , wherein each reference array of the plurality of reference arrays differs in at least one dimension.

4. 4. The system of claim 3, wherein the dimension is a width of a control gate line of a transistor in the respective reference array.

5. 4. The system of claim 3, wherein the dimension is a word line width of a transistor in the respective reference array.

6. The system of claim 3 , wherein the dimension is a width of a floating gate of a transistor in the respective reference array.

7. 4. The system of claim 3, wherein the dimension is the overall width of a non-volatile memory cell in the respective reference array.

8. The system of claim 3 , wherein the dimension is a shallow trench isolation spacing of transistors in the respective reference arrays.

9. The system of claim 1 , wherein each reference array of the plurality of reference arrays has a different doping characteristic.

10. 10. The system of claim 1, wherein the plurality of reference arrays and the neural network array comprise non-volatile memory cells.

11. The system of claim 10 , wherein the non-volatile memory cells are stacked gate flash memory cells.

12. The system of claim 10 , wherein the non-volatile memory cells are split-gate flash memory cells.

13. The system of claim 1 , wherein the reference array generates a bias for the neural network array.

14. The system of claim 1 , wherein the reference array generates biases for rows of the neural network array.

15. The system of claim 1 , wherein the plurality of reference arrays and the vector x matrix multiplication array are within the same physical array.

16. The system of claim 1 , wherein the plurality of reference arrays and the vector by matrix multiplication array are in different physical arrays.

17. The system of claim 1 , wherein each reference array of the plurality of reference arrays has a different electrical characteristic.

18. 1. A method comprising: determining respective metrics for a plurality of reference arrays; identifying a reference array within the plurality of reference arrays for which the determined metric is closest to a target value; and using the identified reference array to generate input biases for a vector-by-matrix multiplication array in an artificial neural network.

19. 20. The method of claim 18, wherein the plurality of reference arrays and the array of artificial neural networks are within the same physical array.

20. 20. The method of claim 18, wherein the plurality of reference arrays and the array of the artificial neural network are in different physical arrays.

21. The method of claim 18 , wherein each reference array of the plurality of reference arrays has a different electrical characteristic.

22. 20. The method of claim 18, wherein each reference array of the plurality of reference arrays has a different doping characteristic.

23. 20. The method of claim 18, wherein calibrating comprises generating bias voltages and applying the bias voltages to memory cells in the vector by matrix multiplication array.

24. 20. The method of claim 18, wherein the reference array generates biases for rows of the neural network array.

25. 20. The method of claim 18, wherein the plurality of reference arrays and the artificial neural network array comprise non-volatile memory cells.

26. 26. The method of claim 25, wherein the non-volatile memory cells are stacked gate flash memory cells.

27. 26. The method of claim 25, wherein the non-volatile memory cells are split-gate flash memory cells.

28. A system comprising:

1. A system comprising: a plurality of reference arrays, one or more of which are used during operation to generate bias voltages for a vector x matrix multiplication array, the plurality of reference arrays being coupled to bit lines in different metal layers.

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