Measurement method for estimating the temperature of a power semiconductor module

Abstract

A measurement method for estimating the temperature of a MOS / MIS power semiconductor module, comprising the steps of: a. applying a positive current I g,ref , and an initial gate-emitter / source voltage V 0,ref is the flat band voltage V fb and b. the voltage across the current source, V ig,ref (t) is measured, and c. the voltage is the flat band voltage V fb When the current I g,ref In the operating state, a positive current I g,op , and an initial gate-emitter / source voltage V 0,op is the flat band voltage V fb and e. the voltage across the current source V ig,op (t) is measured, and f. the voltage is the flat band voltage V fb When the current I g,op g. Stopping the injection of the voltage V ig,ref (t) and voltage V ig,op (t) and h. Comparing the temperature variance T across the module j,dev and estimating

Description

[Technical Field]

[0001] The present disclosure relates to the field of power semiconductor monitoring. [Background technology]

[0002] It is known to monitor the temperature of metal-oxide semiconductor (MOS) power semiconductors or parallel-connected MOS power semiconductors, especially in power semiconductor devices / modules such as multi-chip power modules, for protection, status, and health monitoring. Generally, the free surface of the die is very small. Fixing a sensor on it is difficult, and in some cases, even impossible. Using individual gate accesses of the power die to measure individual gate resistances, a heat-sensitive parameter, is theoretically clear. However, the number of external connections becomes large, making the system implementation complex. It is very difficult to implement at the laboratory level. In actual industrial and operational situations, using individual PN junction sensors is not practical.

[0003] Additionally, because the sensor must be integrated inside the power module's packaging, its presence must be initially planned for during module conception and cannot be retrofitted to existing power modules.

[0004] Many temperature sensitive electrical parameter (TSEP) based methods and on-chip sensors are known for online estimation of the junction temperature of power semiconductors. Below are examples of measurements and operations used to estimate TSEP: Gate voltage plateau detection during turn-on Turn-off delay time (t dOff ) Turn-on delay time (t dOn ) Duration of the Miller Plateau Sub-threshold voltage via auxiliary emitter (source) and power emitter (source) Transient gate current peak at turn-on Apply a sinusoidal gate-emitter voltage and measure the instantaneous voltage drop across the external gate resistor Injecting a DC current into the gate path of the power die and measuring the voltage across the gate-emitter

[0005] In any of these known methods, the necessary calibration of the TSEP is only possible at a uniform temperature. However, since only a single TSEP is available for the parallel dies, temperature non-uniformities during normal operation lead to erroneous estimation of the junction temperature. The accuracy of the TSEP depends on the average temperature, the maximum temperature, or the minimum temperature. As explained in Non-Patent Document 1, the collector-emitter voltage (V ce ) is one of the TSEPs with the highest average temperature accuracy, but dV CE Using other TSEPs such as / dt completely fails to estimate the junction temperature, primarily because the hottest die has the highest Miller capacitance and therefore V CE Furthermore, the average temperature is estimated by the plateau difference of the mirror. In Non-Patent Document 2, a quasi-threshold method is studied for parallel dies. In this method, the lowest threshold voltage (V th ) is measured, and all dies have the same V th If the temperature is j ), but this is not the case (measured errors of up to 25K for a 50K increase). Furthermore, since die performance is temperature-related, temperature imbalances change the sensitivity and linearity of the TSEP.

[0006] Loss and thermal models can be used to compensate the estimated virtual junction temperature up to or including the die-to-die temperature difference. Nevertheless, these methods require complex calibration systems of loss and thermal models and become less accurate during operation of the power module if the solder layers deteriorate or, in general, if differences arise between the operating conditions and the initial model during module operation. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] C. Chen, V. Pickert, B. Ji, C. Ji, A. Knoll and C. Ng, “Comparison of TSEP Performances Operating at Homogeneous and Inhomogeneous Temperature Distribution in Multichip IGBT Power Modules” IEEE Journal of Emerging and Selected Topics in Power Electronics [Non-patent document 2] M. Hoeer, F. Filsecker, M. Wagner and S. Bernet, “Application issues of an online temperature estimation method in a high-power 4.5 kV IGBT module based on the gate-emitter threshold voltage”, 2016, 18th European Conference on Power Electronics and Applica Summary of the Invention [Problem to be solved by the invention]

[0008] The present disclosure improves this situation. [Means for solving the problem]

[0009] A measurement method is proposed for estimating the temperature of a power semiconductor module comprising a single metal-oxide semiconductor, a single metal-insulator semiconductor, or a set of parallel-connected metal-oxide semiconductors or metal-insulator semiconductors, the method comprising: a. Positive current I from the emitter / source of the module to the gate g,refand injecting an initial gate-emitter / source voltage V 0,ref is the flat band voltage V fb and b. The voltage V across the current source ig,ref Measuring (t); c. The module voltage is the flat band voltage V fb When the current I g,ref and stopping the infusion of at least one first series of operations while the module is in a reference state, including: d. A positive current I flows from the emitter / source of the module to the gate. g,op and injecting an initial gate-emitter / source voltage V 0,op is the flat band voltage V fb and e. Voltage V across the current source ig,op Measuring (t); f. The module voltage is the flat band voltage V fb When the current I g,op and stopping the infusion of at least one second series of operations while the module is in an operational state, including: Next, g. The voltage V measured during one first series ig,ref (t) and the voltage V measured during one second series ig,op (t) and h.Comparison of temperature dispersion across the module T j,dev and estimating and at least one third series of operations, including: Includes.

[0010] In another aspect, a power semiconductor module is proposed, comprising a single metal-oxide semiconductor, a single metal-insulator-semiconductor, or a set of parallel-connected metal-oxide semiconductors or metal-insulator-semiconductors, and configured to perform the methods described herein.

[0011] In another aspect, there is proposed computer software comprising instructions which, when executed by a processor, perform a method as defined herein. In another aspect, there is proposed a computer readable non-transitory storage medium having software stored thereon, which, when executed by a processor, performs a method as defined herein.

[0012] The following features can optionally be implemented separately or in combination with each other.

[0013] Each of the at least one first series and the at least one second series comprises: i. Average module temperature T av,ref and T av,op and further comprising obtaining The second series is the average temperature T obtained during at least one first series. av,ref and the average temperature T obtained during the second series av,op The difference between the two is a predetermined value ΔT lim This is repeated until the following occurs:

[0014] The first series may be divided into two series with different mean temperatures T av,ref,n It is executed with The first series is executed during a state different from the operational state of the module.

[0015] The first series may be divided into two series with different mean temperatures T av,ref,n It is executed with Each of the first series is executed during the baseline and operational states of the module and before a predetermined operational deadline in the operational operation of the module is reached.

[0016] The third series, before the comparison, g'. The voltage V measured during at least one first series ig,refFor the waveform of (t), the voltage V measured during at least one second series ig,op (t) is adjusted in time and offset. Further includes:

[0017] Each of the at least one first series is executed when the power transmitted by the module is below a predetermined limit that is below the nominal maximum load of the module.

[0018] Other features, details and advantages are set forth in the following detailed description and figures. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1 is a temperature distribution diagram of a semiconductor device at the beginning of operation (new). [Figure 2] FIG. 1 is a temperature distribution diagram of a semiconductor device during use (deterioration). [Figure 3] 1 is a thermal view of a semiconductor module containing six parallel-connected semiconductor devices. [Figure 4] 4 is an equivalent circuit of the module shown in FIG. 3. [Figure 5] 1 is a circuit according to one embodiment. [Figure 6] 1 is a graph of some data obtained during one embodiment. [Figure 7] 1 is a graph of some data obtained during one embodiment. [Figure 8] 1 is a flowchart executed during one embodiment. [Figure 9] 1 is a flowchart of an algorithm executed during one embodiment. [Figure 10] 1 is a graph of voltage as a function of time. [Figure 11] 11 is the same graph as FIG. 10 after adjusting the values / curves. [Figure 12] 1 is a graph of voltage deviation as a function of temperature deviation. [Figure 13]1 is a graph of gate-emitter voltage as a function of time. DETAILED DESCRIPTION OF THE INVENTION

[0020] Reference is now made to FIGS. 1 to 4. FIGS. 1 and 2 are temperature distribution diagrams of a power semiconductor module 1 having the same architecture but photographed at two different stages of their usage time. The module 1 in FIG. 1 is new and in a short-term operating state, while the module 1 in FIG. 2 has deteriorated due to long-term operation. These photographs clearly show that significant temperature non-uniformity in a single device (here, a die) appears during operation of the module 1. FIGS. 3 and 4 show another power semiconductor module 1 having six parallel-connected semiconductor elements 11 (die). These photographs clearly show that temperature non-uniformity appears between devices (here, dies) within the same module 1 during operation of the module 1.

[0021] Several measurement methods can be used to monitor such temperatures at laboratory level. Here, a measurement method is proposed for estimating the temperature of a power semiconductor module 1. The method is typically not used on a test bench, but under operating conditions when the module is integrated and interconnected in its operating and application environment.

[0022] In the following, a power semiconductor module is an assembly comprising a single metal-oxide-semiconductor (MOS) transistor, a single metal-insulator-semiconductor (MIS) transistor, or a set of parallel-connected MOS / MIS transistors. Here, the transistors are MOSFETs (metal-oxide-semiconductor field-effect transistors), but IGBTs (insulated-gate bipolar transistors) can also be used. When multiple MOS / MIS transistors are connected in parallel, there is a common gate G, a common source S, and a common drain D. For this reason, in the following, the terms single gate, single source, and single drain will be used interchangeably to refer to embodiments with one or more MOS transistor elements. The term "power" is used in its general sense in the technical field of energy conversion (power electronics).

[0023] The method comprises: at least one first series of operations I while module 1 is in a reference state; at least one second series of operations II while module 1 is in an operational state; At least one third series of operations III; Includes.

[0024] The reference state corresponds to a state in which the MOS elements are in a known state, and the temperature non-uniformity within the module 1 is limited to a predetermined maximum value ΔT ref It is known that the reference temperature is less than 1000 kHz, and the smaller the temperature the better. For example, all dies are heated to the same temperature and no power is consumed on the dies. This reference condition allows us to obtain a reference value for module 1.

[0025] In the examples below, such a reference state is controlled. However, in various embodiments, the reference state may correspond to a particular period of operation of module 1 during which MOS device 11 is in a known stable state, e.g., an off state.

[0026] In the following example, module 1 comprises (or is connected to) control circuit 2, which: The voltage of the MOS element 11 of the module 1 is its flat band voltage V fb higher than V 0,ref voltage source 21 (V drive ), such voltage source 21 is not specifically dedicated to the method described herein; in other words, the voltage source 21 is a normal component of the module that is also active during conventional operation of the module. drive )and, For example, a current source 22 (I g )and, a control unit 23 configured to start and stop the current source 22 via a control line CTRL2; voltage measuring means; a computing unit 24 configured to perform a third series of operations III; Includes.

[0027] 5 shows an example of an implementation of the control circuit 2 and the module 1. For simplicity, a single MOS element 11 is shown in FIG. 5. However, instead of one MOS element 11, multiple MOS elements 11 may be connected in parallel. In this example, the control circuit 2 further comprises an analog-to-digital converter (ADC) 25 associated with the control unit 23 and a switch 26 configured to control the powering of the MOS element 11 by the current source 22 and controlled by the control unit 23 via a control line CTRL2.

[0028] Electrical isolation may also be provided between the switch 26 and the ADC 25, and / or between the ADC 25 and the control unit 23, and / or between the signal lines CTRL1 and CTRL2.

[0029] The first series of operations I is for example performed by the control circuit 2 and is driven in particular by its control unit 23. The control unit 23 may include a central processing unit (CPU) and / or a logic port and / or a field programmable gate array (FPGA).

[0030] The first series of operations I a. Positive current I from the emitter / source to the gate of module 1 g,ref and injecting an initial gate-emitter / source voltage V 0,ref is the flat band voltage V fb and b. The voltage V across the current source ig,ref Measuring (t); c. The voltage of module 1 is the flat band voltage V fb When the current I g,ref and stopping the infusion of Includes.

[0031] In one embodiment, in which the first series of operations I is performed by the control circuit 2, the voltage V across the current source ig,ref The measurement of (t) is performed by a voltage measuring means. The current I g,ref The condition can be monitored and detected by the control unit 23 via the ADC 25 of the control circuit 2, or a condition can be imposed for a certain time, for example 2 μs, before stopping the injection of . The condition is met (the voltage of the module 1 reaches the flat band voltage V fb , the control unit 23 sends a control signal to the switch 26 of the control circuit 2 to close the switch 26 so that the current source 22 stops supplying power to the MOS device 11 .

[0032] The first series of operations I is performed at a known average temperature of module 1, for example the maximum nominal average temperature of module 1 during its operation, thereby allowing a measurement value of said average temperature to be obtained. In the following example, the average temperature is 135°C. This temperature is adapted depending on the functionality and operating conditions (application and design) of each architecture of module 1. Optionally, the first series of operations can be repeated at different known average temperatures of module 1 in order to obtain multiple sets of measurements, each related to a known average temperature.

[0033] Thereafter (or before), a second series of operations II is performed. The second series of operations II is substantially similar to the first series I, but is performed while the MOS devices are in an unknown state, or at least during an operating state where the temperature non-uniformity within module 1 is desired. Preferably, the average temperature of module 1 is known.

[0034] The second series of operations II d. A positive current I flows from the emitter / source of module 1 to the gate. g,op (Typically, the injection current I of the first series I g,ref (equal to the gate-emitter / source initial voltage V 0,op is the flat band voltage V fb and e. Voltage V across the current source ig,op Measuring (t); f. The voltage of module 1 is the flat band voltage V fb When the current I g,op and stopping the infusion of Includes.

[0035] In one embodiment, in which the second series of operations II is performed by the control circuit 2, the voltage V across the current source ig,op The measurement of (t) is performed by a voltage measuring means. The current I g,op The condition can be monitored and detected by the control unit 23 via the ADC 25 of the control circuit 2, or a certain time, e.g., 2 μs, can be imposed before stopping the injection. fb , the control unit 23 sends a control signal to the switch 26 of the control circuit 2 to close the switch 26 so that the current source 22 stops supplying power to the MOS device 11 .

[0036] During the second series of operation II, during the operation of the MOS device, especially at the maximum operating point, the junction temperature may vary on a particular power semiconductor surface or on multiple dies in parallel. Therefore, the measured voltage V across the current source ig,op (t) differs from the measurements taken during the first series of operations I. In other words, the waveforms as a function of time t are not equally shaped.

[0037] The operation of the module 1 can be driven by a central processing unit (CPU), preferably the same one as during the first series of operations I, such as the control unit 23 of the control circuit 2 .

[0038] Then, the third series of operations III: g. The voltage V measured during one first series I ig,ref (t) and the voltage V measured during one second series II ig,op (t) and h. From the comparison, the temperature variance T across module 1 j,dev and estimating Includes.

[0039] The third series of operations III is performed by a processing unit, for example, the calculation unit 24 of the control circuit 2. In the examples described here, the calculation unit 24 is considered to be separate from the control unit 23 (see FIG. 5 ) in order to better understand their respective functions. In some embodiments, the calculation unit 24 may be part of the control unit 23 (integrated into the control unit 23) or may be structurally the same component, particularly in embodiments in which isolation is provided between the control unit 23 and the ADC 25.

[0040] Voltage V ig,ref (t) and voltage V ig,opThe comparison of (t) is preferably made against a similar or close average temperature of the module 1. The objective is to identify variations in the acquired voltage given temperature gradients between the power semiconductor elements 11 or within the individual power semiconductor elements of the module 1. FIG. 6 shows an example of such a comparison. In the example of FIG. 6, the graph shows the difference in voltage (|V ig,ref (t)-V ig,op (t)|) as a function of time (t). In the example, all curves correspond to an average temperature of the module 1 of 130°C, and each curve corresponds to a temperature gradient between the power semiconductor elements 11 (here, from 0°C to 20°C in steps of 2°C).

[0041] In one example, the junction temperature dispersion T j,dev The estimation of voltage V ig,ref (t) and V ig,op (t) multiplied by a predetermined coefficient K, e.g., K=11800°C / V, calculated from simulations of the flat-band behavior. This is shown in Figure 7.

[0042] The graphical representation of the comparison in FIG. 7 is merely an example to aid the reader in understanding, and the method is not limited to any particular method of performing such a comparison; the comparison may be made solely by measured numerical data and / or graphical analysis.

[0043] The temperature distribution in a semiconductor region or in an array of parallel-connected semiconductor elements 11 can be estimated using a unique indicator (the voltage across a current source). No individual access is required. Furthermore, the estimation is performed in the most critical operating conditions.

[0044] Voltage V ig,ref (t) and V ig,op The comparison of (t) is preferably carried out with respect to a similar or similar average temperature of the module 1. To ensure this, each of the at least one first series I and the at least one second series II is i. Average temperature of module 1 T av,ref and T av,op and further obtaining the

[0045] The second series II is the average temperature T obtained during at least one first series. av,ref and the average temperature T obtained during the second series av,op The difference between the two is a predetermined value ΔT lim This is repeated until the following occurs:

[0046] For example, the average temperature can be determined as a function of the internal gate resistance using a TSEP-based method known per se. Such a method is described in [1]. The voltage V at the first instant t1 after current injection, e.g., 500 ns after current injection, is ig,ref (t) or V ig,op The measurement at (t) represents the average junction temperature. In fact, the initial voltage immediately after current injection is g,in This method is known to represent the average junction temperature. V ig,ref (t1) or V ig,op (t1) can be correlated to the junction temperature between the first series I and the second series II.

[0047] Advantageously, the temperature non-uniformity is calculated without knowing the operating point of the power semiconductor. g By using the above, a specific circuit is sufficient to measure the average and variance of the junction temperature within a specific power semiconductor or within a parallel power semiconductor element 11.

[0048] In some embodiments, V ig,ref The first series of operations I to obtain (t) is performed when module 1 is in a reference state and not in an operational situation (typically in a laboratory, in a production calibration phase, or in a maintenance state). The first series I is used to measure V under various temperatures. ig,refTo obtain measurements of (t), it can be repeated (N times) at different temperatures. In such conditions, the temperature is independent of the operating conditions and can be selected / driven. For example, an external heating element such as a heating plate can be disposed in the vicinity of the module 1. In another example, the temperature of a heat sink to which the power die is attached can be selected / driven.

[0049] When the first series of operations I is performed in a non-operating state, the temperature variance is estimated with good accuracy for any average temperature during use of the power module.

[0050] This is shown in Figure 8. In the first loop 81, V ig,ref is the first average temperature T av,ref,y The temperature is measured in the situation where it is known that T is uniform in module 1 (module 1 is offline). This means that it is the same at each junction of module 1 (T av,ref,y =T j1,dev =T j2,dev =...=T jN,dev ). Then each average temperature T av,ref,y+N for different average temperatures T av,ref,y+1 The loop is repeated for Next, in substep 82, the average temperature T av,op is determined using, for example, a TSEP-based method as a function of the internal gate resistance. Next, the voltage across module 1, V ig,op Measurement of (t) is performed (operation e corresponding to 83 in FIG. 8). Next, preferably, the determined average temperature T av,op The average temperature closest to T av,ref,y The reference voltage V obtained ig,ref (operation g corresponding to 84 in FIG. 8). Then, the temperature variance T across module 1 is calculated as the minimum of the product of the coefficient K and the difference between the two voltages. j,dev (T j,dev =K·max(|V ig,op -V ig,ref|)) (operation h corresponding to 85 in FIG. 8).

[0051] In some other embodiments, V ig,ref The first series I of operations to obtain (t) is performed when module 1 is in a reference state during operating conditions, early in its use, e.g., before reaching a predetermined number of years of operation for module 1. By way of example only, the predetermined number of years of operation can be set as a percentage of the target / nominal life limit (strictly less than 100%, e.g., 5%, 10%, or 20%), or as a number of hours, such as 1000 hours, 2000 hours, or 10,000 hours, depending on the module, operating conditions, and / or target safety level. The first series I is performed to obtain V under various temperatures. ig,ref This can be repeated (N times) at different temperatures to obtain a measurement of (t). In this condition, a set of measurements for different known temperatures can be obtained.

[0052] Here, the "initial stage" is defined as the number of hours of operation. In such a case, a counter is installed in the control unit 23, which allows defining a time limit for the first series to be performed. In our example, this number is set as 100 hours. Within this time, no degradation occurs on the power semiconductor packaging (module 1) and the temperature of the power semiconductor elements is considered uniform by design. Those skilled in the art will be able to adapt such a limit taking into account the context.

[0053] When the first series of operations I is performed at an early stage of the operating condition, it is possible to extract the temperature non-uniformity fluctuations during operation when the power semiconductor elements are degraded. Furthermore, an optional commissioning phase is required before the power semiconductors are put into use. As a result, V is used as a reference. ig,ref (t) is generated during on-site application, reducing manufacturing complexity.

[0054] In some embodiments, the third series III, prior to comparison, g'. The voltage V measured during at least one first series I ig,ref For the waveform of (t), the voltage V measured during at least one second series II ig,op (t) in terms of time and offset.

[0055] This behavior can be explained by the principle that the flatband voltage varies in time and voltage amplitude depending on the drain-source voltage and / or average temperature. However, it does not affect the shape of the waveform. An example of an algorithm for performing offsets and time shifts is shown in Figure 9. The algorithm searches for the moment t3 at which the waveform has the same amplitude for the first time. To this end, the algorithm first calculates, in step 91, the V ig,op (t0), V ig,ref (t0) and proceed to step 92 or 93 accordingly to search for the voltage at which Vx(t0) is equal to Vy(t3). ig,op and Vy is V ig,ref and vice versa in step 93). Therefore, the time delay t3 is ig,op (t0)=V ig,ref The algorithm then proceeds to step 94 where the amplitude offset is removed. The offset is then calculated by subtracting V from V ig,ref (t) is defined as the voltage difference at time t2, located in the middle of the waveform plateau, e.g., 1 μs. If this offset is small enough, e.g., 4 mV, the algorithm has converged the waveform; if not, the algorithm returns to step 91. The algorithm can be stopped after multiple iterations; experiments have shown that five iterations are sufficient. Figures 10 and 11 show the measured voltage V before and after the adjustment operation, respectively. ig,op (t) is a graph representation of the function Adj(V ig,op In these figures, V ig,op (t) and V ig,refThe difference between Adj(V) and Adj(V) is obtained at different bus voltages and average junction temperatures in the absence of non-uniformities. As will be demonstrated, this adjustment allows for the removal of offsets and delays introduced by external factors such as average temperature or drain-source voltage. Since temperature non-uniformities only change the shape of the waveform, "Adj(V)" is a useful tool for determining the offset and delay. ig,op (t))" and V ig,op The difference between (t) yields the same difference as shown in Figure 6, and the result is utilized in Figure 7 by taking the maximum value. The variation obtained after adjustment as a function of the standard deviation of the junction temperature is shown in Figure 12. In this example, the coefficient K = 1650 °C / V can be used to obtain the temperature gradient.

[0056] In some embodiments, V ig,ref A single measurement of (t) is taken. An arbitrary average junction temperature is determined. This reduces the time required for post-manufacture calibration of the module.

[0057] In some embodiments, each first series I is executed when the power delivered by module 1 is below a predetermined limit below the nominal maximum load of module 1. By way of example only, the predetermined limit can be set as a percentage of the target / nominal maximum load (strictly less than 100%, e.g., 5%, 10%, or 20%). In various embodiments, the limit condition is set as a maximum allowed power dissipation, such as 5%, 10%, or 20% of the nominal maximum power dissipation, depending on the module, operating conditions, and / or target safety level. Combinations of such limits can be implemented. For example, the predetermined condition can be set in control unit 23 to: ig,ref The acquisition of (t) can be triggered. The following conditions give good results: The power semiconductor device is not switching and has a non-zero drain-source voltage, V ds , or a non-zero collector-emitter voltage V ce exists across the power semiconductor element, or When a non-zero drain-source or collector-emitter voltage exists across the power semiconductor devices and the last device is switching, a small collector-emitter current I ce or a small drain-source current I ds flows through the power semiconductor element.

[0058] V ce or V ds Measure the voltage V ig,ref (t) can be stored in a table linked to the V ig,ref V ce or V ds When the value is equal to or close to the value of the variable, a comparison (operation g) can be made.

[0059] Advantageously, the voltage V ce and voltage V ds The sensitivity of the flatband voltage to the gate oxide can be compensated for, and the flatband degradation caused by charge buildup on the gate oxide is also compensated for.

[0060] {theory} Flat band voltage V fb represents the voltage applied to the gate when there are no charges in the oxide or at the oxide-semiconductor interface that would result in flat-band energy in the semiconductor. The voltage is the difference between the work function of the gate metal and the work function of the semiconductor. The work function is the voltage required to pull an electron from the Fermi energy to the vacuum level. This voltage separates the accumulation mode from the depletion mode of the MOS (metal-oxide-semiconductor) structure. During accumulation mode, the MOS capacitance C is related only to the oxide capacitance. During depletion mode, the MOS equivalent capacitance is the sum of the oxide capacitance and the variable capacitance of the depletion layer, C eq It is a series connection with.

[0061] In operation, power semiconductors are typically connected to a positive voltage V ge (e.g., 15V) and negative voltage V ge The diodes are operated by a master controller that alternates between an on-state mode and an off-state mode by applying a voltage (e.g., -15V) to the diodes, respectively.

[0062] Here, the temperature dispersion is determined by the voltage V that the MOS capacitor experiences when it is at a voltage higher than the MOS flat band voltage (for example, about -2V). ge and a low amplitude current source (e.g., 1 mA to 100 mA) supplies a voltage V ge The flat-band voltage V varies between the power semiconductor reference and a known range, typically contained within, for example, -10V to -3V. fb This is measured by considering the change in gate-emitter voltage behavior when discharging a MOS capacitor until the gate-emitter voltage drops below . The discharge characteristic can be seen in Figure 13, where the IGBT voltage V ge The flat-band characteristic can be seen in Figure 1. The discharge of a MOS capacitor shows a plateau in the flat-band voltage, which is easily identifiable and depends on the junction temperature. The flat-band voltage V fb and junction temperature T j This particular relationship between the temperature variance T as a function of the voltage variance j,dev This allows us to estimate

[0063] The flat band voltage V of the die (or any semiconductor device) fb To determine the input impedance of the power semiconductor device, the equivalent capacitor C eq Therefore, the charge Q injected into the gate of the power semiconductor device t Since the amount of (see equation (1)) is controlled and proportional to the equivalent capacitance (see equation (2)), the current source I g It is advantageous in this method to use

number

[0064] Q n is the charge stored in the nth semiconductor, t0 is the initial time, and t is the current time. The equivalent capacitor C eq depends on each flat band voltage Vnfb, so the voltage V igMeasurement of the voltage V obtained at a uniform temperature allows us to determine the equivalent capacitor coefficient at each instant of time t. ig and the voltage V obtained in the unknown state. ig By comparing with the flat band voltage V fb Therefore, to extract the flat-band nonuniformity related to the temperature nonuniformity, we can determine the variation of V ig A method for investigating the variation of is proposed here. [Industrial Applicability]

[0065] The technical solution presented in this specification is used to estimate the junction temperature dispersion (temperature non-uniformity) of at least one MOS type power semiconductor or parallel-connected MOS type power semiconductors by using a flatband voltage measurement method on the parallel gate / source-emitter accesses of the parallel power elements to identify the individual flatband voltage signatures and thus estimate the individual junction temperatures.Since the flatband voltage signatures are also affected by the operating points (e.g., drain-source / collector-emitter voltages) of the power semiconductor elements, the individual temperatures are estimated in relative values.

[0066] Advantageously, the temperature distribution within a semiconductor region or an array of semiconductors connected in parallel can be estimated using an intrinsic indicator (the voltage across a current source), thus eliminating the need for any individual access.

[0067] The present disclosure is not limited to the methods, modules, components, and computer software described herein, which are merely examples, and the present invention encompasses all alternatives that one skilled in the art would contemplate upon reading this document. [Explanation of symbols]

[0068] 1: Module 2: Control circuit 11: Element 21: Voltage source 22: Current source 23: Control unit 24: Computational unit 25: Analog-to-Digital Converter (ADC) 26: Switch 81: Loop 82: Substep 83: Operation 84: Operation 85: Operation

Claims

1. 1. A method of measurement for estimating the temperature of a power semiconductor module comprising a single metal-oxide semiconductor, a single metal-insulator semiconductor, or a set of parallel-connected metal-oxide semiconductors or metal-insulator semiconductors, said method comprising: a. A positive current I flows from the emitter / source of the power semiconductor module to the gate. ｇ，ｒｅｆ and injecting an initial voltage V between the gate and the emitter / source of the power semiconductor module. ０，ｒｅｆ is the flat band voltage V ｆｂ and b. The voltage across the current source, V ｉｇ，ｒｅｆ (t) and c. The voltage of the power semiconductor module is the flat band voltage V ｆｂ When the current I ｇ，ｒｅｆ and stopping the infusion of at least one first series of operations while the power semiconductor module is in a reference state, d. A positive current I flows from the emitter / source of the power semiconductor module to the gate. ｇ，ｏｐ and injecting an initial voltage V between the gate and the emitter / source of the power semiconductor module. ０，ｏｐ is the flat band voltage V ｆｂ and e. Voltage V across the current source ｉｇ，ｏｐ (t) and f. The voltage of the power semiconductor module is the flat band voltage V ｆｂ When the current I ｇ，ｏｐ and stopping the infusion of at least one second series of operations while the power semiconductor module is in an operational state, Next, g. The voltage V measured during one of the first series ｉｇ，ｒｅｆ (t) and the voltage V measured during one of the second series ｉｇ，ｏｐ (t) and h. From the comparison, the temperature dispersion T across the power semiconductor module ｊ，ｄｅｖ and estimating at least one third series of operations, including A method comprising:

2. Each of the at least one first series and the at least one second series comprises: i. The average temperature T of the power semiconductor module ａｖ，ｒｅｆ and T ａｖ，ｏｐ and further comprising obtaining The second series may include at least one of the average temperatures T obtained during the first series. ａｖ，ｒｅｆ and the average temperature T obtained during the second series ａｖ，ｏｐ The difference between ｌｉｍ The method of claim 1 is repeatedly performed until:

3. The first series of pluralities have different average temperatures T ａｖ，ｒｅｆ，ｎ It is executed with the first series is performed during a state different from an operating state of the power semiconductor module; The method of claim 2.

4. The first series of pluralities have different average temperatures T ａｖ，ｒｅｆ，ｎ It is executed with each of the first series is performed during a reference and operational state of the power semiconductor module and before a predetermined operational deadline in the operation of the power semiconductor module is reached; The method according to any one of claims 1 to 3.

5. The third series, prior to the comparison, g'. The voltage V measured during at least one of the first series ｉｇ，ｒｅｆ For the waveform of (t), the voltage V measured during at least one of the second series ｉｇ，ｏｐ (t) in time and offset The method of any one of claims 1 to 3, further comprising:

6. 6. The method of claim 5, wherein each of the at least one first series is executed when the power transmitted by the power semiconductor module is below a predetermined limit that is below a nominal maximum load of the power semiconductor module.

7. 4. A power semiconductor module comprising a single metal oxide semiconductor, a single metal insulator semiconductor, or a set of parallel-connected metal oxide semiconductors or metal insulator semiconductors, and comprising control circuitry configured to perform the method of any one of claims 1 to 3.

8. Computer software comprising instructions for carrying out the method of any one of claims 1 to 3 when said computer software is executed by a processor.

9. A computer-readable, non-transitory recording medium having stored thereon software which, when executed by a processor, performs the method of any one of claims 1 to 3.

Images