Optical semiconductor element and manufacturing method thereof

Abstract

To provide an optical semiconductor element with improved efficiency. [Solution] An optical semiconductor element comprising a semiconductor laminate having at least one semiconductor laminate structure in which an active layer and a tunnel junction layer are laminated, and a first n-type electrode and a second n-type electrode sandwiching the semiconductor laminate, wherein the tunnel junction layer is composed of a p-type InAlAsSbP layer and an n-type InAlAsSbP layer lattice-matched to InAs, and the central emission wavelength is 2000 nm to 5000 nm.

Description

[Technical Field]

[0001] The present invention relates to an optical semiconductor element and a method for manufacturing the same. [Background technology]

[0002] Optical semiconductor devices are known that have two or more vertically stacked active layers with a tunnel junction layer sandwiched between them. Such optical semiconductor devices are used as light-emitting devices to improve optical output when the wavelengths of the stacked active layers are close, or to emit different wavelengths when the wavelengths of the stacked active layers are separated. Similarly, they are used as light-receiving devices to improve light-receiving efficiency when the wavelengths of the stacked active layers are close, or to have sensitivity to different wavelength bands when the wavelengths of the stacked active layers are separated.

[0003] In such optical semiconductor devices, multiple active layers are stacked vertically, so that the active layers are connected in series. In light-emitting devices, when a forward current flows through them, each of the multiple active layers can emit light. In this case, the active layers are generally pn junctions.

[0004] Normally, when the junctions are made in the order of n-type, p-type, n-type (or p-type, n-type, p-type), a thyristor is formed and no current flows. However, because the tunnel junction layer is highly doped, reverse current flows within the tunnel junction layer, allowing current to flow. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special table number 2009-522755 [Patent Document 2] Patent Publication No. 2018-201009 [Patent Document 3] JP 2001-36141 A Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 describes that only Al, Ga, In, and P are preferable as basic constituent materials of the crystal lattice that constitutes the optical semiconductor element, but the wavelength of the element obtained with these materials is red to green with a wavelength of 890 nm or less, and infrared emission cannot be expected. Also, as described in Patent Document 2, conventionally, the concentration of n-type dopant is 1.0 × 10 19 atoms / cm 3 Although a high concentration of dopant or more is considered desirable, if an n-type semiconductor layer and a p-type semiconductor layer containing a high concentration of dopant are present between vertically stacked active layers, the dopant may diffuse into the active layer, potentially causing a decrease in reliability.

[0007] Patent Document 3 discloses a diode element having an electrode on each n-type semiconductor of the npn junction (or each p-type semiconductor of the pnp junction) in an npn junction (or pnp junction) InP-matched semiconductor light-emitting layer. However, there is no description that it can be applied to light-emitting elements of InAs-matched or GaSb-matched systems, and Patent Document 3 aims to enable current to emit light regardless of whether the polarity of the voltage applied to the diode element is positive or negative.

[0008] In recent years, there has been a demand for further improvements in the light-emitting efficiency or light-receiving efficiency of light-emitting or light-receiving elements in InAs-matched or GaSb-matched systems. The present invention has been made in view of this situation, and an object of the present invention is to improve the efficiency of optical semiconductor elements. [Means for solving the problem]

[0009] The present inventors have intensively investigated ways to solve the above problems and have found an optical semiconductor device and a method for manufacturing the same, which is a diode device including at least one active layer and a tunnel junction layer, with n-type electrodes on the uppermost and lowermost n-type semiconductor layers of the npn junction, and the tunnel junction layer including a p-type InAlAsSbP layer and an n-type InAlAsSbP layer, and have completed the present invention.

[0010] (1) a semiconductor laminate having at least one semiconductor laminate structure in which an active layer and a tunnel junction layer are laminated; a first n-type electrode and a second n-type electrode that sandwich the semiconductor laminate; Equipped with the tunnel junction layer is composed of a p-type InAlAsSbP layer lattice-matched to InAs and an n-type InAlAsSbP layer; The central emission wavelength is 2000 nm to 5000 nm. Optical semiconductor element.

[0011] (2) The tunnel junction layer has a dopant concentration of 1.0×10 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm 3 The optical semiconductor element according to (1) above, wherein the optical semiconductor element has a thickness of less than 100 nm.

[0012] (3) the p-type InAlAsSbP layer is located on the active layer side of the tunnel junction layer; a p-type electron blocking layer between the active layer and the tunnel junction layer; The optical semiconductor element according to (1) or (2) above, wherein the total thickness of the layers between the active layer and the tunnel junction layer is 100 nm or less.

[0013] (4) a first semiconductor laminated structure in which a first active layer and a first tunnel junction layer are laminated; a semiconductor laminate including a second semiconductor laminate structure in which a second active layer and a second tunnel junction layer are laminated; a first n-type electrode and a second n-type electrode sandwiching the semiconductor laminate; the first tunnel junction layer and the second tunnel junction layer are each made of a p-type InAlAsSbP layer and an n-type InAlAsSbP layer lattice-matched to InAs, The central emission wavelength is 2000 nm to 5000 nm. Optical semiconductor element.

[0014] (5) The first tunnel junction layer and the second tunnel junction layer have a dopant concentration of 1.0×10 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm 3 The optical semiconductor element according to (4) above, wherein the optical semiconductor element has a thickness of less than 100 nm.

[0015] (6) The optical semiconductor element according to (4) or (5) above, wherein the first active layer and the second active layer have a quantum well structure, and the first wavelength and the second wavelength emitted by the first active layer and the second active layer, respectively, are the same as or similar to each other.

[0016] (7) the p-type InAlAsSbP layer is located on the first active layer side of the first tunnel junction layer; a p-type electron blocking layer between the first active layer and the first tunnel junction layer; The optical semiconductor element according to any one of (4) to (6) above, wherein the total thickness of the layers between the first active layer and the first tunnel junction layer is 100 nm or less.

[0017] (8) the n-type InAlAsSbP layer is located on the second active layer side of the first tunnel junction layer; a spacer layer between the first tunnel junction layer and the second active layer; The optical semiconductor element according to any one of (4) to (7) above, wherein the total thickness of the layers between the first tunnel junction layer and the second active layer is 100 nm or less.

[0018] (9) forming a semiconductor laminate having at least one semiconductor laminate structure in which an active layer and a tunnel junction layer are laminated on an n-type substrate; forming a first n-type electrode and a second n-type electrode; Including, The step of forming the tunnel junction layer includes Note forming an n-type InAlAsSbP layer on a p-type InAlAsSbP layer lattice-matched to InAs; A method for producing an optical semiconductor element having a central emission wavelength of 2000 nm to 5000 nm.

[0019] (10) The tunnel junction layer has a dopant concentration of 1.0×10 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm 3 The method for producing an optical semiconductor element according to (9) above, wherein the [Effects of the Invention]

[0020] It is possible to provide an optical semiconductor element with improved efficiency and a method for manufacturing the same. For example, when used as a light-emitting element, it is possible to provide an optical semiconductor element with high optical output (Po), a lower forward voltage (Vf) than conventional elements, improved luminous efficiency (WPE), and an emission central wavelength of 2000 nm to 5000 nm, and a method for manufacturing the same. When used as a light-receiving element, it is possible to provide an optical semiconductor element with high light conversion efficiency (light-receiving efficiency), and a method for manufacturing the same. [Brief explanation of the drawings]

[0021] [Figure 1] 1 is a cross-sectional view illustrating a first embodiment of an optical semiconductor element according to the present invention. [Figure 2] FIG. 3 is a cross-sectional view illustrating a second embodiment of an optical semiconductor element according to the present invention. [Figure 3] 5A to 5C are cross-sectional views illustrating an example of a method for manufacturing the second embodiment of the optical semiconductor element according to the present invention. [Figure 4] FIG. 4 is a schematic cross-sectional view illustrating an example of a manufacturing method following FIG. 3. [Figure 5] FIG. 5 is a schematic cross-sectional view illustrating an example of a manufacturing method following FIG. 4. [Figure 6] FIG. 4 is a cross-sectional view illustrating a third embodiment of an optical semiconductor element according to the present invention. [Figure 7] 10 is a graph showing the results of measuring the diffusion state of Si ions and Te ions in Example 3 by secondary ion mass spectrometry (SIMS). [Figure 8]10 is a graph showing the results of measuring the diffusion state of Zn ions in Example 3 by secondary ion mass spectrometry (SIMS). [Figure 9] 10 is a graph showing the results of measuring the diffusion state of Te ions in Comparative Example 2 by secondary ion mass spectrometry (SIMS). [Figure 10] 10 is a graph showing the results of measuring the diffusion state of Zn ions in Comparative Example 2 by secondary ion mass spectrometry (SIMS). DETAILED DESCRIPTION OF THE INVENTION

[0022] Prior to describing the embodiments according to the present invention, the following points will be explained in advance.

[0023] In this embodiment, InAlAsSbP, which is lattice-matched to InAs, means that a small amount of Al, Sb, or P may be contained in InAs within the range of lattice matching to InAs. For example, it is InAlAsSb or InAsSbP, and most preferably InAs. Let the composition ratios of Al and Sb be a and b, respectively. 1-a Al a As 1-b Sb b For example, if 0≦a≦0.2 and 0≦b≦0.2, and the composition ratios of Sb and P are b and c, respectively, then InAs 1-b-c Sb b P c For example, 0≦b≦0.1 and 0≦c≦0.2. In this embodiment, the active layer containing Sb is InAs x Sb 1-xIt shall mean a compound also denoted as (0 < x < 1). When denoted as an InAs layer, an AlInAs layer, or an InAsP layer, it means that Sb is not included in the composition ratio, but it is only necessary that Sb source gas is not used during the growth of the layer, and it is acceptable that Sb is included as an inevitable dopant element due to the residual Sb in the chamber or diffusion from an adjacent layer containing Sb. Also, when simply denoted as "AlInAsSb" without specifying the composition ratio in this specification, it shall mean an arbitrary compound in which the chemical composition ratio of group III elements (total of Al and In) to group V elements (total of As and Sb) is 1:1, and the ratios of Al and In as group III elements and the ratios of As and Sb as group V elements are each indefinite. In this case, it shall include the case where either one of Al and In as group III elements is not included, and also the case where either one of As and Sb as group V elements is not included. The component composition ratios of each III-V group element of AlInAsSbP can be measured by photoluminescence measurement, X-ray diffraction measurement, etc.

[0024] In this specification, when specific dopants such as Zn, Te, Si, etc. are not intentionally added, it is referred to as "i-type" or "undoped". An undoped layer may have inevitable dopant contamination during the manufacturing process. Specifically, when the dopant density is low and close to the detection limit in SIMS analysis (secondary ion mass spectrometry) (for example, less than 4×10 16 / cm 3 ), it is regarded as "undoped" and shall be handled as such in this specification.

[0025] The III-V group compound semiconductor in this embodiment shall include at least any one of Al, Ga, In as group III elements and at least any one of P, As, Sb as group V elements.

[0026] The thickness of each layer formed by epitaxial growth can be calculated from cross-sectional observation of the grown layer using a scanning electron microscope (SEM) or a transmission electron microscope (TEM). It is preferable to use an SEM when the film thickness is 10 nm or more, and a TEM when the film thickness is less than 10 nm.

[0027] The values ​​of impurity concentrations of Zn, Te, Si, etc. are determined by SIMS analysis. If the SIMS profile has a peak (maximum value), the impurity concentration value of the layer corresponding to that position is taken as the peak value. For layers without such a peak, the dopant concentration value varies greatly near the boundaries of each semiconductor layer, so the dopant concentration value at the center of each layer in the thickness direction is taken as the dopant concentration value.

[0028] In this specification, the central wavelengths of the emission wavelengths of different active layers are compared, and the description is given assuming that the emission wavelengths are identical, but this is not limited thereto. The central wavelengths of the emission wavelengths may be distant from each other or may be similar to each other. When the central emission wavelengths are distant from each other, different roles can be assigned to each of the central emission wavelengths. In this specification, "the central emission wavelengths of the emission wavelengths are similar to each other" means that the central wavelengths are positioned such that at least a portion of the full width at half maximum range in the emission spectrum overlaps, and for example, this means that the wavelength difference is within the value of the full width at half maximum (e.g., within 100 nm). When the central emission wavelengths are identical or similar to each other, the emission spectra are combined, which is effective in improving the emission intensity. Although the above description is given in the case of a light-emitting element, the same applies to a light-receiving element.

[0029] The optical semiconductor device according to the present invention comprises a semiconductor stack having at least one active layer and at least one tunnel junction layer, a first n-type electrode, and a second n-type electrode. The tunnel junction layer includes a p-type InAlAsSbP layer (e.g., a p-type InAs layer) and an n-type InAlAsSbP layer (e.g., an n-type InAs layer), and the emission central wavelength is 2000 nm or more and 5000 nm or less. The number of active layers and the number of tunnel junction layers are preferably the same, and the active layers and tunnel junction layers are preferably stacked alternately. This allows regions of different conductivity types to be stacked in an npn, npnpn, npnpnpn, or npnpnpnpn. The top and bottom layers of the semiconductor stack are preferably both n-type and serve as n-type contact layers. The first n-type electrode and the second n-type electrode are preferably electrically connected to the first n-type contact layer and the second n-type contact layer, respectively. Since n-type conductivity layers are advantageous in terms of current flow, the total thickness of p-type conductivity layers, including the p-type tunnel junction layer, is preferably 500 nm or less. Furthermore, the value obtained by dividing the total thickness of the p-type conductivity layers by the number of active layers is preferably 200 nm or less, more preferably 130 nm or less. The total thickness of all layers (including the p-type electron blocking layer) between the active layer and the tunnel junction layer, excluding the p-type tunnel junction layer, is preferably 100 nm or less, more preferably 90 nm or less.

[0030] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the aspect ratio of the substrate and each layer is exaggerated from the actual ratio for the sake of convenience. Hereinafter, III-V compound semiconductors composed of three or more elements may be described in a form in which the composition ratio of each element is omitted (for example, "InAsSb").

[0031] (First embodiment) 1, an example of an optical semiconductor element 100, which is a first embodiment of an optical semiconductor element according to the present invention, will be described together with a manufacturing method. The optical semiconductor element 100 includes a growth substrate 105 and a semiconductor stack 120 that emits light when a current is applied. The semiconductor stack 120 is made up of multiple semiconductor layers stacked on the growth substrate 105. As will be described in detail later, the semiconductor stack 120 has a semiconductor stack structure in which (one) active layer and (one) tunnel junction layer are stacked. When a negative voltage is applied to a first n-type electrode 191 on the side opposite the tunnel junction layer side of the active layer, and a forward current flows between the active layer and the tunnel junction layer side (the p-type electron blocking layer 125 side), a current flows in the reverse direction (from the n-type layer to the p-type layer) in the tunnel junction layer due to the tunnel effect. Therefore, when a positive voltage is applied to a second n-type electrode 195 on the side opposite the active layer side of the tunnel junction layer, a current flows, and the optical semiconductor element 100 functions as a light-emitting diode. In addition, the optical semiconductor element 100 has a second n-type electrode 195 formed as an n-type ohmic electrode on the top of the semiconductor laminate 120 and a first n-type electrode 191 formed as a back surface electrode on the back surface of the growth substrate 105. Furthermore, the central emission wavelength of the optical semiconductor element 100 is not less than 2000 nm and not more than 5000 nm.

[0032] The first embodiment is an optical semiconductor device 100 in which a first n-type contact layer 121, a first n-type window layer 122, a spacer layer 123, an active layer 124, a p-type electron blocking layer 125, a p-type window layer 126, a tunnel junction layer 127 (a p-type tunnel junction layer 1271 and an n-type tunnel junction layer 1272), a second n-type window layer 128, and a second n-type contact layer 129 are sequentially formed on a growth substrate 105, and the growth substrate 105 is used as a substrate as is. Furthermore, the optical semiconductor device 100 has a first n-type electrode 191 formed on the back surface of the growth substrate 105 as a back surface electrode, and a second n-type electrode 195 formed on the top of the semiconductor laminate 120 as an n-type ohmic electrode.

[0033] <Substrate> A description will be given of a substrate applicable to the optical semiconductor element 100. The substrate used in the present invention may be any substrate having a thickness sufficient to mechanically maintain the shape of the semiconductor laminate 120 including the active layer 124 and the tunnel junction layer 127, and may be the growth substrate 105 used for epitaxial growth when forming the semiconductor laminate 120 of the optical semiconductor element 100.

[0034] <<Growth substrate>> The growth substrate 105 can be a compound substrate such as GaAs, InP, InAs, GaSb, or InSb. However, in the InAs-matched or GaSb-matched systems, GaAs or InP is lattice mismatched. To form an active layer containing Sb, it is ideal to use an InAs, GaSb, or InSb substrate. However, these substrates are expensive, so from a cost perspective, a GaAs substrate is preferable. The GaAs growth substrate 105 is preferably Si-doped to form an n-type substrate, and the semiconductor laminate 120 is preferably laminated on the (100) plane of the GaAs growth substrate 105. Furthermore, the thickness of the GaAs growth substrate 105 is preferably 200 μm or more and 900 μm or less.

[0035] When a substrate that is lattice-mismatched with the first n-type contact layer 121, such as a GaAs substrate or an InP substrate, is used as the growth substrate 105, it is preferable to provide a buffer layer between the growth substrate 105 and the first n-type contact layer 121 to alleviate the lattice mismatch. The buffer layer may include an InAs buffer layer grown at a low temperature. α Ga 1-α As β Sb 1-β The buffer layer may have a composition gradient in which the compositions α and β of the layers are varied within the range of 0 to 1, or may have a superlattice structure.

[0036] <<First n-type contact layer>> A first n-type contact layer 121 made of a III-V compound semiconductor layer may be provided on the growth substrate 105. The first n-type contact layer 121 has high conductivity and is advantageous for forming an electrode. The thickness of the first n-type contact layer 121 is preferably 20 nm or more and 500 nm or less. Dopants that can be used here include Si, Te, S, Ge, Sn, Se, etc. The dopant concentration of the first n-type contact layer 121 is preferably higher than the dopant concentration of the first n-type window layer 122, which will be described next, and is preferably 8.0×10 18 / cm 3 Over 3.0 x 10 19 / cm 3 It is more preferable that the composition of the first n-type contact layer 121 is, for example, InAs.

[0037] <<First n-type window layer>> A first n-type window layer 122 made of a III-V compound semiconductor layer may be provided on the first n-type contact layer 121, and its thickness is preferably 500 nm to 6000 nm. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se. When the thickness of the first n-type window layer 122 is 500 nm or more, defects are less likely to propagate to the active layer 124, even if the lattice constants of the growth substrate 105 and the active layer 124 differ. Additionally, when the thickness of the first n-type window layer 122 is 500 nm or more, a sufficient number of carriers are supplied to the active layer 124, resulting in increased light emission output. Furthermore, by setting the thickness of the first n-type window layer 122 to 6000 nm or less, excess growth that does not significantly improve characteristics is suppressed, reducing raw material costs and contributing to improved productivity.

[0038] The dopant concentration of the first n-type window layer 122 is preferably lower than that of the first n-type contact layer 121, and is 1.0×10 18 / cm 3 Over 8.0 x 10 18 / cm 3 It is more preferable to set the following:

[0039] The composition of the first n-type window layer 122 is preferably a composition that is lattice-matched to the composition of the active layer 124. The composition of the first n-type window layer 122 is preferably AlInAs having a smaller Al composition ratio (i.e., a smaller bandgap) than the p-type electron blocking layer 125 described later, and more preferably InAs.

[0040] <<Spacer layer>> A spacer layer 123 made of an undoped III-V compound semiconductor layer may be provided on the first n-type window layer 122. The film thickness is preferably 1 nm or more and 100 nm or less, and more preferably 20 nm or more and 90 nm or less. The spacer layer 123 is preferably a layer having the same composition as the barrier layer of the active layer 124 or the first n-type window layer 122 and not doped with an n-type dopant. This spacer layer 123 reduces the amount of n-type dopant diffusing from the first n-type window layer 122 into the active layer 124. <000*********

[0041] <Active layer> The active layer 124 is provided on the spacer layer 123. The active layer 124 is an InAs layer that becomes a light-emitting layer. x1 Sb 1-x1 layer (0 < x1 < 1) may be included. In FIG. 1, the active layer 124 is an InAs y1 P 1-y1 layer (0 < y1 < 1) and further has an InAs x1 Sb 1-x1 layer as the well layer 124w of the active layer and an InAs y1 P 1-y1 layer as the barrier layer 124b of the active layer, and a quantum well structure is exemplarily illustrated. However, the active layer 124 is an InAs x1 Sb 1-x1Alternatively, the quantum well structure may have a single layer structure. The quantum well structure can have a minimum configuration of 1.5 pairs of the first barrier layer 124b, the well layer 124w, and the barrier layer 124b. The components other than Sb are not limited to In and As, and other III-V group compound semiconductors may be used. It is also preferable to adjust the composition difference between the active layer's well layer 124w and the active layer's barrier layer 124b to add strain to the well layer. The active layer 124 having a quantum well structure preferably has a multiple quantum well (MQW) structure with a large number of pairs, as shown in FIG. 1, to improve optical output by suppressing crystal defects. This multiple quantum well structure can be formed by alternately repeating the well layer 124w and the barrier layer 124b. When using a multiple quantum well structure, the number of pairs of well layer 124w and barrier layer 124b is preferably 3 to 40. That is, the number of pairs, including the first barrier layer 124b, is preferably 3.5 to 40.5. Furthermore, the thickness of each well layer 124w is preferably 5 nm or more and 40 nm or less, and the thickness of each barrier layer 124b is preferably 10 nm or more and 50 nm or less. The active layer 124 is preferably undoped. The above composition of the well layer 124w or the active layer 124 is preferably InGaAlAs x1 Sb 1-x1 By adjusting the composition ratio of Ga and Al as the active layer 124b, the central emission wavelength of the optical semiconductor element 100 can be set in the range of 2000 nm to 5000 nm. The central emission wavelength of the optical semiconductor element 100 is preferably 2100 nm to 4800 nm. It is more preferable that the central emission wavelength of the active layer 124 is 3000 nm or more. In addition to InAsP, AlInAs or the like can also be used for the barrier layer 124b.

[0042] <P-type intermediate layer between the active layer and the tunnel junction layer> There is a p-type intermediate layer between the active layer 124 and the tunnel junction layer 127. The film thickness of the entire layer (also referred to as the total film thickness) between the active layer 124 and the tunnel junction layer 127 described later is preferably 100 nm or less, and more preferably 20 nm or more and 90 nm or less. And this p-type intermediate layer preferably includes a p-type electron blocking layer 125. When there are a plurality of pairs of the active layer and the tunnel junction layer sandwiching the p-type intermediate layer, it is sufficient if each p-type intermediate layer satisfies the above film thickness range.

[0043] <p-type electron blocking layer> A p-type electron blocking layer 125 made of a III-V compound semiconductor layer may be provided on the active layer 124, and the film thickness is preferably 5 nm or more and 60 nm or less. Dopants that can be used here include Mg, Zn, C, Be, etc. Also, the p-type dopant concentration is 1.0×10 18 / cm 3 or more and 5.0×10 18 / cm 3 or less, which is preferable. This p-type electron blocking layer 125 is a layer that injects and confines carriers into the active layer 124. Also, the p-type electron blocking layer 125 has an effect of reducing the diffusion of the p-type dopant from the tunnel junction layer 127 described later to the active layer 124.

[0044] The composition of the p-type electron blocking layer 125 is preferably Al z1 In 1-z1 As (0.05 ≦ z1 ≦ 0.40), and more preferably Al z1 In 1-z1 As (0.10 ≦ z1 ≦ 0.35). By setting the Al composition z1 to 0.05 or more, the luminous efficiency by the p-type electron blocking layer 125 can be improved, and by setting it to 0.40 or less, it is possible to suppress the increase in the forward voltage and the decrease in the luminous efficiency. Also, the p-type dopant concentration of the p-type electron blocking layer 125 is preferably smaller than the p-type dopant concentration doped in the p-type tunnel junction layer 1271 described later.

[0045] <p-type window layer> A p-type window layer 126 may be further provided on the p-type electron blocking layer 125. The composition of the p-type window layer 126 preferably has a lower Al content than the composition z1 of the p-type electron blocking layer 125, and is more preferably InAs, for example. The p-type dopant concentration is 1.0×10 18 / cm 3 Over 5.0 x 10 18 / cm 3 It is preferable that:

[0046] The p-type intermediate layer between the active layer 124 and the tunnel junction layer 127 may include a layer other than the p-type electron blocking layer 125 or the p-type window layer 126. Even in this case, in the present invention, the dopant concentration in the tunnel junction layer 127 can be kept low, so that even if p-type dopant diffusion from the p-type tunnel junction layer 1271 occurs, the p-type dopant concentration in the p-type intermediate layer can be kept low, for example, at 5.0×10 18 / cm 3 Furthermore, it is preferable that the total thickness of all layers between the active layer 124 and the tunnel junction layer 127 be 100 nm or less. By making the thickness thin in this manner while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire device can be reduced.

[0047] <Tunnel junction layer> A tunnel junction layer 127 is formed on the p-type window layer 126. The tunnel junction layer 127 is composed of a p-type tunnel junction layer 1271 and an n-type tunnel junction layer 1272, which are lattice-matched to InAs. The n-type tunnel junction layer 1272 is deposited directly on the p-type tunnel junction layer 1271. As described above, the p-type tunnel junction layer 1271 is preferably a p-type InAlAsSbP layer, and the n-type tunnel junction layer 1272 is preferably an n-type InAlAsSbP layer. The p-type tunnel junction layer 1271 is preferably a p-type InAs layer, and the n-type tunnel junction layer 1272 is preferably an n-type InAs layer. The thickness of the tunnel junction layer 127 is preferably 10 nm to 200 nm. Dopants that can be used for the p-type tunnel junction layer 1271 include Mg, Zn, C, and Be, and dopants that can be used for the n-type tunnel junction layer 1272 include Si, Te, S, Ge, Sn, and Se. A p-type tunnel junction layer 1271 is located on the active layer 124 side of the tunnel junction layer 127. The film thickness and dopant concentration of the p-type tunnel junction layer 1271 and the n-type tunnel junction layer 1272 may be the same or different. Furthermore, the dopant concentration of the p-type tunnel junction layer 1271 and the n-type tunnel junction layer 1272 does not need to be uniform within the layer, and a concentration gradient may exist.

[0048] Normally, to form a tunnel junction, the doping rate of the semiconductor must be extremely high, and the depletion layer that occurs at the junction between the n-type and p-type semiconductor layers must be thin enough to allow quantum tunneling. For compound semiconductors, this requires a doping rate of at least 1.0 × 10 19 / cm 3 or more (preferably 1.0 × 10 20 / cm 3 However, in the present invention, a dopant concentration of 1.0×10 18 / cm 3 Over 1.0 x 10 19 / cm 3 The tunnel junction layer had a dopant concentration of 5.0 × 10 18 / cm 3 Over 9.0 x 10 18 / cm 3The following are more preferable. Since less diffusion of the dopant into the active layer 124 leads to improvement in characteristics such as reliability, if quantum tunneling can be caused, it is preferable that the dopant concentration in the tunnel junction layer 127 is low. Also, it is expected that when the dopant concentration is low and the resistance of the tunnel junction layer 127 during energization is high, the current reaching the active layer 124 will spread and the output will be improved. It is also expected that a lower dopant concentration will have the effect of improving the output due to a decrease in light absorption within the layer.

[0049] <<p-type tunnel junction layer>> The p-type dopant concentration in the p-type tunnel junction layer 1271 is 1.0×10 18 atoms / cm 3 or more and preferably less than 1.0×10 19 atoms / cm 3 and more preferably less than 9.0×1 0 18 atoms / cm 3 The film thickness is preferably 5 nm or more and 100 n m or less.

[0050] <<n-type tunnel junction layer>> The n-type dopant concentration in the n-type tunnel junction layer 1272 is 1.0×10 18 atoms / cm 3 or more and preferably less than 1.0×10 19 atoms / cm 3 and more preferably less than 9.0×10 18 atoms / cm 3 The film thickness is preferably 5 nm or more and 100 nm or less.

[0051] <<Second n-type window layer>> A second n-type window layer 128 made of a III-V compound semiconductor layer may be provided on the tunnel junction layer 127, and its thickness is preferably 500 nm or more and 2000 nm or less. Having the second n-type window layer 128 2000 nm or less allows the current to spread over an appropriate range of the LED chip. This not only suppresses surface recombination but also reduces the ohmic resistance of the device, thereby improving light emission efficiency. Furthermore, having the second n-type window layer 128 500 nm or more prevents light from being emitted only directly below the electrode, enabling efficient light extraction. Examples of dopants that can be used here include Si, Te, S, Ge, Sn, and Se. The dopant concentration of the second n-type window layer 128 is 1.0×10 18 atoms / cm 3 Over 5.0 x 10 18 atoms / cm 3 Preferably, it is 1.0 x 10 or less. 18 atoms / cm 3 Over 3.0 x 10 18 atoms / cm 3 It is more preferable that the dopant used is the same as that used in the n-type tunnel junction layer described above.

[0052] The dopant concentration of the second n-type window layer 128 is preferably lower than that of the second n-type contact layer 129, and is 1.0×10 18 / cm 3 Over 8.0 x 10 18 / cm 3 The composition of the second n-type window layer 128 is preferably a composition that is lattice-matched to the composition of the active layer 124. The composition of the second n-type window layer 128 is preferably AlInAs, which has a smaller Al composition ratio (i.e., a smaller band gap) than the aforementioned p-type electron blocking layer 125, and is more preferably InAs.

[0053] <<Second n-type contact layer>> A second n-type contact layer 129 made of a III-V compound semiconductor layer may be provided on the second n-type window layer 128. The thickness of the second n-type contact layer 129 is preferably 20 nm or more and 300 nm or less. The dopant concentration of the second n-type contact layer 129 is higher than that of the second n-type window layer 128, and is 1.0×10 18 atoms / cm 3 Over 3.0 x 10 19 atoms / cm 3 Preferably, it is 1.0 x 10 or less. 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm 3 It is more preferable that the composition of the second n-type contact layer 129 is, for example, InAs.

[0054] <1st n-type electrode and 2nd n-type electrode> A second n-type electrode 195 is provided on a portion of the second n-type contact layer 129. Furthermore, a first n-type electrode 191 is provided on the back surface of the growth substrate 105. The growth substrate 105 and the semiconductor stack 120 are sandwiched between the first n-type electrode 191 and the second n-type electrode 195. That is, the description of the first n-type electrode 191 and the second n-type electrode 195 sandwiching the semiconductor stack 120 does not limit the form in which the semiconductor stack 120 is directly sandwiched between them, but may also sandwich the semiconductor stack 120 via a substrate. Furthermore, the semiconductor stack 120 may be sandwiched in a form in which a mesa is formed in the semiconductor stack 120, and a portion of the first n-type contact layer 121 is exposed and the first n-type electrode 191 is provided thereon, thereby forming two electrodes on the top surface (flip-chip type). Here, the second n-type electrode 195 may include a wiring portion and a pad portion of an ohmic electrode. Although not shown, the pad portion may have a metal layer or solder for bonding. Known metal materials and methods for forming the first n-type electrode 191 and the second n-type electrode 195 can be used. Examples of metal materials that can be used include Ti, Pt, Au, Ag, Al, Zn, and Ni.

[0055] An example of an embodiment of the manufacturing method for the optical semiconductor device 100 described above will be described below. When the growth substrate 105 of the optical semiconductor device 100 is n-type or undoped, the active layer 124 and the tunnel junction layer 127 lattice-matched to InAs are epitaxially grown in this order. A p-type tunnel junction layer 1271 is located on the active layer 124 side of the tunnel junction layer 127. An n-type tunnel junction layer 1272 is formed on and in contact with the p-type tunnel junction layer 1271. The dopant concentration of the tunnel junction layer 127 is 1.0×10 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm 3 It is preferable that it is less than 10 ...

[0056] A p-type electron blocking layer 125 or a p-type window layer 126 having a total thickness of 100 nm or less may be formed between the active layer 124 and the tunnel junction layer 127. Furthermore, one or more layers selected from the group consisting of a first n-type contact layer 121, a first n-type window layer, and a spacer layer 123 may be formed between the growth substrate 105 and the active layer 124, and one or more layers selected from the group consisting of a second n-type window layer 128 and a second n-type contact layer 129 may be formed on the tunnel junction layer 127.

[0057] The semiconductor stack 120 is sandwiched between a second n-type electrode 195 on the second n-type contact layer 129 and a first n-type electrode 191 on the back surface of the growth substrate 105. The second n-type electrode 195 and the first n-type electrode 191 can be formed by, for example, vapor deposition.

[0058] Each semiconductor layer can be formed by epitaxial growth, for example, by a known thin film growth method such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). For example, a predetermined mixture ratio of trimethylindium (TMIn) as an indium source, trimethylgallium (TMGa) or triethylgallium (TEGa) as a gallium source, trimethylaluminum (TMAl) as an aluminum source, arsine (AsH) or tertiarybutylarsine (TBAs) as an arsenic source, trimethylantimony (TMSb), triethylantimony (TESb), or trisdimethylaminoantimony (TDMASb) as an antimony source, and phosphine (PH) or tertiarybutylphosphine (TBP) as a phosphorus source can be used. These source gases are vapor-phase grown using a carrier gas, allowing the desired thickness to be formed depending on the growth time. To dope each layer to p-type or n-type, a dopant source gas may be used as desired. For example, to dope with Zn, DEZn (diethylzinc) gas may be used. Note that InAs is also n-type even when undoped.

[0059] When a forward voltage is applied from second n-type electrode 195 to first n-type electrode 191, the forward voltage is applied to active layer 124, causing active layer 124 to emit light. At this time, a reverse voltage is applied to the tunnel junction (pn junction) in tunnel junction layer 127. As a result, a current also flows in the reverse direction in tunnel junction layer 127 due to the tunnel effect.

[0060] (Second embodiment) An optical semiconductor device 200 according to a second embodiment of the present invention will be described with reference to FIG. 2. The optical semiconductor device 200 is a bonded-type optical semiconductor device obtained by bonding a support substrate and then removing the growth substrate. In principle, components identical to those of the optical semiconductor device 100 are designated by the same reference numerals, the last two of which are three digits, and redundant explanations will be omitted. The optical semiconductor device 200 includes at least a support substrate 280, a metal bonding layer 279 and a metal reflective layer 271 provided on the surface of the support substrate 280, a transparent insulating layer 261 with a through-hole on the metal reflective layer 271, a power distribution unit 260 having an ohmic electrode portion as a second n-type electrode 295 provided in the through-hole, a semiconductor stack 220 provided on the power distribution unit 260, and a first n-type electrode 291 provided on a portion of the semiconductor stack 220.

[0061] The semiconductor laminate 220 in the optical semiconductor element 200 in FIG. 2 has, in order from the side opposite to the support substrate 280, a first n-type contact layer 221, a first n-type window layer 222, a spacer layer 223, an active layer 224, a p-type electron blocking layer 225, a p-type window layer 226, a tunnel junction layer 227, a second n-type window layer 228, and a second n-type contact layer 229.

[0062] The support substrate 280, which is different from the growth substrate, is preferably cheaper and has higher thermal conductivity than the growth substrate, and examples thereof include compound substrates such as Si, Ge, and GaAs, as well as metal substrates using metals that can suppress the thermal expansion coefficient, such as copper alloys, molybdenum, tungsten, and Kovar, and submount substrates in which metal is attached to a ceramic substrate such as AlN. From the standpoints of processability and cost, it is also preferable to use a Si substrate as the support substrate 280.

[0063] An example of an embodiment of the optical semiconductor element 200 and a manufacturing method thereof will be described in more detail below with reference to FIGS. 3 to 5. First, a growth substrate 205 is prepared. Then, with reference to FIG. 3, a semiconductor laminate 220 is formed. At this time, an etching stop layer (not shown) may be formed on the growth substrate 205. The semiconductor laminate 220 is similar to the semiconductor laminate 120 described above.

[0064] <Formation of power distribution section and second n-type electrode> A power distribution section 260 including a transparent insulating film 261 with a through-hole and an ohmic electrode section as a second n-type electrode 295 provided in the through-hole is formed on the second n-type contact layer 229. Any specific method may be used to form the power distribution section 260, but an example of a specific mode for forming the power distribution section 260 will be described below with reference to FIGS.

[0065] First, the transparent insulating layer 261 is formed on the semiconductor stack 220. Known techniques, such as plasma CVD or sputtering, can be used for the film formation. A resist pattern for the power distribution section 260 is then formed on the transparent insulating layer 261 using a photomask. Next, a portion of the transparent insulating layer 261 is removed by etching using the resist pattern to form a through-hole. The through-hole exposes a portion of the outermost surface of the semiconductor stack 220. An ohmic electrode portion serving as the second n-type electrode 295 is then formed, followed by lift-off using the resist pattern, thereby forming the power distribution section 260. The transparent insulating layer 261 and the second n-type electrode 295 are arranged in parallel in the power distribution section 260. For simplification, the second n-type electrode 295 is shown filling the through-hole, but this is not limiting; a gap may be formed between the transparent insulating layer 261 and the second n-type electrode 295.

[0066] The second n-type electrode 295 can be formed by dispersing islands in a predetermined pattern. For example, Au, AuZn, AuBe, AuTi, etc. can be used as the second n-type electrode 295, and it is also preferable to use a laminate structure of these. For example, Ti / Au can be used as the second n-type electrode 295. The film thickness (or total film thickness) of the second n-type electrode 295 is not limited, but can be, for example, 300 nm to 1300 nm, more preferably 350 nm to 800 nm.

[0067] <Formation of metal reflective layer> As shown in FIG. 4, it is also preferable to form a metal reflective layer 271 on the power distribution unit 260. The metal reflective layer 271 can include multiple metal layers, and the metal constituting the metal reflective layer 271 can be Al, Pt, Ti, Ag, or the like in addition to Au. For example, the metal reflective layer 271 may be a single layer made of Au alone, or the metal reflective layer 271 may include two or more Au metal layers. It is preferable that the composition of the metal reflective layer 271 contains 50 mass % or more of Au. To ensure reliable bonding with the metal bonding layer 279 in a subsequent process, it is preferable that the outermost layer of the metal reflective layer 271 (the surface opposite to the semiconductor laminate 220) is an Au metal layer.

[0068] For example, metals may be deposited in the order of Al, Au, Pt, and Au on power distribution section 260 (including the gap if any) to form metal reflective layer 271. The thickness of the Au layer in metal reflective layer 271 may be set to, for example, 400 nm to 2000 nm, and the thickness of the metal layers made of metals other than Au may be set to, for example, 5 nm to 200 nm. Metal reflective layer 271 may be deposited and formed using a common method such as vapor deposition.

[0069] <Bonding to supporting substrate> The bonding to the support substrate will be described with reference to Fig. 4. The semiconductor stack 220 and the power distribution section 260 are bonded to the support substrate 280 via at least a metal bonding layer 279. By providing a metal reflective layer 271, the metal reflective layer 271 and the metal bonding layer 279 may be bonded to each other. The metal bonding layer 279 and the metal reflective layer 271 are placed opposite each other and bonded together, and then heated and compressed at a temperature of about 250°C to 500°C to bond them together.

[0070] <Metal bonding layer> The metal bonding layer 279 can be formed using a metal such as Ti, Pt, or Au, or a metal that forms a eutectic alloy with Au (such as Sn), or solder, and is preferably formed by stacking these layers. For example, the metal bonding layer 279 can be formed by stacking, in this order from the surface of the support substrate 280, Ti with a thickness of 400 nm to 800 nm, Pt with a thickness of 5 nm to 20 nm, and Au with a thickness of 700 nm to 1200 nm. For example, when bonding the metal reflective layer 271 and the metal bonding layer 279, the outermost layer of the metal bonding layer 279 can be made of Au metal, and the outermost layer of the metal reflective layer 271 can also be made of Au, and bonding between the Au layers can be performed by Au-Au diffusion.

[0071] <Support substrate> The support substrate 280 may be a substrate of a different type from the growth substrate 205, and may be a submount substrate based on the semiconductor substrate, metal substrate, or ceramic substrate described above. Because the above-described bonding method is used, the support substrate 280 may be lattice-mismatched with the semiconductor layers formed in this embodiment. While the support substrate 280 may be insulating depending on the application, a conductive substrate is preferred. From the standpoints of processability and cost, a Si substrate is preferably used for the support substrate 280. By using a Si substrate, the thickness of the support substrate 280 can be significantly reduced compared to conventional substrates, making it suitable for implementation in combination with various semiconductor devices. Furthermore, Si substrates are advantageous in terms of heat dissipation compared to InAs or GaAs substrates.

[0072] <Removal of the growth substrate> The removal of the growth substrate will be described with reference to FIG. 5. After bonding the support substrate 280, the growth substrate 205 is removed. When the growth substrate 205 is a GaAs substrate, the growth substrate 205 can be wet-etched using, for example, an ammonia-hydrogen peroxide mixture. When an etching stop layer is used, the etching stop layer may be sequentially removed following the removal of the growth substrate 205. Alternatively, by leaving a portion of the etching stop layer, it may be used as an n-type contact layer that reduces the contact resistance with the first n-type electrode 291.

[0073] <1st n-type electrode> As shown in FIG. 2, a first n-type electrode 291 is formed on the semiconductor laminate 220. The semiconductor laminate 220 is sandwiched between the second n-type electrode 295 and the first n-type electrode 291. A backside electrode 299 may be formed on the backside of the support substrate 280. The first n-type electrode 291 and the backside electrode 299 may include a wiring portion and a pad portion. The first n-type electrode 291 and the backside electrode 299 can be formed by a known method, such as sputtering, electron beam evaporation (also referred to as evaporation), or resistance heating. The electrode pattern can be formed by using a metal mask or by combining photolithography, lift-off, and metal etching.

[0074] The above manufacturing method can provide the optical semiconductor element 200 shown in Fig. 2. These embodiments are merely examples and are not limiting, and suitable modifications are possible, such as providing a slope on the side surface of the element during mesa etching, or the electrode shape may be two electrodes on the top surface or a flip-chip type.

[0075] (Third embodiment) Next, an optical semiconductor device 300 according to a third embodiment of the present invention will be described with reference to FIG. 6. The third embodiment is an embodiment in which an active layer and a tunnel junction layer are further formed on the tunnel junction layer of the first embodiment. Specifically, the optical semiconductor device 300 of FIG. 6 has a semiconductor stack 320 in which a first n-type contact layer 321, a first n-type window layer 322, a first spacer layer 323, a first active layer 324, a first p-type electron blocking layer 325, a first p-type window layer 326, a first tunnel junction layer 327, a second spacer layer 330, a second active layer 331, a second p-type electron blocking layer 332, a second p-type window layer 333, a second tunnel junction layer 334, a second n-type window layer 328, and a second n-type contact layer 329 are sequentially formed on a growth substrate 305. The first active layer 324, the first p-type electron blocking layer 325, the first p-type window layer 326, and the first tunnel junction layer 327 are collectively referred to as a first semiconductor stacked structure 340, and the second active layer 331, the second p-type electron blocking layer 332, the second p-type window layer 333, and the second tunnel junction layer 334 are collectively referred to as a second semiconductor stacked structure 350. In the semiconductor stacked body 320, a first n-type contact layer 321, a first n-type window layer 322, and a first spacer layer 323 are formed, and then the first semiconductor stacked structure 340 and the second semiconductor stacked structure 350 are superimposed with the second spacer layer 330 interposed therebetween, and a second n-type window layer 328 and a second n-type contact layer 329 are further formed thereon. Furthermore, the optical semiconductor element 300 has a second n-type electrode 395 formed as an n-type ohmic electrode on the top of the semiconductor laminate 320, and a first n-type electrode 391 formed as a backside electrode on the backside of the growth substrate 305. The growth substrate 305 and the semiconductor laminate 320 are sandwiched between the first n-type electrode 391 and the second n-type electrode 395. The central emission wavelength of the optical semiconductor element 300 is not less than 2000 nm and not more than 5000 nm. Each component will be described in detail below.

[0076] In the optical semiconductor device 300, since the growth substrate 305, the first n-type contact layer 321, the first n-type window layer 322, and the first spacer layer 323 have the same configuration as the layers below the active layer 124 in the first embodiment, the description thereof is omitted. The semiconductor laminate 320 has two semiconductor laminate structures in which (one) active layer and (one) tunnel junction layer are laminated. When a negative voltage is applied to the first n-type electrode 391 on the side opposite to the first tunnel junction layer 327 side of the first active layer 324 and a current flows in the forward direction between the first tunnel junction layer 327 side (the first p-type electron blocking layer 325 side) of the first active layer 324, a current flows in the reverse direction (from the n-type layer to the p-type layer) through the tunnel junction layer 327 due to the tunnel effect. Then, when a negative voltage is applied to the first tunnel junction layer 327 side of the subsequent second active layer 331 and a current flows in the forward direction between the second tunnel junction layer 334 side (the second p-type electron blocking layer 332 side) of the second active layer 331, a current flows in the reverse direction (from the n-type layer to the p-type layer) through the second tunnel junction layer 334 due to the tunnel effect. Therefore, when a positive voltage is applied to the second n-type electrode 395 on the side opposite to the second active layer 331 side of the subsequent second tunnel junction layer 334, a current flows, and it functions as a so-called double-stack type light-emitting diode in which two active layers are laminated in the vertical direction.

[0077] <First active layer> The first active layer 324 is provided on the first spacer layer 323. The first active layer 324 may include an InAs x1 Sb 1-x1 layer (0 < x1 < 1). The first active layer 324 further has an InAs y1 P 1-y1 layer (0 < y1 < 1), and the InAs x1 Sb 1-x1 layer is the well layer 324w of the first active layer 324, and the InAs y1 P 1-y1It is preferable that the layer be a first active layer having a quantum well structure with the barrier layer 324b of the active layer. Also, the composition other than Sb is not limited to In and As, and another III-V compound semiconductor may be used. Further, the composition difference between the well layer 324w and the barrier layer 324b of the first active layer 324 may be adjusted to apply strain to the well layer 324w. The first active layer 324 more preferably has a multiple quantum well structure as shown in FIG. 6 in order to improve the light output by suppressing crystal defects. This multiple quantum well structure can be formed by a structure in which the well layer 324w and the barrier layer 324b are alternately repeated. When using a multiple quantum well structure, the combination of the well layer 324w and the barrier layer 324b is preferably 3 or more sets and 40 or less sets. That is, including the first barrier layer 324b, it is preferably 3.5 or more sets and 40.5 or less sets. Further, the film thickness of each well layer 324w is preferably 5 nm or more and 40 nm or less, and the film thickness of each barrier layer 324b is preferably 10 nm or more and 50 nm or less. Also, the first active layer 324 is preferably undoped. Also, by adjusting the composition ratio of Ga and Al in InGaAlAs as the above composition of the well layer 324w or the first active layer 324, the emission center wavelength of the optical semiconductor device 300 can be set within the range of 2000 nm or more and 5000 nm or less. The emission center wavelength of the optical semiconductor device 300 is preferably 2100 nm or more and 4800 nm or less. The first active layer 324 more preferably has an emission center wavelength of 3000 nm or more. For the barrier layer 324b, AlInAs or the like can also be used in addition to InAsP. x1 Sb 1-x1 By adjusting the composition ratio of Ga and Al as well, the emission center wavelength of the optical semiconductor device 300 can be set within the range of 2000 nm or more and 5000 nm or less. The emission center wavelength of the optical semiconductor device 300 is preferably 2100 nm or more and 4800 nm or less. The first active layer 324 more preferably has an emission center wavelength of 3000 nm or more. For the barrier layer 324b, AlInAs or the like can also be used in addition to InAsP.

[0078] <Second active layer> A second active layer 331 is provided on the second spacer layer 330. The first wavelength emitted by the first active layer 324 and the second wavelength emitted by the second active layer 331 are preferably the same or approximate to each other. Also, the second active layer 331 is, like the first active layer 324, InAs that becomes a light emitting layer x2 Sb 1-x2 layer (0 < x2 < 1) as the well layer 331w, and InAs y2 P 1-y2It is preferable that the second active layer has a quantum well structure with a layer (0 < y2 < 1) as the barrier layer 331b. Also, the composition other than Sb is not limited to In and As, and another III-V compound semiconductor may be used. Further, the composition difference between the well layer 331w and the barrier layer 331b of the second active layer 331 may be adjusted to apply strain to the well layer 331w. It is more preferable that the second active layer 331 has a multiple quantum well structure as shown in FIG. 6 for improving the light output by suppressing crystal defects. This multiple quantum well structure can be formed by a structure in which the well layer 331w and the barrier layer 331b are alternately repeated. When using a multiple quantum well structure, the combination of the well layer 331w and the barrier layer 331b is preferably 3 or more sets and 40 or less sets. That is, including the first barrier layer 331b, it is preferably 3.5 or more sets and 40.5 or less sets. Further, the film thickness of each well layer 331w is preferably 5 nm or more and 40 nm or less, and the film thickness of each barrier layer 331b is preferably 10 nm or more and 50 nm or less. Also, the second active layer 331 is preferably undoped. Also, by adjusting the composition ratio of Ga and Al in the above composition of the well layer 331w or the second active layer 331 to InGaAlAs x1 Sb 1-x1 the emission center wavelength of the optical semiconductor device 300 can be set within the range of 2000 nm or more and 5000 nm or less. The emission center wavelength of the optical semiconductor device 300 is preferably 2100 nm or more and 4800 nm or less. It is more preferable that the emission center wavelength of the second active layer 331 is 3000 nm or more. For the barrier layer 331b, in addition to InAsP, AlInAs or the like can also be used.

[0079] <First tunnel junction layer> A first tunnel junction layer 327 is provided on the first p-type window layer 326. The first tunnel junction layer 327 is composed of a first p-type tunnel junction layer 3271 and a first n-type tunnel junction layer 3272, both of which are lattice-matched to InAs. The first n-type tunnel junction layer 3272 is deposited directly on the first p-type tunnel junction layer 3271. The first p-type tunnel junction layer 3271 may be a p-type InAlAsSbP layer, and the first n-type tunnel junction layer 3272 may be an n-type InAlAsSbP layer. The thickness of the first tunnel junction layer 327 is preferably 10 nm to 200 nm. Dopants that can be used for the first p-type tunnel junction layer 3271 include Mg, Zn, C, and Be, and dopants that can be used for the first n-type tunnel junction layer 3272 include Si, Te, S, Ge, Sn, and Se. A first p-type tunnel junction layer 3271 is located on the first active layer 324 side of the first tunnel junction layer 327. A first n-type tunnel junction layer 3272 is located on the second active layer 331 side of the first tunnel junction layer 327. The film thickness and dopant concentration of the first p-type tunnel junction layer 3271 and the first n-type tunnel junction layer 3272 may be the same or different. Furthermore, the dopant concentration of the first p-type tunnel junction layer 3271 and the first n-type tunnel junction layer 3272 does not need to be uniform within the layer, and a concentration gradient may exist.

[0080] <<First p-type tunnel junction layer>> The p-type dopant concentration in the first p-type tunnel junction layer 3271 is 1.0×10 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm 3 Preferably, it is less than 9.0 × 10 18 atoms / cm 3 The film thickness is preferably 5 nm or more and 100 nm or less.

[0081] <<First n-type tunnel junction layer>> The n-type dopant concentration in the first n-type tunnel junction layer 3272 is 1.0×10 18 atoms / cm 3 Over 1.0 x 10 19 atoms / cm3 Preferably, it is less than 9.0 × 10 18 atoms / cm 3 The film thickness is preferably 5 nm or more and 100 nm or less.

[0082] <Second tunnel junction layer> A second tunnel junction layer 334 composed of a second p-type tunnel junction layer 3341 and a second n-type tunnel junction layer 3342 lattice-matched to InAs is provided on the second p-type window layer 333. The second tunnel junction layer 334 preferably has the same configuration as the first tunnel junction layer 327. That is, the first p-type tunnel junction layer 3271 and the second p-type tunnel junction layer 3341, and the second n-type tunnel junction layer 3272 and the second n-type tunnel junction layer 3342 preferably have the same composition and the same dopants. The second p-type tunnel junction layer 3341 and the second n-type tunnel junction layer 3342 may have the same or different film thicknesses and dopant concentrations. The first p-type tunnel junction layer 3271 and the second p-type tunnel junction layer 3341, and the first n-type tunnel junction layer 3272 and the second n-type tunnel junction layer 3342 may have the same or different film thicknesses and dopant concentrations. Furthermore, the dopant concentrations of the second p-type tunnel junction layer 3341 and the second n-type tunnel junction layer 3342 do not need to be uniform within the layers, and may have a concentration gradient. Furthermore, for example, it is preferable to use Te or Si as the dopant for the second n-type tunnel junction layer 3342, and it is preferable to use Si as the dopant for the first n-type tunnel junction layer 3272. In this way, by using Si, which is less susceptible to dopant diffusion, for the n-type tunnel junction layer that is adjacent to the active layer and not sandwiching the p-type layer, it is possible to reduce the thickness of the required spacer layer and further improve the light emission efficiency.

[0083] <<Second spacer layer>> A second spacer layer 330 is preferably provided between the first tunnel junction layer 327 and the second active layer 331, and its thickness is preferably 100 nm or less. The thickness of the second spacer layer 330 is more preferably 90 nm or less, and even more preferably 80 nm or less. The second spacer layer 330 preferably has the same composition as the barrier layer 331b of the second active layer 331 or the first n-type tunnel junction layer 3272, and is preferably a layer not doped with an n-type dopant. This second spacer layer 330 has the effect of reducing the amount of n-type dopant diffusing from the first n-type tunnel junction layer 3272 to the second active layer 331. Furthermore, a layer other than the second spacer layer 330 may be provided between the first tunnel junction layer 327 and the second active layer 331. Even in this case, the total thickness of all layers between the first tunnel junction layer 327 and the second active layer 331 is preferably 100 nm or less.

[0084] <P-type intermediate layer between the first active layer and the first tunnel junction layer> A first p-type intermediate layer is provided between the first active layer 324 and the first tunnel junction layer 327. The total thickness of the layers between the first active layer 324 and the first tunnel junction layer 327 is preferably 100 nm or less. The first p-type intermediate layer preferably includes a first p-type electron blocking layer 325.

[0085] <First p-type electron blocking layer> A first p-type electron blocking layer 325 made of a III-V compound semiconductor layer may be provided on the first active layer 324, and the thickness thereof is preferably 5 nm to 60 nm. Dopants that can be used here include Mg, Zn, C, and Be. The p-type dopant concentration is 1.0×10 18 / cm 3 Over 5.0 x 10 18 / cm 3 The first p-type electron blocking layer 325 is a layer that injects and confines carriers into the first active layer 324. The first p-type electron blocking layer 325 also has the effect of reducing the diffusion of p-type dopants from the first tunnel junction layer 327 to the first active layer 324.

[0086] The composition of the first p-type electron blocking layer 325 is Al z1 In 1-z1 As (0.05≦z1≦0.40) is preferred, and Al z1 In 1-z1 It is more preferable that the Al composition z1 is As (0.10≦z1≦0.35). By setting the Al composition z1 to 0.05 or more, the luminous efficiency of the first p-type electron blocking layer 325 can be improved, and by setting it to 0.40 or less, it is possible to prevent a decrease in luminous efficiency due to an increase in forward voltage. In addition, the p-type dopant concentration of the first p-type electron blocking layer 325 is preferably lower than the p-type dopant concentration doped in the first p-type tunnel junction layer 3271.

[0087] <First p-type window layer> A first p-type window layer 326 may be further provided on the first p-type electron blocking layer 325. The composition of the first p-type window layer 326 preferably has a lower Al content than the composition z1 of the first p-type electron blocking layer 325, and is more preferably InAs, for example. The p-type dopant concentration is 1.0×10 18 / cm 3 Over 5.0 x 10 18 / cm 3 It is preferable that:

[0088] The first p-type intermediate layer between the first active layer 324 and the first tunnel junction layer 327 may include a layer other than the first p-type electron blocking layer 325 or the first p-type window layer 326. Even in this case, in the present invention, the dopant concentration in the first tunnel junction layer 327 can be kept low, so that even if p-type dopant diffusion from the first p-type tunnel junction layer 3271 occurs, the p-type dopant concentration in the first p-type intermediate layer can be kept low, for example, 5.0×10 18 / cm 3 Furthermore, it is preferable that the total thickness of all layers between the first active layer 324 and the first tunnel junction layer 327 be 100 nm or less. By making the thickness thin in this manner while suppressing the amount of dopant diffusion, it is expected that the forward voltage of the entire device can be reduced.

[0089] <<Second p-type electron blocking layer>> A second p-type electron blocking layer 332 made of a III-V compound semiconductor may be provided on the second active layer 331, and the thickness thereof is preferably 5 nm to 60 nm. The second p-type electron blocking layer 332 may have the same configuration as the first p-type electron blocking layer 325. The second p-type electron blocking layer 332 is a layer that injects and confines carriers into the second active layer 331. The second p-type electron blocking layer 332 also has the effect of reducing the diffusion of p-type dopants from the second tunnel junction layer 334 to the second active layer 331. The p-type dopant concentration of the second p-type electron blocking layer 332 is preferably lower than the p-type dopant concentration doped in the second p-type tunnel junction layer 3341.

[0090] <<Second p-type window layer>> A second p-type window layer 333 may be further provided on the second p-type electron blocking layer 332. The second p-type window layer 333 may have the same structure as the first p-type window layer 326.

[0091] The layers above the second tunnel junction layer 334, the second n-type electrode 395, and the first n-type electrode 391 have the same configuration as the layers above the tunnel junction layer 127, the second n-type electrode 195, and the first n-type electrode 191 in the first embodiment, and therefore their description will be omitted.

[0092] In the optical semiconductor device 300 according to the third embodiment, the above-described semiconductor layers may be sequentially deposited on the growth substrate 305, and an electrode structure may be formed. In this case, as in the second embodiment, the growth substrate may be removed while a support substrate different from the growth substrate is bonded using the above-described bonding method.

[0093] The above-mentioned first and second embodiments describe embodiments having one semiconductor laminate structure, and the third embodiment describes an embodiment having two semiconductor laminate structures, but the present disclosure is also applicable to semiconductor light-emitting elements, which are optical semiconductor elements having three or more semiconductor laminate structures.

[0094] (Fourth embodiment: light receiving element) The present disclosure is also applicable to semiconductor light-receiving elements, which are optical semiconductor elements, and a semiconductor light-receiving element according to a fourth embodiment of the present invention will be described. For example, by replacing the active layer in the first embodiment with a light absorption layer, the optical semiconductor element of the present invention can be used as an optical semiconductor light-receiving element, and a semiconductor light-receiving element with good optical characteristics can be realized. Similarly, a semiconductor light-receiving element with good optical characteristics can be realized by replacing the active layer in the second and third embodiments with a light absorption layer. [Example]

[0095] [Experimental Example 1] Example 1 First, using MOCVD, a Te-doped, high-dopant-concentration first n-type InAs contact layer 221 (thickness: 0.3 μm), a Te-doped first n-type InAs layer 222 (thickness: 4.9 μm), and an undoped InAs spacer layer 223 (thickness: 75 nm) were sequentially formed on the (100) surface of a Si-doped n-type GaAs growth substrate 205 (substrate thickness: 350 μm). Next, an active layer 224 (total thickness: 430 nm) with a multiple quantum well structure and an emission center wavelength of 4300 nm was formed. The active layer 224 with the multiple quantum well structure was formed of undoped InAs. 0.89 P 0.11 Barrier layer 224b (thickness: 30 nm) and InAs 0.87 Sb 0.13 After stacking 10 layers of InAs well layer 224w (thickness: 10 nm) alternately, 0.89 P 0.11 A barrier layer 224b (thickness: 30 nm) was laminated, and the total number of layers including the last barrier layer 224b was 10.5. 0.32 In 0.68 An As electron blocking layer 225 (thickness: 15 nm) and a Zn-doped p-type InAs window layer 226 (thickness: 50 nm) were formed in this order, and a tunnel junction layer 227 was formed thereon.

[0096] The tunnel junction layer 227 was fabricated by directly forming a Te-doped n-type InAs tunnel junction layer 2272 (thickness: 50 nm) on a Zn-doped p-type InAs tunnel junction layer 2271 (thickness: 50 nm), thereby achieving a tunnel effect at the interface between them. The pressure during growth of the tunnel junction layer 227 was set to 50 Torr, and the ratio of group V elements to group III elements (VIII ratio) in the source gas used was set to 50.

[0097] Next, on the tunnel junction layer 227, a Te-doped second n-type InAs window layer 228 (thickness: 0.9 μm) and a Te-doped, high-dopant-concentration second n-type InAs contact layer 229 (thickness: 0.1 μm) were formed in this order.

[0098] Table 1 below lists the composition and thickness of each layer, the type of dopant, and the dopant concentration determined by SIMS analysis, including dopant diffusion, after all epitaxial growth was completed and the substrate was removed from the MOCVD reactor. The total thickness of the layers between the active layer and the tunnel junction layer (the sum of the p-type window layer and the p-type electron blocking layer) was 65 nm, less than 100 nm. The source gases selected for the formation of each layer were trimethylindium (TMIn) as the indium source, trimethylgallium (TMGa) as the gallium source, trimethylaluminum (TMAl) as the aluminum source, arsine (AsH3) as the arsenic source, triethylantimony (TESb) as the antimony source, and phosphine (PH3) as the phosphorus source. Additionally, diethylzinc (DEZn) was used as the zinc dopant gas, and diethyltellurium (DETe) was used as the tellurium dopant gas.

[0099] The composition of each layer was measured using a BRUKER JV-QC3 XRD instrument. The composition of each layer was calculated by fitting using analytical software (Jordan Valley RADS). The thickness of each layer was calculated from cross-sectional observation of the grown layer using a SEM (scanning electron microscope) or TEM (transmission electron microscope).

[0100] [Table 1]

[0101] A transparent insulating film 261 (thickness: 550 nm) made of SiO was formed on the entire surface of the second n-type InAs contact layer 229 by plasma CVD. A power distribution pattern was formed thereon using resist, and the SiO in areas not covered by the resist was removed by etching to expose the second n-type InAs contact layer 229. Next, Ti (thickness: 10 nm) and Au (thickness: 530 nm) were sequentially formed as ohmic metal portions by vapor deposition, and the resist of the power distribution pattern was removed together with the metal deposited thereon, leaving only the ohmic metal portion formed on the exposed second n-type InAs contact layer 229. This formed the power distribution portion 260 in which the ohmic metal portion and the transparent insulating film 261 were arranged in parallel as the second n-type electrode 295. Furthermore, a metal reflective layer 271 (Al (film thickness: 10 nm) / Au (film thickness: 650 nm) / Pt (film thickness: 100 nm) / Au (film thickness: 900 nm)) was formed on the power distribution section 260 by vapor deposition.

[0102] A metal bonding layer 279 (Ti (thickness: 650 nm) / Pt (thickness: 20 nm) / Au (thickness: 900 nm)) was formed on a support substrate 280 (conductive Si substrate, thickness: 200 μm) by vapor deposition. The metal reflective layer 271 and the metal bonding layer 279 were arranged facing each other and subjected to thermal compression bonding at 300°C. Next, the growth substrate 205 was removed by wet etching using an ammonia-hydrogen peroxide solution mixture to expose the first n-type contact layer 221. Ti (thickness: 150 nm) and Au (thickness: 1250 nm) were formed in this order on the first n-type contact layer 221 by vapor deposition, and the first n-type ohmic electrode and pad electrode were combined to form a first n-type electrode 291. The pattern of the first n-type electrode 291 was formed by a lift-off method using a resist.

[0103] Next, mesa etching was performed to remove the semiconductor laminate 220 between each element (width: 60 μm) to form dicing lines. Then, a back electrode 299 (Ti (film thickness: 10 nm) / Pt (film thickness: 50 nm) / Au (film thickness: 200 nm)) was formed on the back surface of the support substrate 280 by vapor deposition, and heat treatment was performed at 300°C for 1 minute to alloy the ohmic metal portion, the first n-type electrode, and the back electrode. Next, the entire wafer was immersed in a nitric acid solution maintained at 8°C ± 1°C for 5 seconds to roughen the surface of the semiconductor laminate 220 except for the region where the first n-type electrode 291 was formed. Thereafter, the wafer was immersed in ammonia water for 1 minute and then washed with pure water for 1 minute. After the roughening and before dicing, the support substrate 280 was placed on a prober with the back electrode 299 facing downward, and prober measurements were performed on each element. Finally, the wafer was diced to separate into individual chips, thereby producing the optical semiconductor elements according to Example 1. The chip size is 500 μm×500 μm.

[0104] Example 2 Similar to Example 1, each semiconductor layer was epitaxially grown up to the first tunnel junction layer 327. Next, a second active layer 331 and a second tunnel junction layer 334 were formed in this order on the first tunnel junction layer 327. A second n-type window layer 328 and a second n-type contact layer 329 were formed in this order on the second tunnel junction layer 334, similar to the tunnel junction layer 227 in Example 1. Further, similar to Example 1, a first n-type electrode and a second n-type electrode were formed, a support substrate was bonded, and the growth substrate was then removed to obtain a junction-type semiconductor device 300. The second active layer 321 had the same film thickness and composition as the first active layer 324, and the second tunnel junction layer 334 had the same film thickness and composition as the first tunnel junction layer 327. A second spacer layer 330 having the same film thickness and composition as the first spacer layer 323 was formed between the first tunnel junction layer 327 and the second active layer 331. Furthermore, a second p-type electron blocking layer 332 and a second p-type window layer having the same film thickness and composition as the first p-type electron blocking layer 325 and the first p-type window layer, respectively, were formed in this order between the second active layer 331 and the second tunnel junction layer 334.

[0105] Table 2 below lists the composition and thickness of each layer, the type of dopant, and the dopant concentration determined by SIMS analysis, including dopant diffusion, after all epitaxial growth was completed and the substrate was removed from the MOCVD reactor. The total thickness of the layers between the first active layer and the first tunnel junction layer (the sum of the p-type window layer and the p-type electron blocking layer) was 65 nm, and the total thickness of the layers between the second active layer and the second tunnel junction layer (the sum of the p-type window layer and the p-type electron blocking layer) was also 65 nm, both of which are less than 100 nm. It was observed that the Te in the first n-type tunnel junction layer tended to diffuse into the second spacer layer and the first barrier layer on the growth substrate side of the second active layer.

[0106] [Table 2]

[0107] Example 3 The optical semiconductor device 300 of Example 3 was fabricated in the same manner as Example 2, except that the dopant of the first n-type tunnel junction layer 3272 and the second n-type tunnel junction layer 3342 was changed from Te to Si, the dopant concentration was changed, and the dopant of the second n-type window layer and the second n-type contact layer 329 was also changed to Si.

[0108] Table 3 below lists the composition and thickness of each layer, the type of dopant, and the dopant concentration determined by SIMS analysis, including dopant diffusion, after all epitaxial growth was completed and the substrate was removed from the MOCVD reactor. The total thickness of the layers between the first active layer and the first tunnel junction layer (the sum of the p-type window layer and the p-type electron blocking layer) was 65 nm, and the total thickness of the layers between the second active layer and the second tunnel junction layer (the sum of the p-type window layer and the p-type electron blocking layer) was also 65 nm, both of which are less than 100 nm. With Te doping, the Te in the first n-type tunnel junction layer tended to diffuse into the first barrier layer on the growth substrate side of the second active layer, but no such diffusion was observed with Si doping. This indicates that Si is preferable to Te as a dopant for the n-type tunnel junction layer.

[0109] [Table 3]

[0110] (Comparative Example 1) The tunnel junction layer 227 is not formed on the p-type InAs window layer 226, and a Zn-doped p-type InAs contact layer (thickness: 100 nm, dopant concentration: 1.0×10 19 atoms / cm 3 An optical semiconductor device of Comparative Example 1 was fabricated in the same manner as in Example 1, except that a second n-type electrode was formed on the active layer, and the number of pairs of the multiple quantum well structure in the active layer was set to 20.5 pairs. In this case, a p-type ohmic metal portion was used instead of an ohmic metal portion as the second n-type electrode.

[0111] (Comparative Example 2) The second tunnel junction layer 334 was not formed on the second p-type InAs window layer 333, and a Zn-doped p-type InAs contact layer (thickness: 100 nm, dopant concentration: 1.0×10 19 atoms / cm 3 An optical semiconductor device of Comparative Example 2 was fabricated in the same manner as in Example 2, except that an ohmic metal portion serving as a second n-type electrode was formed. In this case, a p-type ohmic metal portion was used instead of an ohmic metal portion serving as a second n-type electrode.

[0112] (Comparative Example 3) The second tunnel junction layer 334 was not formed on the second p-type InAs window layer 333, and a Zn-doped p-type InAs contact layer (thickness: 100 nm, dopant concentration: 1.0×10 19 atoms / cm 3 An optical semiconductor device of Comparative Example 3 was fabricated in the same manner as in Example 3, except that an ohmic metal portion serving as a second n-type electrode was formed on the semiconductor substrate. In this case, a p-type ohmic metal portion was used instead of an ohmic metal portion serving as a second n-type electrode.

[0113] Comparative Example 4 The concentration of Si dopant in the first n-type tunnel junction layer was increased to 2.3 × 10 19 atoms / cm 3 An optical semiconductor device of Comparative Example 4 was produced in the same manner as in Comparative Example 3, except that:

[0114] Example 4 The dopant of the first n-type window layer was changed from Te to Si, and the dopant concentration was increased to 1.5 × 10 18 atoms / cm 3 An optical semiconductor device of Example 4 was produced in the same manner as in Example 3, except that:

[0115] Example 5 In the optical semiconductor device of Example 4, a second n-type window layer was formed on the second tunnel junction layer, whereas in Example 5, a third spacer layer, a third active layer, a third p-type electron blocking layer, a third p-type window layer, and a third tunnel junction layer were further formed on the second tunnel junction layer, and then a second n-type window layer and a second n-type contact layer were formed to produce the optical semiconductor device of Example 5. The composition, film thickness, dopant, and dopant concentration of the "third spacer layer, third active layer, third p-type electron blocking layer, third p-type window layer, and third tunnel junction layer" in Example 5 are the same as those of the "second spacer layer, second active layer, second p-type electron blocking layer, second p-type window layer, and second tunnel junction layer" in Table 3, respectively.

[0116] Example 6 In the optical semiconductor device of Example 4, a second n-type window layer was formed on the second tunnel junction layer, whereas in Example 5, a third spacer layer, a third active layer, a third p-type electron blocking layer, a third p-type window layer, and a third tunnel junction layer were further formed on the second tunnel junction layer, and a fourth spacer layer, a fourth active layer, a fourth p-type electron blocking layer, a fourth p-type window layer, and a fourth tunnel junction layer were further formed on the third tunnel junction layer, and then a second n-type window layer and a second n-type contact layer were formed to produce the optical semiconductor device of Example 6. The compositions, film thicknesses, dopants, and dopant concentrations of the “third spacer layer, third active layer, third p-type electron blocking layer, third p-type window layer, and third tunnel junction layer” and the “fourth spacer layer, fourth active layer, fourth p-type electron blocking layer, fourth p-type window layer, and fourth tunnel junction layer” are the same as those of the “second spacer layer, second active layer, second p-type electron blocking layer, second p-type window layer, and second tunnel junction layer” in Table 3, respectively.

[0117] 7 is a graph showing the results of measuring the diffusion state of Si ions and Te ions in the optical semiconductor element fabricated in Example 3 by secondary ion mass spectrometry (SIMS). In FIG. 7, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of n-type dopants (here, Te, Si, C, H, and O). 3 7, the peak value of Si, which is the n-type dopant doped into the semiconductor laminate 320 in Example 3, is 4.5×10 18 atoms / cm 3 and 5.0 x 10 18 atoms / cm 3 The positions where these peak values ​​are obtained correspond to the first n-type tunnel junction layer 3272 and the second n-type tunnel junction layer 3342, respectively. From the graph of FIG. 7, it can be seen that the semiconductor laminate 320 of Example 3 has a Si concentration of 1.0×10 15 atoms / cm 3 From the above, it can be seen that the Si ions doped into the first n-type tunnel junction layer 3272 and the second n-type tunnel junction layer 3342 hardly diffuse into the first active layer 324 and the second active layer 331.

[0118] In the semiconductor stack 320 of Example 3, the first n-type window layer 322 is doped with Te, as can be seen in the graph of Fig. 7. Diffusion of Te doped in the first n-type window layer 322 toward the first active layer 324 and the first spacer layer 323 was observed.

[0119] 8 is a graph showing the results of measuring the diffusion state of Zn ions in the optical semiconductor element fabricated in Example 3 by SIMS. In FIG. 8, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of the p-type dopant (Zn in this case). 3 ), and the vertical axis on the right side is the secondary ion intensity of Sb (counts / sec). The maximum value of Zn, which is a p-type dopant doped into the semiconductor laminate 320, is 6.0×10 18 atoms / cm 3The positions where the maximum value was reached were positions corresponding to the first p-type tunnel junction layer 3271 and the second p-type tunnel junction layer 3341, and diffusion of Zn from the first p-type tunnel junction layer 3271 to the first active layer 324 and from the second p-type tunnel junction layer 3341 to the second active layer 331 was observed.

[0120] 9 is a graph showing the results of measuring the diffusion state of Te ions in the optical semiconductor element fabricated in Comparative Example 2 by secondary ion mass spectrometry (SIMS). In FIG. 9, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm) of n-type dopants (here, Te, Si, C, H, and O). 3 ), and the vertical axis on the right side is the secondary ion intensity of Sb (counts / sec). From the graph of FIG. 9, it can be seen that the maximum concentration of Te, which is an n-type dopant doped into the semiconductor laminate in Comparative Example 2, is 8.0×10 18 atoms / cm 3 The position where the maximum value was reached was the position corresponding to the n-type tunnel junction layer, and diffusion of Te from the n-type tunnel junction layer toward the undoped spectrum layer and the first barrier layer was observed.

[0121] 10 is a graph showing the results of measuring, by SIMS, the diffusion state of Zn ions in the optical semiconductor element fabricated in Comparative Example 2. In FIG. 10, the horizontal axis represents depth (μm), and the vertical axis on the left represents the concentration (atoms / cm ) of the p-type dopant (Zn in this case). 3 ), and the vertical axis on the right is the secondary ion intensity of Sb (counts / sec). The maximum value of Zn, a p-type dopant doped into the semiconductor laminate, is 6.0 × 10 18 atoms / cm 3 The position where the maximum value was reached was the position corresponding to the p-type tunnel junction layer, and Zn was observed from the p-type tunnel junction layer toward the p-type window layer and the electron blocking layer.

[0122] <Evaluation: Light output evaluation> A current of 300 mA was applied to the optical semiconductor devices obtained in Examples 1 to 3 and Comparative Examples 1 to 3 using a prober, with the first n-type electrode serving as the negative electrode (-) and the second n-type electrode serving as the positive electrode (+) using a constant-current voltage source. The forward voltage Vf (V) and the on-axis light output Po (W) received by a light-receiving element placed directly above the light-emitting element were measured. The emission center wavelength (λc) was also measured using a spectrophotometer via an optical fiber. The reverse current Ir (A) was also measured when a reverse voltage of -0.1 V was applied. The results are shown in Tables 4 and 5.

[0123] [Table 4]

[0124] [Table 5]

[0125] The above results confirmed that increasing the number of active layers and tunnel junction layers, as well as sandwiching the semiconductor stack between n-type electrodes using tunnel junction layers, increased the light output and forward voltage, resulting in increased light emission efficiency. While tunnel junction layers are generally considered to have high resistance and therefore increase forward voltage, the configuration of the present invention, in which the first n-type electrode is formed using tunnel junction layers, reduced the total resistance and forward voltage compared to forming a p-type electrode without using tunnel junction layers. Furthermore, the current spreading through the first n-type contact layer and tunnel junction layers improved the light output and light emission efficiency. Even with multiple active layers, as in Examples 2 and 3, the forward voltage required for operation is smaller than that required for GaAs-matched or InP-matched systems. Therefore, it is possible to further increase the number of active layers and increase the light emission output per unit area. Note that the reverse current is very small, and the present optical semiconductor device is driven only by forward current.

[0126] [Experimental Example 2] Example 7 The composition of the active layer was changed so that the central emission wavelength was 3.3 μm instead of approximately 4 μm, and the number of pairs of the multiple quantum well structure in the active layer was set to 20.5 pairs, and the dopant concentration of the first n-type window layer was set to 2.0 × 10 18 atoms / cm 3 An optical semiconductor device of Example 7 was produced in the same manner as in Example 1, except that: Table 6 below shows the composition and thickness of each layer, the type of dopant, and all the epitaxial layers. SIMS analysis including dopant diffusion after growth is completed and removed from the MOCVD reactor The dopant concentration due to the increase in the n-type window layer is described below. The total thickness of the layers between the active layer and the tunnel junction layer (the sum of the p-type window layer and the p-type electron blocking layer) is 65 nm, which is less than 100 nm. By increasing the dopant concentration of the first n-type window layer, the concentration of Te diffused into the first barrier layer of the first active layer also increased.

[0127] [Table 6]

[0128] (Comparative Example 5) The p-type InAs window layer on the p-type electron blocking layer is made of p-type AlInAs (Al composition: 0.05). No tunnel junction layer is formed on the p-type InAs window layer, and a Zn-doped p-type AlInAs contact layer (Al composition: 0.05, film thickness: 100 nm, dopant concentration: 1.0 × 10) is formed. 19 atoms / cm 3 An optical semiconductor element of Comparative Example 5 was fabricated in the same manner as in Example 7, except that an ohmic metal portion serving as the second n-type electrode was formed. In this case, a p-type ohmic metal portion was used instead of an ohmic metal portion serving as the second n-type electrode.

[0129] <Evaluation: Light output evaluation> As in Example 1, a 300 mA current was applied to the optical semiconductor devices obtained in Example 7 and Comparative Example 5 using a prober with the first n-type electrode as the negative electrode (-) and the second n-type electrode as the positive electrode (+) using a constant current voltage source. The forward voltage Vf (V) and the on-axis light output Po (W) received by the light-receiving element placed directly above the light-emitting element were measured, and the emission center wavelength (λc) was measured using a spectrophotometer via optical fiber. The reverse current Ir (A) was also measured when a reverse voltage of -0.1 V was applied. The results are shown in Table 7.

[0130] [Table 7]

[0131] From the above results, it was confirmed that even when the emission wavelength was changed from approximately 4 μm in Experimental Example 1 to 3.3 μm in Experimental Example 2, the light output and forward voltage increased, and the light emission efficiency increased, by increasing the number of active layers and tunnel junction layers and sandwiching the semiconductor stack between n-type electrodes using the tunnel junction layers, just like in Experimental Example 1. [Explanation of symbols]

[0132] 100, 200, 300 Optical semiconductor element 105, 205, 305 growth substrate 120, 220, 320 Semiconductor laminate 121, 221 First n-type contact layer 122, 222 First n-type window layer 123, 223 spacer layer 124, 224 active layer 124b, 224b Barrier layers of the active layers 124, 224 124w, 224w Active layer 124, 224 well layer 125, 225 p-type electron blocking layer 126, 226 p-type window layer 127, 227 Tunnel junction layer 1271, 2271 p-type tunnel junction layer 1272, 2272 n-type tunnel junction layer 128, 228 2nd n-type window layer 129, 229 Second n-type contact layer 191, 291, 391 1st n-type electrode 195, 295, 395 2nd n-type electrode 260 Power Distribution Department 261 Transparent insulating film 271 Metal reflective layer 279 Metal bonding layer 280 Support substrate 299 Back electrode 321 1st n-type contact layer 322 1st n-type window layer 323 First spacer layer 324 1st active layer 324b Barrier layer of the first active layer 324 324w Well layer of the first active layer 324 325 1st p-type electron blocking layer 326 1st p-type window layer 327 First tunnel junction layer 3271 1st p-type tunnel junction layer 3272 First n-type tunnel junction layer 328 2nd n-type window layer 329 Second n-type contact layer 330 Second spacer layer 331 2nd active layer 332b Barrier layer of the second active layer 331 332w Well layer of the second active layer 331 333 Second p-type window layer 334 Second tunnel junction layer 3341 Second p-type tunnel junction layer 3342 Second n-type tunnel junction layer 340 First semiconductor stack structure 350 Second semiconductor stack structure

Claims

1. a semiconductor laminate having at least one semiconductor laminate structure in which an active layer and a tunnel junction layer are laminated; a first n-type electrode and a second n-type electrode sandwiching the semiconductor laminate; Equipped with the tunnel junction layer is composed of a p-type InAlAsSbP layer lattice-matched to InAs and an n-type InAlAsSbP layer; The emission center wavelength is 2000 nm to 5000 nm. Optical semiconductor element.

2. The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ is less than The optical semiconductor element according to claim 1 .

3. the p-type InAlAsSbP layer is located on the active layer side of the tunnel junction layer; a p-type electron blocking layer between the active layer and the tunnel junction layer; the total thickness of the layers between the active layer and the tunnel junction layer is 100 nm or less; The optical semiconductor element according to claim 1 .

4. a first semiconductor laminated structure in which a first active layer and a first tunnel junction layer are laminated; a semiconductor laminate including a second semiconductor laminate structure in which a second active layer and a second tunnel junction layer are laminated; a first n-type electrode and a second n-type electrode sandwiching the semiconductor laminate; the first tunnel junction layer and the second tunnel junction layer are each made of a p-type InAlAsSbP layer and an n-type InAlAsSbP layer lattice-matched to InAs, The emission center wavelength is 2000 nm to 5000 nm. Optical semiconductor element.

5. The first tunnel junction layer and the second tunnel junction layer have a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ is less than The optical semiconductor element according to claim 4 .

6. the first active layer and the second active layer have a quantum well structure, and a first wavelength and a second wavelength emitted by the first active layer and the second active layer, respectively, are the same as or similar to each other; The optical semiconductor element according to claim 4 .

7. the p-type InAlAsSbP layer is located on the first active layer side of the first tunnel junction layer; a p-type electron blocking layer between the first active layer and the first tunnel junction layer; the total thickness of the layers between the first active layer and the first tunnel junction layer is 100 nm or less; The optical semiconductor element according to claim 4 .

8. the n-type InAlAsSbP layer is located on the second active layer side of the first tunnel junction layer; a spacer layer between the first tunnel junction layer and the second active layer; the total thickness of the layers between the first tunnel junction layer and the second active layer is 100 nm or less; The optical semiconductor element according to claim 4 .

9. forming a semiconductor laminate having at least one semiconductor laminate structure in which an active layer and a tunnel junction layer are laminated on an n-type substrate; forming a first n-type electrode and a second n-type electrode; Including, the step of forming the tunnel junction layer includes the step of forming an n-type InAlAsSbP layer on a p-type InAlAsSbP layer in which the tunnel junction layer is lattice-matched to InAs; The emission center wavelength is 2000 nm to 5000 nm. A method for manufacturing an optical semiconductor element.

10. The tunnel junction layer has a dopant concentration of 1.0×10 １８ atoms / cm ３ Above 1.0 x 10 １９ atoms / cm ３ is less than The method for manufacturing an optical semiconductor element according to claim 9 .

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