Semiconductor Devices

Abstract

To provide a semiconductor device in which separation between a mold resin and a semiconductor chip can be suppressed.SOLUTION: In a semiconductor device in which a semiconductor chip 10 is sealed in a mold resin 60, the semiconductor chip 10 has a constitution that has a cell region 11 in which a semiconductor element is formed and an outer peripheral region 12 which surrounds the cell region 11, and a protection film 140 is formed in the outer peripheral region 12 at one surface side 100a of a semiconductor substrate 100. And, the protection film 140 has a surface 141 being opposite side of the semiconductor substrate 100 side roughened.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device in which a semiconductor chip is sealed with a molding resin. [Background technology]

[0002] Conventionally, semiconductor devices in which a semiconductor chip is sealed with a mold resin have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a semiconductor chip is disposed on a support member, and a mold resin is disposed so as to seal the support member and the semiconductor chip. The semiconductor chip has a cell region and an outer peripheral region surrounding the cell region, and is configured such that, for example, a MOSFET (short for Metal Oxide Semiconductor Field Effect Transistor) element is formed in the cell region.

[0003] In this semiconductor device, a groove is formed in the support member, and the molding resin is prevented from entering the groove and peeling off from the support member. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-216459 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when the inventors of the present invention studied a semiconductor device in which the semiconductor chip is sealed with a mold resin, they found that the mold resin may peel off from the outer edge of the semiconductor chip as well. If the peeling extends to the inner edge of the semiconductor chip, the breakdown voltage of the semiconductor element may change, or wires connected to the semiconductor chip may break.

[0006] In view of the above, an object of the present invention is to provide a semiconductor device that can prevent separation of a molding resin and a semiconductor chip. [Means for solving the problem]

[0007] In claim 1 for achieving the above object, a semiconductor device in which a semiconductor chip (10) is sealed in a mold resin (60) is provided, the semiconductor chip comprising: a support member (20) having one surface (21a); ​​a semiconductor substrate (100) having one surface (100a) and another surface (100b) and on which a semiconductor element is formed; the semiconductor chip being arranged on the support member with the other surface side facing the support member; and a mold resin sealing the support member and the semiconductor chip; the semiconductor chip having a cell region (11) in which the semiconductor element is formed and a peripheral region (12) surrounding the cell region; and a protective film (140) formed on the peripheral region on one surface side of the semiconductor substrate, the protective film having a surface (141) opposite to the semiconductor substrate side that is roughened. The protective film has a surface roughness of 2 nm or more, and the protective film has a surface roughness of less than 5 nm. .

[0008] According to this, the surface of the protective film is roughened, which makes it possible to prevent a decrease in the adhesive strength between the protective film and the molding resin, and to prevent the molding resin from peeling off from the semiconductor chip.

[0009] Furthermore, since the molding resin is prevented from peeling off from the semiconductor chip, the peeling can be prevented from reaching the inner edge of the semiconductor chip.

[0010] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of the semiconductor chip in FIG. [Figure 3]FIG. 3 is a cross-sectional view taken along line III-III in FIG. [Figure 4] FIG. 10 is a diagram showing the relationship between the surface roughness of a protective film and the adhesion strength of the protective film. [Figure 5A] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor chip. [Figure 5B] 5B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 5A. [Figure 5C] FIG. 5C is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 5B. [Figure 5D] 5D is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 5C. [Figure 5E] FIG. 5E is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 5D. [Figure 5F] FIG. 5B is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 5E. [Figure 5G] FIG. 5C is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 5F. [Figure 5H] FIG. 5C is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 5G. [Figure 6] FIG. 10 is a cross-sectional view of a semiconductor chip according to a second embodiment. [Figure 7A] 10A to 10C are cross-sectional views illustrating a manufacturing process of a semiconductor chip according to a second embodiment. [Figure 7B] 7B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 7A. [Figure 7C] 7C is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 7B. [Figure 7D] 7D is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 7C. [Figure 7E] FIG. 7D is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 7D. [Figure 7F] FIG. 7B is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 7E. [Figure 7G] FIG. 7B is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 7F. [Figure 7H] 7B is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 7G. [Figure 8]FIG. 10 is a cross-sectional view of a semiconductor chip according to a third embodiment. [Figure 9A] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor chip according to a third embodiment. [Figure 9B] 9B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 9A. [Figure 9C] 9C is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 9B. [Figure 9D] 9D is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 9C. [Figure 9E] FIG. 9E is a cross-sectional view showing the manufacturing process of the semiconductor chip subsequent to FIG. 9D. [Figure 10] FIG. 10 is a cross-sectional view of a semiconductor chip according to a fourth embodiment. [Figure 11A] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor chip according to a fourth embodiment. [Figure 11B] 11B is a cross-sectional view showing a manufacturing process of the semiconductor chip subsequent to FIG. 11A. [Figure 12] FIG. 10 is a cross-sectional view of a semiconductor chip according to a fifth embodiment. [Figure 13] FIG. 13 is a plan view of a semiconductor chip according to a sixth embodiment. [Figure 14] FIG. 13 is a plan view of a semiconductor chip according to a seventh embodiment. [Figure 15] FIG. 13 is a plan view of a semiconductor chip according to an eighth embodiment. [Figure 16] FIG. 13 is a plan view of a semiconductor chip according to a ninth embodiment. [Figure 17] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. [Figure 18] FIG. 10 is a cross-sectional view of a semiconductor device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals.

[0013] (First embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is preferably mounted on a vehicle such as an automobile and used as a device for driving various electronic devices for the vehicle.

[0014] 1, the semiconductor device of this embodiment includes a semiconductor chip 10, a first lead frame 20, a block body 30, a second lead frame 40, and a control terminal portion 50. The semiconductor device also includes a mold resin 60 that integrally seals these components. In this embodiment, the first lead frame 20 corresponds to a support member.

[0015] The specific configuration of the semiconductor chip 10 will be described later, but as shown in Fig. 2, it has a configuration including a cell region 11 and a peripheral region 12. In the cell region 11, as shown in Fig. 3, a MOSFET element having a gate electrode 118, a source electrode 121, a drain electrode 123, etc. is formed. In the peripheral region 12, as shown in Fig. 2, a pad portion 13 connected to the gate electrode 118, etc. is formed.

[0016] The first lead frame 20 is made of a material with excellent conductivity, such as copper or 42 alloy, and has a shape in which the mounting portion 21 and the main terminal portion 22 are integrally formed. The first lead frame 20 has the semiconductor chip 10 mounted on one surface 21a of the mounting portion 21 via a joining member 71, such as solder. The mounting portion 21 and the main terminal portion 22 may be provided as separate bodies.

[0017] The block body 30 is a rectangular parallelepiped made of a conductive material such as copper or aluminum, and is disposed on the source electrode 121 of the semiconductor chip 10 via a bonding member 72 such as solder.

[0018] Like the first lead frame 20, the second lead frame 40 is made of a highly conductive material such as copper or a 42 alloy, and has a shape in which a mounting portion 41 and a main terminal portion 42 are integrally formed. The second lead frame 40 is arranged so that one surface 41a of the mounting portion 41 is connected to a joining member 73 such as solder arranged on the block body 30. Note that the mounting portion 41 and the main terminal portion 42 may be provided as separate bodies.

[0019] The control terminal section 50 is disposed near the semiconductor chip 10 and is electrically connected to the pad section 13 formed on the semiconductor chip 10 via a wire 80 .

[0020] The molded resin 60 is made of a resin material such as epoxy resin. The molded resin 60 is arranged so that the other surface 21b opposite to the one surface 21a of the mounting portion 21 of the first lead frame 20 and the other surface 41b opposite to the one surface 41a of the mounting portion 41 of the second lead frame 40 are exposed. The molded resin 60 is also arranged so that portions of the main terminals 22, 42 and the control terminals 50 are exposed. Therefore, the semiconductor device of this embodiment is a semiconductor device with a so-called double-sided heat dissipation structure. The molded resin 60 may be mixed with an additive such as silica (not shown) to adjust the thermal expansion coefficient.

[0021] The above is the basic configuration of the semiconductor device of this embodiment. Next, the configuration of the semiconductor chip 10 of this embodiment will be specifically described with reference to Figures 2 and 3. Note that the semiconductor chip 10 in Figure 3 is a cross-sectional view taken along line III-III in Figure 2, with the bonding member 72 and molded resin 60 partially shown to make it easier to understand their positional relationships. Similarly, in each of the figures corresponding to Figure 3 described below, the bonding member 72 and molded resin 60 are partially shown to make it easier to understand their positional relationships.

[0022] As shown in Fig. 2, the semiconductor chip 10 has a planar shape with corners, and in this embodiment, is a rectangular plate. As shown in Fig. 3, a trench-gate MOSFET element is formed as a semiconductor element in the cell region 11 of the semiconductor chip 10. In this embodiment, the peripheral region 12 includes a guard ring region 12a and a connecting region 12b disposed inside the guard ring region 12a. In other words, the peripheral region 12 includes the guard ring region 12a and the connecting region 12b disposed between the cell region 11 and the guard ring region 12a.

[0023] In this embodiment, the semiconductor chip 10 is configured using a silicon carbide (hereinafter also referred to as SiC) substrate as the semiconductor substrate 100. However, the semiconductor substrate 100 may be configured using a silicon substrate or a gallium nitride substrate instead of a SiC substrate.

[0024] The semiconductor substrate 100 of this embodiment is made of SiC and has a high-concentration impurity layer. + The substrate 111 is a n-type substrate made of SiC with a lower impurity concentration than the substrate 111. - A p-type drift layer 112 is epitaxially grown. A p-type base region 113 is epitaxially grown on the drift layer 112. In this embodiment, the base region 113 is formed from the cell region 11 to the peripheral region 12. The base region 113 of the cell region 11 has an n-type impurity in the surface layer. + In the following description, the surface of the semiconductor substrate 100 on the side of the base region 113 is referred to as one surface 100a of the semiconductor substrate 100, and the surface on the side of the substrate 111 is referred to as the other surface 100b of the semiconductor substrate 100.

[0025] The substrate 111 has an n-type impurity concentration of, for example, 1.0×10 19 / cm 3The drift layer 112 has a lower impurity concentration than the substrate 111, and the n-type impurity concentration is, for example, 0.5 to 2.0×10 16 / cm 3 It is said that...

[0026] The base region 113 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 2.0×10 17 / cm 3 The source region 114 has a higher impurity concentration than the drift layer 112, and the n-type impurity concentration in the surface layer is, for example, 2.5×10 18 ~1.0×10 19 / cm 3 , and is composed of a thickness of about 0.5 μm.

[0027] In addition, in the cell region 11, a contact region 115 constituted by a p-type high concentration layer is formed in the surface layer portion of the base region 113. Specifically, this contact region 115 is formed on the opposite side of the source region 114 from a trench 116, which will be described later.

[0028] In the cell region 11, trenches 116, for example, 0.8 μm wide and 1.0 μm deep, are formed so as to extend from the first surface 100a of the semiconductor substrate 100 through the base region 113 and the source region 114 to the drift layer 112. In other words, the base region 113 and the source region 114 are disposed so as to contact the side surfaces of the trenches 116. In this embodiment, the width direction of the trenches 116 is the left-right direction of the paper in FIG. 3, the length direction is the direction perpendicular to the paper, and the depth direction is the direction up and down on the paper. In other words, the trenches 116 in this embodiment extend in a direction intersecting, more specifically, a direction perpendicular to, the stacking direction (hereinafter simply referred to as the stacking direction) of the drift layer 112 and the base region 113. In other words, the trenches 116 extend in one direction in the surface direction of the substrate 111. The trench 116 is formed into a ring-shaped structure by being routed at the tip end in the extension direction. Note that the trench 116 may be formed into a stripe shape with a plurality of trenches formed in parallel at equal intervals.

[0029] The trench 116 is filled with a gate insulating film 117 and a gate electrode 118. Specifically, if the portion of the base region 113 located on the side surface of the trench 116 is defined as a channel region that connects the source region 114 and the drift layer 112 when the MOSFET element is in operation, the gate insulating film 117 is formed on the inner wall surface of the trench 116, including the channel region. The gate insulating film 117 is made of, for example, a thermal oxide film. Then, a gate electrode 118 made of doped polysilicon is formed on the surface of the gate insulating film 117.

[0030] The gate insulating film 117 is formed on surfaces other than the inner wall surfaces of the trench 116. Specifically, the gate insulating film 117 is formed so as to cover a portion of one surface 100a of the semiconductor substrate 100. More specifically, the gate insulating film 117 is formed so as to cover a portion of the surface of the source region 114. In addition, a contact hole 117a exposing the contact region 115 and the remaining portion of the source region 114 is formed in the gate insulating film 117 in a portion different from the portion where the gate electrode 118 is disposed.

[0031] The gate insulating film 117 is also formed on the surface of the base region 113 in the peripheral region 12, and on the surface of a recessed portion 131, which will be described later. The gate electrode 118 extends onto the surface of the gate insulating film 117 in the connecting region 12b of the peripheral region 12. The trench gate structure of this embodiment is configured in the above manner.

[0032] An interlayer insulating film 119 is formed on one surface 100a of the semiconductor substrate 100 so as to cover the gate electrode 118, the gate insulating film 117, etc. The interlayer insulating film 119 is made of BPSG (abbreviation of borophosphosilicate glass) or the like.

[0033] A contact hole 119a is formed in the interlayer insulating film 119, which communicates with the contact hole 117a and exposes the source region 114 and the contact region 115. In addition, in a cross section different from that in FIG. 3, a contact hole is also formed in the interlayer insulating film 119, which exposes a portion of the gate electrode 118 that extends to the connecting region 12b.

[0034] The contact hole 119a formed in the interlayer insulating film 119 is formed to communicate with the contact hole 117a formed in the gate insulating film 117, and functions together with the contact hole 117a as a single contact hole. For this reason, hereinafter, the contact holes 117a and 119a will be collectively referred to as contact holes 120. The contact holes 120 may have any pattern, and may be, for example, a pattern in which a plurality of squares are arranged, a pattern in which rectangular lines are arranged, or a pattern in which lines are lined up. In this embodiment, the contact holes 120 are linear along the longitudinal direction of the trench 116.

[0035] A source electrode 121 is formed on the interlayer insulating film 119, and is electrically connected to the source region 114 and the contact region 115 through a contact hole 120. Also, in a cross section different from that of FIG. 3, a gate wiring is formed on the interlayer insulating film 119, and is electrically connected to the gate electrode 118 through a contact hole that exposes the gate electrode 118. The gate wiring is routed appropriately and electrically connected to one of the pad portions 13 shown in FIG. 2. The source electrode 121 is formed over the entire cell region 11, and its area is made sufficiently larger than that of the pad portion 13.

[0036] The source electrode 121 and the gate wiring are made of, for example, an Al-Si layer. However, the materials constituting the source electrode 121 and the gate wiring are not limited to this, and may be made of only Al or other materials containing Al as a main component. In this embodiment, the source electrode 121 is formed up to the boundary between the cell region 11 and the peripheral region 12.

[0037] A plating layer 122 for improving solder wettability when connecting to an external device is formed on the source electrode 121. For example, this plating layer 122 is formed by laminating a nickel plating layer and a gold plating layer in this order from the source electrode 121 side.

[0038] A drain electrode 123, which corresponds to a second electrode and is electrically connected to the substrate 111, is formed on the back surface of the substrate 111 (i.e., the other surface 100b of the semiconductor substrate 100). With this structure, an n-channel type inversion trench gate structure MOSFET element is formed.

[0039] Although not described in detail, current sensors, temperature sensors, etc. are also appropriately formed on the semiconductor chip 10. These sensors are appropriately electrically connected to the pads 13 shown in FIG.

[0040] Furthermore, in the peripheral region 12, a recessed portion 131 is formed that extends from the one surface 100a side of the semiconductor substrate 100 to the drift layer 112. In this embodiment, the recessed portion 131 is formed from the connecting region 12b to the guard ring region 12a, and has the same depth as the trench 116. Furthermore, the recessed portion 131 in this embodiment is partially recessed so as to have opposing side surfaces. In other words, the recessed portion 131 in this embodiment is formed inside the peripheral region 12, and is not formed so as to reach the outer edge of the semiconductor chip 10.

[0041] In the guard ring region 12a, a plurality of p-type guard rings 124 are provided in the surface layer of the drift layer 112 located below the recessed portion 131 so as to surround the cell region 11. In this embodiment, the top surface layout of the guard rings 124 is a square with rounded corners, a circle, or the like when viewed from the stacking direction.

[0042] The guard ring 124 of this embodiment is formed by, for example, ion implantation, as will be described later. Viewed from the stacking direction means viewed from the normal direction to the surface direction of the substrate 111. Although not shown, the guard ring region 12a may be provided with an EQR (abbreviation for Equi Potential Ring) structure or the like on the outer periphery of the guard ring 124, if necessary.

[0043] In the connecting region 12b, a p-type resurf layer 125 is formed in the surface layer portion of the drift layer 112. For example, when viewed from the stacking direction, the resurf layer 125 is extended to surround the cell region 11 and reach the guard ring region 12a. This allows the equipotential lines to be guided toward the guard ring region 12a, preventing electric field concentration in the connecting region 12b. This prevents a decrease in breakdown voltage.

[0044] As described above, the gate insulating film 117 and the interlayer insulating film 119 are formed up to the peripheral region 12, and are formed along the wall surface of the recess 131 in the portion of the peripheral region 12 where the recess 131 is formed. However, the gate insulating film 117 and the interlayer insulating film 119 are formed so as not to fill the recess 131.

[0045] Moreover, a protective film 140 is formed on the surface 100a of the semiconductor substrate 100 so as to expose the plating layer 122. In other words, the protective film 140 is formed in the connecting region 12b and the guard ring region 12a on the surface 100a of the semiconductor substrate 100. The protective film 140 is made of polyimide, nitride film, or the like.

[0046] In this embodiment, the surface 141 of the protective film 140 opposite the semiconductor substrate 100 is defined as a surface 141. To improve adhesion to the mold resin 60, the surface roughness Ra of the surface 141 is set to 5 nm or more. That is, as shown in FIG. 4 , when the surface roughness Ra of the protective film 140 is less than 5 nm, the greater the surface roughness Ra, the stronger the adhesion between the protective film 140 and the mold resin 60. However, when the surface roughness Ra is 5 nm or more, the adhesion strength between the protective film 140 and the mold resin 60 remains almost unchanged. Therefore, the surface roughness Ra of the protective film 140 is set to 5 nm or more. While FIG. 4 shows the results when the protective film 140 is made of polyimide, similar results would be obtained if the protective film 140 were made of a nitride film or the like. The surface roughness 141 of the protective film 140 is adjusted, for example, by blasting.

[0047] The protective film 140 has a concave-convex structure 150 formed on a surface 141 opposite to the semiconductor substrate 100. In this embodiment, the protective film 140 has recesses 140a formed in the portions thereof located above the recesses 131, corresponding to the recesses 131, thereby forming the concave-convex structure 150. As shown in FIG. 2, the concave-convex structure 150 of this embodiment is formed in a frame shape along the outer edge of the semiconductor chip 10 so as to surround the cell region 11 and the pad portion 13. The mold resin 60 is arranged so as to fill the recesses 140a.

[0048] In this embodiment, the recess 140a is formed by forming the protective film 140 on the recess 131. Therefore, the recess 131, and the gate insulating film 117 and interlayer insulating film 119 formed on the recess 131 are formed so as to prevent the recess 140a from disappearing when the protective film 140 is formed. For example, if the distance between the interlayer insulating films 119 formed on opposing side surfaces of the recess 131 is d and the thickness of the protective film 140 is t, it is preferable to adjust the size of the recess 131 and the thicknesses of the gate insulating film 117 and interlayer insulating film 119 so that d≧2t holds. The recess 140a has a depth of, for example, about 1 μm.

[0049] In the semiconductor device of this embodiment, since the semiconductor chip 10 has such a configuration, when the mold resin 60 peels off from the semiconductor chip 10, the peeling can be prevented from reaching the source electrode 121 and the like located on the inner edge side. That is, when the mold resin 60 peels off from the semiconductor chip 10, the peeling tends to occur from the outer edge at the interface between the protective film 140 and the mold resin 60. The peeling tends to spread along the interface between the protective film 140 and the mold resin 60. However, in the semiconductor device of this embodiment, since the concave-convex structure 150 is formed, the direction of the peeling changes when the peeling reaches the concave-convex structure 150. Therefore, the extension of the peeling can be prevented, and the peeling can be prevented from reaching the source electrode 121 and the like.

[0050] In this case, it is preferable that the angle θ1 between the surface 141 and the side surface 142a of the recess 140a is 45° or more. That is, when peeling reaches the recess 140a from the outer edge, the stress affecting the peeling is dispersed into a stress in the direction of extension and a stress in the direction along the interface between the protective film 140 and the mold resin 60. Therefore, by setting the angle θ1 to 45° or more, it becomes easier to make the stress in the direction along the interface between the protective film 140 and the mold resin 60 larger than the stress in the direction of extension of the peeling. Therefore, it becomes easier to change the propagation direction of more than half of the stress affecting the peeling, and it is possible to further prevent the peeling from reaching the source electrode 121, etc.

[0051] The above is the configuration of the semiconductor chip 10 and the semiconductor device according to this embodiment. Next, a method for manufacturing the semiconductor chip 10 will be described with reference to Figures 5A to 5H.

[0052] 5A, drift layer 112 and base region 113 are formed on substrate 111 to form semiconductor substrate 100. Drift layer 112 and base region 113 are formed on the surface side of substrate 111 by, for example, epitaxial growth or the like.

[0053] Next, as shown in FIG. 5B, a mask (not shown) is placed on the surface 100a of the semiconductor substrate 100, and ion implantation or the like is performed to form the source region 114 and the contact region 115 in this order.

[0054] 5C, a mask (not shown) is placed on one surface 100a of semiconductor substrate 100, and anisotropic etching or the like is performed to form trench 116 and recessed portion 131. In this embodiment, trench 116 and recessed portion 131 are formed in the same process, so that trench 116 and recessed portion 131 have the same depth. However, trench 116 and recessed portion 131 may be formed in separate processes, so that trench 116 and recessed portion 131 have different depths.

[0055] 5D, a gate insulating film 117 is formed on the wall surfaces of the trench 116, the surface 100a of the semiconductor substrate 100, and the wall surfaces of the recessed portion 131 by thermal oxidation or the like. Then, the gate electrode 118 is formed by CVD (short for chemical vapor deposition), patterning, or the like. Note that the gate electrode 118 is extended to the connecting region 12b as described above.

[0056] Next, as shown in FIG. 5E, a mask (not shown) is placed on the surface 100a of the semiconductor substrate 100, and ion implantation or the like is performed to form the guard ring 124 and the resurf layer 125.

[0057] Thereafter, as shown in Fig. 5F, an interlayer insulating film 119 is formed by a CVD method or the like. Then, a mask (not shown) is placed on the interlayer insulating film 119, and anisotropic etching or the like is performed to form a contact hole 120. Then, as shown in Fig. 5G, a source electrode 121 is formed by a CVD method, patterning, or the like.

[0058] Next, as shown in FIG. 5H, protective film 140 is formed by a CVD method, patterning, or the like. At this time, since protective film 140 is formed on recessed portion 131, recessed portions 140a are formed on surface 141 of protective film 140 due to recessed portion 131, and uneven structure 150 is formed by recessed portions 140a. Note that recessed portion 140a is preferably formed so that angle θ1 formed between surface 141 and side surface 142a is 45° or more, as described above. That is, the conditions for forming protective film 140, the shape of recessed portion 140a, and the thicknesses of gate insulating film 117 and interlayer insulating film 119 are preferably adjusted so that angle θ1 is 45° or more.

[0059] After that, although not shown, the drain electrode 123 and the like are formed on the other surface 100b of the semiconductor substrate 100, thereby completing the semiconductor chip 10.

[0060] According to the present embodiment described above, the surface roughness of the surface 141 of the protective film 140 is set to 5 nm or more. This makes it possible to prevent a decrease in the adhesive strength between the protective film 140 and the mold resin 60, and to prevent the mold resin 60 from peeling off from the semiconductor chip 10.

[0061] Furthermore, the protective film 140 has a concave-convex structure 150 formed on its surface 141. Therefore, when the molding resin 60 peels off from the outer edge of the protective film 140 of the semiconductor chip 10, the direction of the peeling can be changed by the concave-convex structure 150, thereby reducing the stress that causes the peeling to spread. This prevents the peeling from spreading to the inner edge of the semiconductor chip 10. Furthermore, since the peeling is prevented from reaching the inner edge of the semiconductor chip 10 in this way, a SiC substrate with a high Young's modulus or the like can be used as the semiconductor substrate 100, and the selectivity of the semiconductor substrate 100 can also be improved.

[0062] (1) In this embodiment, the recessed portion 131 is formed in the semiconductor substrate 100, thereby forming the recessed portion 140a on the surface of the protective film 140. Therefore, the recessed portion 140a can be formed on the surface 141 of the protective film 140 by an easy method.

[0063] (2) In the semiconductor device described above, when the molding resin 60 peels off from the semiconductor chip 10, the molding resin 60 is likely to peel off from the outer edge of the semiconductor chip 10. For this reason, by forming the uneven structure 150 to surround the cell region 11 and the pad portion 13 as in this embodiment, the uneven structure 150 is formed between the starting point of peeling and the source electrode 121 or the pad portion 13. Therefore, the uneven structure 150 can effectively prevent the peeling from reaching the source electrode 121 or the pad portion 13.

[0064] (2) In this embodiment, the angle θ1 between the surface 141 and the side surface 142a of the recess 140a is set to 45° or more. This makes it easier to increase the stress along the interface between the protective film 140 and the molding resin 60 compared to the stress in the direction of the peeling (i.e., the surface direction of the semiconductor substrate 100). This further prevents the peeling from reaching the inner edge of the semiconductor chip 10.

[0065] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the configuration of the recess 140a is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0066] 6, the semiconductor chip 10 of this embodiment does not have a recessed portion 131 or a resurf layer 125 formed in the semiconductor substrate 100. The guard ring 124 is formed from the one surface 100a side of the semiconductor substrate 100.

[0067] Furthermore, in the semiconductor chip 10, a stopper wiring 160 is formed on a gate insulating film 117 formed on one surface 100a of the semiconductor substrate 100, closer to the outer edge than the guard ring 124. Note that the stopper wiring 160 in this embodiment is not electrically connected to other electrodes or the like and is at a floating potential. In other words, the stopper wiring 160 in this embodiment is made of a dummy wiring. Furthermore, the stopper wiring 160 in this embodiment is made of the same material as the gate electrode 118. In this embodiment, the stopper wiring 160 corresponds to a stopper member.

[0068] The interlayer insulating film 119 has an opening 119b formed in a portion covering the stopper wiring 160 to expose a part of the stopper wiring 160. In this embodiment, the opening 119b is formed simultaneously with the contact hole 120, as will be described later.

[0069] As described above, the protective film 140 is disposed on the interlayer insulating film 119. The protective film 140 is disposed so as to fill the opening 119b of the interlayer insulating film 119, and a recess 140a depending on the opening 119b is formed on the surface 141 side.

[0070] In this embodiment, since the opening 119b is formed closer to the outer edge than the guard ring 124, the recess 140a is also formed closer to the outer edge than the guard ring 124. For this reason, when the guard ring 124 has rounded corners, the uneven structure 150 is preferably arranged in the stacking direction so that the rounded corners include a portion where the guard ring 124 is not arranged. This makes it possible to prevent the semiconductor chip 10 from becoming larger.

[0071] The above is the configuration of the semiconductor chip 10 in this embodiment. Next, a method for manufacturing the semiconductor chip 10 will be described with reference to Figures 7A to 7H.

[0072] In this embodiment, as shown in Fig. 7A, a semiconductor substrate 100 having a drift layer 112 is prepared. Then, as shown in Fig. 7B, a mask (not shown) is placed and ion implantation or the like is performed to sequentially form a base region 113, a source region 114, a contact region 115, and a guard ring 124.

[0073] 7C, a process similar to that of Fig. 5C is carried out to form trenches 116. However, in this embodiment, recessed portions 131 are not formed.

[0074] 7D and 7E, a gate insulating film 117 and a gate electrode 118 are formed in this order by performing a process similar to that of FIG. 5D. In this embodiment, as shown in FIG. 7E, when the gate electrode 118 is formed by patterning, the stopper wiring 160 is also formed at the same time. Therefore, the stopper wiring 160 in this embodiment is made of the same material as the gate electrode 118.

[0075] 7F, the same process as that of FIG. 5F is performed to form an interlayer insulating film 119 and form a contact hole 120 in the interlayer insulating film 119. In this embodiment, an opening 119b that exposes the stopper wiring 160 is also formed at the same time. At this time, the stopper wiring 160 can prevent the semiconductor substrate 100 from being etched by the etching that is performed to expose the opening 119b. In other words, the stopper wiring 160 of this embodiment also functions as an etching stopper.

[0076] Next, as shown in Fig. 7G, a process similar to that of Fig. 5G is performed to form source electrode 121. Thereafter, as shown in Fig. 7H, a process similar to that of Fig. 5H is performed to form protective film 140. At this time, since protective film 140 is formed on opening 119b, recessed portion 140a resulting from opening 119b is formed on surface 141 of protective film 140.

[0077] After that, although not shown, the drain electrode 123 and the like are formed on the other surface 100b of the semiconductor substrate 100, thereby completing the semiconductor chip 10.

[0078] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the first embodiment can be obtained.

[0079] (1) In this embodiment, the recess 140a is formed in the surface of the protective film 140 by forming the opening 119b in the interlayer insulating film 119. Even when the recess 140a is formed in the surface 141 of the protective film 140 in this manner, the recess 140a can be formed in the surface 141 of the protective film 140 by a simple method. Furthermore, in this embodiment, the stopper wiring 160 is formed so as to be exposed from the opening 119b. Therefore, when the opening 119b is formed in the interlayer insulating film 119, etching of the semiconductor substrate 100 can be suppressed. Note that the stopper wiring 160 may be made of a different material from that of the gate electrode 118, or may be made of an insulating material.

[0080] (2) In this embodiment, the stopper wiring 160 is made of the same material as the gate electrode 118 and is formed at the same time when the gate electrode 118 is formed. The opening 119b in the interlayer insulating film 119 is formed at the same time when the contact hole 120 is formed. Therefore, the recess 140a can be formed in the surface 141 of the protective film 140 while suppressing an increase in the number of manufacturing steps.

[0081] (3) In this embodiment, the concave-convex structure 150 is formed closer to the outer edge than the guard ring 124. Therefore, when the molding resin 60 peels off from the outer edge of the semiconductor chip 10, the peeling can be prevented from spreading quickly.

[0082] (Third embodiment) A third embodiment will be described. This embodiment is different from the second embodiment in that the configuration of the recess 140a is changed. As the rest is the same as the second embodiment, a description thereof will be omitted here.

[0083] 8, in the semiconductor chip 10 of this embodiment, a recess 140a is formed in the surface 141 of the protective film 140, but an opening 119b is not formed in the interlayer insulating film 119. In addition, the stopper wiring 160 in the second embodiment is not arranged.

[0084] The above is the configuration of the semiconductor chip 10 in this embodiment. Next, a method for manufacturing the semiconductor chip 10 will be described with reference to Figures 9A to 9E.

[0085] 7A to 7C, as shown in Fig. 9A, a process similar to that of Fig. 5D is carried out to form the gate insulating film 117 and the gate electrode 118. However, in this embodiment, the gate electrode 118 is formed so as not to form the stopper wiring 160.

[0086] 9B, a process similar to that shown in FIG. 7F is performed to form an interlayer insulating film 119, and a contact hole 120 is formed in the interlayer insulating film 119. Subsequently, as shown in FIG. 9C, a process similar to that shown in FIG. 7G is performed to form a source electrode 121.

[0087] 9D, a process similar to that of FIG. 7H is performed to form a protective film 140. In this embodiment, since the opening 119b is not formed, the surface 141 is substantially flattened after the process of FIG. 9D is performed.

[0088] 9E, the protective film 140 is etched using a photoresist (not shown) as a mask, thereby forming a recess 140a in the protective film 140. After that, although not particularly shown, the drain electrode 123 and the like are formed on the other surface 100b of the semiconductor substrate 100, thereby manufacturing the semiconductor chip 10.

[0089] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the first embodiment can be obtained.

[0090] (1) In this embodiment, the recesses 140a are formed by etching on the surface of the protective film 140. This makes it easy to adjust the shape of the recesses 140a, and makes it easy to fine-tune the angle θ1 between the surface 141 and the side surface 142a.

[0091] (Fourth embodiment) A fourth embodiment will be described. In this embodiment, convex portions are formed on the surface 141 of the protective film 140 in comparison with the third embodiment. As the rest is the same as the third embodiment, a description thereof will be omitted here.

[0092] In the semiconductor chip 10 of this embodiment, as shown in FIG. 10, a convex wiring 170 is formed on the interlayer insulating film 119 on the outer edge side of the guard ring 124. The convex wiring 170 is not electrically connected to other electrodes, etc., and is at a floating potential. In other words, the convex wiring 170 of this embodiment is made of a dummy wiring. The convex wiring 170 of this embodiment is made of the same material as the source electrode 121. In this embodiment, the convex wiring 170 corresponds to a convex member.

[0093] As described above, the protective film 140 is disposed on the interlayer insulating film 119, and is disposed so as to cover the convex wiring 170 as well. Therefore, convex portions 140b resulting from the convex wiring 170 are formed on the surface 141 side of the protective film 140. Note that, similar to the first embodiment, it is preferable that the angle θ2 formed between the side surface 142b of the convex portion 140b and the surface 141 is 45° or more. In this embodiment, the concave-convex structure 150 is formed by the convex portions 140b.

[0094] The above is the configuration of the semiconductor chip 10 in this embodiment. Next, a method for manufacturing the semiconductor chip 10 will be described with reference to Figures 11A and 11B.

[0095] 9A and 9B, the source electrode 121 is formed by performing a process similar to that shown in FIG. 9C, as shown in FIG. 11A. In this embodiment, when the source electrode 121 is formed by patterning, the convex wiring 170 is left as shown in FIG. 11A. Therefore, the convex wiring 170 in this embodiment is made of the same material as the source electrode 121.

[0096] 11B, a process similar to that of FIG. 9D is performed to form the protective film 140. At this time, since the protective film 140 is formed on the convex wiring 170, convex portions 140b resulting from the convex wiring 170 are formed on the surface 141 of the protective film 140. After that, although not particularly shown, the drain electrode 123 and the like are formed on the other surface 100b side of the semiconductor substrate 100, thereby manufacturing the semiconductor chip 10.

[0097] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the concave-convex structure 150 is formed on the surface 141, so that it is possible to obtain the same effects as the first embodiment. Note that in this embodiment, the stress direction is changed by the convex portions 140b during peeling.

[0098] (1) In this embodiment, the convex portion wiring 170 is formed on the interlayer insulating film 119, thereby forming the convex portion 140b on the surface of the protective film 140. Even when the convex portion 140b is formed on the surface of the protective film 140 in this way, the convex portion 140b can be formed on the surface 141 of the protective film 140 by a simple method.

[0099] (2) In this embodiment, the convex wiring 170 is made of the same material as the source electrode 121 and is formed at the same time as forming the source electrode 121. Therefore, the convex portion 140b can be formed on the surface 141 of the protective film 140 while suppressing an increase in the number of manufacturing steps.

[0100] (Modification of the fourth embodiment) A modification of the fourth embodiment will be described. In the fourth embodiment, the convex wiring 170 does not have to be made of the same material as the source electrode 121, and may be made of the same material as the other wirings. For example, in the case where the EQR structure is provided, the convex wiring 170 may be made of the same material as the wirings that make up the EQR structure. Furthermore, the convex wiring 170 (i.e., the convex member) may be formed of a different material from the other wirings, or may be made of an insulating material.

[0101] (Fifth embodiment) A fifth embodiment will be described. This embodiment is different from the fourth embodiment in that the configuration of the convex portion 140b is changed. As the rest is the same as the fourth embodiment, a description thereof will be omitted here.

[0102] 12, in the semiconductor chip 10 of this embodiment, a convex portion 140b is formed on the surface 141 of the protective film 140, but no convex portion wiring 170 is formed. Note that the convex portion 140b in this embodiment is formed by arranging a protrusion 180 on the surface of the protective film 140.

[0103] For example, the protrusions 180 are formed by applying a material to form a convex shape using a dispenser, a 3D printer, or the like, and then hardening the material after forming the protective film 140. The protrusions 180 may be made of the same material as the protective film 140, or may be made of a different material.

[0104] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the fourth embodiment can be obtained.

[0105] (Sixth embodiment) A sixth embodiment will be described. This embodiment is different from the first embodiment in that the location where the concave-convex structure 150 is formed is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0106] 13, in the semiconductor chip 10 of this embodiment, the concave-convex structure 150 is separated into multiple parts and is formed near each corner of the semiconductor chip 10. Specifically, the concave-convex structure 150 is arranged in the outer peripheral region 12 between the corner of the semiconductor chip 10 and the cell region 11 and the pad portion 13.

[0107] The location of the concave-convex structure 150 of this embodiment can also be applied to the second to fifth embodiments. When the guard ring 124 has rounded corners, it is preferable that the concave-convex structure 150 is arranged in the stacking direction so as to include a portion where the guard ring 124 is not arranged due to the rounding. This can prevent the semiconductor chip 10 from becoming large.

[0108] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the first embodiment can be obtained.

[0109] (1) In the semiconductor device described above, when the molding resin 60 peels off from the semiconductor chip 10, the molding resin 60 is likely to peel off from the outer edge of the semiconductor chip 10, but the molding resin 60 is particularly likely to peel off from the corners of the semiconductor chip 10. For this reason, by arranging the uneven structure 150 between the corners of the semiconductor chip 10 and the cell region 11 and pad portion 13, as in this embodiment, the uneven structure 150 can effectively prevent the peeling from reaching the source electrode 121 and pad portion 13.

[0110] (Seventh embodiment) A seventh embodiment will be described. This embodiment is different from the first embodiment in that the location where the concave-convex structure 150 is formed is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0111] First, in the semiconductor chip 10 described above, the source electrode 121 has a plane area that is sufficiently larger than that of the pad portion 13. Therefore, if the molding resin 60 peels off from the semiconductor chip 10 and the peeling reaches the pad portion 13, the impact will be greater than if the peeling reaches the source electrode 121.

[0112] Therefore, in the semiconductor chip 10 of this embodiment, as shown in FIG. 13, the concave-convex structure 150 is formed so as to surround each pad portion 13.

[0113] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the first embodiment can be obtained.

[0114] (1) In this embodiment, the concave-convex structure 150 is formed so as to surround the pad portion 13. This makes it possible to prevent peeling from reaching at least the pad portion 13, which is most affected by peeling. Furthermore, since the space around the pad portion 13 is wide due to restrictions on the wire bonding device, etc., arranging the concave-convex structure 150 in this space makes it possible to prevent the semiconductor chip 10 from becoming larger.

[0115] (Eighth embodiment) An eighth embodiment will be described. This embodiment is different from the seventh embodiment in that the location where the concave-convex structure 150 is formed is changed. As the rest is the same as the seventh embodiment, a description thereof will be omitted here.

[0116] First, in the semiconductor chip 10 described above, wiring is formed connecting the pad portion 13 and the cell region 11, but this wiring may make it difficult to form the concave-convex structure 150 so as to surround the pad portion 13. For this reason, in the semiconductor chip 10 of this embodiment, as shown in FIG. 15 , the concave-convex structure 150 is formed so as to substantially surround the pad portion 13 rather than completely surround the pad portion 13. In this embodiment, the concave-convex structure 150 is formed in a substantially U-shape so as not to block the portion of the pad portion 13 on the cell region 11 side. In other words, the concave-convex structure 150 is formed so as not to intersect with the imaginary line connecting the pad portion 13 and the cell region 11. However, when the molding resin 60 peels off as described above, peeling is likely to occur from the corners of the semiconductor chip 10, so it is preferable that the concave-convex structure 150 be formed at least between the corners of the pad portion 13 and the semiconductor chip 10.

[0117] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the first embodiment can be obtained.

[0118] (1) Even if the pad portion 13 is not completely surrounded by the concave-convex structure 150 as in this embodiment, the concave-convex structure 150 can prevent peeling from reaching the pad portion 13, and therefore, the same effect as in the seventh embodiment can be obtained. Furthermore, by making the pad portion 13 not completely surrounded by the concave-convex structure 150, it becomes easier to arrange connection wiring through the unsurrounded portion, and the degree of freedom in design can be improved.

[0119] (Ninth embodiment) A ninth embodiment will be described. This embodiment is different from the eighth embodiment in that the location where the concave-convex structure 150 is formed is changed. As the rest is the same as the eighth embodiment, a description thereof will be omitted here.

[0120] In the semiconductor chip 10 of this embodiment, as shown in FIG. 16, the concave-convex structure 150 is disposed between the pad portion 13 and the outer edge of the semiconductor chip 10.

[0121] According to the present embodiment described above, the protective film 140 has a surface roughness of 5 nm or more and the uneven structure 150 is formed on the surface 141, so that the same effects as those of the first embodiment can be obtained.

[0122] (1) Even if a concave-convex structure 150 is formed between the pad portion 13 and the outer edge of the semiconductor chip 10 as in this embodiment, the concave-convex structure 150 can prevent peeling from reaching the pad portion 13, thereby achieving the same effect as in the above-mentioned eighth embodiment.

[0123] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0124] For example, in each of the above embodiments, the semiconductor elements formed on the semiconductor chip 10 can be changed as appropriate. Specifically, the semiconductor elements may be MOSFETs of a p-channel type trench gate structure in which the conductivity type of each component is reversed from that of an n-channel type. Furthermore, the semiconductor elements may be configured to have an IGBT formed thereon with a similar structure in addition to a MOSFET. In the case of an IGBT, the n-channel type in the first embodiment may be + The substrate 111 is p + Except for the change to a collector layer of the type described above, this is the same as the MOSFET described in the first embodiment. Furthermore, the gate structure may be a planar gate structure instead of a trench gate structure.

[0125] Furthermore, in each of the above embodiments, the concave-convex structure 150 may be formed so as to reach the outer edge of the semiconductor chip 10 in an unrestricted portion of the semiconductor chip 10. For example, in the above first embodiment, the recess 140a formed on the surface 141 of the protective film 140 may be formed so as to reach the outer edge of the semiconductor chip 10 and may not have an opposing side surface.

[0126] In the above-described embodiments, a semiconductor device including a first lead frame 20 and a second lead frame 40, in which the other surface 21b of the first lead frame 20 and the other surface 41b of the second lead frame 40 are exposed from the mold resin 60, has been described as an example. However, the configuration of the semiconductor device is not limited thereto. For example, the semiconductor device may have a single-sided heat dissipation structure in which heat is dissipated only from the drain electrode 123 side of the semiconductor chip 10. In the single-sided heat dissipation structure, as shown in FIG. 17, a connection terminal 91 may be disposed near the semiconductor chip 10 instead of the second lead frame 40, and the source electrode 121 may be connected to the connection terminal 91 via a wire 81. Furthermore, as shown in FIG. 18, a lead terminal 92 may be disposed on the source electrode 121 via a bonding member 72, and a portion of the lead terminal 92 may be exposed from the mold resin 60. Although not particularly shown, the semiconductor device may be configured such that the molding resin 60 is disposed to cover the other surface 21b of the first lead frame 20 and the other surface 41b of the second lead frame 40.

[0127] The above embodiments can also be combined as appropriate. For example, in the first embodiment, the concave-convex structure 150 may be formed closer to the outer edge than the guard ring 124 when viewed from the stacking direction, as in the second to fifth embodiments. Furthermore, in the second to fifth embodiments, the concave-convex structure 150 may be formed on the guard ring 124, as in the first embodiment. The protective film 140 may include at least one of the recesses 140a of the first to third embodiments and at least one of the protrusions 140b of the fourth and fifth embodiments. That is, the concave-convex structure 150 formed on the protective film 140 may include a plurality of different recesses 140a and protrusions 140b. The locations where the concave-convex structures 150 of the sixth to ninth embodiments are formed can be applied as appropriate to the first to fifth embodiments. [Explanation of symbols]

[0128] 10 Semiconductor chips 11 Cell Area 12 Outer area 20 First lead frame (support member) 100a one side 100b other side 140 Protective film 141 Surface 150 Uneven structure

Claims

1. A semiconductor device in which a semiconductor chip (10) is sealed in a molding resin (60), a support member (20) having one surface (21a) and another surface (21b); a semiconductor substrate (100) having one surface (100a) and another surface (100b) and on which a semiconductor element is formed, the semiconductor chip being placed on the support member with the other surface facing the one surface of the support member; the molding resin sealing the support member and the semiconductor chip, The semiconductor chip has a cell region (11) in which the semiconductor element is formed and a peripheral region (12) surrounding the cell region, and a protective film (140) is formed in the peripheral region on one surface side of the semiconductor substrate, The protective film has a roughened surface (141) opposite to the semiconductor substrate side, The protective film has a surface roughness of 2 nm or more, The protective film has a surface roughness of less than 5 nm.

2. The semiconductor device according to claim 1 , wherein the other surface of the support member is exposed from the molding resin.

3. a lead frame (40) having one surface (41a) and another surface (41b), the one surface being arranged in a state where it faces one surface of the semiconductor substrate of the semiconductor chip; 3. The semiconductor device according to claim 1, wherein the other surface of the lead frame is exposed from the molding resin.

4. 4. The semiconductor device according to claim 3, further comprising a block body (30) made of a conductive material disposed between the lead frame and the semiconductor chip.

5. a main terminal portion (22) electrically connected to the semiconductor chip; 5. The semiconductor device according to claim 1, wherein the main terminal portion extends in a direction along one surface of the support member, and a portion opposite to the semiconductor chip side is exposed from the molding resin.

6. A control terminal portion (50) electrically connected to the semiconductor chip is provided.

6. The semiconductor device according to claim 5, wherein the control terminal portion extends in a direction along one surface of the support member, and a portion opposite to the semiconductor chip side is exposed from the molding resin.

7. The semiconductor device according to claim 6 , wherein the main terminal portion and the control terminal portion are exposed from different portions of the molding resin.

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