Multi-bit cell, multi-bit arithmetic device and method thereof

Abstract

To provide a multi-bit operation apparatus and a method thereof.SOLUTION: A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store an individual weight capacitance, and to generate charge data by performing an operation on the output signal and the weight capacitance.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a multi-bit cell, a multi-bit arithmetic device, and a method thereof. [Background technology]

[0002] Neural network operations also include MAC (multiply-accumulate) operations (or multiply-and-add operations) that repeat multiplication and addition. At a particular node of the neural network, the node value of the previous layer may be multiplied by the weight mapped thereto, and then an appropriate activation function may be applied. To perform such an operation, a memory access operation in which appropriate inputs and weights are loaded at a desired time point, and a MAC operation in which the loaded inputs and weights are multiplied and added may be repeated. Furthermore, operations involving inputs and weights may be required in fields other than neural networks. Instead of using a commonly known digital computer to process operations involving inputs and weights, attempts have been made to use other hardware architectures to more efficiently process operations involving inputs and weights. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] U.S. Patent Application Publication No. 2020 / 0202204 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a multi-bit cell, a multi-bit arithmetic device, and a method thereof. It is also an object of the present invention to provide a computer-readable recording medium having a program recorded thereon for executing the method. The technical problems to be solved by the present invention are not limited to the above-described technical problems, and other technical problems may be inferred from the following embodiments. [Means for solving the problem]

[0005] As a means for solving the above technical problem, a multi-bit cell according to one embodiment includes: a memory storing weight resistors corresponding to multi-bit weights; a current source applying current to the memory so that a weight voltage is generated from the weight resistor; a plurality of multiplexers connected in parallel with each other and in series with the memory, each outputting one of the weight voltages and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected respectively to the plurality of multiplexers, each storing a separate weight capacitance and generating charge data by performing an operation related to the output signal and the weight capacitance.

[0006] A multi-bit arithmetic device according to another aspect includes a plurality of the multi-bit cells, and can output second sum data generated by summing the first sum data output from each of the multi-bit cells.

[0007] According to yet another aspect, a multi-bit operation method includes: generating weight voltages from weight resistors by applying current to a memory storing weight resistors corresponding to multi-bit weights; receiving multi-bit inputs related to a plurality of capacitors, each storing a separate weight capacitance; transmitting one of the weight voltages and a first fixed voltage to each of the plurality of capacitors based on the multi-bit input; and generating charge data to be stored in each of the plurality of capacitors by performing an operation related to the transmitted signal and the weight capacitances.

[0008] A computer-readable recording medium according to yet another embodiment includes a recording medium having a program recorded thereon for executing the above-described method on a computer. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 illustrates a neural network node model according to at least one embodiment. [Figure 2] FIG. 1 illustrates a neural network according to at least one embodiment. [Figure 3A] 1 is a diagram illustrating a multi-bit arithmetic device according to at least one embodiment; [Figure 3B] 1 is a diagram illustrating a multi-bit arithmetic device according to at least one embodiment; [Figure 4] FIG. 1 is a block diagram illustrating the configuration of a multi-bit cell according to at least one embodiment. [Figure 5] FIG. 1 is a circuit diagram of a multi-bit cell according to at least one embodiment. [Figure 6] FIG. 1 is a circuit diagram of a memory according to at least one embodiment. [Figure 7] 1 is a circuit diagram of a multi-bit cell in which a first fixed voltage is output from each of the multiplexers, according to at least one embodiment. [Figure 8]1 is a circuit diagram of a multi-bit cell in which the capacitors all store the same weight capacitance according to at least one embodiment; [Figure 9] FIG. 1 is a circuit diagram of a multi-bit cell according to at least one embodiment in which the multi-bit cell includes multiple memories. [Figure 10] FIG. 1 is a circuit diagram of a multi-bit cell according to at least one embodiment in which the multi-bit cell includes multiple memories. [Figure 11] 1 is a flowchart illustrating a method of operating a multi-bit cell in accordance with at least one embodiment. [Figure 12] 1 is a block diagram illustrating a configuration of a multi-bit arithmetic device according to at least one embodiment. [Figure 13] FIG. 1 is a circuit diagram of a multi-bit arithmetic unit according to at least one embodiment. [Figure 14] 1 is a graph illustrating multi-bit operation time versus digital conversion time according to at least one embodiment. [Figure 15] 1 is a flowchart illustrating a method of operating a multi-bit arithmetic unit according to at least one embodiment. [Figure 16] FIG. 1 is a block diagram illustrating the configuration of a multi-bit arithmetic unit array according to at least one embodiment. [Figure 17] FIG. 1 is a block diagram illustrating an electronic system according to at least one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Throughout the drawings and detailed description, the same reference numerals are used for identical or similar components unless otherwise stated. The drawings may not be to scale, and the relative size, proportions, and description of components in the drawings may be exaggerated for clarity, illustration, and convenience.

[0011] The following detailed description is provided to aid in gaining a comprehensive understanding of the disclosed method, apparatus, and / or system. However, various changes, modifications, and equivalents of the disclosed method, apparatus, and / or system will become apparent after understanding the disclosure of this application. For example, the order of operations disclosed herein is merely exemplary and is not limited to the operations disclosed herein, but may be changed as clearly understood after understanding the disclosure of this application, except for operations that necessarily occur in a specific order. Furthermore, to improve clarity and conciseness after understanding the disclosure of this application, descriptions of features known in the art may be omitted.

[0012] The terms used in this embodiment are currently commonly used terms, and are selected as much as possible while taking into consideration the functions of the embodiment. However, this may vary depending on the intentions of those skilled in the art, precedents, or the emergence of new technologies. In addition, in certain cases, arbitrarily selected terms may be used, and in such cases, their meanings will be described in detail in the description of the embodiment. Therefore, the terms used in this embodiment should be defined based on the meanings of the terms and the overall content of the embodiment, rather than simply by their names.

[0013] In the description of the present embodiment, when a part is said to be connected to another part, this does not only mean that they are directly connected to each other, but also means that they are electrically connected via another component between them. Furthermore, when a part is said to include a component, this does not mean that the other component is excluded, but that the part may further include the other component, unless otherwise specified.

[0014] The terms "comprise" or "include" used in this embodiment should not be construed as including all of the various components or steps described in the specification, but should be construed as including none of the various components or steps, or as including additional components or steps.

[0015] Additionally, terms including ordinal numbers, such as "first" or "second," may be used in this specification to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0016] The following description of the embodiments should not be construed as limiting the scope of the invention, and any matter that can be easily inferred by a person skilled in the art should be construed as falling within the scope of the invention. Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings for illustrative purposes only.

[0017] FIG. 1 illustrates a neural network node model according to at least one embodiment.

[0018] Various attempts have been made to develop computer devices that can efficiently process vast amounts of information by replicating biological neurons or the biological neural network formed by interconnecting biological neurons. The neural network node model 11 is also an example of neuromorphic operations performed by a hardware computing device or hardware computing processor. The neural network node model 11 also includes a multiplication operation that multiplies information from multiple neurons by synaptic weights, an addition operation (Σ) that involves values ​​multiplied by synaptic weights (w0x0, w1x1, w2x2), and an operation that applies a characteristic function (b) and an activation function (f) to the result of the addition operation. The execution of the neuromorphic operations can provide neuromorphic operation results. Here, values ​​such as x0, x1, x2, ... correspond to axon values, and w0, w1, ... correspond to axon values. w2Values ​​such as *, *, ... may correspond to synaptic weights. The nodes, values, and weights of the neural network node model 11 may also be referred to as "neurons," "axon values," and "synaptic weights," respectively, but such references are not intended to convey any connection to the way neural network architectures are computationally mapped or intuitively perceive information, or the way human neurons operate. That is, these terms are merely technical terms referring to the nodes, values, and weights of a hardware implementation of the neural network node model 11.

[0019] FIG. 2 illustrates a neural network (e.g., neural network 20) ​​according to at least one embodiment.

[0020] Referring to FIG. 2, an example of a neural network including a neural network formed by interconnecting nodes, i.e., a neural network 20, is illustrated. The neural network 20 may be an example of a deep neural network (DNN). For ease of explanation, the neural network 20 is illustrated as including two hidden layers, but may include multiple hidden layers. Also, in FIG. 2, the neural network 20 is illustrated as including a separate input layer 21 for receiving input data, but the input data may be directly input to the hidden layer.

[0021] In the neural network 20, nodes in layers other than the output layer are connected to nodes in the next layer via links for transmitting output signals. The nodes can receive the output of an activation function related to the weighted input of a node included in a previous layer via these links. The weighted input is the node's input (node ​​value) multiplied by a weight, where the input corresponds to an axon value and the weight corresponds to a synaptic weight. The weight is also referred to as a parameter of the neural network 20. The activation functions include sigmoid, hyperbolic tangent (tanh), and ReLU (rectified linear unit), and nonlinearity can be formed in the neural network 20.

[0022] The output of any one node 22 included in such a neural network 20 can be expressed as in Equation 1 below.

[0023]

number

[0024] 3A and 3B are diagrams illustrating a multi-bit arithmetic device according to at least one embodiment.

[0025] Here, FIG. 3A is a diagram for explaining the architecture of a multi-bit arithmetic device according to one embodiment, and FIG. 3B is a diagram exemplarily illustrating a neural network including operations performed by the multi-bit arithmetic device of FIG. 3A.

[0026] 3A, the multi-bit arithmetic device 30 includes a plurality of multi-bit cells connected in parallel and an electric power source (e.g., a voltage source or a current source) that applies a voltage or current to the multi-bit cells. Only the minimum components for explaining the neural network of FIG. 3B are shown in FIG. 3A, and other components that may be included in the multi-bit arithmetic device 30 will be described later with reference to FIG. 12.

[0027] The multi-bit cell is a unit circuit included in the multi-bit arithmetic device 30 and receives a multi-bit input. The number of multi-bit cells connected in parallel is not particularly limited and may be, for example, a power of 2. For convenience of explanation, a structure in which three multi-bit cells are connected in parallel will be described as an example.

[0028] Referring to FIG. 3B, a neural network having three nodes in the first layer and two nodes in the second layer is illustrated. The first layer also serves as one of the input layer and hidden layer in FIG. 2. The second layer receives a value obtained by multiplying the output value of the first layer by a weight and inputting the resultant value into an activation function, which has the resultant value as a node value and is also provided as an input to the next layer. Specifically, in the first node a1 of the second layer, for example, three multiplication operations are performed to multiply the output value of the first layer by the weight corresponding to each link, and an addition operation is performed to sum up the resultant values, as shown in Equation 2 below. Here, for convenience of explanation, details related to the activation function will be omitted.

[0029]

number

[0030] The resistance value of the multi-bit cell related to the power supply is determined by the inputs X1, X2, and X3 applied to each multi-bit cell and the weight W 11 ,W 21 ,W 31 The inputs and weights are also multi-bit. Here, input "X1" refers to the output value or node value of the first node (first layer) and means the input applied to the first multi-bit cell. Similarly, input "X2" and input "X3" refer to the input or node value of the second and third nodes, respectively, and mean the inputs applied to the second and third multi-bit cells, respectively. Weight "W 11In ", the left "1" refers to the first node of the first layer, and the right "1" refers to the first node of the second layer. 11 " is the weight associated with the link between the first node of the first layer and the first node of the second layer, and means the weight applied to the first multi-bit cell. Similarly, the weight W 21 and weight W 31 and denote the weights applied to the second and third multi-bit cells, respectively.

[0031] FIG. 4 is a block diagram illustrating the configuration of a multi-bit cell (eg, multi-bit cell 100) in accordance with at least one embodiment.

[0032] 4, the multi-bit cell 100 may include a memory 110, a current source 120, a plurality of multiplexers 130, and a plurality of capacitors 130. The multi-bit cell 100 illustrated in FIG. 4 illustrates components related to the present embodiment. Therefore, after understanding the present disclosure, a person skilled in the art will understand that, in a non-limiting embodiment, the multi-bit cell 100 may further include other general components in addition to the components illustrated in FIG. 4.

[0033] The memory 110 may store the multi-bit weight in the form of a resistor. The multi-bit weight stored in the memory 110 in the form of a resistor is called a weight resistor. If the multi-bit weight is 3 and the corresponding resistance is 12 kΩ, the memory 110 may store the multi-bit weight of 3 in the form of a weight resistor of 12 kΩ. For example, the memory 110 may be a non-volatile memory, such as a resistive random access memory (ReRAM), a phase change memory (PCM), or a magnetic random access memory (MRAM). However, the types of memory 110 described above are merely examples, and any type capable of storing resistance information may be used.

[0034] The current source 120 may apply a current to the memory 110. The current source 120 may apply a constant current to the memory 110 regardless of the magnitude of the resistance or voltage. For example, the current source 120 may apply a DC bias current that sets the operating point of the multi-bit cell 100. Even if the current source 120 applies the same current to the memory 110, the voltage of the memory 110 may vary depending on the resistance of the memory 110. When the current source 120 applies a current to the memory 110, a weight voltage may be generated from the weight resistance stored in the memory 110. According to Ohm's law, the weight voltage may be generated by multiplying the weight resistance by the current. Non-limiting examples of the weight voltage will be described in more detail below with reference to FIG. 5.

[0035] The multi-bit cell 100 can receive a multi-bit input. Unlike a one-bit input that is expressed only as 1 or 0, the multi-bit input can include multiple inputs. For example, the multi-bit input can be composed of the values ​​of each digit that express the multi-bit input. If the multi-bit input is a three-bit input, the multi-bit input can also be expressed as 3'b101, and 2'b102. 2 Digit "1", 2 1 digit "0" and 2 0 In this case, "1", "0" and "1" are possible input values ​​included in the multi-bit input. The multi-bit weight and the number of bits in the multi-bit input are also the same.

[0036] The multiplexer 131 is connected in series with the memory 110 and may receive a wait voltage and a fixed voltage via another line. The fixed voltage is a voltage of a fixed magnitude that is applied to the multiplexer 131 at a fixed level. The multiplexer 131 may also receive one of a plurality of inputs constituting a multi-bit input. The multiplexer 131 may output one of the wait voltage and the fixed voltage based on the received input. For example, the multiplexer 131 may output the wait voltage when it receives a 1 and the fixed voltage when it receives a 0. Non-limiting embodiments of the multiplexer 131 will be described in more detail below with reference to FIG. 5 . Alternatively, the multiplexer 131 may receive multiple fixed voltages and output one of the wait voltage and the multiple fixed voltages based on the multiple inputs. The multiplexer 131 may output one signal to be transmitted to the capacitor 141.

[0037] A plurality of multiplexers 131 may be connected in parallel. A plurality of multiplexers 130 may be connected in series with the memory 110, and may all receive the same signal (a wait voltage and a fixed voltage). The multiplexers 130 may receive a multi-bit input and output one of a wait voltage and a fixed voltage based on the multi-bit input. The signal output by each multiplexer, either a wait voltage or a fixed voltage, may also be determined by the value of the received input. For example, if the multi-bit input is 3'b101, then 2 2 The multiplexer that receives the digit "1" and the 2 0 The multiplexers that receive the "1" digit output the same signal, 1 A multiplexer that receives the digit "0" can output a different signal.

[0038] The capacitor 141 is connected to the multiplexer 131 and may receive a signal output from the multiplexer 131. The capacitor 141 may store a weight capacitance. The capacitor 141 may generate charge data by performing an operation related to the received signal and the weight capacitance. The operation performed by the capacitor 141 will be described in detail below with reference to FIG. 5.

[0039] A plurality of capacitors 141 may be connected in parallel. Each capacitor 130 is also connected in series with a corresponding multiplexer 130. Thus, one capacitor 141 is also connected to one multiplexer 131. Each of the plurality of capacitors 130 may have a separate weight capacitance. The weight capacitances may be different for each capacitor, may be the same for each capacitor, or may only be partially different.

[0040] FIG. 5 is a circuit diagram of a multi-bit cell (eg, multi-bit cell 100) according to at least one embodiment.

[0041] 5, the multi-bit cell 100 also includes a memory 110, a current source 120, a plurality of multiplexers 130, and a plurality of capacitors 131. The multi-bit cell 100 receives a multi-bit input 150, and each input 151 included in the multi-bit input 150 is also input to each multiplexer 131.

[0042] The circuit diagram shown in Fig. 5 only shows components related to this embodiment, and it will be apparent to those skilled in the art that the circuit diagram may further include other general-purpose components in addition to the components shown in Fig. 5.

[0043] 5, the wait voltage and the first fixed voltage are also input to the multiplexer 131. In addition, one input 151 constituting the multi-bit input 150 may be received by the multiplexer 131. The one input 151 received by the multiplexer 131 acts as a selector signal (SEL) for the multiplexer 131, allowing one signal of the wait voltage and the first fixed voltage to be output from the multiplexer 131.

[0044] The one signal output from the multiplexer 131 is also transmitted to the capacitor 141. The one signal output from the multiplexer 131 may be transmitted to the left terminal of the capacitor 141, and a second fixed voltage may be transmitted to the right terminal of the capacitor 141. Therefore, a voltage having a potential difference between the one signal output from the multiplexer 131 and the second fixed voltage may be applied to the capacitor 141. A calculation method related to the multi-bit input 150 and the multi-bit weight will be described in detail below.

[0045] The memory 110 can store weight resistors corresponding to the multi-bit weights. The weight resistor values ​​corresponding to the multi-bit weights can be different for each value of the multi-bit weight. The weight resistors can be set to increase linearly as the multi-bit weights increase. For example, the weight resistors can increase at a constant rate as the multi-bit weights increase at a constant rate, like an arithmetic progression. An example of weight resistors for a 3-bit weight is shown in Table 1.

[0046] [Table 1] The multi-bit cell 100 can generate a weight voltage from a weight resistor by applying a current to the memory 110 using the current source 120. When a current is applied to the weight resistor stored in the memory 110, the current is multiplied by the weight resistor according to Ohm's law, resulting in a weight voltage. Since the current source 120 outputs a constant current, the weight voltage can be proportional to the weight resistor. An example of a weight voltage for a 3-bit weight is shown in Table 2.

[0047] [Table 2] The multi-bit cell 100 can receive a multi-bit input 150 by using a plurality of capacitors 141 that receive a single-bit input 151. The number and weight capacitance of the capacitors 130 are also set to enable reception of the multi-bit input 150.

[0048] For example, the multi-bit cell 100 includes a number of capacitors 130 corresponding to the number of bits of the multi-bit input 150, and the capacitors 130 can store weight capacitances of values ​​corresponding to the number of digits of the multi-bit input 150. When the multi-bit input 150 is 3 bits, the multi-bit input 150 can also be expressed as 3'b000 to 3'b111. The number of digits of the multi-bit input 150 can be 2. 0 , 2 1 and 2 2 In this case, the multi-bit cell 100 includes three capacitors 130, each of which has a capacitance 20 times the unit capacitance and a capacitance 2 times the unit capacitance. 1 times, and 2 of the unit capacitance 2 5, a 3-bit multi-bit input 150 is applied, and three capacitors 130 are shown, each storing a capacitance weight of 1, 2, and 4 times the unit capacitance.

[0049] The capacitor 130 can indirectly receive the multi-bit input 150 via the multiplexer 130. As described above, the multi-bit input 150 includes multiple inputs, and each input is also received by a multiplexer coupled to a corresponding capacitor. The value of each digit of the multi-bit input 150 can be input to a multiplexer coupled to a capacitor corresponding to the value of each digit of the multi-bit input 150. For example, if the multi-bit input 150 is 3 bits, then the value of each digit of the multi-bit input 150 can be input to a multiplexer coupled to a capacitor corresponding to the value of each digit of the multi-bit input 150. 0 The value of the digit is input indirectly to the capacitor CAP0, which stores a capacitance weight of 1 times the unit capacitance, 1 The value of the digit is input indirectly to capacitor CAP1, which stores a capacitance weight twice the unit capacitance, 2 The value of each digit can be indirectly input to a capacitor CAP2, which stores a capacitance weight four times the unit capacitance. The value of each digit of the multi-bit input 150 is directly input to a multiplexer, and the signal output from the multiplexer is transmitted to the capacitor based on the input, so that the value of each digit can be indirectly input to the capacitor.

[0050] When the multi-bit input 150 is 3'b110 (or 6), a 1 is input to the multiplexer corresponding to CAP2, a 1 is input to the multiplexer corresponding to CAP1, and a 0 is input to the multiplexer corresponding to CAP0. An example of the values ​​input to each multiplexer depending on the value of the 3-bit multi-bit input 150 is also shown in Table 3.

[0051] [Table 3] In this way, multiplexer 130 can receive an input of 1 or 0. In multiplexer 130, a multiplexer that receives an input of "1" can output a wait voltage, and a multiplexer that receives an input of "0" can output a first fixed voltage. However, this is merely an example, and various modifications are possible, such as inverting the 0 / 1 logic by setting the multiplexer, or allowing the multiplexer to receive inputs of other types, or determining the signal to output based on multiple inputs. Using the example of Table 3, an example of a signal transmitted from multiplexer 130 to each capacitor is also shown in Table 4.

[0052] [Table 4] The capacitor 141 may receive a signal output from the multiplexer 131 at one end and a second fixed voltage at the opposite end. The capacitor 141 may perform a subtraction or difference operation on the signal output from the multiplexer 131 and the second fixed voltage. Thus, the capacitor 141 may perform a subtraction operation on the second fixed voltage and the weight voltage or the first fixed voltage. The difference is a potential difference across the capacitor 141 and may correspond to the voltage applied to the capacitor 141. For example, if the first fixed voltage is set to have the same value as the second fixed voltage, the difference between the first fixed voltage and the second fixed voltage may correspond to 0V. However, depending on the structure and configuration of the multi-bit cell 100, the first fixed voltage and the second fixed voltage may be set to different values, in which case the difference may correspond to a value other than 0V.

[0053] The magnitude of the second fixed voltage is also set so that the difference between it and the weight voltage is proportional to the multi-bit weight. In the example of Table 2, the second fixed voltage is also 525mV, which is the average value of the weight voltage. The relationship between the weight voltage, the second fixed voltage, and the difference between the weight voltage and the second fixed voltage is summarized in Table 5.

[0054] [Table 5] As shown in Table 5, the magnitude of the second fixed voltage is also set so that the difference value and the multi-bit weight are proportional. In the example of Table 5, the first fixed voltage can also be set to be the same as the second fixed voltage.

[0055] Table 6 shows the multi-bit inputs 150, multi-bit weights, weight voltages according to the multi-bit weights, and the difference between the second fixed voltages and the weight voltages set for each of the multiple multi-bit cells 100 according to the example of Table 2.

[0056] [Table 6] The multi-bit input 150 and multi-bit weight values ​​shown in Table 6 are arbitrarily set based on 3 bits and can be varied in various ways. A "row" in Table 6 can correspond to one multi-bit cell 100. Therefore, Table 6 shows results for 16 multi-bit cells 100.

[0057] Since the first fixed voltage is set to be the same as the second fixed voltage, the capacitor 130 to which the first fixed voltage is transmitted has the same potential across both ends, and the potential difference is 0 V. In this case, the capacitor is applied with a voltage of 0 V and can generate 0 C charge data.

[0058] Table 7 shows the difference values ​​calculated for each capacitor of the multi-bit cell 100, ie, the potential difference across each capacitor, according to the example of the above table.

[0059] [Table 7] The capacitor 141 can generate charge data by multiplying the difference value and the weight capacitance. That is, the capacitor 141 can generate charge data by multiplying the weight capacitance and the difference value (voltage) by the calculation Q=C×V.

[0060] Table 8 shows the charge data generated on each capacitor for the example of Table 7.

[0061] [Table 8] The multi-bit cell 100 may output first summed data generated by summing the charge data generated by each of the capacitors 130. In the example of Table 8, the multi-bit cell 100 corresponding to row 1 may output first summed data of -100 mC, and the multi-bit cell 100 corresponding to row 4 may output first summed data of 1,225 mC. The first summed data of each row may be summed and then converted into a digital signal. A non-limiting example of this will be described below with reference to FIG. 12.

[0062] Meanwhile, the operation method of the multi-bit cell 100 can be verified by comparing the multiplication result of the multi-bit input 150 and the multi-bit weight with the first summed data. The product of the multi-bit input 150 and the multi-bit weight for row 1 is −4, and the product of the multi-bit input 150 and the multi-bit weight for row 4 is 49. Referring to Table 5, it can be confirmed that the difference between the weight voltage and the second fixed voltage is 25 times the multi-bit input 150. Here, the first summed data for row 1 is −4×25mC, and the first summed data for row 4 is 49×25mC, so it can be confirmed that the first summed data corresponds to the above multiplication result.

[0063] Therefore, the multi-bit cell 100 can perform multi-bit operations by receiving the multi-bit input 150 via a plurality of capacitors 130 that store individual capacitance weights, rather than directly multiplying the multi-bit input 150 and the multi-bit weight, and converting the multi-bit weight into a voltage weight.

[0064] FIG. 6 is a circuit diagram of a memory (eg, memory 110 (FIG. 4)) according to at least one embodiment.

[0065] Referring to FIG. 6, the memory 110 also includes a plurality of resistive elements 111 .

[0066] The memory 110 also includes a number of resistance elements 111 corresponding to the number of bits of the multi-bit weight. For example, if the multi-bit weight is N bits, the memory 110 includes 2 N 6, the multi-bit weight is 3 bits, and the memory 110 includes 2 3 It also includes seven resistor elements 111, each of which is -1.

[0067] The resistor elements 111 are also connected in series with each other. The resistor element 111a can store two resistance values, so the memory 110 can store two resistors connected in series. N -One resistor element 111 is used, and 2 N The multi-bit cell 100 is also configured to have resistance values. The multi-bit cell 100 can adjust the weight resistance by controlling the on / off of each of the resistance elements 111. The multi-bit cell 100 determines the on / off of each resistance element via the WR_SEL signal and can apply a current or voltage to each resistance element via the Sub Bit-line[7:0] signal line.

[0068] For example, if the correspondence between multi-bit weights and weight resistances is as shown in Table 1, one resistor element can store 7 kΩ and the remaining resistor elements can store 1 kΩ, or each resistor element can store 1 kΩ or 2 kΩ. The multi-bit cell 100 can store one of the weight resistances 7 kΩ, 8 kΩ, ..., 13 kΩ, or 14 kΩ in the memory 110 by controlling the on / off of the resistor elements 111 connected in series. Therefore, weight resistances from 7 kΩ to 14 kΩ can be represented in 1 kΩ increments from the memory 110.

[0069] The resistive element 111a may be a magnetic tunnel junction (MTJ) or an MRAM, but this is merely an example, and any element that stores resistance and is controlled by a transistor may be a resistive element without limitation.

[0070] FIG. 7 is a circuit diagram of a multi-bit cell (eg, multi-bit cell 100) in accordance with at least one embodiment in which a first fixed voltage is output from each of the multiplexers (eg, multiplexer 130).

[0071] Referring to FIG. 7, in the multi-bit cell 100, if a wait voltage is not used, the current source 120 may be disabled and only the first fixed voltage may be applied to the multiplexer .

[0072] For example, when the multi-bit input 150 is 0, the multi-bit cell 100 does not use a wait voltage and only the first fixed voltage may be applied to the multiplexer 130. The multi-bit input 150 being 0 means that all of the individual inputs 151 constituting the multi-bit input 150 are 0. When the multi-bit input 150 is 3 bits, the multi-bit input 150 being 0 may also be expressed as 3'b000. The multiplexer 130 may receive inputs of all 0. The multiplexer 130 may output the first fixed voltage in response to the input of 0. Because the wait voltage is not transmitted to the capacitor 130, the current source 120 for generating the wait voltage does not need to operate. Therefore, the multi-bit cell 100 may reduce power consumption by turning off the current source 120. For example, the multi-bit cell 100 can control the current applied from the current source 120 to 0 μA using an I_EN signal, which is an enable signal that controls the current source 120.

[0073] However, depending on the structure and configuration of the multi-bit cell 100, all of the multiplexers 130 may output the first fixed voltage in various cases other than when the multi-bit input 150 is 0. When all of the multiplexers 130 output the first fixed voltage, the wait voltage is not used in the multi-bit cell 100, so the current source 120 is controlled to be off, and power consumption of the multi-bit cell 100 may be reduced.

[0074] FIG. 8 is a circuit diagram of a multi-bit cell (eg, multi-bit cell 100) in which the capacitors (eg, capacitor 130) all store the same weight capacitance according to at least one embodiment.

[0075] Referring to FIG. 8, each capacitor 130 can store a weight capacitance of a unit capacitance.

[0076] The multi-bit cell 100 also includes a number of capacitors 130 corresponding to the number of bits of the multi-bit input 150. For example, the multi-bit cell 100 includes 2 capacitors 130 for an N-bit multi-bit input 150. N It may also include one capacitor 130. Here, the weight capacitance stored in the capacitor 130 is also a unit capacitance. N One capacitor 130 has 0 to 2 N A multi-bit input 150 may be received having a value of −1.

[0077] 8, the multi-bit cell 100 can receive inputs in various formats, such as a thermometer code input, a binary input, and a ternary input.

[0078] FIG. 9 is a circuit diagram of a multi-bit cell (eg, multi-bit cell 100) according to at least one embodiment in which the multi-bit cell includes multiple memories.

[0079] Referring to FIG. 9, the memory 110 includes a first memory 110a and a second memory 110b that store different weight resistors, and the multi-bit cell 100 further includes a sign multiplexer 132 that receives a sign input 152.

[0080] The weight resistors of the first memory 110a and the second memory 110b can be variously set, such as having the same absolute value but different signs, or having the same sign but different values. The sign multiplexer 132 is also connected to the first memory 110a and the second memory 110b. The multi-bit cell 100 can receive a sign input 152 in addition to the multi-bit input 150 via the sign multiplexer 132. The sign multiplexer 132 can determine one of the first memory 110a and the second memory 110b to which current from the current source 120 is applied based on the sign input 152. The sign multiplexer 132 can connect a line from the determined memory 110 to the current source 120 so that current is applied to the determined memory 110. The multi-bit cell 100 can generate a weight voltage from the weight resistor stored in the determined memory 110 based on the sign input 152.

[0081] The multi-bit cell 100 can receive more diverse inputs and perform operations related to the various weights by including multiple memories 110 that store different weight resistors. When the resistor weights of the first memory 110a are positive numbers and the resistor weights of the second memory 110b are negative numbers, the multi-bit cell 100 can receive signed integer inputs and perform operations related thereto.

[0082] FIG. 10 is a circuit diagram of a multi-bit cell (eg, multi-bit cell 100) according to at least one embodiment in which the multi-bit cell includes multiple memories.

[0083] 10, the memory 110 includes a first memory 110a and a second memory 110b that store different weight resistors, and the current source 120 includes a first current source 120a that applies a current to the first memory 110a and a second current source 120b that applies a current to the second memory 110b. The multi-bit cell 100 can receive a multi-bit input 150 that includes a sign input.

[0084] The first memory 110a can store a first weight resistor, and the second memory 110b can store a second weight resistor. The first and second weight resistors can be variously set to have the same absolute value but different signs, or the same sign but different values.

[0085] The first current source 120a and the second current source 120b can apply currents of the same magnitude. The first current source 120a can apply a current to the first memory 110a to generate a first weight voltage, and the second current source 120b can apply a current to the second memory 110b to generate a second weight voltage.

[0086] The multiplexers 130 can output one signal from among a first weight voltage, a second weight voltage, and a first fixed voltage based on a multi-bit input 150 including a sign input. For example, the multiplexer 131 can output a first fixed voltage when the absolute value of the input is 0, and can output one signal from among a first weight voltage and a second weight voltage based on the sign input when the absolute value is 1.

[0087] The multi-bit cell 100 can receive more diverse inputs and perform operations related to the various weights by including multiple memories 110 that store different weight resistors. When the resistor weights of the first memory 110a are positive numbers and the resistor weights of the second memory 110b are negative numbers, the multi-bit cell 100 can receive signed integer inputs and perform operations related thereto.

[0088] FIG. 11 is a flowchart illustrating a method of operating a multi-bit cell (eg, multi-bit cell 100) in accordance with at least one embodiment.

[0089] Referring to Figure 11, the method of operating the multi-bit cell is comprised of steps that are processed in time sequence in the multi-bit cell shown in Figure 4. Therefore, even if omitted below, it should be understood that the contents described regarding the multi-bit cell with reference to Figures 4 through 10 also apply to the method of Figure 4.

[0090] In step 1110, the multi-bit cell can generate a weight voltage from a weight resistor by applying a current to a memory that stores a weight resistor corresponding to the multi-bit weight.

[0091] The memory also includes resistor elements connected in series, the number of which corresponds to the number of bits of the multi-bit weight. The multi-bit cell can adjust the weight resistance by controlling the on / off of each resistor element.

[0092] The weight resistors are also set to increase linearly as the multi-bit weight increases.

[0093] In step 1120, a multi-bit cell can receive a multi-bit input associated with a plurality of capacitors, each storing a separate weight capacitance.

[0094] The value of each digit that makes up the multi-bit input is also input to a multiplexer coupled to a capacitor corresponding to the digit.

[0095] In step 1130, the multi-bit cell may transmit one of a weight voltage and a reference voltage to each of the plurality of capacitors based on the multi-bit input.

[0096] The multiplexers each receive an input of 1 or 0, and among the multiplexers, a multiplexer that receives 1 can output a wait voltage, and a multiplexer that receives 0 can output a first fixed voltage.

[0097] When the multi-bit input is 0, the multiple multiplexers all output a first fixed voltage, and the multi-bit cell controls the current source to be turned off, thereby reducing power consumption.

[0098] The magnitude of the second fixed voltage transmitted to the opposite end of the capacitor to which the output signal is transmitted is the same as the magnitude of the first fixed voltage, and the magnitude of the second fixed voltage is also set so that the difference between the second fixed voltage and the weight voltage is proportional to the multi-bit weight.

[0099] The multi-bit cell includes capacitors whose number corresponds to the number of bits of the multi-bit input, and each capacitor can store a weight capacitance whose value corresponds to each digit of the multi-bit input.

[0100] In operation 1140, the multi-bit cell may generate charge data to be stored in each of the plurality of capacitors by performing an operation related to the transmitted signal and the weight capacitance.

[0101] Among the plurality of capacitors, the capacitor to which the first fixed voltage is transmitted has the same potential at both ends, and therefore, a voltage of 0V is applied to the capacitor, and charge data of 0C can be generated.

[0102] The plurality of capacitors receive an output signal at one end and a second fixed voltage at the opposite end of the one end, and can generate charge data by subtracting the second fixed voltage from the output signal and multiplying the difference by a weight capacitance.

[0103] The multi-bit cell can output first summed data generated by summing the charge data generated by each of the plurality of capacitors.

[0104] In one embodiment, the memory also includes a first memory and a second memory that store different weight resistances. The multi-bit cell further includes a code multiplexer that determines, based on a code input, one of the first memory and the second memory to which a current is applied. The multi-bit cell can generate a weight voltage from the weight resistance stored in the determined memory.

[0105] In another embodiment, the memory includes a first memory storing a first weight resistor and a second memory storing a second weight resistor. The current source includes a first current source and a second current source applying currents of the same magnitude. The first current source can apply a current to the first memory to generate a first weight voltage, and the second current source can apply a current to the second memory to generate a second weight voltage. The multiplexers can each output one of a first weight voltage, a second weight voltage, and a first fixed voltage based on a multi-bit input including a sign input.

[0106] FIG. 12 is a block diagram illustrating the configuration of a multi-bit arithmetic unit (e.g., multi-bit arithmetic unit 1200) in accordance with at least one embodiment.

[0107] 12, a multi-bit arithmetic device 1200 includes a plurality of multi-bit cells 200 and a converter 300. The converter 300 includes a comparator 310, a plurality of reference voltage cells 320, and a successive approximation register (SAR) logic 330. Only components related to this embodiment are shown in the multi-bit arithmetic device 1200 illustrated in FIG. 12. Therefore, it will be apparent to those skilled in the art that the multi-bit arithmetic device 1200 may further include other general-purpose components in addition to the components illustrated in FIG. 12. The multi-bit cell 100 of FIG. 12 may correspond to the multi-bit cell 100 of FIG. 4.

[0108] The multi-bit arithmetic device 1200 also includes a plurality of multi-bit cells 200. The multi-bit arithmetic device 1200 can generate second summed data by summing all of the first summed data output from each of the multi-bit cells 200. The multi-bit arithmetic device 1200 can output the second summed data and input it to the converter 300. The converter 300 can convert the second summed data, which is analog data, into digital data.

[0109] FIG. 13 is a circuit diagram of a multi-bit arithmetic unit (e.g., multi-bit arithmetic unit 1200) according to at least one embodiment.

[0110] Referring to FIG. 13, a plurality of multi-bit cells 200 are connected in parallel to each other, and the reference voltage cells 320, the number of which corresponds to the number of the multi-bit cells 200, are also connected in parallel to each other.

[0111] The multi-bit arithmetic unit 1200 may convert the second summed data, which is analog data, into digital data. The multi-bit arithmetic unit 1200 may input the second summed data to the comparator 310 to convert it into digital data. The comparator 310 may store data in which the range from the minimum value to the maximum value of the second summed data is divided into a predetermined number of ranges and classify the second summed data based on the stored data. The comparator 310 may output data indicating a specific range to which the value of the second summed data belongs, among the predetermined number of ranges.

[0112] The SAR logic 330 can convert the data transmitted from the comparator 310 into digital data based on the reference voltage data transmitted from the reference voltage cell 320. The SAR logic 330 can perform digital conversion by comparing the magnitude of the data transmitted from the comparator 310 with the reference voltage data. For example, the SAR logic 330 can perform digital conversion by repeating a method of maintaining a bit value if the data transmitted from the comparator 310 is greater than the reference voltage data, and erasing the bit value if the data transmitted from the comparator 310 is smaller than the reference voltage data.

[0113] 13 is merely an example, and the multi-bit cells 200 and the reference voltage cells 320 may be separated from each other. For example, the multi-bit cells 200 and the reference voltage cells 320 may receive signals from separate voltage sources or current sources.

[0114] FIG. 14 is a graph illustrating multi-bit operation time versus digital conversion time according to at least one embodiment.

[0115] 14, the multi-bit operation time for generating charge data, first summed data, and second summed data through multi-bit operation and the digital conversion time for converting the second summed data into digital data can be separated, and the multi-bit operation device can improve operation efficiency and power efficiency by performing the multi-bit operation and the digital conversion at different times.

[0116] During the multi-bit operation time, a sample voltage may be applied to the multi-bit cells and a multi-bit input may be received so that the multi-bit cells can perform a multi-bit operation. When first summed data is output from each of the multi-bit cells, the multi-bit operation device may generate second summed data by summing the first summed data.

[0117] During the digital conversion time, the sample voltage applied to the multi-bit cell is turned off, and the converter including the SAR logic can operate. The converter can convert the second sum data, which is analog data, into digital data.

[0118] FIG. 15 is a flowchart illustrating a method of operation of a multi-bit arithmetic unit (e.g., multi-bit arithmetic unit 1200) in accordance with at least one embodiment.

[0119] Referring to Figure 15, the method of operating the multi-bit arithmetic device is composed of steps that are processed in time sequence in the multi-bit arithmetic device shown in Figure 12. Therefore, even if omitted below, it should be understood that the contents described with respect to the multi-bit arithmetic device with reference to Figures 12 to 14 also apply to the method of Figure 15.

[0120] In step 1510, each of the plurality of multi-bit cells may output first summed data.

[0121] In operation 1520, the multi-bit arithmetic unit may output second summed data generated by summing the first summed data output from each of a plurality of multi-bit cells.

[0122] In step 1530, the multi-bit arithmetic unit may convert the second sum data, which is analog data, into digital data.

[0123] The multi-bit arithmetic unit also includes a converter that converts the second summed data, which is analog data, into digital data. The converter also includes a comparator, a plurality of reference voltage cells, and SAR logic.

[0124] FIG. 16 is a block diagram illustrating the configuration of a multi-bit arithmetic unit array (e.g., multi-bit arithmetic unit array 1600) in accordance with at least one embodiment.

[0125] 16, a multi-bit arithmetic unit array 1600 includes a plurality of multi-bit arithmetic units 1100a to 1100n. Each multi-bit arithmetic unit 1100a includes a converter 300a, which can output digital data 301a. The multi-bit arithmetic unit array 1600 shown in FIG. 14 only includes components relevant to this embodiment. Therefore, it will be apparent to those skilled in the art that the multi-bit arithmetic unit array 1600 may further include other general-purpose components in addition to the components shown in FIG. 16. The multi-bit arithmetic unit 1100a and converter 300a of FIG. 16 may correspond to the multi-bit arithmetic unit 1100 and converter 300 of FIG. 12.

[0126] Each of the multi-bit arithmetic devices 1100a-1100n can generate and output digital data by converting the second sum data output from the multi-bit cells. The multi-bit arithmetic device array 1600 can output a final arithmetic result related to the input to the multi-bit arithmetic device array 1600 by combining the digital data 301a-301n output from each of the multi-bit arithmetic devices 1100a-1100n. The multi-bit arithmetic device array 1600 may correspond to the neural network 20 of FIG. 2, which is composed of multiple layers including an input layer and an output layer, for example.

[0127] FIG. 17 is a block diagram illustrating an electronic system (e.g., electronic system 1700) according to at least one embodiment.

[0128] 17, electronic system 1700 analyzes input data and extracts useful information based on multi-bit arithmetic unit 1730, and makes a situational decision based on the extracted information or controls the configuration of an electronic device in which electronic system 1700 is installed. For example, electronic system 1700 can be applied to robotic devices such as drones and advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, mobile devices, video display devices, measurement devices, and Internet of Things (IoT) devices, and can also be installed in various other types of electronic devices.

[0129] The electronic system 1700 includes a multi-bit arithmetic device 1730, as well as a central processing unit (CPU) 1710, a random access memory (RAM) 1720, an external memory 1740, a sensor module 1750, and a communication module (Tx / Rx module) 1760. Furthermore, the electronic system 1700 may further include an input / output module, a security module, a power control device, etc. Part of the hardware configuration of the electronic system 1700 is also mounted on a semiconductor chip. The multi-bit arithmetic device 1730 may be an on-chip implementation of the multi-bit arithmetic device described above in the drawings, or may be a device that includes the multi-bit arithmetic device described above in the drawings as a part thereof.

[0130] The CPU 1710 controls the overall operation of the electronic system 1700. The CPU 1710 may include one processor core (single core) or multiple processor cores (multi-core). The CPU 1710 may process or execute programs and / or data stored in the external memory 1740. The CPU 1710 may control the functions of the multi-bit arithmetic device 1730 by executing programs stored in the external memory 1740. The functions of the CPU 1710 may also be embodied as a graphics processing unit (GPU), an application processor (AP), etc.

[0131] The RAM 1720 can temporarily store programs, data, or instructions. For example, programs and / or data stored in the external memory 1740 can be temporarily stored in the RAM 1720 by control code or startup code of the CPU 1710. The RAM 1720 can also be embodied as a memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM).

[0132] The multi-bit arithmetic unit 1730 may perform a multi-bit operation on received input data and generate an information signal based on the result of the operation. The multi-bit arithmetic unit 1730 may be used in a neuromorphic device or a neural network device. The neural network may include, but is not limited to, a convolutional neural network (CNN), a recurrent neural network (RNN), deep belief networks, restricted Boltzmann machines, etc. The multi-bit arithmetic unit 1730 may correspond to a hardware accelerator dedicated to a neural network. In addition to a neuromorphic or neural network, the multi-bit arithmetic unit 1730 may also be applied to various systems that perform operations related to multi-bit inputs and multi-bit weights.

[0133] The information signal may include various types of recognition signals such as a voice recognition signal, an object recognition signal, a video recognition signal, and a biometric information recognition signal. For example, the multi-bit arithmetic device 1730 may receive frame data included in a video stream as input data and generate a recognition signal related to an object included in an image represented by the frame data. Depending on the type or function of the electronic device in which the electronic system 1700 is installed, the multi-bit arithmetic device 1730 may receive various types of input data and generate a recognition signal based on the input data.

[0134] The external memory 1740 is a storage location for storing data, and can store an operating system (OS), various programs, and various data. The external memory 1740 may include volatile memory or nonvolatile memory. The nonvolatile memory includes read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FeRAM). The volatile memory includes dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). External memory 1740 may include, for example, a hard disk drive (HDD), a solid static drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), an extreme digital (xD), or a memory stick.

[0135] The sensor module 1750 can collect information about the surroundings of the electronic device in which the electronic system 1700 is installed. The sensor module 1750 can sense or receive signals (e.g., video signals, audio signals, magnetic signals, biosignals, touch signals, etc.) from outside the electronic device and convert the sensed or received signals into data. To this end, the sensor module 1750 can be any of various types of sensing devices, such as a microphone, an imaging device, an image sensor, a LiDAR (light detection and ranging) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, or a touch sensor.

[0136] The sensor module 1750 can provide the converted data as input data to the multi-bit arithmetic unit 1730. For example, the sensor module 1750 can include an image sensor to capture an external environment of the electronic device, generate a video stream, and sequentially provide successive data frames of the video stream as input data to the multi-bit arithmetic unit 1730. However, without being limited thereto, the sensor module 1750 can provide various types of data to the multi-bit arithmetic unit 1730.

[0137] The communication module 1760 may include various wired or wireless interfaces capable of communicating with external devices. For example, the communication module 1760 may include a communication interface connectable to a wired local area network (LAN), a wireless local area network (WLAN) such as wireless fidelity (Wi-Fi), a wireless personal area network (WPAN) such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or a mobile cellular network such as 3G (3rd generation), 4G (4th generation), LTE (long term evolution), or 5G (5th generation).

[0138] The electronic system 1700 may further include a processor, a memory device for storing and executing program data, permanent storage such as a disk drive, a communication port for communicating with external devices, as well as user interface devices such as a touch panel, keys, buttons, etc. Methods embodied by software modules or algorithms may also be stored on a computer-readable recording medium as computer-readable code or program instructions executable on a processor.

[0139] 11 and 15 may also be recorded on a computer-readable recording medium having one or more programs recorded thereon, including instructions for executing the methods. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical media such as compact disc read-only memories (CD-ROMs) and digital versatile discs (DVDs); magneto-optical media such as floptical disks; and hardware devices specially configured to store and execute program instructions, such as ROMs, RAMs, and flash memories. Examples of program instructions include not only machine language code, such as that produced by a compiler, but also high-level language code that can be executed by a computer using an interpreter, etc.

[0140] Although the present embodiment has been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the claims also fall within the scope of the present invention. [Explanation of symbols]

[0141] 100 multi-bit cells 110 memory 120 current source 130 Multiple Multiplexers 131 Multiplexer 140 Multiple Capacitors 141 Capacitor

Claims

1. In a multi-bit cell, a memory for storing weight resistors corresponding to the multi-bit weights; a current source that applies a current to the memory so that a weight voltage is generated from the weight resistor; a plurality of multiplexers connected in parallel to each other and connected in series to the memory, each multiplexer outputting one of the wait voltage and a first fixed voltage based on a multi-bit input; a plurality of capacitors respectively connected to the plurality of multiplexers, each storing a separate weight capacitance, and generating charge data by performing an operation relating to the output signal and the weight capacitance;

2. The memory includes: a plurality of resistor elements connected in series, the number of which corresponds to the number of bits of the multi-bit weight; The multi-bit cell comprises:

2. The multi-bit cell according to claim 1, wherein the weight resistance is adjusted by controlling on / off of each of the resistance elements.

3. Each of the plurality of multiplexers includes: receiving an input of 1 or an input of 0; receiving an input of one and outputting the wait voltage; The multi-bit cell of claim 1 , wherein the multi-bit cell outputs the first fixed voltage upon receiving an input of 0.

4. The multi-bit cell of claim 1 , wherein when the first fixed voltage is output from any of the multiplexers, the multi-bit cell reduces power consumption by turning off the current source.

5. a second fixed voltage transmitted to one end of a capacitor opposite to the end to which the output signal is transmitted is equal to the first fixed voltage; 2. The multi-bit cell of claim 1, wherein a capacitor to which the first fixed voltage is applied has the same potential across both ends of the plurality of capacitors, and thus receives a voltage of 0V and generates charge data of 0C.

6. 6. The multi-bit cell of claim 5, wherein the weight resistor is set to increase linearly as the multi-bit weight increases, and the magnitude of the second fixed voltage is set so that a difference between the weight resistor and the second fixed voltage is proportional to the multi-bit weight.

7. the multi-bit cell includes the capacitors, the number of which corresponds to the number of bits of the multi-bit input; 2. The multi-bit cell of claim 1, wherein the capacitors store weight capacitances of values ​​corresponding to respective digits of the multi-bit input.

8. 8. The multi-bit cell according to claim 7, wherein the value of each digit constituting the multi-bit input is input to a multiplexer of the multiplexers coupled to a capacitor of the capacitor corresponding to the digit.

9. The plurality of capacitors include:

2. The multi-bit cell of claim 1, wherein the output signal is transmitted at one end and a second fixed voltage is transmitted at an end opposite to the one end, the charge data is generated by subtracting the second fixed voltage from the output signal and multiplying the subtracted value by the weight capacitance.

10. The multi-bit cell according to claim 1 , wherein the multi-bit cell outputs first summed data generated by summing charge data generated by each of the plurality of capacitors.

11. The memory includes a first memory and a second memory for storing different weight resistances; The multi-bit cell further includes a code multiplexer that determines one of the first memory and the second memory to which the current is applied based on a code input; 11. The multi-bit cell of claim 1, wherein a weight voltage is generated from the determined weight resistance stored in the memory.

12. The memory includes a first memory storing a first weight resistance and a second memory storing a second weight resistance; the current source includes a first current source that applies a current to the first memory so that a first wait voltage is generated, and a second current source that applies a current to the second memory so that a second wait voltage is generated; 11. The multi-bit cell of claim 1, wherein each of the multiplexers outputs one of the first wait voltage, the second wait voltage, and the first fixed voltage based on the multi-bit input including a sign input.

13. In a multi-bit arithmetic device, A multi-bit cell according to claim 10, a multi-bit arithmetic unit that outputs second summed data generated by summing the first summed data output from each of the multi-bit cells;

14. The multi-bit arithmetic unit a converter that converts the second sum data, which is analog data, into digital data; The converter comprises:

14. The multi-bit arithmetic unit of claim 13, comprising a comparator, a plurality of reference voltage cells, and successive approximation register (SAR) logic.

15. In the multi-bit operation method, generating weight voltages from the weight resistors by applying currents to a memory storing the weight resistors corresponding to the multi-bit weights; receiving a multi-bit input associated with a plurality of capacitors, each capacitor storing a distinct weight capacitance; outputting one signal of the weight voltage and a first fixed voltage to each of the plurality of capacitors based on the multi-bit input; generating charge data to be stored in each of the plurality of capacitors by performing an operation on the output signal and the weight capacitance.

16. The multi-bit operation method includes:

16. The multi-bit operation method of claim 15, further comprising: outputting first summed data generated by summing the charge data stored in each of the plurality of capacitors.

17. The multi-bit operation method includes: performing the step of outputting the first summed data in each of a plurality of multi-bit cells; 17. The multi-bit operation method of claim 16, further comprising: outputting second summed data generated by summing the first summed data output from each of the plurality of multi-bit cells.

18. The multi-bit operation method includes:

18. The multi-bit calculation method of claim 17, further comprising converting the second sum data, which is analog data, into digital data.

19. A computer program product causing a processor to carry out a method according to any one of claims 15 to 18.

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