Semiconductor element and semiconductor device including the same

Abstract

To provide a semiconductor element and a semiconductor device including the same.SOLUTION: A semiconductor element 1 includes a bottom electrode 100, an upper electrode 200 that is arranged separated from the bottom electrode 100, and a dielectric layer that is arranged between the bottom electrode 100 and the upper electrode 200 and includes a first metal oxide layer 310, a second metal oxide layer 320, and a third metal oxide layer 330, and the first oxide layer 310, second oxide layer 320, and third oxide layer 330 are arranged sequentially between the bottom electrode 100 and the upper electrode 200 in the thickness direction.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor element and a semiconductor device including the same. [Background technology]

[0002] As electronic devices are downscaled, the space occupied by semiconductor elements within the device is also shrinking. This requires that the size of semiconductor elements such as capacitors be reduced, as well as the thickness of capacitor dielectric layers. However, in such cases, large leakage current occurs through the capacitor's dielectric layer, making it difficult to operate the element. Summary of the Invention [Problem to be solved by the invention]

[0003] The problem to be solved by the present invention is to provide a semiconductor element having a high electric capacity and a low leakage current value, and a semiconductor device including the same.

[0004] Another problem to be solved by the present invention is to provide a semiconductor device having a dielectric layer containing three or more metal oxide layers. [Means for solving the problem]

[0005] An electronic device according to one embodiment also includes a lower electrode, an upper electrode spaced apart from the lower electrode, and a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including a first metal oxide layer, a second metal oxide layer, and a third metal oxide layer.

[0006] The first metal oxide layer may contain one or more metal elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu.

[0007] The second metal oxide layer may include at least one metal element selected from the group consisting of Y, Sc, and Ce.

[0008] The third metal oxide layer may contain one or more metal elements selected from the group consisting of Al, Mg, and Be.

[0009] The first metal oxide layer, the second metal oxide layer, and the third metal oxide layer may be sequentially disposed in a thickness direction between a lower electrode and an upper electrode.

[0010] The second metal oxide layer may further contain one or more metal elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu.

[0011] The second metal oxide layer is A x B y O z (wherein A is one or more elements selected from the group consisting of Y, Sc, and Ce, B is one or more elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu, and O is oxygen, and x+y+z=1).

[0012] In the second metal oxide layer, the content of the A element (x) is 0.01 or more and 1.0 or less relative to the content of the B element (y).

[0013] The above A x B y O z In the compound represented by the formula: x is greater than 0.0 and is also less than or equal to 0.2.

[0014] The above A x B y O z In the compound represented by the formula: x may be greater than 0.0 and less than or equal to 0.15.

[0015] The above A x B y O z In the compound represented by the formula (I), y is greater than 0.0 and is 0.5 or less.

[0016] The above A x B y O z In the compound represented by the formula (I), y may be 0.2 or more and 0.5 or less.

[0017] The first metal oxide layer is disposed adjacent to the bottom electrode, and the thickness of the first metal oxide layer is also 40% or more of the total thickness of the dielectric layer.

[0018] The thickness of the second metal oxide layer is not less than 5 Å and not more than 50 Å.

[0019] The thickness of the dielectric layer is not less than 20 Å and not more than 100 Å.

[0020] The bottom electrode, the top electrode, or both may each independently comprise a metal, a metal nitride, a metal oxide, or a combination thereof.

[0021] The lower electrode, the upper electrode, or both of them may contain a metal nitride represented by MM’N (where M is an element selected from one or more of Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U; M’ is different from M and is an element selected from one or more of H, Li, As, Se, N, O, P, S, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U; and N is nitrogen).

[0022] An electronic device according to an embodiment includes a lower electrode, an upper electrode disposed apart from the lower electrode, and a metal oxide layer disposed between the lower electrode and the upper electrode and containing a compound represented by A x B y O z (where A is an element selected from one or more of Y, Sc, and Ce; B is an element selected from one or more of the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu; O is oxygen; and x + y + z = 1 (0 < x ≤ 0.2, 0 < y ≤ 0.5)).

[0023] The thickness of the metal oxide layer is 10 Å or more and also 50 Å or less.

[0024] A x B y Oz In the compound represented by the formula: x is greater than 0.0 and is equal to or less than 0.15.

[0025] The above A x B y O z In the compound represented by the formula (I), y is 0.2 or more and 0.5 or less.

[0026] Also, according to one embodiment, an electronic device includes a lower electrode, an upper electrode spaced apart from the lower electrode, and a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including one or more first metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu, one or more second metal elements selected from Y, Sc, and Ce, and one or more third metal elements selected from the group consisting of Al, Mg, and Be, wherein the second metal element and the third metal element have a concentration gradient in the thickness direction of the dielectric layer, and may have maximum concentrations at different positions, respectively.

[0027] The second metal element may have a maximum concentration at a position that is 40% to 90% of the thickness of the dielectric layer away from the lower electrode.

[0028] The content of the second metal element is more than 0.0 at % and 5.0 at % or less relative to the total amount of metal elements in the dielectric layer.

[0029] The third metal element may have a maximum concentration at a position more than 0% and not more than 20% of the thickness of the dielectric layer away from the upper electrode.

[0030] The third metal element is present in an amount exceeding 0.0 at % and not more than 5.0 at % relative to the total amount of metal elements in the dielectric layer.

[0031] In the dielectric layer, the content of the second metal element is 10% or more and 200% or less than the content of the third metal element.

[0032] According to an embodiment, a semiconductor device includes a field effect transistor and any one of the above electronic elements electrically connected to the field effect transistor.

[0033] The field effect transistor may include a semiconductor layer including a source region and a drain region, a gate insulating layer disposed on the semiconductor layer, and a gate electrode disposed on the gate insulating layer. [Effects of the Invention]

[0034] According to the present invention, a semiconductor device having high capacitance and excellent leakage current blocking / reducing properties and a semiconductor device including the same can be provided. Such a semiconductor device can realize an improved integration density and contribute to the miniaturization of electronic devices. [Brief explanation of the drawings]

[0035] [Figure 1] 1 is a schematic diagram of a semiconductor device according to one embodiment. [Figure 2] 1 is a schematic diagram of a semiconductor device according to one embodiment. [Figure 3A] 1 is a schematic diagram of a semiconductor device according to one embodiment. [Figure 3B] 1 is a schematic diagram of a semiconductor device according to one embodiment. [Figure 4A] 1 is a circuit diagram of a memory cell including a semiconductor element and a capacitor. [Figure 4B] 1 is a schematic diagram of a semiconductor device according to an embodiment; [Figure 5] FIG. 1 is a layout diagram of a semiconductor device according to an embodiment. [Figure 6] 6 is a cross-sectional view of the semiconductor device taken along line AA' in FIG. 5. [Figure 7] FIG. 7 is a cross-sectional view showing a modification of FIG. 6. [Figure 8] 1 is a conceptual diagram illustrating a device architecture that can be applied to an electronic device according to an embodiment. [Figure 9]1 is a conceptual diagram illustrating a device architecture that can be applied to an electronic device according to an embodiment. [Figure 10] 1 is a transmission electron microscopy-energy dispersive spectroscopy (TEM-EDS) analysis result of a dielectric layer according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0036] The terms used in this specification are merely used to describe specific embodiments and are not intended to limit the technical concept. The terms "upper" and "above" may include not only things that are immediately in contact with each other but also things that are not in contact with each other but are immediately above, below, left, or right.

[0037] The singular includes the plural unless the context clearly dictates otherwise. Terms such as "comprise" or "have" indicate the presence of a feature, number, step, operation, component, part, ingredient, material, or combination thereof stated in the specification, unless specifically stated to the contrary, and should not be understood to preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, ingredients, materials, or combinations thereof.

[0038] Terms such as "first," "second," and "third" may be used to describe various components, but are used only to distinguish one component from another and do not limit the order, type, etc. of the components. Furthermore, terms such as "unit," "means," "module," and "... section" refer to a comprehensive structural unit that processes a certain function or operation, and may be realized by hardware or software, or by a combination of hardware and software.

[0039] Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component (width, thickness, etc. of layers, regions, etc.) in the drawings may be exaggerated for clarity and convenience. It should be noted that the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0040] According to one aspect, a semiconductor device having low leakage current and high capacitance can be provided. The semiconductor device can also be a capacitor.

[0041] 1 is a schematic diagram of a capacitor according to an embodiment. Referring to FIG. 1, the capacitor 1 may include a lower electrode 100, an upper electrode 200 spaced apart from the lower electrode 100, and a dielectric layer 300 disposed between the lower electrode 100 and the upper electrode 200.

[0042] The lower electrode 100 is also disposed on a substrate (not shown). The substrate is part of a structure supporting the capacitor and part of a device connected to the capacitor. The substrate may include a semiconductor material pattern, an insulating material pattern, and / or a conductive material pattern. The substrate may include, for example, a substrate 11′, a gate stack 12, an interlayer insulating layer 15, a contact structure 20′, and / or a bit line structure 13 shown in FIGS. 5 and 6 (described below). The substrate may also include a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and / or an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0043] The upper electrode 200 is also disposed opposite the lower electrode 100 at a distance. The lower electrode 100 and / or the upper electrode 200 may each independently include a metal, a metal nitride, a metal oxide, or a combination thereof. Specifically, the lower electrode 100 and / or the upper electrode 200 may each independently include a metal such as ruthenium (Ru), titanium (Ti), tantalum (Ta), niobium (Nb), iridium (Ir), molybdenum (Mo), tungsten (W), or platinum (Pt); titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), or tungsten nitride (WN). and / or conductive metal oxides such as platinum oxide (PtO), iridium oxide (IrO), ruthenium oxide (RuO), strontium ruthenium oxide (SrRuO), barium strontium ruthenium oxide ((Ba,Sr)RuO), calcium ruthenium oxide (CaRuO), lanthanum strontium cobalt oxide ((La,Sr)CoO).

[0044] For example, the lower electrode 100 and / or the upper electrode 200 may each independently contain a metal nitride represented by MM’N. M is a metal element, M’ is an element different from M, and N is nitrogen. Such a metal nitride may include a MN metal nitride doped with the element M’. M may be one or more elements selected from Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. M’ may be one or more elements selected from H, Li, As, Se, N, O, P, S, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U. In the metal nitride MM’N, when the composition ratios of M, M’, and N are x:y:z, 0≦x≦2, 0≦y≦2, 0<z≦4, and one of x and y is not 0.

[0045] The lower electrode 100 and / or the upper electrode 200 may each independently be a single material layer or a laminated structure of a plurality of material layers. For example, the lower electrode 100 and / or the upper electrode 200 may each independently be a single layer of titanium nitride (TiN) or a single layer of niobium nitride (NbN). Alternatively, the lower electrode 100 and / or the upper electrode 200 may have a laminated structure including a first electrode layer containing titanium nitride (TiN) and a second electrode layer containing niobium nitride (NbN).

[0046] The dielectric layer 300 may include a first metal oxide layer 310, a second metal oxide layer 320, and a third metal oxide layer 330. The first metal oxide layer 310 may be disposed adjacent to the lower electrode 100, and the third metal oxide layer 330 may be disposed adjacent to the upper electrode 200, spaced apart and facing the first metal oxide layer 310. The second metal oxide layer 320 may be disposed between the first metal oxide layer 310 and the third metal oxide layer 330. In other words, the first metal oxide layer 310, the second metal oxide layer 320, and the third metal oxide layer 330 may be disposed sequentially in the thickness direction of the dielectric layer 300.

[0047] The first metal oxide layer 310 may have a high dielectric constant. For example, the first metal oxide layers 310 may each independently have a dielectric constant of 20 or more and 70 or less. For example, the first metal oxide layers 310 may include one or more metals selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu. Specifically, the first metal oxide layers 310 may each independently include hafnium oxide (HfO), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO), hafnium zirconium oxide (HfZrO), zirconium silicon oxide (ZrSiO), tantalum oxide (TaO), titanium oxide (TiO), strontium titanium oxide (SrTiO), lead zinc niobate (PbZnNbO), etc. The first metal oxide layer 310 may also include a metal nitride oxide such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), or hafnium oxynitride (HfON); a silicate such as ZrSiON or HfSiON; or an aluminate such as ZrAlON or HfAlON.

[0048] The second metal oxide layer 320 may contain one or more metal elements selected from Y, Sc, and Ce, and may further contain one or more metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu.x B y O z (wherein A is one or more elements selected from the group consisting of Y, Sc, and Ce; B is one or more elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu; O is oxygen; and x+y+z=1). The content of the A element (x) may be greater than 0.0, 0.001 or greater, 0.005 or greater, 0.01 or greater, 0.015 or greater, 0.02 or greater, 0.2 or less, 0.18 or less, or 0.15 or less. The content of the B element (y) may be greater than 0.0, 0.05 or greater, 0.10 or greater, 0.15 or greater, 0.18 or greater, 0.20 or greater, 0.22 or greater, 0.50 or less, 0.45 or less, 0.40 or less, or 0.35 or less. In addition, the content of element A (x) is 0.01 or more, 0.02 or more, 0.05 or more, 0.07 or more, 0.10 or more, 1.0 or less, 0.9 or less, 0.8 or less, or 0.7 or less relative to the content of element B (y).

[0049] The third metal oxide layer 330 may contain one or more metal elements selected from the group consisting of Al, Mg, and Be.

[0050] As a result, the dielectric layer 300 contains three or more metal elements. Specifically, the dielectric layer 300 may contain one or more metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu; one or more metal elements selected from Y, Sc, and Ce; and one or more metal elements selected from the group consisting of Al, Mg, and Be. Such a dielectric layer 300 exhibits superior effects in terms of capacitance and leakage current of a capacitor compared to a dielectric layer containing two metal elements. For example, a dielectric layer containing three metal elements, Zr, Al, and Y, may exhibit higher capacitance compared to a dielectric layer containing Zr and Al and a dielectric layer containing Zr and Y.

[0051] Furthermore, the positions of the second metal oxide layer 320 and the third metal oxide layer 330 within the dielectric layer may affect the capacitance and leakage current of the capacitor. Specifically, when the third metal oxide layer 330 is disposed closer to the electrode than the second metal oxide layer 320, the capacitance of the capacitor is higher and the leakage current is lower than when the second metal oxide layer 320 is disposed closer to the electrode than the third metal oxide layer 330.

[0052] The thickness of the dielectric layer 300 is equal to or greater than 20 Å and equal to or less than 100 Å. Specifically, the dielectric layer 300 can have a thickness of equal to or greater than 25 Å, equal to or greater than 30 Å, equal to or greater than 35 Å, and equal to or less than 90 Å, equal to or less than 80 Å, equal to or less than 70 Å, or equal to or less than 60 Å.

[0053] The first metal oxide layer 310 is disposed adjacent to the lower electrode and may have a thickness of 40% or more of the total thickness of the dielectric layer 300. Specifically, the thickness of the first metal oxide layer 310 may be 45% or more, 50% or more, 55% or more, 60% or more, 65% or more, 90% or less, 85% or less, 80% or less, or 75% or less of the total thickness of the dielectric layer 300. For example, the thickness of the first metal oxide layer 310 may be 10 Å or more, 15 Å or more, 20 Å or more, 50 Å or less, 45 Å or less, 40 Å or less, or 35 Å or less.

[0054] The thickness of the second metal oxide layer 320 can be 5 Å or more, 10 Å or more, 15 Å or more, 20 Å or more, 50 Å or less, 45 Å or less, 40 Å or less, or 35 Å or less. The thickness of the second metal oxide layer 320 can be 1% or more, 3% or more, 5% or more, 8% or more, 10% or more, 50% or less, 40% or less, 30% or less, 20% or less, or 10% or less of the total thickness of the dielectric layer 300.

[0055] The thickness of the third metal oxide layer 330 can be 1 Å or more, 2 Å or more, 5 Å or more, 10 Å or more, 30 Å or less, 25 Å or less, 20 Å or less, or 15 Å or less. The thickness of the third metal oxide layer 330 can be 0.1% or more, 0.5% or more, 1% or more, 3% or more, 5% or more, 30% or less, 25% or less, 20% or less, 15% or less, 10% or less, or 5% or less of the total thickness of the dielectric layer 300.

[0056] The boundaries between the first metal oxide layer 310, the second metal oxide layer 320, and the third metal oxide layer 330 may be unclear. Specifically, the boundaries between the first metal oxide layer 310 and the second metal oxide layer 320, the second metal oxide layer 320 and the third metal oxide layer 330, or all of them may be unclear. For example, if the first metal oxide layer 310, the second metal oxide layer 320, and the third metal oxide layer 330 are made of similar compositions or are thin, the boundaries between adjacent layers may not be clearly defined due to material diffusion between them.

[0057] The capacitor 1 may further include an interface layer (not shown) between the lower electrode 100 and the dielectric layer 300 and / or between the upper electrode 200 and the dielectric layer 300. The interface layer can act as a barrier layer that prevents the diffusion and / or migration of impurities between the lower electrode 100 and the dielectric layer 300 and / or between the upper electrode 200 and the dielectric layer 300. For example, the interface layer can prevent some atoms (e.g., nitrogen atoms) contained in the upper electrode 200 / lower electrode 100 from penetrating into the dielectric layer 300, and can also prevent some atoms (e.g., oxygen atoms) contained in the dielectric layer 300 from diffusing into the upper electrode 200 / lower electrode 100. The interface layer may include an electrically conductive transition metal oxide, such as a metal oxide such as titanium oxide, tantalum oxide, niobium oxide, or molybdenum oxide; or a metal oxynitride such as titanium oxynitride (TiON), tantalum oxynitride (TaON), niobium oxynitride (NbON), or molybdenum oxynitride (MoON). Specifically, the interface layer may include an oxide of a metal included in the lower electrode 100 and / or the upper electrode 200. For example, the lower electrode 100 may include a metal nitride represented by MM'N, and the interface layer between the lower electrode 100 and the dielectric layer 300 may include a metal oxynitride represented by MM'N. The interface layer may be formed to a thickness that does not allow it to function as a dielectric layer, for example, about 1 Å to 10 Å.

[0058] A capacitor according to another embodiment includes a dielectric layer between an upper electrode 200 and a lower electrode 100, the dielectric layer including one or more first metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu, one or more second metal elements selected from Y, Sc, and Ce, and one or more third metal elements selected from the group consisting of Al, Mg, and Be, where the second and third metal elements may have a concentration gradient in the thickness direction of the dielectric layer. FIG. 2 is a schematic diagram of such a capacitor 2. Referring to FIG. 2, the capacitor 2 includes a lower electrode 100, an upper electrode 200 spaced apart from the lower electrode 100, and a dielectric layer 302 disposed between the lower electrode 100 and the upper electrode 200, where the dielectric layer 302 may include the second and third metal elements having maximum concentrations at different positions. Specifically, the second metal element may have a maximum concentration (content) at a position (322) that is 40% or more, 45% or more, 50% or more, 55% or more, 60% or more, 65% or more, 90% or less, 85% or less, 80% or less, or 75% or less of the thickness of the dielectric layer 302 away from the lower electrode 100. Also, the third metal element may have a maximum concentration (content) at a position (332) that is more than 0%, 1% or more, 3% or more, 5% or more, 20% or less, 15% or less, 10% or less, or 5% or less of the thickness of the dielectric layer 302 away from the upper electrode 200.

[0059] The first metal element, the second metal element, and / or the third metal element can be contained in the dielectric layer 302 at an appropriate content according to the desired dielectric constant of the dielectric layer, the leakage current value of the capacitor, and the like. For example, the content of the second metal element in the dielectric layer 302 is more than 0.0 at%, 0.2 at% or more, 0.3 at% or more, 0.5 at% or more, 5.0 at% or less, 4.5 at% or less, 4.0 at% or less, 3.5 at% or less, 3.0 at% or less, 2.5 at% or less, 2.0 at% or less, or 1.5 at% or less based on the total amount of the metal elements in the dielectric layer. The content of the third metal element in the dielectric layer 302 is more than 0.0 at%, 0.3 at% or more, 0.5 at% or more, 1.0 at% or more, 1.5 at% or more, 2.0 at% or more, 5.0 at% or less, 4.5 at% or less, 4.0 at% or less, 3.5 at% or less, 3.0 at% or less, or 1.5 at% or less based on the total amount of the metal elements in the dielectric layer. The content of the first metal element in the dielectric layer 302 is 80 at% or more, 85 at% or more, 90 at% or more, 92 at% or more, 94 at% or more, 95 at% or more, less than 100 at%, 98 at% or less, or 96 at% or less based on the total amount of the metal elements in the dielectric layer. Also, the content of the second metal element in the dielectric layer 302 is 10% or more, 20% or more, 30% or more, 200% or less, 170% or less, or 150% or less based on the content of the third metal element.

[0060] The lower electrode 100, the upper electrode 200, the interface layer (not shown), etc. are as described above, and the dielectric layer 302 can refer to the content of the dielectric layer 300 described above.

[0061] Referring to FIG. 3A, a capacitor 3a according to still another embodiment further includes a metal oxide layer 323 represented by A x B y O z (where A is an element selected from one or more of Y, Sc, and Ce, B is an element selected from one or more of the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu, O is oxygen, and x + y + z = 1 (0 < x ≤ 0.2, 0 < y ≤ 0.5)). x By O z In the compound represented by the formula (1), x is greater than 0.0 and is equal to or less than 0.15, and y is equal to or greater than 0.2 and is equal to or less than 0.5, or equal to or less than 0.4. The thickness of the metal oxide layer 323 is equal to or greater than 10 Å, equal to or greater than 15 Å, equal to or greater than 20 Å, and equal to or less than 50 Å, equal to or less than 45 Å, or equal to or less than 40 Å.

[0062] Referring to FIG. 3B, the capacitor 3b may further include a metal oxide layer 333 between the upper electrode 200 and the metal oxide layer 323, the metal oxide layer 333 containing one or more metals selected from the group consisting of Al, Mg, and Be, and may further include a metal oxide layer 313 between the metal oxide layer 323 and the lower electrode 100, the metal oxide layer 313 containing one or more metals selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Ti, Al, and Lu. For example, the metal oxide layer 313 may include hafnium oxide (HfO), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO), hafnium zirconium oxide (HfZrO), zirconium silicon oxide (ZrSiO), tantalum oxide (TaO), titanium oxide (TiO), strontium titanium oxide (SrTiO), or lead zinc niobate (PbZnNbO), or may include a nitrided metal oxide such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), or hafnium oxynitride (HfON), a silicate such as ZrSiON or HfSiON, or an aluminate such as ZrAlON or HfAlON.

[0063] The capacitors 1, 2, 3a, and 3b can have a low leakage current value. Specifically, the capacitors 1, 2, 3a, and 3b have a leakage current value of 1.0×10 when a voltage of 1.0 V is applied. -4 A / cm 2 Below, 5.0x10 -5 A / cm 2 Below, 1.0x10 -5 A / cm 2 Below, 5.0x10 -6 A / cm2 Less than or equal to 1.0x10 -6 A / cm 2 The following leakage current values ​​can be shown:

[0064] According to one embodiment, a semiconductor device (e.g., a capacitor) may be fabricated by forming a lower electrode 100 on a substrate, forming a dielectric layer 300 including metal oxide layers 310, 320, and 330 having desired composition and thickness on the lower electrode 100, and then forming an upper electrode 200 thereon. The lower electrode 100, the dielectric layer 300, and the upper electrode 200 may be formed by methods known in the art. For example, they may each be independently formed by a deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or sputtering. Among these, atomic layer deposition (ALD) has the advantage of being capable of forming a layer that is uniform at the atomic level and can be performed at a relatively low temperature.

[0065] Specifically, the lower electrode 100, the dielectric layer 300, and the upper electrode 200 may each be independently formed by repeating one or more deposition cycles that include supplying a metal precursor, purging the metal precursor, supplying a reactive gas (e.g., a nitriding agent or oxygen source), and purging the reactive gas.

[0066] For example, the lower electrode 100 and / or upper electrode 200 containing a metal nitride can be fabricated by supplying a metal precursor and a nitriding agent onto a substrate or a dielectric layer and reacting them at an appropriate temperature. The process temperature is appropriately adjusted depending on the thermal stability of the metal precursor and / or the nitriding agent, and can be 100°C or higher and 700°C or lower.

[0067] The metal precursor is MR x or M'R x M or M' is as described above, and R is a C1-C 10 Alkyl groups, C2-C 10Alkenyl group, carbonyl group (C=O), halide, C6-C 10 Aryl groups, C6-C 10 Cycloalkyl groups, C6-C 10 Cycloalkenyl group, (C=O)R (where R is hydrogen or C1-C 10 alkyl group), C1-C 10 Alkoxy groups, C1-C 10 Amidinate group, C1-C 10 Alkylamide group, C1-C 10 alkylimido group, -N(Q)(Q') (Q and Q' are independently C-C 10 alkyl group or hydrogen), Q(C=O)CN (Q is hydrogen or C1-C 10 alkyl group) and C1-C 10 There may be one or more β-diketonate groups, and x may be greater than 0 and less than or equal to 6.

[0068] The metal precursor is MH y or M'H y M and M' are as defined above, and H may include one or more of F, Cl, Br, and I. y is also greater than 0 and equal to or less than 6.

[0069] The nitriding agent is a reactive gas containing nitrogen element and may include NH3, N2H2, N3H and / or N2H4.

[0070] Unreacted metal precursors, reactive gases (e.g., nitriding agents), and / or their by-products may also be removed by purging, which may utilize an inert gas such as Ar, He, Ne, and / or N gas.

[0071] After the formation of the lower electrode 100, an interfacial layer (not shown) may be formed on the lower electrode 100, or after the formation of the dielectric layer 300, on the dielectric layer 300. The interfacial layer may be formed by providing precursors and / or sources of the elements that make up the interfacial layer on the lower electrode 100 or the dielectric layer 300. Alternatively, the interfacial layer may be formed by providing an oxygen source to the lower electrode 100 and oxidizing a portion of the surface of the lower electrode 100.

[0072] The dielectric layers 300, 302 can also be fabricated by providing a first metal precursor, a second metal precursor, a third metal precursor, and an oxygen source on the lower electrode and adjusting the order, time, amount, etc. of the supply so that the dielectric layers 300, 302 have a desired composition, concentration, and / or thickness. For example, the dielectric layers 300, 302 may be fabricated by providing a first metal precursor (e.g., a zirconium precursor) and an oxygen source on the lower electrode to form a first metal oxide layer 310, providing a first metal precursor (e.g., a zirconium precursor), a second metal precursor (e.g., an yttrium precursor), and an oxygen source on the first metal oxide layer 310 to form a second metal oxide layer 320, and providing a third metal precursor (e.g., an aluminum precursor) and an oxygen source on the second metal oxide layer 320 to form a third metal oxide layer 330. The first metal precursor, the second metal precursor, the third metal precursor, and / or the oxygen source may be simultaneously or intermittently / crosswise supplied onto the lower electrode. For example, two or more of the first metal precursor, the second metal precursor, the third metal precursor, and the oxygen source may be simultaneously supplied onto the lower electrode through two or more inlets, or the first metal precursor, the second metal precursor, the third metal precursor, and the oxygen source may be sequentially supplied onto the lower electrode.

[0073] The composition, concentration, and / or thickness of metal elements within the dielectric layers 300 and 302 may vary due to material diffusion. For example, the third metal oxide layer 330 may further include one or more metal elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu, and may have different contents, concentrations, and / or positions within the dielectric layers of Al, Mg, and / or beryllium (Be) due to material diffusion from the adjacent second metal oxide layer 320.

[0074] The metal precursors, such as the first metal precursor, the second metal precursor, or the third metal precursor, may each independently be selected from the group consisting of AR x , B.R. x or CR x A is a first metal element, B is a second metal element, C is a third metal element, and R is a C1-C 10 Alkyl groups, C2-C 10 Alkenyl group, carbonyl group (C=O), halide, C6-C 10 Aryl groups, C6-C 10 Cycloalkyl groups, C6-C 10 Cycloalkenyl group, (C=O)R (where R is hydrogen or C1-C 10 alkyl group), C1-C 10 Alkoxy groups, C1-C 10 Amidinate group, C1-C 10 Alkylamide group, C1-C 10 alkylimido group, -N(Q)(Q') (Q and Q' are independently C-C 10 alkyl group or hydrogen), Q(C=O)CN (Q is hydrogen or C1-C 10 alkyl group) and C1-C 10 There may be one or more β-diketonate groups, and x may be greater than 0 and less than or equal to 6.

[0075] Examples of oxygen sources include O3, H2O, O2, N2O, O2, and / or plasma. The dielectric layers 300, 302 and / or the metal oxide layers 310, 320, and 330 may be subjected to a heat treatment. Specifically, the heat treatment may be performed after the dielectric layers 300, 302 and / or the upper electrode 200 are formed. As another example, the heat treatment may be performed after the first metal oxide layer 310, the second metal oxide layer 320, and / or the third metal oxide layer 330 are formed. During the heat treatment, metal elements in the dielectric layers 300, 302 may undergo material diffusion, and some or all of the metal oxides in the dielectric layers 300, 302 and / or the metal oxide layers 310, 320, and 330 may be crystallized or the crystal grain size may increase.

[0076] The heat treatment may be carried out at a temperature of, but is not limited to, 400° C. to 1,100° C. The heat treatment may be carried out for a time period of, but is not limited to, 1 nanosecond or more, 1 microsecond or more, 0.001 seconds or more, 0.01 seconds or more, 0.05 seconds or more, 0.1 seconds or more, 0.5 seconds or more, 1 second or more, 3 seconds or more, 5 seconds or more, 10 minutes or less, 5 minutes or less, 1 minute or less, or 30 seconds or less.

[0077] According to another aspect, a semiconductor device may be provided. The semiconductor device may have memory characteristics, such as a dynamic random access memory (DRAM). The semiconductor device may also have a configuration in which a field-effect transistor and a capacitor are electrically connected, and the capacitor may be the semiconductor element.

[0078] 4A is a circuit diagram of a memory cell of a memory device including a semiconductor device and a capacitor, and FIG. 4B is a schematic diagram showing a semiconductor device (a connection structure including a capacitor and a field effect transistor) according to an embodiment.

[0079] 4A and 4B are examples of a semiconductor device D1 including the capacitor 1 of FIG. 1, and the semiconductor device D1 may include the capacitor 2 of FIG. 2 and / or the capacitors 3a and 3b of FIGS. 3A and 3B.

[0080] 4A, semiconductor device D1 may be included in a memory device such as a memory cell and may include a transistor 10 and a capacitor 1 electrically connected to a source region 11b of transistor 10. The memory device may include a plurality of bit lines and a plurality of word lines, and may further include a plurality of memory cells. Each word line is also electrically connected to a gate electrode 12b of transistor 10, and each bit line is also electrically connected to a drain region 11a of transistor 10. An electrode of capacitor 1 is also connected to, for example, a voltage controller (not shown).

[0081] 4B, the semiconductor device D1 has a structure in which the capacitor 1 including the dielectric layer 300 and the field effect transistor 10 are electrically connected by a contact 20. For example, one of the electrodes 100, 200 of the capacitor 1 can be electrically connected by the contact 20 to one of the source region 11b and the drain region 11a of the transistor 10.

[0082] The field-effect transistor 10 may include a substrate 11 and a gate electrode 12b disposed to face the channel 11c, and may further include a gate insulating layer 12a between the substrate 11 and the gate electrode 12b.

[0083] The substrate 11 may include a semiconductor material such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and may be modified into various forms such as silicon on insulator (SOI).

[0084] The substrate 11 may include a source region 11b, a drain region 11a, and a channel 11c electrically connected to the source region 11b and the drain region 11a. The source region 11b may be electrically connected to or in contact with one end of the channel 11c, and the drain region 11a may be electrically connected to or in contact with the other end of the channel 11c. In other words, the channel 11c is also defined as a substrate region in the substrate 11 between the source region 11b and the drain region 11a.

[0085] The source region 11b, the drain region 11a, and the channel 11c may also be formed independently by implanting impurities into different regions of the substrate 11, in which case the source region 11b, the channel 11c, and the drain region 11a may contain the substrate material as a base material.

[0086] The source region 11b and the drain region 11a may also be formed of a conductive material, and may, for example, each independently include a metal, a metal compound, or a conductive polymer.

[0087] The channel 11c may also be realized by a separate material layer (thin film) (not shown). In this case, for example, the channel 11c may include not only semiconductor materials such as Si, Ge, SiGe, and III-V group semiconductors, but also oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional materials, quantum dots (QDs), and / or organic semiconductors. For example, the oxide semiconductor may include InGaZnO, etc., the two-dimensional material may include transition metal dichalcogenides (TMDs) or graphene, and the quantum dots may include colloidal quantum dots (QDs) or nanocrystalline structures.

[0088] The gate electrode 12b is disposed on the substrate 11, spaced apart from the substrate 11, and facing the channel 11c. The gate electrode 12b may have a conductivity of 1 MΩ / sq or less. The gate electrode 12b may include a metal, a metal nitride film, a metal carbide, and / or polysilicon. For example, the metal may include aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and / or tantalum (Ta), and the metal nitride film may include a titanium nitride film (TiN film) and / or a tantalum nitride film (TaN film). The metal carbide may also be a metal carbide doped (or containing) aluminum and / or silicon, and specific examples thereof may include TiAlC, TaAlC, TiSiC, or TaSiC. The gate electrode 12b may have a structure in which multiple materials are stacked, for example, a stacked structure of a metal nitride layer / metal layer such as TiN / Al, or a stacked structure of a metal nitride layer / metal carbide layer / metal layer such as TiN / TiAlC / W. The gate electrode 12b may include titanium nitride (TiN) or molybdenum (Mo), and various modifications of the above examples may also be used.

[0089] A gate insulating layer 12a may be further disposed between the substrate 11 and the gate electrode 12b. The gate insulating layer 12a may include a paraelectric material or a high-dielectric material and may have a dielectric constant of 20 to 70. The gate insulating layer 12a may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, etc., or a two-dimensional insulator (2D insulator) such as h-BN (hexagonal boron nitride). For example, the gate insulating layer 12a may be silicon oxide (SiO2), silicon nitride (SiN x), and the like, may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalate (PbSc 0.5 Ta 0.5 The gate insulating layer 12a may include a metal nitride oxide such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), or yttrium oxynitride (YON); a silicate such as ZrSiON, HfSiON, YSiON, or LaSiON; or an aluminate such as ZrAlON or HfAlON. The gate insulating layer 12a may also include the dielectric layers 300 and 302 described above. The gate insulating layer 12a, together with the gate electrode 12b, can form a gate stack.

[0090] The contact 20 may include a suitable conductive material, such as tungsten, copper, aluminum, polysilicon, etc. In some embodiments, the contact 20 may be omitted. For example, the lower electrode 100 may be disposed so as to directly contact the source region 11b and / or the drain region 11a. In this case, the conductive material included in the source region 11b and / or the drain region 11a and / or the lower electrode may function as the contact 20.

[0091] The arrangement of the capacitor 1 and the field effect transistor 10 can be modified in various ways. For example, the capacitor 1 can be disposed on the substrate 11 or embedded in the substrate 11.

[0092] While FIGS. 4A and 4B illustrate a semiconductor device 1 having one capacitor 1 and one field-effect transistor 10, a semiconductor device D10 may have a structure in which a plurality of capacitors and a plurality of field-effect transistors are repeatedly arranged, as shown in FIG. 5. Referring to FIG. 5, the semiconductor device D10 may further include a substrate 11' including a source, a drain, and a channel, a field-effect transistor including a gate stack 12, a contact structure 20' arranged on the substrate 11' so as not to overlap with the gate stack 12, and a capacitor 1' arranged on the contact structure 20', and a bit line structure 13 electrically connecting the plurality of field-effect transistors. While FIG. 5 illustrates a semiconductor device D10 in which the contact structures 20' and the capacitors 1' are repeatedly arranged along the X and Y directions, the present invention is not limited thereto. For example, the contact structures 20' may be arranged along the X and Y directions, and the capacitors 1' may be arranged in a hexagonal shape, such as a honeycomb structure.

[0093] Fig. 6 is an example of a cross-sectional view taken along line AA' in the semiconductor device D10 of Fig. 5. Fig. 7 shows a modified example of Fig. 6.

[0094] 6 and 7, the substrate 11′ may have a shallow trench isolation (STI) structure including an isolation layer 14. The isolation layer 14 may be a single layer of one type of insulating film or a multi-layer structure of two or more types of insulating films. The isolation layer 14 may include an isolation trench 14T in the substrate 11′, and the isolation trench 14T may be filled with an insulating material. The insulating material may include, but is not limited to, fluoride silicate glass (FSG), undoped silicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma enhanced tetraethyl ortho-silicate (PE-TEOS), and / or tonosilazene (TOSZ).

[0095] The substrate 11′ may further include an active region AC defined by an isolation film 14 and gate line trenches 12T arranged to extend in the X direction parallel to the top surface of the substrate 11′. The active region AC may have a relatively long island shape having a short axis and a long axis. As exemplarily shown in FIG. 5, the long axis of the active region AC is also arranged along the D3 direction parallel to the top surface of the substrate 11′. The gate line trenches 12T may be arranged to intersect with the active region AC at a predetermined depth from the top surface of the substrate 11′ or within the active region AC. The gate line trenches 12T may also be arranged within the isolation trenches 14T, and the gate line trenches 12T within the isolation trenches 14T may have a lower bottom surface than the gate line trenches 12T in the active region AC.

[0096] The first source / drain 11'ab and the second source / drain 11''ab are also disposed in upper portions of the active region AC located on both sides of the gate line trench 12T.

[0097] A gate stack 12 may be disposed within the gate line trench 12T. Specifically, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be sequentially disposed within the gate line trench 12T. The gate insulating layer 12a and the gate electrode 12b may refer to the above-described contents, and the gate capping layer 12c may include silicon oxide, silicon oxynitride, and / or silicon nitride. The gate capping layer 12c may be disposed on the gate electrode 12b to fill the remaining portion of the gate line trench 12T.

[0098] Bit line structures 13 may also be disposed on the first source / drains 11′ab. The bit line structures 13 may be disposed parallel to the top surface of the substrate 11′ and extend in the Y direction. The bit line structures 13 are electrically connected to the first source / drains 11′ab and may include bit line contacts 13a, bit lines 13b, and a bit line capping layer 13c, which are sequentially disposed on the substrate. For example, the bit line contacts 13a may include polysilicon, the bit lines 13b may include a metal material, and the bit line capping layer 13c may include an insulating material such as silicon nitride or silicon oxynitride. While FIGS. 6 and 7 illustrate the bit line contacts 13a having a bottom surface flush with the top surface of the substrate 11′, the bit line contacts 13a may extend from the top surface of the substrate 11′ to within a recess (not shown) formed at a predetermined depth, so that the bottom surface of the bit line contacts 13a is lower than the top surface of the substrate 11′.

[0099] Optionally, the bit line structure 13 may include a bit line interlayer (not shown) between the bit line contact 13a and the bit line 13b. The bit line interlayer may include a metal silicide, such as tungsten silicide, and / or a metal nitride, such as tungsten nitride. Bit line spacers (not shown) may also be formed on sidewalls of the bit line structure 13. The bit line spacers may have a single-layer structure or a multi-layer structure and may include an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride. The bit line spacers may also include air spaces (not shown).

[0100] The contact structure 20' is also disposed on the second source / drain 11''ab. The contact structure 20' and the bit line structure 13 are also disposed on different source / drains on the substrate. The contact structure 20' has a structure in which a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) are sequentially stacked on the second source / drain 11''ab. The contact structure 20' may further include a barrier layer (not shown) surrounding the side and bottom of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metal material, and the barrier layer may include a conductive metal nitride.

[0101] The capacitor 1′ may be electrically connected to the contact structure 20′ and disposed on the substrate 11′. Specifically, the capacitor 1′ may include a lower electrode 100 electrically connected to the contact structure 20′, a dielectric layer 300 disposed on the lower electrode 100, and an upper electrode 200 disposed on the dielectric layer 300. The dielectric layer 300 may be disposed on the lower electrode so as to be parallel to a surface of the lower electrode.

[0102] An interlayer insulating layer 15 may be further disposed between the capacitor 1′ and the substrate 11′. The interlayer insulating layer 15 is also disposed in the space between the capacitor 1′ and the substrate 11′ where no other structures are disposed. Specifically, the interlayer insulating layer 15 is also disposed to cover wiring structures and / or electrode structures, such as the bit line structure 13, the contact structure 20′, and the gate stack 12, on the substrate. For example, the interlayer insulating layer 15 may surround the walls of the contact structure 20′. The interlayer insulating layer 15 may include a first interlayer insulating layer 15a surrounding the bit line contact 13a and a second interlayer insulating layer 15b covering the side and / or top surfaces of the bit line 13b and the bit line capping layer 13c.

[0103] The lower electrode 100 of the capacitor 1′ is also disposed on the interlayer insulating layer 15, specifically on the second interlayer insulating layer 15b. When multiple capacitors 1′ are disposed, the bottom surfaces of the multiple lower electrodes 100 may be separated by the etching stop layer 16. In other words, the etching stop layer 16 may include an opening 16T, and the bottom surfaces of the lower electrodes 100 of the capacitor 1′ may be disposed within such opening 16T.

[0104] The lower electrode 100 may have a cup shape as shown in Fig. 6. As another example, the lower electrode 100 may have a pillar shape such as a cylindrical, rectangular, or polygonal pillar extending along the vertical direction (Z direction) as shown in the figure.

[0105] Furthermore, the capacitor 1 ′ may further include a support portion (not shown) for preventing the lower electrode 100 from tilting or falling over, and the support portion is also disposed on the sidewall of the lower electrode 100 .

[0106] The semiconductor devices D10 and D30 can be manufactured by a general method known in the art. Specifically, the semiconductor devices D10 and D30 can be manufactured by the following steps i) to xvi).

[0107] i) forming an isolation trench 14T in the substrate 11′ and forming an isolation film 14 in the isolation trench 14T (defining an active region AC of the substrate 11′ by the isolation film 14 and / or the isolation trench 14T);

[0108] ii) filling the inside of the isolation trench 14T with an insulating material;

[0109] iii) implanting impurity ions into the substrate 11' to form first source / drains 11'ab and second source / drains 11''ab in the upper region of the active region AC;

[0110] iv) forming a gate line trench 12T in the substrate 11′;

[0111] v) forming a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c inside the gate line trench 12T;

[0112] vi) forming a first interlayer insulating layer 15a on the substrate 11' and forming openings (not shown) exposing the top surfaces of the first source / drains 11'ab;

[0113] vii) forming a bit line structure 13 electrically connected to the first source / drain 11'ab on the opening of vi);

[0114] viii) forming a second interlayer insulating layer 15b covering the top and side surfaces of the bit line structure 13;

[0115] ix) forming openings (not shown) in the first interlayer insulating layer 15a and the second interlayer insulating layer 15b to expose the top surfaces of the second source / drains 11''ab;

[0116] x) forming a contact structure 20' electrically connected to the second source / drain 11''ab on the opening of ix);

[0117] xi) forming an etching stop layer 16 and a mold layer (not shown) on the second interlayer insulating film 15b and the contact structure 20′;

[0118] xii) forming an opening (not shown) in the etch stop layer 16 and the mold layer (not shown) to expose the top surface of the contact structure 20';

[0119] xiii) forming a lower electrode 100 to cover the inner wall of the opening (to cover the bottom and side surfaces) of xii);

[0120] xiv) Removing the mold layer (not shown)

[0121] xv) forming a dielectric layer 300 on the lower electrode 100

[0122] xvi) forming the upper electrode 200 on the dielectric layer 300

[0123] The types and / or order of the above steps are not limited and may be adjusted, omitted, or added as appropriate. Forming components in each step may utilize deposition processes, patterning processes, etching processes, and the like known in the art. For example, an etch-back process may be used to form the electrodes. In step v), the gate electrode 12b may be formed by forming a conductive layer on the gate insulating layer 12a and then removing a predetermined height of the upper portion of the conductive layer through an etch-back process. In step xiii), the lower electrode 100 may be formed by forming an electrode to cover the upper surface of the mold layer and the bottom and side surfaces of the opening, and then removing a portion of the electrode on the upper surface of the mold layer through an etch-back process, thereby fabricating a structure having a plurality of lower electrodes 100. As another example, a planarization process may be used. For example, in step v), the gate capping layer 12c may be formed by filling the remaining portion of the gate line trench 12T with an insulating material and then planarizing the insulating material until the upper surface of the substrate 11′ is exposed.

[0124] The semiconductor device and semiconductor device may be applied to various electronic devices. Specifically, the semiconductor device and / or semiconductor device may be applied as a logic element or a memory element in various electronic devices. Specifically, the semiconductor device and semiconductor device may be used for arithmetic operations, program execution, temporary data storage, etc. in electronic devices such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices. The semiconductor device and semiconductor device according to an embodiment are useful for electronic devices that transmit a large amount of data continuously.

[0125] 8 and 9 are conceptual diagrams that schematically illustrate electronic element architectures that may be applied to electronic devices, according to one embodiment.

[0126] Referring to FIG. 8, the electronic device architecture 1000 may include a memory unit 1010, an ALU (arithmetic logic unit) 1020, and a control unit 1030. The memory unit 1010, the ALU 1020, and the control unit 1030 are electrically connected to each other. For example, the electronic device architecture 1000 may be implemented as a single chip including the memory unit 1010, the ALU 1020, and the control unit 1030. Specifically, the memory unit 1010, the ALU 1020, and the control unit 1030 are interconnected on-chip via metal lines and can communicate directly. The memory unit 1010, the ALU 1020, and the control unit 1030 may also be monolithically integrated on a single substrate to form a single chip. An input / output device 2000 may be connected to the electronic device architecture (chip) 1000. The memory unit 1010 may include both a main memory and a cache memory. Such an electronic device architecture (chip) 1000 may also be an on-chip memory processing unit.

[0127] The memory unit 1010, the ALU 1020, and / or the control unit 1030 may each independently include the semiconductor elements described above. Referring to FIG. 9, the cache memory 1510, the ALU 1520, and the control unit 1530 may constitute a central processing unit (CPU) 1500, and the cache memory 1510 may include a static random access memory (SRAM). A main memory 1600 and an auxiliary storage 1700 may be provided separately from the CPU 1500. The main memory 1600 may be a dynamic random access memory (DRAM) and may include the semiconductor elements described above.

[0128] In some cases, the electronic device architecture is also embodied in a form in which the computing unit elements and memory unit elements are adjacent to each other on a single chip without division into sub-units.

[0129] Hereinafter, the technical contents of the semiconductor device will be described in more detail through embodied embodiments, however, the following embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

[0130] Example 1 The bottom electrode was formed via a DC (direct current) sputter ALD method.

[0131] A dielectric layer was formed on the lower electrode via atomic layer deposition (ALD). Specifically, a first metal oxide layer containing zirconium oxide (ZrO) was formed, followed by a second metal oxide layer containing zirconium (Zr) and yttrium (Y) on the first metal oxide layer, and then a third metal oxide layer containing aluminum (Al) on the second metal oxide layer. The amounts of the zirconium (Zr) precursor and the yttrium (Y) precursor used during the formation of the second metal oxide layer were adjusted so that the zirconium (Zr), yttrium (Y), and oxygen (O) ratios in the second metal oxide layer were 0.09, 0.26, and 0.65, respectively.

[0132] A top electrode was formed on the dielectric layer via DC sputtering or ALD.

[0133] The layers and electrodes thus formed were subjected to rapid thermal annealing (RTA) at temperatures between 400°C and 1,000°C to fabricate capacitors.

[0134] The TEM-EDS analysis results of the manufactured dielectric layer are shown in Figure 10. Referring to Figure 10, it can be seen that yttrium (Y) and aluminum (Al) have concentration gradients in the thickness direction in the manufactured dielectric layer, and that they each have their maximum concentrations at different positions.

[0135] Examples 2 to 5 A capacitor was manufactured in the same manner as in Example 1, except that the amounts of zirconium (Zr) precursor and yttrium (Y) precursor were varied during the formation of the second metal oxide layer to adjust the ratio of elements in the second metal oxide layer.

[0136] Comparative Example 1 A capacitor was manufactured in the same manner as in Example 1, except that a metal oxide layer containing yttrium (Y) was formed on the first metal oxide layer instead of the second and third metal oxide layers.

[0137] Comparative Example 2 A capacitor was manufactured in the same manner as in Example 1, except that a metal oxide layer containing zirconium (Zr) and aluminum (Al) was formed on the first metal oxide layer instead of the second metal oxide layer and the third metal oxide layer.

[0138] Electrical Characterization 1 A voltage of 1.0 V was applied to the capacitors manufactured by the methods of Example 1, Comparative Example 1, and Comparative Example 2 to measure the capacitance. The capacitances were normalized based on the capacitance of the capacitor of Comparative Example 1, and the capacitances of each capacitor are listed in Table 1.

[0139] Referring to Table 1, the capacitor of Example 1, which contains three metal elements, i.e., zirconium (Zr), aluminum (Al), and yttrium (Y), or three metal oxide layers in the dielectric layer, exhibited higher capacitance than Comparative Examples 1 and 2, which contain two metal elements or two metal oxide layers.

[0140] [Table 1]

[0141] Electrical Characterization 2 A voltage of 1.0 V was applied to the capacitors manufactured by the methods of Examples 1 to 5 and Comparative Example 1, and the capacitances were measured. The capacitances were normalized based on the capacitance of the capacitor of Comparative Example 1, and the capacitances of the capacitors are shown in Table 2.

[0142] Furthermore, a voltage of 1.0 V was applied to Examples 1 to 5 and Comparative Example 1, and the leakage current values ​​were measured. The results are shown in Table 2.

[0143] Referring to Table 2, the capacitors of Examples 1 to 5, which contain three metal elements, yttrium (Y), aluminum (Al), and zirconium (Zr), or three metal oxide layers in the dielectric layer, exhibited lower leakage current values ​​than Comparative Example 1, which contains two metal elements, aluminum (Al) and zirconium (Zr), or two metal oxide layers. In addition, the capacitors of Examples 1 to 4, in which the ratio of yttrium (Y) in the second metal oxide layer was 0.15 or less, exhibited higher electrical capacitance than Comparative Example 1.

[0144] [Table 2]

[0145] Example 6 Except for changing the order of introducing the aluminum (Al) precursor and the yttrium (Y) precursor and changing the positions of aluminum (Al) and yttrium (Y) in the dielectric layer, a capacitor was fabricated in the same manner as in Example 1. Specifically, a capacitor was fabricated that included a third metal oxide layer containing zirconium (Zr) and aluminum (Al) on a first metal oxide layer, and a second metal oxide layer containing yttrium (Y) on the third metal oxide layer.

[0146] Electrical Characterization 3 A voltage of 1.0 V was applied to the capacitors of Examples 1 and 6, and the capacitance and leakage current value when 1.0 V was applied were measured and shown in Table 3. The capacitance was normalized based on the capacitance of the capacitor of Example 1.

[0147] Referring to Table 3, the capacitors of Examples 1 and 6 have similar levels of capacitance, but the capacitor of Example 6, in which yttrium (Y) rather than aluminum (Al) is disposed adjacent to the upper electrode, exhibits a higher leakage current value than Example 1.

[0148] [Table 3]

[0149] Examples 7 and 8 Capacitors were fabricated in the same manner as in Example 1, except that the thicknesses of the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer were adjusted so that the second metal oxide layer was positioned at a distance of 40% or more of the total thickness of the dielectric layer from the lower electrode (Example 7) and at a distance of less than 40% of the total thickness of the dielectric layer from the lower electrode (Example 8). As a result, the dielectric layer of Example 7 had a maximum concentration of yttrium (Y) at a position 40% or more of the thickness of the dielectric layer from the lower electrode, and the dielectric layer of Example 8 had a maximum concentration of yttrium (Y) at a position less than 40% of the thickness of the dielectric layer from the lower electrode.

[0150] Electrical Characterization 4 A voltage of 1.0 V was applied to the capacitors of Examples 7 and 8, and the capacitance and leakage current value when 1.0 V was applied were measured and shown in Table 4. The capacitance was normalized based on the capacitance of the capacitor of Example 7.

[0151] Referring to Table 4, the capacitor of Example 7, in which the second metal oxide layer was positioned at a distance of 40% or more of the total thickness of the dielectric layer from the lower electrode, exhibited a higher capacitance and a lower leakage current value than Example 8.

[0152] [Table 4]

[0153] Although the present embodiment has been described in detail above, the scope of the rights is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concepts defined in the claims also fall within the scope of the rights. [Explanation of symbols]

[0154] 1,1',2,3a,3b semiconductor element 100 Lower electrode 200 Upper electrode 300,302 Dielectric layer 310 First metal oxide layer 320 Second metal oxide layer 330 Third metal oxide layer D1, D10, D30 Semiconductor device

Claims

1. A lower electrode; an upper electrode spaced apart from the lower electrode; an electronic element comprising: a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer comprising: a first metal oxide layer containing one or more metal elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu; a second metal oxide layer containing Y and Zr; and a third metal oxide layer containing one or more metal elements selected from the group consisting of Al, Mg, and Be.

2. The electronic device according to claim 1 , wherein the first metal oxide layer, the second metal oxide layer, and the third metal oxide layer are sequentially disposed in a thickness direction between the lower electrode and the upper electrode.

3. 3. The electronic device according to claim 1, wherein the second metal oxide layer further contains one or more metal elements selected from the group consisting of Hf, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu.

4. 4. The electronic device according to claim 1, wherein the second metal oxide layer contains a compound represented by AxByOz (wherein A is one or more elements selected from the group consisting of Y, Sc, and Ce, B is one or more elements selected from the group consisting of Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, Sr, and Lu, O is oxygen, and x+y+z=1).

5. The electronic device according to claim 4 , wherein the content of the A element (x) relative to the content of the B element (y) in the second metal oxide layer is 0.01 or more and 1.0 or less.

6. 6. The electronic device according to claim 4, wherein in the compound represented by AxByOz, x is more than 0.0 and is 0.2 or less.

7. 7. The electronic device according to claim 4, wherein in the compound represented by AxByOz, x is greater than 0.0 and is 0.15 or less.

8. 8. The electronic device according to claim 4, wherein in the compound represented by AxByOz, y is greater than 0.0 and is 0.5 or less.

9. 9. The electronic device according to claim 4, wherein in the compound represented by AxByOz, y is 0.2 or more and 0.5 or less.

10. the first metal oxide layer is disposed adjacent to the bottom electrode; 10. The electronic device according to claim 1, wherein the thickness of the first metal oxide layer is 40% or more of the total thickness of the dielectric layer.

11. The electronic device according to claim 1 , wherein the second metal oxide layer has a thickness of 5 Å or more and 50 Å or less.

12. 12. The electronic device according to claim 1, wherein the thickness of the dielectric layer is not less than 20 Å and not more than 100 Å.

13. 13. The electronic device of claim 1, wherein the bottom electrode, the top electrode, or both each independently comprise a metal, a metal nitride, a metal oxide, or a combination thereof.

14. The bottom electrode, the top electrode, or both of them may be selected from the group consisting of MM'N (where M is Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, M' is an element selected from the group consisting of Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U, and M' is different from M and is selected from the group consisting of H, Li, As, Se, N, O, P, S, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, G 14. The electronic device according to claim 1, comprising a metal nitride represented by the formula (I) in which N is one or more elements selected from the group consisting of Zn, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and U, and N is nitrogen.

15. A lower electrode; an upper electrode spaced apart from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including one or more first metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu, a second metal element which is Y, one or more third metal elements selected from the group consisting of Al, Mg, and Be, and a fourth metal element which is Zr; The second metal element and the third metal element have a concentration gradient in the thickness direction of the dielectric layer, and have maximum concentrations at different positions, respectively.

16. The electronic device according to claim 15 , wherein the second metal element has a maximum concentration at a position that is 40% to 90% of the thickness of the dielectric layer away from the lower electrode.

17. The electronic device of claim 15 or 16, wherein the content of the second metal element is more than 0.0 at % and not more than 5.0 at % relative to the total amount of metal elements in the dielectric layer.

18. 18. The electronic device according to claim 15, wherein the third metal element has a maximum concentration at a position that is more than 0% and not more than 20% of the thickness of the dielectric layer away from the upper electrode.

19. A lower electrode; an upper electrode spaced apart from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including one or more first metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu, one or more second metal elements selected from Y, Sc, and Ce, and one or more third metal elements selected from the group consisting of Al, Mg, and Be; the second metal element and the third metal element have a concentration gradient in a thickness direction of the dielectric layer, and have maximum concentrations at different positions, respectively; The electronic device, wherein the third metal element is present in an amount exceeding 0.0 at % and not more than 5.0 at % relative to the total amount of metal elements in the dielectric layer.

20. A lower electrode; an upper electrode spaced apart from the lower electrode; a dielectric layer disposed between the lower electrode and the upper electrode, the dielectric layer including one or more first metal elements selected from Hf, Zr, Nb, Ta, Pr, Nd, Gd, Dy, Yb, Pb, Zn, Si, Ti, and Lu, one or more second metal elements selected from Y, Sc, and Ce, and one or more third metal elements selected from the group consisting of Al, Mg, and Be; the second metal element and the third metal element have a concentration gradient in a thickness direction of the dielectric layer, and have maximum concentrations at different positions, respectively; An electronic device, wherein the content of the second metal element in the dielectric layer is 10% or more and 200% or less of the content of the third metal element.

21. a field effect transistor; A semiconductor device comprising: the field effect transistor; and the electronic device according to claim 1 , electrically connected to the field effect transistor.

22. The field effect transistor is 22. The semiconductor device according to claim 21, comprising: a semiconductor layer including a source region and a drain region; a gate insulating layer disposed on the semiconductor layer; and a gate electrode disposed on the gate insulating layer.

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