Semiconductor device, method of forming a semiconductor device, and device

Abstract

To solve the problem of collapse of pillars caused by capillary force in trenches resulting from drying the pillars after wet cleaning.SOLUTION: A semiconductor fabrication method comprises the steps of: providing a stack on a substrate, the stack including a plurality of device layers including electrically conductive layers; patterning the stack using etching to form trenches extending through the stack and pillars between the trenches; providing a carbon-containing liner on sidewalls of the trenches; wet cleaning and drying the stack after providing the carbon-containing liner; filling spaces between the pillars with one or more materials; and electrically coupling contact lines to the electrically conductive layers to form a semiconductor device. The carbon-containing liner includes a carbon-doped liner, such as a carbon-doped oxide liner provided by way of atomic layer deposition of an oxide at a temperatures of about 100°C to about 300°C using carbon as a precursor.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates generally to the field of semiconductor manufacturing, and more particularly to semiconductor manufacturing, including the provision of high aspect ratio features in semiconductor structures by etching procedures followed by wet cleaning and drying. [Background technology]

[0002] The storage device may include a non-volatile memory such as a multi-stack 3D memory cell or array. The memory cell typically includes a high aspect ratio cell structure created by performing successive etches to form successively deeper trenches into a layer structure and using a wet cleaning procedure followed by drying after at least one of the etches.

[0003] In particular, current integration schemes for fabricating 3D memory structures rely on providing a nitride liner and an oxide etch-protective liner that are deposited over the nitride liner using atomic layer deposition (ALD) after a first etch of various layers of the 3D memory structure. The first etch may first etch through a first subset of the layers of the 3D memory structure to form a first trench, and the nitride liner and etch-protective liner may be deposited over the first trench. The nitride liner and oxide etch-protective liner are provided to protect one or more underlying layers within the various layers of the 3D memory structure during a second etch of the various layers. The nitride layer may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the oxide may be deposited using ALD. For example, a second etch may then etch through a second subset of the layers of the 3D memory structure to form a second trench that is longer than the first trench. Another nitride liner and another oxide etch protection liner are then applied using ALD to protect any sensitive layers during the final etch through the remaining subset of layers of the 3D memory structure, forming a third trench that is longer than the second trench.

[0004] The ALD oxide layer laid down between successive etches is typically hydrophilic, which leads to high surface tension during the second and final etch, wet clean dry processes, which tend to subject high aspect ratio pillars to line wobble and / or pattern collapse. Thus, in some previous approaches, capillary forces within the trenches caused by drying the pillars after wet clean can cause the pillars to wobble (e.g., tip over) relative to each other.

[0005] Pattern collapse during the wet clean and dry process is a challenge for high aspect ratio cell structures and is expected to worsen with cell scaling. Pattern collapse can be caused by capillary forces exerted on trench sidewalls during the wet clean and dry processes. Capillary forces can act to tip the high aspect ratio features that define the trench relative to each other, leading to reliability issues associated with memory devices formed therefrom. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic block diagram of components of a computer system according to some embodiments.

[0007] [Figure 2] FIG. 2 is a schematic diagram of a memory partition in accordance with certain embodiments.

[0008] [Figure 3] 1 is a schematic diagram of a memory array in accordance with certain embodiments.

[0009] [Figure 4] 1 is a schematic perspective three-dimensional view of a semiconductor structure for a 3D memory architecture according to some embodiments. FIG.

[0010] [Figure 5] 1 is a cross-sectional side view of a semiconductor pattern in which high aspect ratio features thereof have undergone pattern collapse or upturning.

[0011] [Figure 6A] 2 is a schematic cross-sectional view of a multi-layer semiconductor structure after a first etching process to provide a first trench, according to one embodiment. FIG.

[0012] [Figure 6B] FIG. 6B is a view similar to FIG. 6A showing the structure of FIG. 6A provided with a first etch protection liner, according to one embodiment.

[0013] [Figure 6C] FIG. 6C is a view similar to FIG. 6B showing the structure of FIG. 6B subjected to a second etch to deepen the first trench into a second, longer trench, according to one embodiment.

[0014] [Figure 6D] FIG. 6D is a view similar to FIG. 6C showing the structure of FIG. 6C provided with a second etch-protective liner, according to one embodiment.

[0015] [Figure 6E] 6E is a view similar to FIG. 6D showing the structure of FIG. 6D subjected to a final etch to deepen the second trench into a third, longer trench, according to one embodiment, and the structure of FIG. 6E is used in the semiconductor architecture of a microelectronic device, according to one embodiment.

[0016] [Figure 7] 1 illustrates an exemplary process for patterning a semiconductor structure according to certain embodiments.

[0017] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0018] Although the figures depict a particular computer system, the concepts of various embodiments are applicable to any suitable computer system. Examples of systems in which the teachings of the present disclosure can be used include desktop computer systems, server computer systems, storage systems, handheld devices, tablets, other thin notebooks, system-on-a-chip (SOC) devices, and embedded applications. Some examples of handheld devices include mobile phones, digital cameras, media players, personal digital assistants (PDAs), and handheld PCs. Embedded applications may include microcontrollers, digital signal processors (DSPs), SOCs, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other system capable of performing the functions and operations taught below. Various embodiments of the present disclosure may be used in any suitable computing environment, such as personal computing devices, servers, mainframes, cloud computing service provider infrastructures, data centers, communications service provider infrastructures (e.g., one or more portions of an evolved packet core), or other environments including one or more computing devices.

[0019] 1 shows a block diagram of components of a computer system 100 according to some embodiments. System 100 includes a central processing unit (CPU) 102 coupled to an external input / output (I / O) controller 104, a storage device 106, such as a solid-state drive (SSD), and a system memory device 107. During operation, data may be transferred between storage device 106 and / or system memory device 107 and CPU 102. In various embodiments, particular memory access operations (e.g., read and write operations) involving storage device 106 or system memory device 107 may be issued by an operating system and / or other software applications executed by processor 108. In various embodiments, storage device 106 may include a storage device controller 118 and one or more memory chips 116, each containing any suitable number of memory partitions 122.

[0020] In various embodiments, memory partition 122 may include a 3D cross-point memory array, which in some embodiments may include a transistorless (e.g., at least in relation to the data storage elements of the memory) stackable cross-point architecture in which memory cells are located at the intersections of row and column address lines arranged in a grid.

[0021] During a read operation, a differential bias, sometimes referred to as a demarcation voltage (VDM), may be applied across the terminals of the memory cell, and the state of the memory cell may be sensed based on the memory cell's response to the applied bias. For example, the memory cell may either enter a conductive ON state (logic 1) or remain in a weakly conductive OFF state (logic 0). The applied voltage at which the memory cell transitions from a state sensed as a logic 1 to a state sensed as a logic 0 may be termed the memory cell's threshold voltage. Thus, as an example, if VDM is higher than the memory cell's threshold voltage, the memory cell may be sensed as storing a logic 1, and if VDM is lower than the memory cell's threshold voltage, the memory cell may be sensed as storing a logic 0.

[0022] CPU 102 includes a processor 108, such as a microprocessor, embedded processor, digital signal processor (DSP), network processor, handheld processor, application processor, co-processor, SOC, or other device for executing code (e.g., software instructions). In the illustrated embodiment, processor 108 includes two processing elements (cores 114A and 114B in the illustrated embodiment), which may include asymmetric or symmetric processing elements. However, a processor may include any number of processing elements, which may be symmetric or asymmetric. CPU 102 may be referred to herein as a host computing device (although a host computing device may be any suitable computing device operable to issue memory access commands to storage device 106).

[0023] A processing element refers to hardware or logic for supporting a software thread. Examples of hardware processing elements include a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element capable of maintaining a processor state, such as an execution state or an architectural state. In other words, in one embodiment, a processing element refers to any hardware capable of being associated with code, such as a software thread, an operating system, an application, or independently other code. A physical processor (or processor socket) typically refers to an integrated circuit that potentially contains any number of other processing elements, such as cores or hardware threads.

[0024] A core 114 (e.g., 114A or 114B) may refer to logic located on an integrated circuit capable of maintaining independent architectural states, each of which is associated with at least some dedicated execution resources. A hardware thread may refer to any logic located on an integrated circuit capable of maintaining independent architectural states, each of which shares access to execution resources. As will be appreciated, the nomenclature boundaries between hardware threads and cores overlap when certain resources are shared and other resources are dedicated to architectural state. However, often cores and hardware threads are viewed by an operating system as individual logical processors, and the operating system can schedule operations on each logical processor independently.

[0025] A processing element may also include one or more arithmetic logic units (ALUs), floating point units (FPUs), caches, instruction pipelines, interrupt handling hardware, registers, or other hardware to facilitate the operation of the processing element.

[0026] I / O controller 110 is an integrated I / O controller that includes logic for communicating data between CPU 102 and I / O devices, which may refer to any suitable logic capable of transferring data to and / or receiving data from an electronic system, such as CPU 102. For example, an I / O device may include an audio / video (A / V) device controller, such as a graphics accelerator or an audio controller; a data storage device controller, such as a memory device, magnetic storage disk, or optical storage disk controller; a wireless transceiver, a network processor, a network interface controller, or a controller for another input device, such as a monitor, printer, mouse, keyboard, or scanner, or other suitable device. In particular embodiments, an I / O device may include a storage device controller 118 of storage device 106 coupled to CPU 102 through I / O controller 110. I / O circuitry (not shown) of storage device controller 118 may be used to communicate data and signals between the CPU and storage device controller 118 of storage device 106.

[0027] I / O devices may communicate with I / O controller 110 of CPU 102 using any suitable signaling protocol, such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), Universal Serial Bus (USB), Serial Attached SCSI (SAS), Serial ATA (SATA), Fibre Channel (FC), IEEE 802.3, IEEE 802.11, or other current or future signaling protocols. In particular embodiments, I / O controller 110 and associated I / O devices may communicate data and commands in accordance with a logical device interface specification such as Non-Volatile Memory Express (NVMe) (e.g., as described in one or more of the specifications available at www.nvmexpress.org / specifications / ) or Advanced Host Controller Interface (AHCI) (e.g., as described in one or more AHCI specifications such as the Serial ATA AHCI Specification, Rev. 1.3.1, available at http: / / www.intel.com / content / www / us / en / io / serial-ata / serial-ata-ahci-spec-rev1-3-1.html). In various embodiments, I / O devices coupled to I / O controller 110 may be located off-chip (e.g., not on the same chip as CPU 102) or may be integrated on the same chip as CPU 102.

[0028] CPU memory controller 112 is an integrated memory controller that controls the flow of data to and from one or more system memory devices 107. CPU memory controller 112 may include logic operable to read from, write to, or request other operations from system memory devices 107. In various embodiments, CPU memory controller 112 may receive write requests from cores 114 and / or I / O controller 110 and provide data specified in these requests to system memory devices 107 for storage therein. CPU memory controller 112 may also read data from system memory devices 107 and provide the read data to I / O controller 110 or cores 114. During operation, CPU memory controller 112 may issue commands including one or more addresses of system memory devices 107 to read data from or write data to memory (or perform other operations). In some embodiments, CPU memory controller 112 may be implemented on the same chip as CPU 102, and in other embodiments, CPU memory controller 112 may be implemented on a different chip than CPU 102. I / O controller 110 may perform similar operations in connection with one or more storage devices 106.

[0029] The CPU 102 may also be coupled to one or more other I / O devices through an external I / O controller 104. In particular embodiments, the external I / O controller 104 may couple a storage device 106 to the CPU 102. The external I / O controller 104 may include logic for managing the flow of data between one or more CPUs 102 and the I / O devices. In particular embodiments, the external I / O controller 104 is located on a motherboard along with the CPU 102. The external I / O controller 104 may exchange information with components of the CPU 102 using a point-to-point or other interface. According to alternative embodiments, the external I / O controller 104 may be used to couple the CPU 102 to I / O devices other than the storage device 106, which may be directly coupled to the CPU 102.

[0030] In this disclosure, the I / O controller 110, the CPU memory controller 112, and the external I / O controller 104 may each be referred to as an "external controller" from the perspective of the storage device 106.

[0031] System memory device 107 may store any suitable data, such as data used by processor 108 to provide functionality of computer system 100. For example, data associated with programs executed or files accessed by cores 114 may be stored in system memory device 107. As such, system memory device 107 may include system memory that stores data and / or sequences of instructions executed or otherwise used by cores 114. In various embodiments, system memory device 107 may store temporary data, persistent data (e.g., user files or instruction sequences) that maintains its state even after power to system memory device 107 is removed, or a combination thereof. System memory device 107 may be dedicated to a particular CPU 102 or may be shared with other devices in computer system 100 (e.g., one or more other processors or other devices).

[0032] In various embodiments, system memory device 107 may include memory, including any number of memory partitions, memory device controllers, and other support logic (not shown). The memory partitions may include non-volatile memory and / or volatile memory.

[0033] Nonvolatile memory is a storage medium that does not require power to maintain the state of data stored by the medium, and therefore, nonvolatile memory may have a consistent state even when power to the device containing the memory is interrupted. In various embodiments, nonvolatile memory may be byte or block addressable. Non-limiting examples of nonvolatile memory include solid-state memory (e.g., planar or three-dimensional (3D) NAND flash memory or NOR flash memory), 3D cross-point memory, phase change memory or SXP memory (e.g., memory that uses chalcogenide glass phase change material in memory cells), ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM), ovonic memory, antiferroelectric memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), memristors, silicon The memory devices may include single-level or multi-level phase change memories (PCM), spin Hall effect magnetic RAM (SHE-MRAM) and spin transfer torque magnetic RAM (STTRAM), resistive memories, magnetoresistive random access memories (MRAM), memories incorporating memristor technology, resistive memories including metal oxide based, oxygen vacancy based and conductive bridge random access memories (CB-RAM), spin-engineered magnetic junction memory based devices, magnetic tunnel junction (MTJ) based devices, DW (domain wall) and SOT (spin orbit transfer) based devices, thyristor based memory devices, or any combination of the above or other memories.

[0034] Volatile memory is a storage medium that requires power to maintain the state of the data stored by the medium (thus, volatile memory is memory whose state (and therefore the data stored therein) is indeterminate when power is removed from the device containing the memory). Dynamic volatile memory requires the data stored in the device to be refreshed in order to maintain its state. An example of dynamic volatile memory includes DRAM (Dynamic Random Access Memory), or some variations of Synchronous DRAM (SDRAM). The memory subsystems described herein may utilize a number of memory technologies, such as DDR3 (Double Data Rate Version 3, approved by JEDEC (Joint Electronic Device Engineering Commission) on June 27, 2007). Originally released by the JEDEC (now Release 21), DDR4 (DDR Version 4, JESD79-4 initial specification published by JEDEC in September 2012), DDR4E (DDR Version 4, Enhanced, currently under review by JEDEC), LPDDR3 (Low Power DDR Version 3, JESD209-3B, published by JEDEC in August 2013), LPDDR4 (Low Power Double Data Rate (LPDDR) Version 4, JESD209-4, originally published by JEDEC in August 2014), WIO2 (Wide I / O2 deIO2), JESD229-2, originally published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, originally published by JEDEC in October 2013), DDR5 (DDR version 5, currently under consideration by JEDEC), LPDDR5, originally published by JEDEC in January 2020, HBM2 (HBM version 2), originally published by JEDEC in January 2020, or any other or combination of memory technologies and technologies based on derivatives or extensions of such specifications.

[0035] Storage device 106 may store any suitable data, such as data used by processor 108 to provide functionality of computer system 100. For example, data associated with programs executed or files accessed by cores 114A and 114B may be stored in storage device 106. Storage device 106 may store data and / or sequences of instructions executed or otherwise used by cores 114A and 114B. In various embodiments, storage device 106 may store persistent data (e.g., user files or software application code) that maintains its state even after power to storage device 106 is removed. Storage device 106 may be dedicated to CPU 102 or may be shared with other devices of computer system 100 (e.g., another CPU or other devices).

[0036] In the illustrated embodiment, storage device 106 includes a storage device controller 118 and four memory chips 116 each including four memory partitions 122 operable to store data, although a storage device may include any suitable number of memory chips, each having any suitable number of memory partitions. Memory partitions 122 include a plurality of memory cells operable to store data. The cells of memory partitions 122 may be arranged in any suitable manner, such as rows (e.g., word lines) and columns (e.g., bit lines), a three-dimensional structure, sectors, or otherwise. In various embodiments, cells may be logically grouped into banks, blocks, sub-blocks, word lines, pages, frames, bytes, slices, or other suitable groupings. In various embodiments, memory partitions 122 may include any of the volatile or non-volatile memories listed above or other suitable memory. In particular embodiments, each memory partition 122 includes one or more 3D cross-point memory arrays. 3D cross-point arrays are described in more detail in connection with the following figures.

[0037] In various embodiments, storage device 106 may include a solid-state drive, a memory card, a universal serial bus (USB) drive, a non-volatile dual in-line memory module (NVDIMM), storage integrated into a device such as a smartphone, camera, or media player, or other suitable mass storage device.

[0038] In particular embodiments, one or more memory chips 116 are embodied in a semiconductor package. In various embodiments, the semiconductor package may include a case that contains one or more semiconductor chips (also referred to as dies). The package may also include contact pins or leads used to connect to external circuitry. In various embodiments, the memory chip may include one or more memory partitions 122.

[0039] Thus, in some embodiments, storage device 106 may include a package containing multiple chips, each containing one or more memory partitions 122. However, storage device 106 may include any suitable arrangement of one or more memory partitions and associated logic in any suitable physical location. For example, memory partitions 122 may be embodied in one or more different physical media, such as a circuit board, a semiconductor package, a semiconductor chip, a disk drive, other media, or any combination thereof.

[0040] System memory device 107 and storage device 106 may include any suitable type of memory and are not limited to any particular speed, technology, or form factor of memory in various embodiments. For example, storage device 106 may be a disk drive (e.g., a solid-state drive), a flash drive, memory integrated into the computing device (e.g., memory integrated into a circuit board of the computing device), a memory module that may be inserted into a memory socket (e.g., a dual in-line memory module), or other type of storage device. Similarly, system memory 107 may have any suitable form factor. Furthermore, computer system 100 may include multiple different types of storage devices.

[0041] System memory device 107 or storage device 106 may include any suitable interface for communicating with CPU memory controller 112 or I / O controller 110 using any suitable communication protocol, such as a DDR-based protocol, PCI, PCIe, USB, SAS, SATA, FC, System Management Bus (SMBus), or other suitable protocol. System memory device 107 or storage device 106 may also include a communication interface for communicating with CPU memory controller 112 or I / O controller 110 according to any suitable logical device interface specification, such as NVMe, AHCI, or other suitable specification. In particular embodiments, system memory device 107 or storage device 106 may include multiple communication interfaces, each communicating with CPU memory controller 112 and / or I / O controller 110 using a separate protocol.

[0042] The storage device controller 118 may include logic for receiving requests from the CPU 102 (e.g., via an interface communicating with the CPU memory controller 112 or the I / O controller 110), executing the requests in connection with the memory chips 116, and providing data associated with the requests to the CPU 102 (e.g., via the CPU memory controller 112 or the I / O controller 110). The storage device controller 118 may also be operable to detect and / or correct errors encountered during memory operations via an error correction code (ECC engine). In one embodiment, the controller 118 also tracks the number of times a particular cell (or logical grouping of cells) has been written to perform wear leveling, for example, via a wear leveling engine, detects when a cell is approaching the estimated number of times it can be reliably written, and / or adjusts read operations based on the number of times the cell has been written. When performing wear leveling, the storage device controller 118 may attempt to spread write operations evenly among the cells of the memory chips 116 to equalize the number of operations (e.g., write operations) performed by each cell. In various embodiments, controller 118 may also monitor various characteristics of storage device 106, such as temperature or voltage, and report related statistics to CPU 102. Storage device controller 118 may be implemented on the same circuit board or device as memory chips 116, or may be implemented on a different circuit board or device. For example, in some environments, storage device controller 118 may be a centralized storage controller that manages memory operations for multiple different storage devices 106 of computer system 100.

[0043] In various embodiments, storage device 106 also includes program control logic 124 operable to control programming sequences that are performed when data is written to or read from memory chips 116. In various embodiments, program control logic 124 may provide various voltages (or information indicating which voltages should be provided) that are applied to memory cells during programming and / or reading of data (or perform other operations related to read or program operations), perform error correction, and perform other suitable functions.

[0044] In various embodiments, program control logic 124 may be integrated on the same chip as storage device controller 118 or may be on a different chip. While in the illustrated embodiment, program control logic 124 is shown as part of storage device controller 118, in various embodiments, all or a portion of program control logic 124 may be separate from and communicatively coupled to storage device controller 118. For example, all or a portion of program control logic 124 described herein may be located on memory chip 116. In various embodiments, references to a "controller" herein may refer to any suitable control logic, such as storage device controller 118, chip controller 126, or partition controller. In some embodiments, references to a controller may contemplate logic distributed over multiple components, e.g., logic of storage device controller 118, chip controller 126, and / or partition controller.

[0045] In various embodiments, storage device controller 118 may receive a command from a host device (e.g., CPU 102), determine the target memory chip for the command, and communicate the command to the target memory chip's chip controller 126. In some embodiments, storage device controller 118 may modify the command before sending it to chip controller 126.

[0046] In various embodiments, the storage device controller 118 may send commands to the memory chip 116 to perform host-initiated read operations and device-initiated read operations. A host-initiated read operation may be performed in response to receiving a read command from a host coupled to the storage device 106, such as the CPU 102. A device-initiated read operation may be a read operation performed in response to a device-initiated read command generated by the storage device 106, independent of receiving a read command from the host. In various embodiments, the storage device controller 118 may be the component that generates the device-initiated read command. The storage device 106 may initiate device-initiated read commands for any suitable reason. For example, upon power-up of the storage device, the storage device 106 may initiate multiple read and write back commands to reinitialize the data on the storage device 106 (e.g., to account for any drift that occurred while the storage device 106, or portions thereof, were powered off or idle for an extended period of time).

[0047] The chip controller 126 may receive a command from the storage device controller 118 and determine the target memory partition 122 for the command. The chip controller 126 may then send the command to the controller of the determined memory partition 122. In various embodiments, the chip controller 126 may modify the command before sending it to the controller of the partition 122.

[0048] In some embodiments, all or some of the elements of system 100 reside on (or are coupled to) the same circuit board (e.g., motherboard). In various embodiments, any suitable division between the elements may exist. For example, the elements depicted in CPU 102 may be located on a single die (e.g., on-chip) or package, or all of the elements of CPU 102 may be located off-chip or off-package. Similarly, the elements depicted in storage device 106 may be located on a single chip or on multiple chips. In various embodiments, storage device 106 and the computing host (e.g., CPU 102) may be located on the same circuit board or device, while in other embodiments, storage device 106 and the computing host may be located on different circuit boards or devices.

[0049] The components of system 100 may be coupled together in any suitable manner. For example, a bus may couple any of the components together. The bus may include any known interconnect, such as a multi-drop bus, a mesh interconnect, a ring interconnect, a point-to-point interconnect, a serial interconnect, a parallel bus, a coherent (e.g., cache coherent) bus, a layered protocol architecture, a differential bus, and a Gunning Transceiver Logic (GTL) bus. In various embodiments, an integrated I / O subsystem includes point-to-point multiplexing logic between various components of system 100, such as cores 114, one or more CPU memory controllers 112, I / O controller 110, integrated I / O devices, direct memory access (DMA) logic (not shown), etc. In various embodiments, the components of computer system 100 may be coupled together through one or more networks including any number of intervening network nodes, such as routers, switches, or other computing devices. For example, a computing host (e.g., CPU 102) and storage device 106 may be communicatively coupled through a network.

[0050] Although not shown, system 100 may use a battery and / or a power outlet connector and associated systems for receiving power, a display for outputting data provided by CPU 102, or a network interface that allows CPU 102 to communicate over a network. In various embodiments, the battery, power outlet connector, display, and / or network interface may be communicatively coupled to CPU 102. Other power sources, such as renewable energy (e.g., solar power or motion-based power), may also be used.

[0051] Storage device SRAM / DRAM 130 and chip SRAM / DRAM 128 are adapted to execute firmware or software internal to storage device 106 and memory chip 116, respectively. For example, logic implemented by program control logic 124 may be moved from a memory storing the logic to SRAM / DRAM 130 such that the logic may be executed by storage device controller 118 having access to the logic instructions by the associated SRAM / DRAM 128 upon issuance of a command to execute the logic, e.g., from the host or CPU 102. Similarly, logic implemented by chip controller 126 may be moved from a memory storing the logic to the associated SRAM / DRAM 128 (or another type of memory) such that the logic may be executed by the associated chip controller 126 having access to the logic instructions by the associated SRAM / DRAM 128 upon issuance of a command to execute the logic, e.g., from the host or CPU 102.

[0052] FIG. 2 shows a detailed exemplary diagram of memory compartment 122 of FIG. 1 , according to certain embodiments. In one embodiment, memory compartment 122 may include 3D cross-point memory, which may include phase change memory or other suitable memory types. In certain embodiments, phase change memory may utilize chalcogenide materials for memory elements. A memory element is a unit of a memory cell that actually stores information. During operation, phase change memory may store information in a memory element by changing the phase of the memory element between an amorphous phase and a crystalline phase. The material of the memory element (e.g., a chalcogenide material) may exhibit either an amorphous phase or a crystalline phase, exhibiting low or high conductivity. Generally, the amorphous phase has low conductivity (high impedance) and is associated with a reset state (logic 0), and the crystalline phase has high conductivity (low impedance) and is associated with a set state (logic 1). The memory element may be included within a memory cell 207 (e.g., a phase change memory cell) that also includes a selector, e.g., a selection device, coupled to the memory element. The selection device may be configured to facilitate combining multiple memory elements into an array.

[0053] In some embodiments, the 3D cross-point memory array 206 may include a transistor-less (e.g., at least in relation to the memory's data storage elements) stackable cross-point architecture in which memory cells 207 are located at the intersections of row address lines and column address lines arranged in a grid. Row address lines 215 and column address lines 217, referred to as word lines (WL) and bit lines (BL), respectively, intersect in the shape of a grid, with each memory cell 207 coupled between the WL and BL where they intersect (e.g., at a cross-point). At the crossing point, the WL and BL may be located in different vertical planes such that the WL crosses over but does not physically touch the BL. As described above, the architecture may be stackable such that a word line may cross over a bit line located below the word line and over another bit line of another memory cell located above the word line. Note that row and column are terms of convenience used to provide a qualitative description of the arrangement of WLs and BLs in the cross-point memory. In various embodiments, the cells of the 3D cross-point memory array may be individually addressable. In some embodiments, bit storage may be based on changes in bulk resistance of the 3D cross-point memory cell. In various embodiments, the 3D cross-point memory may include any of the features of 3D XPoint memory manufactured by INTEL CORPORATION (Optane™ is an Intel trademark for Intel's 3D cross-point (3D XPoint™ technology)).

[0054] During a programming operation (e.g., a write operation), the phase of the memory element can be changed by applying a first bias voltage to the WL and a second bias voltage to the BL, resulting in a differential bias voltage across the memory cell, which can cause current to flow in the memory element. The differential bias voltage can be maintained across the memory cell for a period of time sufficient to cause the memory element to "snap back" and transition from an amorphous state to a crystalline state or from a crystalline state to an amorphous state (e.g., by applying heat generated by current). Snapback is a property of a composite memory element that results in an abrupt change in conductivity and an associated abrupt change in voltage across the memory element.

[0055] In a read operation, a target memory cell is selected by applying a first bias voltage to a selected WL and a second bias voltage to a selected BL, which cross over the target memory cell over a time interval. The resulting differential bias voltage (demarcation read voltage (VDM)) across the memory element is configured to be greater than the maximum set voltage and less than the minimum reset voltage of the memory element. The selection of the selected WL and selected BL and the application of the first and second bias voltages may be implemented by decoders within switch circuits such as the WL switch circuit 220 and the BL switch circuit 240. In response to the application of VDM, the target memory element may or may not snap back depending on whether the memory element is in a crystalline state (set) or an amorphous state (reset). A sense circuit coupled to the memory element is configured to detect the presence or absence of snapback during the sense time interval. The presence of snapback may then be interpreted as a logic 1, and the absence of snapback may be interpreted as a logic 0.

[0056] The differential bias at which a memory cell transitions from being sensed as a logic 1 (e.g., due to the memory cell snapping back) to being sensed as a logic 0 (e.g., due to the memory cell not snapping back) may be termed the threshold voltage (sometimes referred to as the snapback voltage). Thus, if VDM is higher than the threshold voltage of the memory cell, the memory cell may be sensed as storing a logic 1, and if VDM is lower than the threshold voltage of the memory cell, the memory cell may be sensed as storing a logic 0.

[0057] In some embodiments, the applied bias, e.g., the VDM of a read pulse, may be high enough to turn on only 3D cross point cells in a crystalline state, which may have a lower threshold voltage than 3D cross point cells in an amorphous state. In some embodiments, the VDM may be supplied through a negative control node and / or a positive control node. For example, the bit line electrode of the 3D cross point cell may be the positive control node, and the word line electrode coupled to the cell may provide the VDM bias.

[0058] For a write or read operation, one memory cell 207A among many cells, such as 1000 cells, may be selected as the target cell for the read or write operation, and this cell is at the cross section of BL 217A and WL 215A. All cells coupled to BL 217A and all cells coupled to WL 215A other than cell 207A may still receive a portion of the VDM (e.g., approximately half of the VDM), and only cell 207A receives the full VDM.

[0059] 2, memory partition 122 includes memory partition controller 210, word line control logic 214, bit line control logic 216, and memory array 206. A host device (e.g., CPU 102) may provide read and / or write commands including memory addresses and / or associated data to memory partition 122 (e.g., via storage device controller 118 and chip controller 126) and may receive read data from memory partition 122 (e.g., via chip controller 126 and storage device controller 118). Similarly, storage device controller 118 may provide host-initiated read and write commands or device-initiated read and write commands including memory addresses to memory partition 122 (e.g., via chip controller 126). Memory partition controller 210 (together with word line control logic 214 and bit line control logic 216) is configured to perform memory access operations, e.g., reading and / or writing to one or more target memory cells.

[0060] The memory array 206 corresponds to at least a portion of a 3D cross-point memory (which may include, e.g., phase-change memory cells or other suitable memory cells) and includes a plurality of word lines 215, a plurality of bit lines 217, and a plurality of memory cells, such as memory cell 207. Each memory cell is coupled between a word line (“WL”) and a bit line (“BL”) at a cross point of the WL and the BL. Each memory cell includes a memory element configured to store information and may include a memory cell selection device (e.g., a selector) coupled to the memory element. The selection device may include an ovonic threshold switch, a diode, a bipolar junction transistor, a field-effect transistor, or the like. The memory array 206 may be configured to store binary data, which may be written to (e.g., programmed with) or read from.

[0061] The memory partition controller 210 may manage communications with the chip controller 126 and / or the storage device controller 118. In particular embodiments, the memory partition controller 210 may analyze one or more signals received from another controller to determine whether a command sent over the bus should be consumed by the memory partition 122. For example, the controller 210 may analyze the address of the command and / or the value of the enable signal lines to determine whether the command applies to the memory partition 122. The controller 210 may be configured to identify one or more target WLs and / or BLs associated with a received memory address (which may be separate from the memory partition address that identifies the memory partition 122, although in some embodiments, a portion of the address field of the command may identify the memory partition while another portion of the address field may identify one or more WLs and / or BLs). The memory partition controller 210 may be configured to manage the operation of the WL control logic 214 and the BL control logic 216 based at least in part on identifiers of the WLs and / or BLs included in the received command. The memory partition controller 210 may include a memory partition controller, circuitry 211, and a memory controller interface 213. Although memory controller interface 213 is shown as a single block in FIG. 2, it may include multiple interfaces, for example, a separate interface for each of WL control logic 214 and BL control logic 216.

[0062] The WL control logic 214 includes a WL switch circuit 220 and a detection circuit 222. The WL control logic 214 is configured to receive a target WL address from the memory partition controller 210 and select one or more WLs for read and / or write operations. For example, the WL control logic 214 may be configured to select a target WL by coupling a WL select bias voltage to the target WL. The WL control logic 214 may be configured to deselect a WL by decoupling the target WL from the WL select bias voltage and / or by coupling a WL deselect bias voltage to the WL. The WL control logic 214 may be coupled to multiple WLs 215 included in the memory array 206. Each WL may be coupled to multiple memory cells corresponding to multiple BLs 217. The WL switch circuit 220 may include multiple switches, each configured to couple (or decouple) a respective WL, e.g., WL 215A, to a WL select bias voltage to select the respective WL 215A. For example, the WL switch circuit 220 may include multiple switches, each corresponding to a specific WL. In one embodiment, each switch includes a metal-oxide-semiconductor field-effect transistor (MOSFET) pair including a positive-type (p-type) metal-oxide-semiconductor transistor (PMOS) and a negative-type (n-type) MOS transistor (NMOS), which may form a complementary MOS circuit (CMOS).

[0063] The BL control logic 216 includes a BL switch circuit 224. In some embodiments, the BL control logic 216 may also include a sensing circuit, such as the sensing circuit 222. The BL control logic 216 is configured to select one or more BLs for read and / or write operations. The BL control logic 216 may be configured to select a target BL by coupling a BL select bias voltage to the target BL. The BL control logic 216 may be configured to deselect a BL by isolating the target BL from the BL select bias voltage and / or by coupling a BL deselect bias voltage to the BL. The BL switch circuit 224 is similar to the WL switch circuit 220, except that the BL switch circuit 224 is configured to couple a BL select bias voltage to the target BL.

[0064] The sense circuit 222 is configured to detect the state of one or more sensed memory cells 207 (e.g., by the presence or absence of a snapback event during a sense interval), for example, during a read operation. The sense circuit 222 is configured to provide a logic level output, for example, to the memory partition controller 210, regarding the result of the read operation. For example, a logic level corresponding to a logic 1 when the applied VDM is higher than the threshold voltage of the memory cell or a logic 0 when the applied VDM is lower than the threshold voltage of the memory cell may be output. In particular embodiments, a logic 1 may be output when a snapback is detected and a logic 0 may be output when a snapback is not detected.

[0065] As an example, in response to signals from memory partition controller 210, WL control logic 214 and BL control logic 216 may be configured to select a target memory cell for a read operation, e.g., memory cell 207A, by coupling WL 215A to a WL select bias voltage and BL 217A to a BL select bias voltage, and coupling the other WLs and BLs to their respective deselect bias voltages. One or both of sense circuits 222 may then be configured to monitor WL 215A and / or BL 217A over a sensing interval to determine the state of memory cell 207A (e.g., to determine whether a snapback event occurs). For example, if sense circuit 222 detects a snapback event, memory cell 207A may be in a SET state, whereas if sense circuit 222 does not detect a snapback event during the sensing interval, memory cell 207A may be in a RESET state.

[0066] As such, the WL control logic 214 and / or the BL control logic 216 may be configured to select a target memory cell for a read operation, initiate the read operation, sense the selected memory cell (e.g., for a snapback event) during a sensing interval, and provide the results of the sensing to, for example, the memory partition controller 210.

[0067] In particular embodiments, the sense circuit 222 may include a WL load connected to the WL electrode or gate and a BL load connected to the BL electrode or gate. When a particular word line and bit line is selected in the array, the difference between the WL load or WL voltage and the BL voltage corresponds to the read VDM. The VDM may induce a current (icell) in the memory cell 207A. A comparator, such as a sense amplifier, may compare icell to a reference current to read a logic state 1 or logic state 0 depending on whether the memory cell is a set cell or a reset cell. Thus, the reference current may be selected so that the current of the target memory cell is lower than the reference current before the snapback of the target memory cell and higher than the reference current after the snapback of the target memory cell. In this way, the output of the sense amplifier / comparator may indicate the state of the target memory cell. A latch may be coupled to the output of the comparator to store the output of the read operation.

[0068] For each matrix of the array, multiple sense amplifiers may be provided, and the sensing circuit 222 may process a maximum number of bits sensed from the sense amplifiers at one time, for example, 128 bits. Thus, 128 memory cells may be sensed at one time by the sense amplifiers of the sensing circuit 222.

[0069] 3 shows a detailed illustrative diagram of memory array 206 of FIG. 2, according to a particular embodiment. In various embodiments, memory cells 207 of memory array 206 may be divided into logical groups (and memory array 206 may include multiple slices), such as slices 302. In the embodiment shown, slice 302 includes multiple memory cells 207 coupled to the same WL 215A, although slice 302 may include memory cells in any suitable arrangement.

[0070] In particular embodiments, a slice may include a payload portion 304 and a metadata portion 306. Memory cells in the payload portion 304 may store data written to the storage device 106 by a host (e.g., CPU 102 / 104). For example, the host may send a write command specifying payload data to be written to the storage device 106 at a particular logical address. The payload of the write command may be stored in the payload portion 304 of one or more slices 302 (in various embodiments, the payload portion 304 may be large enough to hold payload data from multiple write commands from the host). In various embodiments, the size of the payload portion of a slice may have any suitable size, e.g., 1 kibibyte (KiB), 2 KiB, 4 KiB, 8 KiB, or other suitable size.

[0071] Memory cells in the metadata portion 306 of a slice 302 may store metadata associated with payload data stored in the payload portion 304 of the slice 302 or the slice itself. The metadata portion 306 may store any suitable metadata associated with the payload data or the slice. For example, the metadata portion 306 may store parity bits and / or cyclic redundancy check (CRC) bits used during error detection and correction, such as by the storage device controller 118. In alternative embodiments, error detection and / or correction may be performed at any suitable level for the storage device 106, such as by the chip controller 126 or a partition controller.

[0072] FIG. 4 is a perspective view of an example of a portion of a stack 400 of a 3D cross-point memory device including a memory array such as those of FIGS. 2 and 3. The specific layers are merely examples and will not be described in detail here. The stack 400 is built on a substrate structure 422, such as silicon or other semiconductor. The stack 400 includes multiple pillars 420 as memory cell stacks of memory cells 207. In the view of the stack 400, the WL and BL are orthogonal to each other and cross or intersect each other in a cross-hatch pattern. The cross-point memory structure includes at least one memory cell stacked between the BL and WL layers. As shown, word lines (WL) 215 are between the layers of elements, and bit lines (BL) 217 ​​are located at the top of the circuitry. Such a configuration is by way of example only, and the BL and WL structures may be interchanged. Thus, in one representation of the stack 400, the WL may be the metal structure labeled 217, and the BL may be the metal structure labeled 215. More generally, WL and BL may be referred to as "address lines," referring to signal lines used to address memory cells. Different architectures may use different numbers of stacks of devices and different configurations of WL and BL. It should be understood that the spaces / trenches 421 running in one direction and the spaces / trenches 423 running in a direction perpendicular to the trenches 421 (trenches 421 and 423 defined between pillars 420) are typically filled with an insulator. In one example, the BL and WL of stack 400 are made of tungsten metal.

[0073] At least some of the WLs 215 may correspond to the WLs 215 of FIG. 2. At least some of the BLs 217 may correspond to the BLs 217 of FIG. 2. A substrate structure 422, such as a silicon substrate, may include control circuitry (not shown) therein, such as control circuitry including transistors, row decoders, page buffers, etc. The memory cells 207 may correspond to the memory cells 207 of FIG. 2. The control circuitry of the substrate structure 422 may include, for example, a memory partition controller, such as the memory partition controller 210, BL control logic, such as the BL control logic 216, and WL control logic, such as the WL control logic 214 of FIG. 2. Each row of the WLs 215 extending in the Y direction (corresponding cells coupled to corresponding BLs) defines a memory array and may correspond to a memory array, such as the memory array 206 of FIGS. 2 and 3. Some of the WLs and some of the BLs may include dummy WLs or dummy BLs (not shown in FIG. 4) corresponding to the dummy WLs and dummy BLs in the dummy array 206B of FIGS. 2 and 3.

[0074] Semiconductor processing (eg, manufacturing) can be used to form semiconductor devices, such as integrated circuits, memory devices such as those described above in connection with FIGS. 1-4, microelectromechanical devices (MEMs), and the like.

[0075] Examples of memory devices that can be formed by semiconductor processing include, but are not limited to, volatile and non-volatile memory, such as NAND flash memory, NOR flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), and erasable programmable ROM (EPROM), among others.

[0076] Semiconductor processing may include forming features or patterns on and / or within a substrate, such as a semiconductor substrate, such as substrate 422 in FIG. 4. In some examples, one or more materials, such as silicon-based materials (e.g., silicon oxide (SiO), silicon nitride (SiN), tetraethyl orthosilicate (TEOS), and / or polysilicon), conductors, etc., may be formed on the semiconductor. Layers made of one or more materials are shown in FIG. 4 by way of example, for example, between WL215 and BL217. For example, deposition processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electrochemical deposition, and / or molecular beam epitaxy, among others, may be used to form materials on the semiconductor. Portions of the one or more materials, and in some cases portions of the semiconductor, may then be removed, such as by wet and / or dry etching, to form features, such as pillars, that will eventually make up each of pillars 420 in FIG. 4. In some examples, the pillars may have a high aspect ratio (e.g., height to width or diameter ratio) and may be referred to as high aspect ratio (HAR) pillars. For example, the pillars may be separated from one another by HAR apertures.

[0077] During processing, the substrate and pillars may be subjected to wet processing, such as wet cleaning followed by drying. For example, wet cleaning may help to remove residues left behind by removal processes or other processes, etc.

[0078] In particular, current integration schemes for fabricating 3D memory structures, such as the structure in the example shown in FIG. 4, rely on providing a nitride liner and an oxide etch-protective liner that is deposited over the nitride liner using atomic layer deposition (ALD) after a first etch of various layers of the 3D memory structure. The first etch may first etch through a first subset of the layers of the 3D memory structure to form a first trench, and the nitride liner and etch-protective liner may be deposited over the first trench. The nitride liner and oxide etch-protective liner are provided to protect one or more underlying layers within the various layers of the 3D memory structure during a second etch of the various layers. The nitride layer may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the oxide may be deposited using ALD. For example, a second etch may then etch through a second subset of the layers of the 3D memory structure to form a second trench that is longer than the first trench. Another nitride liner and another oxide etch protection liner are then provided using ALD to protect any sensitive layers during the final etch through the remaining subset of layers of the 3D memory structure, forming a third trench that is longer than the second trench, which may correspond, by way of example, to trench 421 or 423 in FIG.

[0079] The ALD oxide layer laid down between successive etches is typically hydrophilic, which results in high surface tension during the second etch and final etch wet-clean-dry process, which tends to subject high-aspect-ratio pillars to line wobble and / or pattern collapse. Thus, in some previous approaches, capillary forces within the trenches caused by drying the pillars after the wet clean can cause the pillars to wobble (e.g., tip over) relative to each other.

[0080] For example, FIG. 5 shows a structure 500 including two adjacent HAR pillars 502 and 504 that are overturned (e.g., sometimes referred to as bridging) relative to one another due to capillary forces of a liquid 506 that forms a meniscus 505 during drying. The capillary forces can be affected by the speed of drying, the liquid used, and the composition of the sidewall surface of the trench defined by the pillars, as shown. The liquid, e.g., an aqueous liquid, may be provided during a wet cleaning process after etching the pillars 502 into the structure. The drying-induced capillary forces that cause the lines to bend / overturn are directly related to the water contact angle θ between the surface of the liquid 506 and the surfaces of the sidewalls 503 and 505 of the HAR pillars 502 and 504, respectively, that contact the liquid. The larger the contact angle, the more hydrophobic the contact surfaces. The HAR pillars may correspond to the multilayer pillars of a 3D memory structure. During the drying stage, bridging tends to remain, which can lead to defects in semiconductor devices.

[0081] Surface modification chemistry (SMC) can be used to modify oxide and nitride surfaces, and therefore their surface hydrophobicity and surface tension, during drying. However, SMC technology is too complex and expensive for 3D memory technology. SMC is typically tailored to modify only specific surfaces within a stack containing multiple materials, and adapting it to 3D memory manufacturing processes is technically complex and expensive, and even if successful, it may not result in materials that are consistent with other materials within the stack, such as a 3D memory stack.

[0082] Various drying methods (e.g., Maragoni drying) are also offered to minimize pattern collapse. To eliminate the meniscus effect during drying, advanced cleaning / drying methods, such as gas-phase HF, which draws out residues without using liquids, or supercritical fluid drying (at sufficiently high pressures without surface tension), are offered. However, commonly available drying methods (e.g., Maragoni drying) are limited in their effectiveness and expensive. For example, 3D cross-point techniques are too aggressive for them (in terms of feature size, number of required etches, etc.), leading to the need for more advanced / expensive drying techniques, such as supercritical fluid drying.

[0083] The present disclosure includes processing methods, such as semiconductor processing methods related to the formation of semiconductor devices such as integrated circuits, memory devices, MEMs, etc., among others. For example, one such method includes providing a carbon-doped etch protective liner on sidewalls of a plurality of first trenches defined by a plurality of pillars in a multi-layer semiconductor structure, performing an etching process to remove material at the bottom of the plurality of first trenches while leaving at least a portion of the etch protective liner on the sidewalls of the plurality of first trenches, performing an etching process to deepen the first trenches to form a plurality of second trenches, wet cleaning and drying the multi-layer semiconductor structure after performing the etching process and while at least a portion of the etch protective liner is on the sidewalls of the plurality of second trenches, and performing further processing on the multi-layer semiconductor structure to integrate it into a semiconductor device. According to some embodiments, performing further processing may include providing a subsequent carbon-doped etch protective liner on sidewalls of the plurality of second trenches; performing a subsequent etching process to remove material at the bottom of the plurality of second trenches while leaving at least a portion of the etch protective liner on the sidewalls of the plurality of second trenches; performing an etching process to deepen the second trenches to form a plurality of third trenches; and wet cleaning and drying the multilayer semiconductor structure after performing the subsequent etching process and while the at least a portion of the subsequent etch protective liner is on the sidewalls of the plurality of third trenches.

[0084] Some embodiments relate to engineering trench sidewall liners in memory cells to correct surface tension-induced pattern deformation during wet cleaning by providing a carbon-containing liner on the sidewalls of the cell trench after dry etching and before wet cleaning and drying. Semiconductor pillar tipping during the drying phase of wet cleaning is typically caused by capillary forces during drying, which are related to the cell aspect ratio, spatial critical dimensions, and contact angle along the cell sidewall. By providing a carbon-containing liner, capillary forces can be reduced, which can help eliminate pillar tipping.

[0085] The carbon-containing liner may include a carbon-doped material such as a carbon-doped oxide material, e.g., a carbon-doped silicon oxide material such as SiOC. The carbon-containing liner may include a carbon-doped nitride material, e.g., a carbon-doped silicon nitride material such as SiCN. The carbon-containing liner may include a carbide material, e.g., a silicon carbide material.

[0086] Some embodiments include replacing a SiO liner (e.g., deposited using atomic layer deposition (ALD)) on the sidewalls of trenches in a semiconductor structure, such as one provided between the first and second etches or between the second and final etches, with a liner that has a higher contact angle surface when contacted by a wet cleaning solution, to control pattern deformation of the pillars that define the trench. For example, some embodiments provide an ALD-deposited carbon-doped liner, such as SiOC, on the sidewalls of the trench. The addition of carbon to the oxide reduces the hydrophilicity of the surface, reducing the surface tension (contact angle) that causes pattern deformation and tipping during drying after the wet etch. Providing a SiCN or SiC liner / seal in addition to or instead of a carbon-doped silicon oxide liner is another potential embodiment. In embodiments in which SiCN or SiC is provided as part of the etch-protective liner, an additional oxide layer may not be necessary for etch protection because the carbon-doped SiN slows down its etch rate. Therefore, SiCN or SiC alone can act as a hydrophobic etch protective liner without the need for an additional oxide layer.

[0087] Adding carbon to the liner reduces the hydrophilicity of the trench surface, reducing the surface tension (contact angle) during drying, which can cause pattern distortion. Transmission electron microscopy (TEM) using energy dispersive X-ray spectroscopy is one method for detecting the use of carbon or carbon-doped etch liners in semiconductor devices containing HAR pillars. In Wang et al., "ALD of Carbon Doped Silicon Oxide," J. Vac. Sci. Technol. A36(2), 2018, 021509-1), ALD SiOC has been demonstrated at temperatures below 150°C.

[0088] Embodiments provide numerous technical advantages, including a reduced likelihood of pillar tipping (e.g., collapse) during semiconductor processing involving HAR pillars compared to previous approaches. Pillar tipping can be caused by drying that occurs after wet cleaning, as previously noted. Providing a carbon-containing etch protection liner or etch stop layer, such as a carbon-doped etch protection liner, contributes to the hydrophobicity of the etch protection liner compared to etch protection liners that do not contain carbon. In this way, the pillar tipping effect resulting from the meniscus in the wet cleaning solution in the trench during drying is mitigated.

[0089] Embodiments advantageously help extend current wet cleaning to future nodes, improve process robustness at current nodes, and help reduce technology costs by eliminating the need for advanced cleaning / drying options.

[0090] Some embodiments further advantageously provide a carbon-doped liner, where the presence of carbon extends the liner's etch resistance, providing better etch protection for underlying layers. In such cases, the etch-protective oxide liner can be eliminated if a carbon-doped nitride liner or silicon carbide liner is provided as the etch-protective liner. This simplifies the method for forming the multilayer semiconductor structure and reduces its cost. Additionally, reducing the number of etch-protective liners advantageously allows for wider trenches than would be possible if an oxide layer were present.

[0091] As used herein, the term semiconductor may refer to, for example, a material, a wafer, or a substrate, and includes any underlying semiconductor structure. "Semiconductor" is understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, underlying semiconductor structures, and epitaxial silicon supported by other semiconductor structures. Additionally, when reference is made to a semiconductor in the following description, previous process steps may have been used to form regions / junctions in the underlying semiconductor structure, and the term semiconductor may include the underlying materials that include such regions / junctions.

[0092] 6A-6C illustrate cross-sectional views of processing stages, such as semiconductor processing methods, associated with forming semiconductor devices, such as integrated circuits, memory devices (e.g., 3D cross-point memory devices similar to those described in connection with FIGS. 1-4 above), portions of MEMS, among other things, in accordance with numerous embodiments of the present disclosure. For example, the processing steps may be associated with forming DRAM memory devices, NAND flash memory devices, or NOR flash memory devices, capacitors (e.g., memory cell arrays thereof), among other things.

[0093] 6A shows a portion of a first multilayer semiconductor structure 600A (e.g., for use in a semiconductor device) after some processing steps have occurred. The structure may include a base structure such as a substrate 622 (e.g., a semiconductor such as a silicon-based or tungsten-based semiconductor substrate). In some examples, to form the structure 600A, one or more materials may be used to form the first layer 601, the second layer 602, the third layer 603, the fourth layer 604, and the fifth layer 605 of the first multilayer semiconductor structure 600A. Such materials may include, by way of example, silicon-based materials, conductive materials (e.g., metals), among others, and may be formed on (e.g., above) a surface 622, e.g., an upper surface, of the substrate 622 using, for example, a deposition process such as PVD, CVD, ALD, electrochemical deposition, and / or molecular beam epitaxy, among others.

[0094] As shown in FIG. 6A, first trenches 621A can be formed by a first etch through a mask 606, such as a silicon nitride (SiN) hard mask, to create pillars 626A, e.g., nanofeatures (e.g., having a width or diameter of about 0.1 nanometers to about 100 nanometers). Pillars 626A can be formed by removing portions of layers, e.g., portions of material from fifth layer 605, fourth layer 604, and third layer 603. The removal process forms first trenches 621A, e.g., spaces or openings through one or more layers of material, stopping above, on, or within one of the layers, e.g., third layer 603 in the illustrated example (e.g., as shown in FIG. 6A). First trenches 621A can be between adjacent pillars 626A.

[0095] In some examples, the first trench 621A, and thus the structure 600A of FIG. 6A, may be formed using a dry removal process, such as dry etching. A mask 606, such as an imaging resist (e.g., photoresist), such as a silicon nitride mask, may be formed over a layer in the multilayer semiconductor structure 600A and patterned to expose regions thereof. The exposed regions may then be removed, for example, by a dry etching process, to form the first trench 621A.

[0096] 6B shows the structure of FIG. 6A after depositing a first nitride liner 630 and a first oxide liner 632 in the first trench 621A of the first multi-layer semiconductor structure 600A to form structure 600B. While the first nitride liner 630 and the first oxide liner 632 are shown deposited on the mask 606 as well as the trench walls in FIG. 6B, embodiments are not limited in this respect. Some embodiments provide a carbon-containing liner on at least a portion of the sidewalls of the trench in the semiconductor structure prior to etching to deepen the trench and wet cleaning and drying it.

[0097] 6B, nitride liner 630 and oxide liner 632 together provide an etch-protective liner or carbon-containing liner 634 for one or more of material layers 604-605 during a subsequent second etch, which will be described in the context of FIG. 6C. Liner 634 is carbon-containing to the extent that it includes at least one liner containing carbon, in this case carbon-doped oxide 632. Embodiments are not limited to the use of nitride and oxide layers described herein, but include within their scope the provision of an etch-protective liner (which itself may include one or more layers) within a trench in a semiconductor structure to provide etch protection for one or more material layers of the underlying semiconductor structure.

[0098] According to some embodiments, the etch protection liner can be substantially conformal with respect to the surface of each trench. According to embodiments, the surface of the etch protection liner can be doped with carbon. For example, if the etch protection liner includes an oxide liner 632, the oxide liner 632 can be a carbon-doped oxide layer. Compared to an alternative etch protection liner 634 (e.g., oxide liner 632) that is not carbon-doped and is therefore more hydrophilic, the carbon doping of the etch protection liner 634 has the effect of increasing the contact angle with the wet cleaning liquid that fills the corresponding trench during wet cleaning, due to the surface facing the corresponding second trench 621C. The increased contact angle can help substantially reduce the HAR tipping effect caused by the capillary force of the liquid acting against the trench wall, as described by way of example in the context of FIG. 4 . In this way, the problem of defective semiconductor products caused by the tipping effect during the wet cleaning and drying process is eliminated.

[0099] According to some embodiments, carbon doping of the oxide layer can be implemented using, for example, ALD of the oxide using a carbon precursor. The oxide layer can be carbon doped to include, by way of example and in terms of atomic percentage, about 10% to about 30% atomic percent carbon, about 10% to about 50% atomic percent carbon, or about 15% to about 20% atomic percent carbon.

[0100] Concentrations, amounts, and other numerical data may be expressed or presented herein in a range format. It should be understood that such range format is used merely for convenience and brevity and should therefore be interpreted flexibly as including not only the numerical values ​​explicitly recited as the limits of the range, but also all individual numerical values ​​or subranges subsumed within the range, as if each numerical value and subrange were explicitly recited. By way of example, a numerical range of "about 1 to about 5" should be interpreted not only as including the explicitly recited values ​​of about 1 to about 5, but also as including each individual value and subrange within the stated range. Thus, this numerical range individually includes individual values, such as 2, 3, and 4, and subranges, such as 1 to 3, 2 to 4, and 3 to 5, as well as 1, 1.5, 2, 2.3, 3, 3.8, 4, 4.6, 5, and 5.1. Embodiments are not limited to providing the etch protective liner 634 on upward-facing regions of the mask, or even on upward-facing surfaces of layers to be etched in an etch subsequent to the first etch (in this case, the upward-facing surface of the third layer 603). Thus, at a minimum, embodiments encompass providing a carbon-doped etch protective liner on the sidewalls of the plurality of first trenches to protect at least one layer of the multi-layer semiconductor structure whose sidewalls face the first trenches.

[0101] FIG. 6C shows the structure of FIG. 6B after a second etch and wet clean, resulting in a second multilayer semiconductor structure 600C that defines a second trench 621C and a second HAR pillar 626C. Similar to structure 600A, multilayer semiconductor structure 600C can be formed using a dry removal process, such as a second dry etch. The second etch in the example of FIG. 6C removes some or all of third layer 603, including any etch-protective liner 634 that may have been present on the bottom surface of the first plurality of trenches 621A. The first trench 621A in FIG. 6A exposes an area of ​​multilayer semiconductor structure 600A for the second etch. The exposed area can then be removed, such as by a second dry etch process, to extend (deepen) the first trenches to form second trenches 621C therefrom. An etch protection liner 634, including a carbon-doped oxide liner 632, serves to protect layer 604 during a second etch to deepen first trench 621A into second trench 621C.

[0102] In FIG. 6C, after performing a drying process in the form of a second etch and providing the first etch-protective liner 634, a wet cleaning process may be performed on the structure of FIG. 6B to remove residue on the exposed surfaces of the pillars 626C, for example, in the second trenches 621C. In some examples, the wet cleaning process may include an aqueous wet clean that may include hydrofluoric acid (HF). In one example, the aqueous wet clean may include a standard clean 1 (SC-1) that may include deionized (DI) water, aqueous ammonium hydroxide, and aqueous hydrogen peroxide. For example, the standard clean 1 may be performed before and after applying HF. In some cases, a standard clean 2 (SC-2) that may include deionized (DI) water, aqueous hydrochloric acid, and aqueous hydrogen peroxide may be performed after the standard clean 1 as part of the aqueous wet clean. The wet cleaning process may further include a rinse with liquid DI water following the aqueous wet clean.

[0103] FIG. 6D illustrates the structure of FIG. 6C after depositing a second nitride liner 640 and a second oxide liner 642 in the second trench 621C of the second multilayer semiconductor structure 600C. While FIG. 6D shows the second nitride liner 640 and the second oxide liner 642 deposited on the mask 606 as well as the trench walls, embodiments are not limited thereto. Some embodiments provide a carbon-doped etch protection liner on at least the sidewalls of the trench in the semiconductor structure prior to etching to deepen the trench and wet cleaning and drying thereof. The etch protection liner 644 in FIG. 6D can be deposited in the same manner as the etch protection liner 634 in FIG. 6B.

[0104] 6D, nitride liner 640 and oxide liner 642 together provide an etch-protective liner or carbon-containing liner 644 for one or more of material layers 603-605 during the subsequent final etch described in the context of FIG. 6E. Liner 644 is carbon-containing to the extent that it includes at least one liner containing carbon, in this case carbon-doped oxide 642. Embodiments are not limited to the use of nitride and oxide layers described herein, but include within their scope the provision of an etch-protective liner (which itself may include one or more layers) within a trench in a semiconductor structure to provide etch protection for one or more material layers of the underlying semiconductor structure.

[0105] Similar to the etch protection liner 634 described in the context of the second etch, according to some embodiments, the etch protection liner 644 can be substantially conformal with respect to the surface of each trench. According to embodiments, the surface of the etch protection liner can be doped with carbon. For example, if the etch protection liner includes an oxide liner 642, the oxide liner 642 can be a carbon-doped oxide layer. Compared to an alternative etch protection liner 644 (e.g., oxide liner 642) that is not carbon-doped and is therefore more hydrophilic, the carbon doping of the etch protection liner 644 has the effect of increasing the contact angle with the wet cleaning liquid that fills the corresponding trench during wet cleaning, due to the surface facing the corresponding second trench 621C. The increased contact angle can help substantially reduce the HAR tipping effect caused by the capillary force of the liquid acting against the trench wall, as described by way of example in the context of FIG. 4 . In this way, the problem of defective semiconductor products caused by the tipping effect during the wet cleaning and drying process is eliminated.

[0106] According to some embodiments, similar to the oxide liner 632 described in the context of Figure 6B, carbon doping of the oxide liner 642 can be implemented using, for example, ALD of an oxide using a carbon precursor. The oxide layer can be carbon doped to include, for example, about 10% to about 30% atomic percent carbon, about 10% to about 50% atomic percent carbon, or about 15% to about 20% atomic percent carbon.

[0107] In both cases of Figures 6C and 6D, the oxide liner 632 / 642 is where the wet cleaning liquid meniscus pulls the pillars together by capillary forces during drying as shown in Figure 4. These forces can be reduced by carbon doping the oxide, as previously explained.

[0108] FIG. 6E shows the structure of FIG. 6D after a final etch and wet clean, resulting in a third multilayer semiconductor structure 600E that defines a third trench 621E and a third HAR pillar 626E. Similar to structure 600C, multilayer semiconductor structure 600E can be formed using a dry removal process, such as a final dry etch. The final etch in the example of FIG. 6E removes any remaining portions of third layer 603, including any etch-protective liner 644 that may have been present at the bottom of second trenches 621C. The second trench 621C in FIG. 6C exposes an area of ​​multilayer semiconductor structure 600C for the final etch. The exposed area can then be removed, such as by a final dry etch process, to extend (deepen) the second trenches to form third trenches 621E therefrom. An etch protection liner 644, comprising a carbon-doped oxide liner 642, serves to protect layer 604 during the final etch to deepen second trench 621C into third trench 621E.

[0109] In FIG. 6E, after performing a final etch and drying process to provide the second etch-protective liner 644, a wet cleaning process may be performed on the structure of FIG. 6D to remove residue that may form on the exposed surfaces of the pillars 626E, such as in the third trenches 621E. In some examples, the wet cleaning process may include an aqueous wet clean that may include hydrofluoric acid (HF). In one example, the aqueous wet clean may include a standard clean 1 (SC-1) that may include deionized (DI) water, aqueous ammonium hydroxide, and aqueous hydrogen peroxide. For example, the standard clean 1 may be performed before and after applying HF. In some cases, a standard clean 2 (SC-2) that may include deionized (DI) water, aqueous hydrochloric acid, and aqueous hydrogen peroxide may be performed after the standard clean 1 as part of the aqueous wet clean. The wet cleaning process may further include a rinse with liquid DI water following the aqueous wet clean.

[0110] Figures 6A-6E merely provide an example of a method and resulting structure according to some embodiments. The embodiments are not necessarily limited to semiconductor processes including multi-layer structures under a mask, five-layer structures under a mask, or 3D memory structures with the illustrated sequential material layers. For example, the layers described may have other layers between, below, or above them. Additionally, while the various etching processes in the second and final etches suggest that the entire upward-facing portion of the liner is etched during each etch, it is possible that in reality, some of the upward-facing portion of the liner may not be etched. Portions of the liner on the sidewalls, including the surfaces that create the trench sidewalls, may also be partially etched during each etch. The hard mask may also be made thinner with each successive etch, although these possibilities are not shown in Figures 6A-6E.

[0111] Thickness ranges for nitride and oxide layers according to some exemplary embodiments may include about 1 nm to about 5 nm for nitride layers and about 0.5 nm to about 3 nm for oxide layers. The nitride layer may be applied using plasma-enhanced chemical vapor deposition (PECVD) or ALD. In addition to silicon oxide, the oxide liner may include metal oxides such as HfOx, AlOx, or TiOx, for example. For FP etching, the oxide liner provides etch protection, and the nitride liner provides an adhesion layer underneath the oxide liner. For the final etch, the oxide may be used as a gap-filling material to enable wetting and adhesion during fabrication.

[0112] According to some embodiments, when the carbon-containing liner comprises SiCN or SiC, they may be formed by implanting carbon into SiN or amorphous Si.

[0113] According to some embodiments, providing a carbon-doped liner can include doping an initial liner material, such as an oxide, with carbon using carbon implantation after deposition of the initial liner (e.g., oxide) material. According to another embodiment, ALD of a carbon-doped liner material can be performed, where the initial liner material is ALD deposited using a precursor that includes carbon (in this case, the carbon-containing liner material is deposited as a carbon-doped material, rather than carbon doping after deposition).

[0114] According to one embodiment, if ALD is used to provide the carbon-containing liner, the ALD deposition temperature can be from about 100° C. to about 300° C., according to one example.

[0115] According to one embodiment, the carbon-containing liner may include a material that includes carbon dispersed substantially uniformly throughout, or may include a material that exhibits a graded carbon-containing material with more carbon on its surface facing the trench.

[0116] 7 shows an example of a process 700 according to some embodiments. The process includes providing a stack on a substrate in operation 702, the stack including multiple device layers including a conductive layer, patterning the stack using etching to form trenches extending through the stack and pillars between the trenches in operation 704, providing a carbon-containing liner on sidewalls of the trenches in operation 706, wet cleaning and drying the stack after providing the carbon-containing liner in operation 708, filling spaces between the pillars with one or more materials in operation 710, and electrically coupling contact lines to the conductive layer to form semiconductor devices in operation 712.

[0117] The flow described in Figure 7 is merely representative of operations that may occur in a particular embodiment. Various embodiments of the present disclosure contemplate any suitable signaling mechanism for achieving the functionality described herein. Some of the operations shown in Figure 7 may be repeated, combined, modified, or eliminated as appropriate. Furthermore, operations may be performed in any suitable order without departing from the scope of a particular embodiment.

[0118] A design may go through various stages from creation to simulation to manufacturing. Data representing the design can represent the design in multiple formats. First, hardware may be represented using a hardware description language (HDL) or another functional description language to be useful in simulation. Additionally, a circuit-level model using logic and / or transistor gates may be generated at some stages of the design process. Furthermore, most designs, at some stage, reach a data level that represents the physical placement of various devices in a hardware model. When conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be data specifying the presence or absence of various features on different mask layers of a mask used to manufacture the integrated circuit. In some implementations, such data may be stored in a database file format, such as Graphic Data System II (GDS II), Open Artwork System Interchange Standard (OASIS), or a similar format.

[0119] In some implementations, software-based hardware models and HDL and other functional description language objects may include register transfer language (RTL) files, among other examples. Such objects may be machine-analyzable, such that design tools can accept HDL objects (or models), analyze the HDL objects for attributes of the described hardware, and determine a physical circuit and / or chip layout from the objects. The output of the design tools may be used to manufacture physical devices. For example, design tools may determine the configuration of various hardware and / or firmware elements from the HDL objects. HDL objects may include bus widths, registers (including sizes and types), memory blocks, physical link paths, fabric topology, and the like, among other attributes that would be implemented to realize the system modeled in the HDL objects. Design tools may include tools for determining the topology and fabric configurations of systems-on-chips (SoCs) and other hardware devices. In some cases, HDL objects may be used as the basis for developing models and design files that can be used to manufacture equipment to produce the described hardware. In fact, the HDL objects themselves can be provided as input to manufacturing system software to result in the described hardware.

[0120] In any design representation, data may be stored in any form of machine-readable medium. Memory, or magnetic or optical storage such as a disk, may be a machine-readable medium that stores information transmitted via light or radio waves that are modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying code or a design is transmitted, a new copy is made to the extent that copying, buffering, or transmission of the electrical signal is performed. Thus, a communications provider or network provider may at least temporarily store an item, e.g., information encoded in a carrier wave, on a tangible, machine-readable storage medium to embody the techniques of embodiments of the present disclosure.

[0121] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware such as a microcontroller associated with a non-transitory medium that stores code adapted to be executed by the microcontroller. Thus, in one embodiment, reference to a module refers to hardware specifically configured to recognize and / or execute code held on the non-transitory medium. Furthermore, in another embodiment, the use of a module refers to a non-transitory medium containing code specifically adapted to be executed by a microcontroller to perform a plurality of predetermined operations. As can be expected, in yet another embodiment, the term module (in this example) may refer to a combination of a microcontroller and a non-transitory medium. Often, the boundaries of multiple modules shown as separate typically vary and potentially overlap. For example, a first module and a second module may share hardware, software, firmware, or a combination thereof, while potentially maintaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, e.g., transistors, registers, or other hardware such as programmable logic devices.

[0122] Logic may be used to implement any of the functions of various components, such as CPU 102, external I / O controller 104, processor 108, cores 114A and 114B, I / O controller 110, CPU memory controller 112, storage device 106, system memory device 107, memory chip 116, storage device controller 118, address translation engine 120, memory partition 122, program control logic 124, chip controller 126, memory array 306, memory partition controller 310, word line control logic 314, bit line control logic 316, or other entities or components described herein, or any subcombination thereof. "Logic" may refer to hardware, firmware, software, and / or combinations of each to perform one or more functions. In various embodiments, logic may include a microprocessor or other processing element operable to execute software instructions, discrete logic such as an application specific integrated circuit (ASIC), a programmed logic device such as a field programmable gate array (FPGA), a storage device containing instructions, a combination of logic devices (e.g., as found on a printed circuit board), or other suitable hardware and / or software. Logic may include one or more gates or other circuit components. In some embodiments, logic may also be embodied entirely as software. Software may be embodied as a software package, code, instructions, instruction sets, and / or data recorded on a non-transitory computer-readable storage medium. Firmware may be embodied as hard-coded (e.g., non-volatile) code, instructions, instruction sets, and / or data in a storage device.

[0123] The use of the phrases “to” or “configured to” may, in one embodiment, refer to arranging, combining, manufacturing, selling, importing, and / or designing an apparatus, hardware, logic, or element to perform a specified or determined task. In this example, an inoperative apparatus or element thereof is still “configured” to perform a specified task if it is designed, coupled, and / or interconnected to perform the specified task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate “configured” to provide an enable signal to a clock does not include any underlying logic gates that may provide a 1 or a 0. Instead, the logic gate is coupled in some manner such that a 1 or 0 output enables the clock during operation. Again, note that the use of the term “configured to” does not require operation, but instead focuses on the hidden state of the apparatus, hardware, and / or element. In the hidden state, the apparatus, hardware, and / or element is designed to perform a particular task when the apparatus, hardware, and / or element is operating.

[0124] Additionally, in one embodiment, the use of the terms "enable" or "operable" refers to any device, logic, hardware, and / or element that is designed in a manner that allows the device, logic, hardware, and / or element to be used in a specified manner. It should also be noted that in one embodiment, the use of the terms "will," "enable," or "operable" refers to the hidden state of the device, logic, hardware, and / or element, in which case the device, logic, hardware, and / or element is not operational but is designed to allow the device to be used in a specified manner.

[0125] As used herein, a value includes any known representation of a number, state, logic state, or binary logic state. Often, the use of logic levels, logic values, or logic values, also referred to as "ones" and "zeros," simply represents a binary logic state. For example, a one refers to a high logic level and a zero refers to a low logic level. In one embodiment, a storage cell, such as a transistor cell or flash cell, may be capable of holding a single logic value or multiple logic values. However, other representations of values ​​in computer systems are used. For example, the decimal number 10 may also be represented as the binary value 1010 and the hexadecimal character A. Thus, a value includes any representation of information capable of being held in a computer system.

[0126] Furthermore, a state may be represented by a value or portion of a value. As an example, a first value, such as a logic one, may represent a default or initial state, while a second value, such as a logic zero, may represent a non-default state. Additionally, in one embodiment, the terms reset and set refer to default and updated values ​​or states, respectively. For example, a default value potentially includes a high logic value, i.e., reset, while an updated value potentially includes a low logic value, i.e., set. Note that any combination of multiple values ​​may be utilized to represent any number of states.

[0127] The method, hardware, software, firmware, or code embodiments described above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium that is executable by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system. For example, a non-transitory machine-accessible medium includes random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM), ROM, magnetic or optical storage media, flash storage devices, electrical storage devices, optical storage devices, acoustic storage devices, other forms of storage devices for retaining information received from a transitory (propagated) signal (e.g., carrier wave, infrared signal, digital signal), and the like, which are distinct from non-transitory media that may receive information therefrom.

[0128] The instructions used to program logic to implement embodiments of the present disclosure may be stored in memory in the system, such as DRAM, cache, flash memory, or other storage. Additionally, the instructions may be distributed over a network or using other computer-readable media. Thus, a machine-readable storage medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), including, but not limited to, floppy diskettes, optical disks, compact disks, read-only memories (CD-ROMs), and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs), erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), magnetic or optical cards, flash memories, or tangible machine-readable storage media used to transmit information over the Internet via the form of electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Thus, a computer-readable medium includes any type of tangible machine-readable storage medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).

[0129] Some example embodiments are provided below.

[0130] Example 1 includes a semiconductor device comprising: a multilayer semiconductor structure including: a substrate; a plurality of device layers on the substrate, the plurality of device layers defining trenches extending through the plurality of device layers and pillars between the trenches; one or more materials filling the trenches; and a carbon-containing liner on at least a portion of a sidewall of the trench and disposed between the pillars and the one or more materials filling the trenches, wherein one or more of the plurality of device layers includes a conductive layer; and an electrical contact line electrically coupled to one or more of the plurality of device layers.

[0131] Example 2 includes the subject matter of Example 1, optionally, wherein the carbon-containing liner includes at least one of a carbon-doped oxide liner or a carbon-doped nitride liner.

[0132] Example 3 includes the subject matter of Example 1, optionally, the carbon-containing liner includes a carbon-doped nitride liner, and at least a portion of the sidewalls of the trench on which the carbon-doped nitride liner is located do not include an oxide liner thereon.

[0133] Example 4 includes the subject matter of example 1, optionally, the carbon-containing liner includes at least one of SiOC, SiCN, or SiC.

[0134] Example 5 includes the subject matter of Example 1, optionally, the carbon-containing liner includes a nitride liner on at least a portion of the sidewalls of the trench, and a carbon-doped oxide liner on the nitride liner, such that the nitride liner is between the pillar and the carbon-doped oxide liner.

[0135] Example 6 includes the subject matter of Example 5, and optionally, the nitride liner is a first nitride liner, the previous carbon-doped oxide liner is a first carbon-doped oxide liner, and the carbon-containing liner further includes one or more additional nitride and carbon-doped oxide liner pairs disposed on the first carbon-doped oxide liner such that a surface of the last carbon-doped oxide liner of the additional liner pairs faces the interior of the trench.

[0136] Example 7 includes the subject matter of example 1, and optionally, the device is a non-volatile memory device, the pillars include memory cells of the non-volatile memory device, and the memory cells are defined in part by multiple device layers.

[0137] Example 8 includes the subject matter of Example 1, and optionally, the carbon-containing liner includes a liner made of a material containing, in terms of atomic percentage, about 10% to about 50% carbon, about 10% to about 30% carbon, or about 15% to about 20% carbon.

[0138] Example 9 includes the subject matter of Example 1, and optionally includes a liner made of a material that is one of substantially uniformly doped through its thickness or non-uniformly doped through its thickness.

[0139] Example 10 includes a method of forming a device, the method including providing a stack on a substrate, the stack including a plurality of device layers including a conductive layer; patterning the stack using etching to form trenches extending through the stack and pillars between the trenches; providing a carbon-containing liner on sidewalls of the trenches; wet cleaning and drying the stack after providing the carbon-containing liner; filling spaces between the pillars with one or more materials; and electrically connecting contact lines to the conductive layer to form a semiconductor device.

[0140] Example 11 includes the subject matter of example 10, optionally wherein providing a carbon-containing liner includes providing a carbon-doped liner at a temperature between about 100°C and about 300°C.

[0141] Example 12 includes the subject matter of example 10, optionally, wherein providing a carbon-containing liner includes providing a carbon-doped liner using atomic layer deposition of a liner material with a carbon precursor.

[0142] Example 13 includes the subject matter of example 10, optionally including a nitride liner on the sidewalls of the trench and a carbon-doped oxide liner on the nitride liner, such that the nitride liner is between the pillar and the carbon-doped oxide liner.

[0143] Example 14 includes the subject matter of Example 13, and optionally further includes: the trench is a first trench, the pillar is a first pillar, the etch is a first etch, the nitride liner is a first nitride liner, and the carbon-doped oxide liner is a first carbon-doped oxide liner; and the method further includes, after wet cleaning and drying the stack, patterning the stack with a second etch to deepen the first trench and lengthen the first pillar to form second trenches extending through the stack and second pillars between the second trenches; providing a second carbon-containing liner on sidewalls of the second trenches; after providing the second carbon-containing liner, wet cleaning and drying the stack; and filling spaces between the second pillars with one or more materials.

[0144] Example 15 includes the subject matter of example 10, and optionally, the device is a non-volatile memory device, the pillars include memory cells of the non-volatile memory device, and the memory cells are defined in part by multiple device layers.

[0145] Example 16 includes the subject matter of Example 10, and optionally, the carbon-containing liner includes a liner made of a material containing, in terms of atomic percentage, about 10% to about 50% carbon, about 10% to about 30% carbon, or about 15% to about 20% carbon.

[0146] Example 17 includes a device comprising: input / output (I / O) circuitry for coupling the device to an external controller; and one or more dies, each of the dies comprising: a substrate; multiple device layers on the substrate defining trenches extending through the multiple device layers and pillars between the trenches; one or more materials filling the trenches; and a carbon-containing liner on at least a portion of sidewalls of the trenches and disposed between the pillars and the one or more materials filling the trenches, wherein one or more of the multiple device layers comprises a conductive layer; and electrical contact lines electrically coupled to one or more of the multiple device layers.

[0147] Example 18 includes the subject matter of Example 17, and optionally, the device is a memory module, each of the dies is a non-volatile memory device, the pillars include memory cells of the non-volatile memory device, and the memory cells are defined in part by multiple device layers.

[0148] Example 19 includes the subject matter of example 17, optionally, the carbon-containing liner includes at least one of a carbon-doped oxide liner or a carbon-doped nitride liner.

[0149] Example 20 includes the subject matter of example 17, optionally wherein the carbon-containing liner comprises a carbon-doped nitride liner, and wherein at least a portion of a sidewall of the trench upon which the carbon-doped nitride liner is located does not include an oxide liner thereon.

[0150] Example 21 includes the subject matter of example 17, optionally, the carbon-containing liner includes at least one of SiOC, SiCN, or SiC.

[0151] Example 22 includes the subject matter of example 17, optionally including the carbon-containing liner: a nitride liner on at least a portion of the sidewalls of the trench; and a carbon-doped oxide liner on the nitride liner, such that the nitride liner is between the pillar and the carbon-doped oxide liner.

[0152] Example 23 includes the subject matter of Example 22, optionally wherein the nitride liner is a first nitride liner, the carbon-doped oxide liner is a first carbon-doped oxide liner, and the carbon-containing liner further includes one or more additional nitride and carbon-doped oxide liner pairs disposed on the first carbon-doped oxide liner such that a surface of the last carbon-doped oxide liner of the additional liner pairs faces the interior of the trench.

[0153] Example 24 includes the subject matter of Example 17, and optionally, the carbon-containing liner includes a liner made of a material containing, in terms of atomic percentage, about 10% to about 50% carbon, about 10% to about 30% carbon, or about 15% to about 20% carbon.

[0154] Example 25 includes the subject matter of example 17, and optionally includes a liner made of a material that is one of substantially uniformly doped through its thickness or non-uniformly doped through its thickness.

[0155] Example 26 includes a device comprising one or more processors and one or more computer-readable media containing instructions that, when executed by the one or more processors, cause the one or more processors to perform a method, technique, or process described in or related to any of the preceding examples or portions thereof.

[0156] Example 27 includes a signal as described in or related to any of the above examples or any part or portion thereof.

[0157] Example 28 includes a datagram, packet, frame, segment, protocol data unit (PDU), or message described in or relating to any of the above examples, or any part or portion thereof, or otherwise described in this disclosure.

[0158] Example 29 includes a signal encoded with data as described in or related to any of the above examples, or any part or portions thereof, or as otherwise described in this disclosure.

[0159] Example 30 includes a signal encoded with a datagram, packet, frame, segment, protocol data unit (PDU), or message described in or relating to any of the above examples, or any part or portion thereof, or otherwise described in this disclosure.

[0160] Example 31 includes an electromagnetic signal carrying computer-readable instructions, the execution of which by one or more processors causes the one or more processors to perform a method, technique, or process described in or related to any of the above examples or portions thereof.

[0161] Example 32 includes a computer program including instructions, the execution of which by a processing element causes the processing element to perform a method, technique, or process described in or related to any of the above examples or portions thereof.

[0162] Throughout this specification, a reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0163] In the foregoing specification, the detailed description has been made with reference to certain exemplary embodiments. However, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the appended claims. Accordingly, the specification and drawings should be regarded in an illustrative, rather than a restrictive, sense. Furthermore, the above use of the terms embodiment and other exemplary language does not necessarily refer to the same embodiment or the same example, but may refer to different and separate embodiments, as well as potentially the same embodiment.

Claims

1. a plurality of device layers on the substrate, the plurality of device layers defining trenches extending through the plurality of device layers and pillars between the trenches; one or more materials filling the trenches; and a carbon-containing liner disposed along sidewalls of the trenches between the pillars and the one or more materials filling the trenches, wherein one or more of the plurality of device layers comprises a conductive layer, the sidewalls defining a stepped configuration in a depth direction of the trench, the carbon-containing liner including a first carbon-containing liner portion extending along the sidewalls and terminating at a first step of the stepped configuration, and a second carbon-containing liner portion extending along the sidewalls and terminating at a second step of the stepped configuration; electrical contact lines electrically coupled to the one or more of the plurality of device layers; Semiconductor devices.

2. The semiconductor device of claim 1, wherein the carbon-containing liner comprises a carbon-doped nitride liner, and the sidewalls of the trench on which the carbon-doped nitride liner is located do not comprise an oxide liner thereon.

3. A semiconductor device as described in claim 1 or 2, wherein the carbon-containing liner comprises a nitride liner and a carbon-doped oxide liner on the nitride liner, such that the nitride liner is between the pillar and the carbon-doped oxide liner.

4. A multilayer semiconductor structure comprising: a substrate; a plurality of device layers on the substrate, the plurality of device layers defining trenches extending through the plurality of device layers and pillars between the trenches; one or more materials filling the trenches; and a carbon-containing liner on at least a portion of a sidewall of the trench and disposed between the pillars and the one or more materials filling the trenches, wherein one or more of the plurality of device layers comprises a conductive layer; electrical contact lines electrically coupled to the one or more of the plurality of device layers; the carbon-containing liner includes a nitride liner on the at least a portion of the trench sidewall, and a carbon-doped oxide liner on the nitride liner, such that the nitride liner is between the pillar and the carbon-doped oxide liner. Semiconductor devices.

5. The semiconductor device of claim 1 or 4, wherein the carbon-containing liner comprises at least one of a carbon-doped oxide liner or a carbon-doped nitride liner.

6. 5. The semiconductor device of claim 4, wherein the carbon-containing liner comprises a carbon-doped nitride liner, and the at least a portion of the trench sidewall overlying the carbon-doped nitride liner does not comprise an oxide liner thereon.

7. The semiconductor device of claim 1 , wherein the carbon-containing liner comprises at least one of SiOC, SiCN, or SiC.

8. 5. The semiconductor device of claim 4, wherein the nitride liner is a first nitride liner, the carbon-doped oxide liner is a first carbon-doped oxide liner, and the carbon-containing liner further comprises one or more additional nitride and carbon-doped oxide liner pairs disposed on the first carbon-doped oxide liner such that a surface of a last carbon-doped oxide liner of the one or more additional nitride and carbon-doped oxide liner pairs faces the interior of the trench.

9. the semiconductor device is a non-volatile memory device; the pillars contain memory cells of the non-volatile memory device, the memory cells being defined in part by the plurality of device layers; 9. The semiconductor device according to claim 1.

10. 10. The semiconductor device of claim 1, wherein the carbon-containing liner comprises a liner made of a material containing, in terms of atomic percentage, about 10% to about 50% carbon, about 10% to about 30% carbon, or about 15% to about 20% carbon.

11. 11. The semiconductor device of claim 1, wherein the carbon-containing liner comprises a liner made of a material that is one of: substantially uniformly doped through its thickness; or non-uniformly doped through its thickness.

12. A device, Input / Output (I / O) circuitry for coupling the device to an external controller; One or more dies having the semiconductor device according to any one of claims 1 to 11; Equipped with device.

13. The device is a memory module, each of the one or more dies is a non-volatile memory device, the pillars include memory cells of the non-volatile memory device, the memory cells being defined in part by the plurality of device layers; The device of claim 12.

14. 1. A method of forming a semiconductor device, comprising: providing a stack on a substrate, the stack including a plurality of device layers including a conductive layer; patterning the stack using a first etch to form first trenches extending through the stack and first pillars between the first trenches; providing a first carbon-containing liner on a sidewall of the first trench; wet cleaning and drying the stack after applying the first carbon-containing liner; after wet cleaning and drying the stack, patterning the stack using a second etch to deepen the first trenches and lengthen the first pillars to form second trenches extending through the stack and second pillars between the second trenches; providing a second carbon-containing liner on a sidewall of the second trench; wet cleaning and drying the stack after applying the second carbon-containing liner; filling a space between the first pillar and the second pillar with one or more materials; electrically connecting contact lines to the conductive layer to form the semiconductor device; A method comprising:

15. 15. The method of claim 14, wherein providing each of the first carbon-containing liner and the second carbon-containing liner comprises providing a carbon-doped liner at a temperature between about 100°C and about 300°C.

16. 15. The method of claim 14, wherein providing each of the first and second carbon-containing liners comprises using atomic layer deposition of a material for each of the first and second carbon-containing liners with a carbon precursor.

17. 17. The method of claim 14, wherein each of the first carbon-containing liner and the second carbon-containing liner comprises a nitride liner and a carbon-doped oxide liner on the nitride liner, the nitride liner being between a corresponding one of the first pillar or the second pillar and the corresponding carbon-doped oxide liner.

18. the semiconductor device is a non-volatile memory device; the first pillar and the second pillar together comprise a memory cell of the non-volatile memory device, the memory cell being defined in part by the plurality of device layers.

18. The method of any one of claims 14 to 17.

19. 19. The method of any one of claims 14 to 18, wherein each of the first carbon-containing liner and the second carbon-containing liner comprises a liner made of a material containing, in terms of atomic percentage, about 10% to about 50% carbon, about 10% to about 30% carbon, or about 15% to about 20% carbon.

20. A method of forming a semiconductor device, comprising: providing a stack on a substrate, the stack including a plurality of device layers including a conductive layer; patterning the stack using etching to form trenches extending through the stack and pillars between the trenches; providing a carbon-containing liner on the sidewalls of the trench; wet cleaning and drying the stack after applying the carbon-containing liner; filling the spaces between the pillars with one or more materials; electrically connecting contact lines to the conductive layer to form the semiconductor device; Including, the carbon-containing liner comprises a nitride liner on the sidewalls of the trench and a carbon-doped oxide liner on the nitride liner, such that the nitride liner is between the pillar and the carbon-doped oxide liner.

21. The method of claim 20, wherein the step of providing the carbon-containing liner includes providing a carbon-doped liner at a temperature of about 100°C to about 300°C.

22. The method of claim 20, wherein the step of providing the carbon-containing liner includes providing a carbon-doped liner using atomic layer deposition of the carbon-containing liner material together with a carbon precursor.

23. The method of claim 23, wherein the trench is a first trench, the pillar is a first pillar, the etch is a first etch, the nitride liner is a first nitride liner, the carbon doped oxide liner is a first carbon doped oxide liner, and the method comprises: after wet cleaning and drying the stack, patterning the stack using a second etch to deepen the first trenches and lengthen the first pillars to form second trenches extending through the stack and second pillars between the second trenches; providing a second carbon-containing liner on a sidewall of the second trench; wet cleaning and drying the stack after applying the second carbon-containing liner; further comprising filling the spaces between the pillars with one or more materials comprises filling the spaces between the first pillars and the second pillars with the one or more materials.

23. The method of any one of claims 20 to 22.

24. The semiconductor device according to claim 2, wherein the semiconductor device is a non-volatile memory device; the pillars contain memory cells of the non-volatile memory device, the memory cells being defined in part by the plurality of device layers; 24. The method of any one of claims 20 to 23.

25. A method described in any one of claims 20 to 24, wherein the carbon-containing liner comprises a liner made of a material containing, in terms of atomic percentage, about 10% to about 50% carbon, about 10% to about 30% carbon, or about 15% to about 20% carbon.

26. 26. A device comprising one or more computer-readable media containing instructions that, when executed by the one or more processors, cause the one or more processors to perform the method of any one of claims 14 to 25.

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