transistor

Abstract

To provide a novel metal oxide.SOLUTION: A crystalline metal oxide includes a first layer and a second layer. The first layer has a wider bandgap than the second layer. By the first layer and the second layer, a crystal lattice is formed. When a carrier is excited in the metal oxide, carriers are transmitted through the second layer. The first layer includes an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, and the second layer includes In.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a metal oxide and a transistor including the metal oxide. One aspect of the present invention relates to a semiconductor device, a semiconductor wafer, a module, and an electronic device. do.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, electronic device etc. may be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an article, a method, or a manufacturing method. is a process, machine, manufacture, or composition of matter. This concerns the [Background technology]

[0004] In oxide semiconductors, there are c-axis ally coupled oxides (CAAC) that are neither single crystal nor amorphous. nc (nanocrystalline) structure and nc (nanocrystalline) ) structure has been found (see Non-Patent Documents 1 and 2).

[0005] In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used to Techniques for fabricating transistors are disclosed.

[0006] In the latter half of the 1980s, the energy A layer with a large energy band width and a semiconductor layer with a small energy band width interact quantum mechanically. A multilayer structure technology using this method has been disclosed (see Patent Document 1).

[0007] In Patent Document 1, a semiconductor layer-insulator layer-semiconductor layer is formed in the channel formation region of a transistor. A superlattice structure consisting of repeated multilayer structures is provided, and each layer is The layers are stacked so that the surfaces of the layers are aligned along the direction of carrier movement. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 63-94680 [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, pp.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a novel metal oxide. An object of one embodiment of the present invention is to provide a novel transistor. An object of one embodiment is to provide a semiconductor device with large on-state current. An object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of the present invention is to provide a semiconductor device having favorable electrical characteristics. One of the goals is to

[0011] Another embodiment of the present invention provides a semiconductor device capable of retaining data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device having a high data writing speed. Another object of the present invention is to provide a device that can reduce power consumption. It is an object of the present invention to provide a semiconductor device that can achieve this.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0013] One aspect of the present invention is a crystalline metal oxide, wherein the crystalline metal oxide is a first layer and , and a second layer, wherein the first layer has a wider band gap than the second layer, and the first layer, The first and second layers form a crystal lattice, which excites carriers in the crystalline metal oxide. In this case, the carrier is transmitted through the second layer.

[0014] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; Each of the first layer and the second layer is approximately parallel to the surface of the crystalline metal oxide on which it is formed. The first layer and the second layer form a crystal lattice, forming a crystalline metal oxide. When carriers are excited in the material, the carriers are transmitted through the second layer.

[0015] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; The first layer is composed of an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn and the second layer contains In, and each of the first layer and the second layer contains The first and second layers are arranged approximately parallel to the surface on which the crystalline metal oxide is formed. Therefore, when a crystal lattice is formed and carriers are excited in the crystalline metal oxide, Carriers are transmitted through the second layer.

[0016] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; Each of the first layer and the second layer is approximately perpendicular to the surface of the crystalline metal oxide on which it is formed. The first layer and the second layer form a crystal lattice, forming a crystalline metal oxide. When carriers are excited in the material, the carriers are transmitted through the second layer.

[0017] Another embodiment of the present invention is a crystalline metal oxide, the crystalline metal oxide comprising: a first layer and a second layer, the first layer having a wider band gap than the second layer; The first layer is composed of an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn and the second layer contains In, and each of the first layer and the second layer contains The first layer and the second layer are arranged approximately perpendicular to the surface on which the crystalline metal oxide is formed. Therefore, when a crystal lattice is formed and carriers are excited in the crystalline metal oxide, Carriers are transmitted through the second layer.

[0018] In the crystalline metal oxide, the distance between the first layer and the second layer is 1 nm or less. In addition, in the crystalline metal oxide, it is preferable that the crystalline metal oxide is c When observed from the axial direction using a TEM, crystalline metal oxides have hexagonal lattice points. preferable.

[0019] Another aspect of the present invention is a semiconductor device comprising a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide layer comprising a first layer and a second layer. , the first layer has a wider band gap than the second layer, and the first layer and the second layer , which are arranged approximately parallel to the channel length direction of the transistor, and the first layer, The second layer forms a crystal lattice, and when a voltage is applied to the gate, the crystalline metal oxide is formed. When carriers are excited in the material, they are transported from the source to the drain through the second layer. The rear is transmitted.

[0020] Another aspect of the present invention is a semiconductor device comprising a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide layer comprising a first layer and a second layer. , the first layer has a wider band gap than the second layer, and the first layer and the second layer Each of the first and second layers is arranged approximately parallel to the surface of the crystalline metal oxide on which it is formed. The second layer forms a crystal lattice, and when a voltage is applied to the gate, the crystalline metal oxide When carriers are excited in the second layer, they are transported from the source to the drain. The data is transmitted.

[0021] Another aspect of the present invention is a semiconductor device comprising a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide layer comprising a first layer and a second layer. , the first layer has a wider band gap than the second layer, and the first layer and the second layer Each of the first and second layers is disposed approximately perpendicular to the surface of the crystalline metal oxide on which it is formed. The second layer forms a crystal lattice, and when a voltage is applied to the gate, the crystalline metal oxide When carriers are excited in the second layer, they are transported from the source to the drain. The data is transmitted.

[0022] Another aspect of the present invention is a semiconductor device comprising a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide is a first metal oxide and a first a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide are each a first layer and a second layer, the first layer having a wider band gap than the second layer, The first layer and the second layer are arranged approximately parallel to the channel length direction of the transistor. A crystal lattice is formed by the first layer and the second layer, and a voltage is applied to the gate. When carriers are excited in a crystalline metal oxide, they are transported from the source through the second layer. Carriers are transferred from the gate to the drain.

[0023] Another aspect of the present invention is a semiconductor device comprising a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide is a first metal oxide and a first a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide are each a first layer and a second layer, the first layer having a wider band gap than the second layer, The first layer of the second metal oxide and the second layer of the second metal oxide are The metal oxide is disposed approximately parallel to the surface on which the metal oxide is to be formed, and the first layer and the second layer A crystal lattice is formed, and when a voltage is applied to the gate, carriers are excited in the crystalline metal oxide. When the second layer is applied, carriers are transferred from the source to the drain through the second layer.

[0024] In the transistor, a third metal oxide The material covers the top surface and side surfaces of the second metal oxide, and the gate covers the top surface of the second metal oxide and the side surfaces of the second metal oxide. and a side surface of the second metal oxide, and the side surface of the second metal oxide is in the c-axis direction of the third metal oxide and the c-axis direction of the first metal oxide. It is preferable that the c-axis direction of the metal oxide of the first metal oxide is different from that of the second metal oxide.

[0025] Another aspect of the present invention is a semiconductor device comprising a crystalline metal oxide and a gate, a source, and a drain. and a crystalline metal oxide is a first metal oxide and a first a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide are each a first layer and a second layer, the first layer having a wider band gap than the second layer, The first layer of the second metal oxide and the second layer of the second metal oxide are The metal oxide is disposed approximately perpendicular to the surface on which the metal oxide is formed, and the first layer and the second layer are A crystal lattice is formed, and when a voltage is applied to the gate, carriers are excited in the crystalline metal oxide. When the second layer is applied, carriers are transferred from the source to the drain through the second layer.

[0026] In the transistor, a first region that does not overlap with the second metal oxide is formed in the gate. The bottom surface of the first region is lower than the bottom surface of the second metal oxide, and the first region and the second region are The bottom surface of the second region located opposite to the second metal oxide is the bottom surface of the second metal oxide. A lower position is preferable.

[0027] In the transistor, a second metal oxide and a gate electrode are formed under the first metal oxide. It is preferable to have a second gate overlapping at least a portion of the region where the first and second gates overlap.

[0028] In the above transistor, either the channel length or the channel width of the transistor is Preferably, one or both have an area of ​​100 nm or less.

[0029] In the above transistor, the first layer is made of an element M (M is Al, Ga, Y, and S). n) and Zn, and the second layer contains In. is preferred. [Effects of the Invention]

[0030] According to one embodiment of the present invention, a novel metal oxide can be provided. According to one embodiment of the present invention, a novel transistor can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. A semiconductor device having high frequency characteristics can be provided. Therefore, a highly reliable semiconductor device can be provided. It is possible to provide a semiconductor device that can be miniaturized or highly integrated. In this manner, a semiconductor device having good electrical characteristics can be provided.

[0031] According to one embodiment of the present invention, a semiconductor device capable of retaining data for a long period of time is provided. According to one embodiment of the present invention, a semiconductor device capable of writing data at a high speed can be provided. Furthermore, according to one embodiment of the present invention, power consumption can be reduced. A semiconductor device can be provided.

[0032] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0033] [Figure 1] 1A and 1B are a cross-sectional view and a band diagram of a transistor according to one embodiment of the present invention, a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention, and a diagram illustrating the energy of the conduction band minimum of the crystals. [Figure 2] A diagram explaining the layer structure of a metal oxide crystal, as well as the lattice vibration of metal oxide atoms and carrier transmission. [Figure 3] A diagram explaining lattice vibration of atoms and carrier transmission in metal oxides. [Figure 4] FIG. 10 is a perspective view of a transistor according to one embodiment of the present invention. [Figure 5] 1A and 1B are cross-sectional views of a transistor according to one embodiment of the present invention and a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention. [Figure 6] FIG. 10 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 7] FIG. 10 is a perspective view of a transistor according to one embodiment of the present invention. [Figure 8] FIG. 10 is a cross-sectional view of a transistor according to one embodiment of the present invention. [Figure 9] FIG. 10 is a perspective view of a transistor according to one embodiment of the present invention. [Figure 10] 1A and 1B are a cross-sectional view and a band diagram of a transistor according to one embodiment of the present invention, and a diagram illustrating crystals contained in a metal oxide according to one embodiment of the present invention. [Figure 11] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 13] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 14] Cross-sectional TEM image and local Fourier transform image of an oxide semiconductor. [Figure 15] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 16]1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 19] FIG. 1 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. [Figure 20] 1A and 1B are a block diagram and a schematic diagram illustrating a configuration example of a memory device of one embodiment of the present invention. [Figure 21] FIG. 1 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. [Figure 22] 1A and 1B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 23] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. [Figure 24] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 25] 1 is a cross-sectional TEM image according to an embodiment of the present invention. [Figure 26] 1 is a cross-sectional TEM image according to an embodiment of the present invention. [Figure 27] 1A to 1C are diagrams illustrating a cross-sectional TEM image of a sample according to an example and an EDX line analysis. [Figure 28] FIG. 10 is a graph showing temperature dependence of VG-ID characteristics of a transistor. [Figure 29] FIG. 10 is a diagram for explaining a method for calculating an operating frequency. [Figure 30] FIG. 10 is a diagram showing the calculation results of the operating frequency. [Figure 31] FIG. 10 is a diagram showing the calculation results of the operating frequency. [Figure 32] 1A and 1B are graphs showing carrier concentrations and Hall mobilities of oxide semiconductors according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0034] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be practiced in various different ways without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0035] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in the drawings as a schematic illustration, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals between different drawings. In addition, when referring to similar functions, In such cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0036] In addition, the invention can be easily understood, especially in top views (also called "plan views") and perspective views. In order to simplify the description, some components may be omitted. The information may be omitted.

[0037] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" The term "the" or "third" can be used interchangeably in the description. The ordinal numbers listed may not match the ordinal numbers used to identify an aspect of the present invention. There may be cases where this is the case.

[0038] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in describing the same with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those described above, and can be rephrased appropriately depending on the situation.

[0039] For example, in this specification, it is explicitly stated that X and Y are connected. In this case, X and Y are electrically connected, and X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification. Therefore, it is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. It shall be.

[0040] Here, X and Y are the object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, layer, etc.).

[0041] In this specification, a transistor includes a gate, a drain, and a source. It is an element having at least three terminals including a drain (drain terminal, drain Between the drain electrode and the source terminal The channel forming region is formed in the channel. A current can be passed between the source and the drain through the channel forming region. In this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0042] The functions of the source and drain may differ depending on whether transistors with different polarities are used or whether the circuit This may happen when the direction of the current changes during operation. In the specification, the terms source and drain may be used interchangeably. do.

[0043] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source electrode) in the region where the source is formed or the channel forming region This refers to the distance between the transistor and the drain (drain region or drain electrode). In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of the transistor may not be determined to a single value. In the above, the channel length is any one value, maximum value, minimum value or the like in the channel forming region. or the average value.

[0044] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor where current flows when the semiconductor is on). In the channel forming region, the channel is formed in a direction perpendicular to the channel length direction. The length of the formation region. In one transistor, the channel width is the length of the entire region. In other words, the channel width of a transistor does not necessarily take the same value. Therefore, in this specification, the channel width is determined as the width of the channel forming region. The value is any one of the values, the maximum value, the minimum value, or the average value.

[0045] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in a top view of the star (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective When the channel width becomes larger than the apparent channel width and its effect cannot be ignored For example, in a transistor that is miniaturized and in which the gate electrode covers the side of the semiconductor, The proportion of the channel formation region formed on the side surface may become large. The effective channel width is larger than the upper channel width.

[0046] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, the effective Channel width is difficult to measure accurately.

[0047] In this specification, when the term "channel width" is simply used, it refers to the apparent channel width. In this specification and the like, when simply referring to the channel width, it may refer to the effective channel width. It may refer to the channel width. The channel width and other parameters can be determined by analyzing cross-sectional TEM images. This can be done.

[0048] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. This can cause problems such as an increase in the density of defect levels in semiconductors and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the properties of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and oxides There are transition metals other than the main components of semiconductors, such as hydrogen, lithium, sodium, and silicon. In the case of oxide semiconductors, water also functions as an impurity. In the case of an oxide semiconductor, for example, oxygen vacancies can be created by the inclusion of impurities. In addition, when the semiconductor is silicon, there are cases where an impurity that changes the properties of the semiconductor is formed. The pure substances include, for example, oxygen, Group 1 elements excluding hydrogen, Group 2 elements, Group 13 elements, and Group 1 elements. Group 5 elements, etc.

[0049] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains a large amount of silicon dioxide rather than oxygen. It has a high nitrogen content.

[0050] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0051] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes cases where the angle is between -5 degrees and 5 degrees. In addition, "approximately parallel" means that two straight lines are arranged at an angle of between -30 degrees and 30 degrees. Also, "perpendicular" means that two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. "Perpendicular" refers to two straight lines that form an angle between 60 degrees and 120 degrees.

[0052] In this specification and the like, the term "barrier film" refers to a film that prevents the permeation of impurities such as water and hydrogen, and oxygen. If the barrier film is conductive, it is called a conductive barrier. It is sometimes called the rear membrane.

[0053] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the semiconductor layer of a transistor, Such a metal oxide may be referred to as an oxide semiconductor. In this case, the transistor can be referred to as a transistor including an oxide or an oxide semiconductor. Cut.

[0054] In this specification, normally off means that no potential is applied to the gate, or The current per 1 μm of channel width that flows through a transistor when a ground potential is applied to the gate is 1×10 at room temperature -20 A or less, 1 x 10 at 85°C -18 A or below, or 1 x 10 at 125°C -16 This means that it is A or below.

[0055] (Embodiment 1) In this embodiment, a metal oxide according to one embodiment of the present invention and a semiconductor device having the metal oxide will be described. The transistor will be described with reference to FIGS.

[0056] <Transistor configuration example> FIG. 1A is a cross-sectional view of a transistor 10 of one embodiment of the present invention in the channel length direction. do.

[0057] As shown in FIG. 1A, a transistor 10 is disposed on a substrate (not shown). An oxide 230, an insulator 250 disposed on the oxide 230, and a dielectric layer 250 disposed on the insulator 250. The oxide 230 also has a conductor 260 disposed thereon. a region 234 which functions as a region where a channel is formed (hereinafter also referred to as a channel forming region); , the region 231 (region 231a, and region 231b) functioning as a source region or a drain region. 231b). The insulator 250 functions as a gate insulating film. 260 functions as a gate electrode.

[0058] FIG. 1B shows a transistor shown in FIG. 1A at a point X1-X2. This is a model of the band diagram on the chain line. In Figure 1(B), we ignore the k-space and Note that FIG. 1(B) shows the state where no voltage is applied between the gate and source. The solid line located on the conductor 260 indicates the position of the Fermi surface of the conductor 260. The solid line at 50 indicates the position of the bottom of the conduction band of the insulator 250. The solid line indicates the position of the conduction band minimum of the oxide 230.

[0059] The transistor 10 controls the resistance of the channel portion by applying a potential to the gate. That is, the potential applied to the gate can change the conduction between the source and drain. It is possible to control the conduction (transistor on state) and non-conduction (transistor off state). do.

[0060] The transistor 10 has an oxide 230 including a channel forming region, which functions as a semiconductor. It is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor). Compared to semiconductors made of silicon and other materials, the transistors have good switching characteristics. This is preferable because an extremely small off-state current can be obtained.

[0061] In addition, a transistor using an oxide semiconductor for a channel formation region has a Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be deposited using a sputtering method or the like, making them suitable for highly integrated semiconductors. It can be used in transistors that make up devices.

[0062] In addition, a transistor using an oxide semiconductor has an insufficient region in a channel formation region of the oxide semiconductor. The presence of impurities and oxygen vacancies can cause fluctuations in electrical characteristics and reduce reliability. Furthermore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, Therefore, oxygen vacancies in the channel formation region are unlikely to occur. For example, the oxide 23 is formed by interposing an insulator 250 or the like therebetween. By supplying oxygen to the SiO2 layer, the oxygen vacancies can be compensated for. This suppresses fluctuations in electrical properties. It is possible to provide a transistor having stable electrical characteristics and improved reliability. can.

[0063] It is also preferable to use a metal oxide with a low carrier density for the oxide 230. Intrinsic or substantially highly purified intrinsic metal oxides have fewer carrier sources, The carrier density can be reduced. In addition, the semiconductor is highly intrinsic or substantially highly intrinsic. The metal oxide has a low defect state density, and therefore the trap state density may also be low.

[0064] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, magnesium, etc. It is preferable to use a metal oxide. In particular, the element M is aluminum (Al), gallium (Ga), , yttrium (Y), or tin (Sn) may be used. In-Ga oxide and In-Zn oxide may also be used.

[0065] In addition, conductive layers functioning as source and drain electrodes are formed on the oxide 230 in contact therewith. In this case, the element contained in the conductive film absorbs the oxygen of the oxide 230. When the oxide 230 has a function of forming a conductive film, the oxide 230 is preferably formed between the oxide 230 and the conductive film, or in the vicinity of the surface of the oxide 230. In this case, a low resistance region may be formed in part in the low resistance region. Impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the defects function as donors, increasing the carrier density. In addition, at least a part of the low resistance region may be a source region or It is included in the region 231 that functions as the drain region.

[0066] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non crystalline oxide semiconductors.

[0067] The channel formation region of the transistor is formed with a metal oxide film that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferable to use a It is desirable to increase the mobility of the metal oxide used in the transistor. improves carrier transmission or reduces scattering sources that affect carrier transmission It is necessary.

[0068] Therefore, it is possible to use a crystalline metal oxide for the oxide 230 including the channel formation region. It is also preferable that the crystals of the metal oxide have a first layer and a second layer. It is preferable that the first layer and the second layer are alternately stacked. The first layer preferably has a wider band gap than the second layer. In the literature, the first layer has a wider band gap than the second layer, and the first layer is called a wide The second layer has a gap between the first and second layers. The narrow gap is sometimes expressed as the second layer having a narrow gap. The crystalline metal oxide has a narrow gap between the first layer and the second layer. It is preferable to have the crystals sandwiched between the first layer.

[0069] The oxide 230 has a first layer and a second layer, which respectively form the channel of the transistor 10. The first and second layers of the oxide 230 are arranged approximately parallel to the longitudinal direction. are each approximately parallel to the channel length direction of the transistor 10. In addition, each of the first and second layers of the oxide 230 is an oxide. It is preferable that the insulating layer 220 is disposed approximately parallel to the surface on which the oxide 230 is to be formed.

[0070] Examples of crystalline metal oxides include single-crystal oxide semiconductors and CAAC-OS. Crystalline metal oxides can improve carrier transmission. The mobility of the metal oxide is increased, and the on-state current of a transistor using the metal oxide is increased. As a result, the electrical characteristics of the transistor can be improved.

[0071] [Carrier transmission model] Below, we will explain the carrier transport model in crystalline metal oxides. CAAC-OS is an example of a crystalline metal oxide. is a metal oxide (In-M-Zn) composed of indium, element M, zinc, and oxygen. Also called oxide.

[0072] CAAC-OS has a c-axis orientation and multiple nanocrystals (mostly nanocrystals) in the ab-plane direction. The crystal structure is distorted and consists of interconnected crystal regions (with a large diameter of less than 10 nm). The distortion occurs when multiple nanocrystals are connected to each other, resulting in a gap between areas with a uniform lattice arrangement and other areas. This refers to a region where the lattice arrangement changes direction between a region where the lattice arrangement is uniform and a region where the lattice arrangement changes direction.

[0073] When CAAC-OS is viewed from the c-axis direction, the nanocrystals are basically hexagonal, but The shape is not limited to regular hexagons, and they may be non-regular hexagons. In CAAC-OS, the lattice arrangement may be a heptagon. Even in this case, it is difficult to identify clear grain boundaries. In other words, it is clear that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is because it is possible to

[0074] The hexagonal shape of a crystalline metal oxide is due to the transmission of light from the c-axis direction of the metal oxide. Transmission Electron Microscope (TEM) This can be confirmed by observing the image using a microscope.

[0075] An enlarged view of region 51 of oxide 230 shown in FIG. 1(A) is shown in FIG. 1(C). The oxide 230 is an In-M-Zn oxide having a CAAC structure. a, and the composition of the oxide 230 is In:M:Zn=1:1:1 [atomic ratio]. In Fig. 1(C), the c-axis (c-axis) of the In-M-Zn oxide with CAAC structure The s) direction is the up-down direction of the paper, and the ab plane direction is the left-right direction and normal direction of the paper. In FIG. 1C, the oxide 230 has a composition of In:M:Zn=1:1:1. [Atomic ratio] In-M-Zn oxide with CAAC structure was shown, but it is not limited to this. The oxide 230 may be any crystalline metal oxide, for example, a metal oxide having a composition formula of In (1+ α) M (1-α) O3(ZnO) m (α is a real number between 0 and 1, and m is a real number between 0 and 1) The oxide may be an In-M-Zn oxide having a CAAC structure or a single crystal structure.

[0076] As shown in Figure 1(C), the In-M-Zn oxide with the CAAC structure has indium and oxygen (hereinafter referred to as InO layer), and a layer containing element M, zinc, and oxygen ( Hereinafter, a layered crystal structure (also called a layered crystal or layered structure) is formed by stacking the (M,Zn)O layer. In this specification, the (M,Zn)O layer is referred to as an InO layer. The InO layer is located between the InO layer and the adjacent InO layer in the c-axis direction, and contains the element M, zinc, and oxygen. Indium, element M, and zinc are mutually substitutable. Therefore, some of the indium may be contained in the (M,Zn)O layer. A portion of the element M or a portion of zinc may be contained in the InO layer.

[0077] In this specification and the like, the structure in which the first layer and the second layer are alternately stacked is referred to as a crystalline structure. If the unit cell of the crystal structure can be expressed by a certain space group, the stacked structure The structure is sometimes called a crystal lattice. For example, In-M-Zn oxide with a CAAC structure In this case, the first layer is an (M,Zn)O layer and the second layer is an InO layer. The element does not have to be formed of two layers, but may be formed of three or more layers.

[0078] In addition, the larger the distance between the first layer and the second layer, the The interaction between the two atoms becomes weaker, and the crystal lattice becomes structurally unstable. It is preferable that the distance between the atoms constituting the molecule is close to that between the first layer and the second layer. The distance is preferably 1 nm or less, more preferably 0.7 nm or less, and even more preferably 0.5 nm or less. In this way, the crystal lattice formed by the first layer and the second layer is becomes structurally stable.

[0079] As shown in FIG. 1C, the c-axis of the crystal of the CAAC-OS is aligned along the oxide 230 The direction of the normal to the surface on which the transistor 10 is formed or the film surface. In the cross-sectional view, the c-axis of the crystal of the CAAC-OS is oriented in the vertical direction of the paper. The ab plane of the crystal of the CAAC-OS is the surface on which the oxide 230 is formed or the film surface. In other words, the InO layer and the (M,Zn)O layer are each approximately parallel to the oxide 2 Therefore, the CAAC-OS has a property that the The ab plane of the crystal is parallel to the left-right direction of the paper and the normal direction to the paper.

[0080] Here, in the band diagram model shown in FIG. 1(B), the conduction of the oxide 230 An enlarged view of the region 52 at the bottom of the band is shown in FIG. 1(D). In FIG. 1(D), k-space is ignored. The region 52 corresponds to the region 51 in the real space.

[0081] The InO layer and the (M,Zn)O layer have different ratios of constituent elements contained in each layer. Therefore, the InO layer and the (M,Zn)O layer have different band gaps. The (M,Zn)O layer has a different electron affinity. and have different differences in the difference between the vacuum level energy and the energy Ec of the bottom of the conduction band.

[0082] Gallium oxide is known to have a larger band gap than indium oxide. Therefore, when the element M is Ga, the band gap of the (M,Zn)O layer is It is estimated that the band gap of the (M,Zn)O layer is larger than that of the InO layer. The summation force is estimated to be smaller than the electron affinity of the InO layer. The difference between the vacuum level energy and the conduction band minimum energy is It is estimated that this is larger than the difference between the energy of the vacuum level and the energy of the bottom of the conduction band. Therefore, the conduction band minimum of the InO layer is lower than that of the (M,Zn)O layer. It is estimated that the (M,Zn)O layer is located in the band gap region closer to the InO layer. Because of the large gap, the (M,Zn)O layer is sometimes described as having a wide gap. In addition, the InO layer has a smaller band gap than the (M,Zn)O layer, so The nO layer is sometimes said to have a narrow gap.

[0083] In addition, since the InO layer and the (M,Zn)O layer form a crystal lattice, The conduction band minimum of the (M,Zn)O layer is at the boundary between the InO layer and the (M,Zn)O layer. Therefore, as shown in Figure 1(D), The conduction band minimum of the oxide 230 is equal to the conduction band minimum of the InO layer and the conduction band minimum of the (M,Zn)O layer. It is assumed that the edge and the level appear repeatedly. In the figure, the conduction band near the bottom of the (M,Zn)O layer is convex, and the conduction band of the InO layer is The InO layer and the (M,Zn)O layer are formed in the ab-plane direction. Therefore, the minimum of the conduction band in the ab plane direction is constant. The electrons are more likely to be transmitted along the ab-plane direction of the InO layer, where the conduction band minimum is lower.

[0084] Carriers injected from the source are sandwiched between the (M,Zn)O layers with a wide gap. The results are concentrated in the narrow gap InO layer. In D), the carrier transport direction, i.e., the direction from the source to the drain, is the InO layer. This roughly coincides with the ab plane direction (the left-right direction of the paper and the normal direction of the paper). In other words, the main carrier transmission path is the InO layer. When excited, carriers are transported through the InO layer.

[0085] Carriers flow from the source to the drain through the channel forming region. To increase the transmission speed of the semiconductor, it is necessary to form a channel region in which carriers can easily flow in the channel length direction. As described above, in the crystal of the In-M-Zn oxide, Therefore, the ab plane of the crystal of In-M-Zn oxide is It is preferable to align the surface in the direction of carrier flow.

[0086] The layered structure preferably also extends to the region 231 of the oxide 230. This allows the region 231a and the region 231b to be separated by the channel forming region. This can facilitate the transmission of carriers.

[0087] It is estimated that electrons are quantized and move in the ab-plane direction. The electrons contained in the InO layer are The electrons are blocked by the (M,Zn)O layer and there is no lattice scattering, so they are directed in the ab-plane direction of the InO layer. In other words, the mobility in the ab-plane direction is estimated to be higher than that in the c-axis direction. do.

[0088] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the conduction band with low trap level density due to grain boundaries is The bottom edge is spread in the ab-plane direction (this is referred to as a large level in the present specification). Therefore, it can be said that the decrease in electron mobility is unlikely to occur. The crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. AAC-OS can be said to be a metal oxide with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the metal oxides having CAAC-OS are stable. Metal oxides containing -OS are heat-resistant and highly reliable.

[0089] Furthermore, metal oxides tend to have higher mobility as the temperature increases. This is due to the lattice dispersion. The thermal lattice vibration of atoms and the transfer of carriers are shown in Figure 1. 2 and 3.

[0090] Figure 2(A) shows the crystal structure of an In-M-Zn oxide having a CAAC structure. In A), W_(M,Zn)O represents the thickness of the (M,Zn)O layer in the c-axis direction. , W_(M,Zn)O is the (M,Zn) band in the band diagram shown in Figure 1(D). The width of the convex part at the bottom of the conduction band of the InO layer can be expressed as the width of the convex part at the bottom of the conduction band of the InO layer in the c-axis direction. In addition, W_InO is the In band diagram shown in FIG. It can also be referred to as the width of the depression at the bottom of the conduction band of the O layer.

[0091] In addition, Wa_(M,Zn)O shown in FIG. 2(B) is a temperature T that is a reference temperature (e.g., The thickness of the (M,Zn)O layer in the c-axis direction at approximately room temperature (RT) 2(B) shows the temperature T as a reference temperature (for example, room temperature (R .T.)) is approximately the same as the thickness of the InO layer in the c-axis direction. 2(C), Wb_(M,Zn)O is a material whose temperature T is a reference temperature (e.g., room temperature (R. T)) , Wb_InO shown in FIG. 2(C) is a temperature T, which is a reference temperature (for example, room temperature (RT )) and the thickness of the InO layer in the c-axis direction at temperatures higher than In Figures 2(B) and 2(C), the wavy lines on the right side of the figures indicate the paths along which carriers propagate through the InO layer. This shows how it works.

[0092] The larger the mass number of an atom, the smaller the lattice vibration of the atom caused by heat. In the case of In-Ga-Zn oxide, the mass number of the atoms is the largest, followed by Ga and Therefore, Ga and Zn are more likely to be degraded by heat than In. The lattice vibration is large. Therefore, when the temperature rises, the lattice vibration of the (Ga,Zn The vibration of the atoms that make up the (Ga,Zn)O layer increases. In comparison, the atomic bonds between the InO layer and the (Ga,Zn)O layer are weaker, so Ga and Zn The lattice vibration in the c-axis direction is larger than the lattice vibration in the ab-plane direction. Ga_(Ga,Zn)O is larger than Wa_(Ga,Zn)O (see Figure 2(C)). Assuming that the lattice constant of the layered crystal in the c-axis direction does not change with temperature, Wb_(Ga As the (Zn)O layer becomes larger, the Wb_InO becomes relatively smaller (see Figure 2(C)). In other words, the higher the temperature, the smaller the thickness of the InO layer in the c-axis direction.

[0093] 3(A) to 3(C) are band diagrams for the crystal structure shown in FIG. 2(A). 3(A) to 3(D) are diagrams showing the structure of the InO layer and the state in which carriers are transmitted through the InO layer. In 3(C), the source is at the back of the paper and the drain is at the front of the paper. The left-right direction of the paper corresponds to the c-axis direction of the CAAC-OS. The wavy curved surface in the figure indicates the conduction band minimum of the CAAC-OS. In 3(C), the black circles represent carriers (e.g., electrons), and the dotted lines represent the schematic of the carriers. Show the trajectory.

[0094] Figure 3(A) shows a model at a temperature Ta, which is almost the same as the reference temperature (e.g., room temperature (RT)). Wa_(M,Zn)O is the width of the convex part at the bottom of the conduction band of the (M,Zn)O layer. Wa_InO is the width of the depression at the bottom of the conduction band of the InO layer. The model shows a temperature Tb higher than the temperature at which the (M,Zn)O is the width of the convex part at the bottom of the conduction band of the (M,Zn)O layer, and Wb_InO is the In The width of the depression at the bottom of the conduction band of the O layer is shown in Fig. 3(C). Wc_(M,Zn)O is the width of the convex part of the conduction band minimum of the (M,Zn)O layer. and Wc_InO is the width of the depression at the bottom of the conduction band of the InO layer.

[0095] As mentioned above, when the temperature increases, the (Ga,Zn)O layer becomes more oxidized than the InO layer. The atomic vibrations in the (Ga,Zn)O layer are larger than those in the InO The bond between the (Ga,Zn)O layer and the (Ga,Zn)O layer is weak, so the lattice vibration of Ga and Zn in the c-axis direction The lattice vibration in the ab plane direction is larger than that in the ab plane direction. Thus, Wc_(Ga,Zn)O>Wb_(Ga,Zn)O>Wa_(Ga,Zn)O, Assuming that the lattice constant in the c-axis direction of the layered crystal does not change with temperature, W As the amount of (Ga,Zn)O increases, the amount of W_InO becomes relatively small. As shown in Figures 3(A) to 3(C), Wa_InO>Wb_InO>Wc_InO. In other words, as the temperature increases, the thickness of the InO layer in the c-axis direction on the band diagram decreases. Become smaller.

[0096] As mentioned above, the main carrier transmission path is the InO layer. As the thickness of the InO layer in the c-axis direction on the bond diagram decreases, the carriers The carriers are transmitted more evenly through the ab plane of the layer. The metal oxide has a higher mobility because the light is transmitted more linearly to the transistor. By using metal oxide in the channel formation region of the transistor, the frequency characteristics improve as the temperature increases. will improve.

[0097] As mentioned above, the higher the temperature, the more planar the carriers propagate along the ab plane of the InO layer. In other words, in crystalline metal oxides, carriers are scattered by lattice vibrations (so-called It is assumed that phonon scattering is unlikely to occur. By narrowing the channel (also called shortening the channel), the drain electric field becomes stronger, and the carrier drift The improvement in drift velocity due to the shortened channel is due to phonon scattering. However, in crystalline metal oxides, phonon scattering is difficult to occur, The drift velocity increase due to the shortened channel is difficult to suppress. It is expected that metal oxides are less likely to exhibit short channel effects. A transistor using an oxide for a channel formation region can be miniaturized. For example, Either one or both of the channel length and the channel width of the transistor is set to 100n The area can be less than m.

[0098] In this specification, a thin film having a narrow gap is sandwiched between a first layer having a wide gap. The carrier transport along the ab plane of the second layer is called multi-atomic layer conduction (MALT). -Atomic Layers Transport). The material in which T occurs is the second layer with a narrow gap, which is separated from the first layer with a wide gap. The first and second layers are not limited to semiconductor materials sandwiched between layers. Even if the carrier is selectively or preferentially transported to either the first layer or the second layer, The MALT may be generated in a material such as a graphene layer structure. Examples include graphite, which is a

[0099] <Transistor variation 1> 4 is a perspective view of a transistor 10a according to one embodiment of the present invention. In the figure, some elements are omitted for clarity. 4) is a cross-sectional view of a transistor 10a according to one embodiment of the present invention. 1 is a cross-sectional view of the transistor 10a taken along the line A1-A2; 5B is a cross-sectional view of the semiconductor device in the channel length direction. 1 is a cross-sectional view of a transistor 10a in the channel width direction of the transistor 10a. It is also a plan view.

[0100] As shown in FIG. 5A, the transistor 10a is disposed on a substrate (not shown). An insulator 224, an oxide 230b disposed on the insulator 224, and a layer of oxide 230b an oxide 230c disposed on the insulating layer 230c; an insulator 250 disposed on the oxide 230c; and a conductor 260 disposed on the body 250.

[0101] As shown in FIG. 5B, the oxidized layer is formed in the channel width direction of the transistor 10a. The insulating material 230c is provided to cover the top and side surfaces of the oxide 230b. The insulator 250 is formed so as to cover the top and side surfaces of the oxide 230b via the oxide 230c. The conductor 260 is connected to the oxide 230c and the insulator 250 via the oxide 230c. It is provided to cover the top and side surfaces of oxide 230b.

[0102] The insulator 250 functions as a gate insulating film, and the conductor 260 functions as a gate electrode. The oxide 230b also functions as a channel forming region of the transistor 10a. and a region 231 (region 23) that functions as a source region or a drain region. The channel forming region has an oxide 230c. The slits may be formed as follows.

[0103] As shown in FIG. 5B, the transistor 10a has a first layer including an oxide 230b. Each of the second layers is approximately 1000 nm in thickness relative to the surface on which the oxide 230b is formed (the upper surface of the insulator 224). It differs from transistor 10 in that it is arranged vertically. The arrangement direction of the first layer and the second layer of the oxide 230b of a is determined by the surface on which the oxide 230b is formed. It can be said that the transistor 10 differs from the transistor 10 in that it is parallel to the surface. In the transistor 10a, the first and second layers of the oxide 230b are The transistor 10 is arranged in parallel with the channel length direction. The oxide 230b of the substrate 10a is formed by the first and second layers. The oxide 230 of the transistor 10 is substantially perpendicular to the surface of the They have a similar configuration.

[0104] Here, an enlarged view of region 53 of oxide 230b shown in FIG. 5(B) is shown in FIG. 5(C). The oxide 230b shown in FIG. 5(C) is an In-M-Zn oxide having a CAAC structure. do.

[0105] As shown in FIG. 5C, in the oxide 230b of the transistor 10a, CAAC- The c-axis of the crystal of the OS is aligned with the surface on which the oxide 230b is formed or the film surface. Therefore, in FIG. 5B, the CAAC-OS has The c-axis of the crystal is oriented in the left-right direction of the paper. The b-plane is approximately parallel to the normal direction to the surface on which the oxide 230b is formed or the film surface. In other words, the InO layer and the (M,Zn)O layer are arranged approximately perpendicular to the surface on which they are formed. Therefore, in FIG. 5B, the ab plane of the crystal of the CAAC-OS is It is parallel to the vertical direction of the paper and the normal direction of the paper.

[0106] When providing such oxide 230b, for example, a structure is formed on the insulator 224, The oxide 230b is formed on the side surface of the structure, and then the structure is removed. Here, it is preferable that the side surface of the structure is approximately perpendicular to the upper surface of the insulator 224. I wish.

[0107] In addition, in the channel width direction of the transistor 10a, the bottom surface of the insulator 224 is used as a reference. When the oxide 230b is removed, the bottom surface of the conductor 260 in the region that does not overlap with the oxide 230b is covered with the oxide 230. In particular, in the conductor 260, the oxide 230b overlaps the bottom surface of the oxide 230a. The bottom surface of the first region (which can also be called the bottom surface on the A3 side) that does not fold, and the conductor 260 In this case, the bottom surface (A The bottom surface of the oxide 230b is preferably lower than the bottom surface of the oxide 230b. Here, the oxide 230b and the conductor 260 are preferably in a region where they do not overlap. The difference between the height of the bottom surface of the oxide 230b and the height of the bottom surface of the oxide 260 is 0 nm or more and 100 nm or less. or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less Let's say.

[0108] A conductor 260 functioning as a gate electrode is formed on the side of the oxide 230b in the channel forming region. The upper surface is covered with oxide 230c and insulator 250. As shown in Fig. 2B, the electric field of the conductor 260 is easily applied to the entire region 234 of the oxide 230b. In particular, by placing the bottom surface of the conductor 260 below the bottom surface of the oxide 230b, the conductive The electric field of the body 260 can also be applied to the bottom surface of the oxide 230b.

[0109] In this way, in the cross section of the transistor 10a in the channel width direction, the gate is exposed from almost the entire periphery. A gate electric field can be applied to region 234 of oxide 230b. Since a channel can be formed throughout the region 234 of transistor 10a, The on-state current can be increased and the frequency characteristics can be improved. By forming a channel in the entire region 234 of the transistor 10b, the off-current of the transistor 10a It is also possible to reduce it.

[0110] Here, the oxide 230b has a thickness and a length in the channel width direction of several nm to several tens of nm. It is preferable to form such oxide 230b in the form of a long, thin wire. 4 and 5, oxide 230b and oxide 2 30c, the insulator 250, and the conductor 260 can be formed into an elongated wire-like structure. These can also be called nanowires. As shown, the electric field of the conductor 260 can be applied to the entire region 234 of the oxide 230b. Therefore, it can also be called a nanowire transistor.

[0111] The oxide 230b of transistor 10a is The metal oxide layer is rotated by 90 degrees around the axis of the channel length. The transistor 10a is nanowire-like, i.e., conductive across the region 234 of the oxide 230b. By applying an electric field to the conductive material 260, the metal oxide layer is Therefore, the metal oxide 230b is formed on the surface on which the oxide 230b is to be formed. Even if the angles of the oxide layers are different, the transistor 10a and the transistor 10 have the same characteristics. Then it can be considered.

[0112] The oxide 230c contains a metal oxide having a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. Metal oxides with a small difference between the energy of the vacant level and the energy of the bottom of the conduction band may be used. By doing so, the probability that carriers can move to the gate electrode and the gate insulating film is can be reduced.

[0113] In addition, when the oxide 230c has a function of suppressing the diffusion of oxygen, the oxide 230b The oxide 230 can be prevented from diffusing into the gate insulating film or the gate electrode. When oxide 230c has a function of suppressing the diffusion of impurities, the oxide 230c is formed above the oxide 230c. This can prevent impurities from diffusing from the structure into the oxide 230b.

[0114] Although the oxide 230c is illustrated as a single layer in FIGS. 4 and 5, the oxide 230c is A laminated structure may also be used.

[0115] <Transistor variation 2> FIG. 6 shows a transistor 10b as a modification of the transistor 10a. 6(B) is a cross-sectional view of a transistor 10b according to one embodiment of the present invention. FIG. 6(A) is a cross-sectional view of the transistor 10b in the channel length direction. FIG. 2 is a cross-sectional view of a transistor 10b in the channel width direction.

[0116] In addition, in the transistor 10b, the transistor 10 and the transistor 10a are configured The same symbols are used for structures that have the same functions as those of structures that form the same circuit. The constituent materials of transistor 10b are described in detail in transistors 10 and 10a. The materials described in can be used.

[0117] The transistor 10b has an oxide 230b and a conductor 260 overlapping under the insulator 224. The transistor 10 has a conductor 205 overlapping at least a portion of the region. The transistor 10b differs from the transistor 10a in that the oxide There is no compound 230c.

[0118] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a back gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. By changing the voltage applied to the transistor 10b independently of the voltage applied to the transistor 10b, the threshold voltage of the transistor 10b can be In particular, applying a negative potential to the conductor 205 can control the voltage (Vth). This makes it possible to increase the Vth of the transistor 10b and reduce the off-state current. Therefore, applying a negative potential to the conductor 205 is more effective than not applying a negative potential. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0119] The conductor 205 is provided to be larger than the channel forming region in the oxide 230b. In particular, as shown in FIG. 6B, the conductor 205 is formed in the channel of the oxide 230b. It is preferable that the film is stretched also in the region outside the end portion intersecting with the width direction. , the conductor 205 and the conductor 206 are formed on the outer side of the oxide 230 in the channel width direction. 260 is preferably overlapped via an insulator 224 .

[0120] By having the above structure, as shown in FIG. 6(B), The electric field of the conductor 260 and the electric field of the conductor 205, which functions as the second gate electrode, The oxide 230b can electrically surround the channel forming region. This electric field allows a stronger electric field to be applied to the bottom surface of the oxide 230b.

[0121] In this way, in the cross section of the transistor 10b in the channel width direction, the gate is exposed from almost the entire periphery. A gate electric field can be applied to region 234 of oxide 230b. Since a channel can be formed throughout the region 234 of transistor 10b, The on-state current can be increased and the frequency characteristics can be improved. By forming a channel in the entire region 234 of the transistor 10b, the off-current of the transistor 10b is It is also possible to reduce it.

[0122] Similarly to the transistor 10a, the transistor 10b has a conductor 260 and a conductor The electric field of the body 205 can be applied to the entire region 234 of the oxide 230b, They can be called wire or nanowire transistors.

[0123] In this specification and the like, the electric field of the first gate electrode and the second gate electrode The structure of the transistor that electrically surrounds the channel formation region is called the surrounded It can also be called a channel (S-channel) structure.

[0124] <Transistor variation 3> 7 and 8 show a transistor 10c as a modification of the transistor 10a. 7 is a perspective view of a transistor 10c according to one embodiment of the present invention. In order to clarify the figure, some elements are omitted. Also, in Fig. 8(A) and Fig. 8(B), 8A is a cross-sectional view of a transistor 10c according to one embodiment of the present invention. 1-A2 is a cross-sectional view of the transistor 10c; 8B is a cross-sectional view in the channel length direction. 1 is a cross-sectional view of a transistor 10c in the channel width direction of the transistor 10c. It is also a diagram.

[0125] In addition, in the transistor 10c, the transistor 10, the transistor 10a, and The same reference numerals are used to designate structures having the same functions as those constituting the transistor 10b. In this section, the constituent materials of the transistor 10c are the transistor 10, the transistor The materials described in detail for transistor 10a and transistor 10b can be used.

[0126] Transistor 10c has oxide 230a between insulator 224 and oxide 230b. The oxide 230 is different from the transistor 10a in that the oxide 230 is formed on the insulator 224. Oxide 230a, oxide 230b on oxide 230a, and oxide 230b on oxide 230b. 30c and has.

[0127] The oxide 230a is preferably the same as the oxide 230c. For example, The oxide 230a is made of a metal oxide having a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. It is also possible to use a metal oxide having a small difference between the energy of the first gate and the energy of the bottom of the conduction band. By doing so, the probability that carriers can move to the insulator 224 can be reduced.

[0128] The oxide 230a has an upper surface that is at least in a region 234, as shown in FIG. 8(B). It is preferable that the first oxide layer 230b contacts the first oxide layer 230b and the side surface of the first oxide layer 230c contacts the second oxide layer 230c. By doing so, in the region 234, the oxide 230b is separated from the oxide 230a and the oxide 230b. Therefore, the oxide 230b can be covered by the insulating material in the region 234. 224 and the insulator 250. This allows the oxide 230b to This reduces the probability that carriers can move out, and prevents oxygen from diffusing to the outside and from the outside. This can suppress the diffusion of impurities.

[0129] <Transistor Variation 4> 9 is a perspective view of a transistor 10d according to one embodiment of the present invention. In the figure, some elements are omitted for clarity. 10B is a cross-sectional view of a transistor 10d according to one embodiment of the present invention. 10d in the direction indicated by A1-A2 in FIG. 9; 10(B) is also a cross-sectional view of the channel length direction of 10d. 1 is a cross-sectional view of a transistor 10d in the direction shown, showing the channel width of the transistor 10d. It is also a cross-sectional view in the direction.

[0130] In addition, in the transistor 10d, the transistor 10, the transistor 10a, the transistor The structures having the same functions as the structures constituting the transistors 10b and 10c are designated by the same reference numerals. In this section, the constituent materials of the transistor 10d are Transistor 10, transistor 10a, transistor 10b and transistor 10c in detail The materials described in can be used.

[0131] As shown in FIG. 10A, the transistor 10d is disposed on a substrate (not shown). The insulator 224 is formed of an oxide 230b, and the oxide 230b is formed of an oxide 230b. an oxide 230c disposed on the insulating layer 250; and an insulator 250 disposed on the oxide 230c. and a conductor 260 disposed on the edge 250.

[0132] As shown in FIG. 10B, the oxide film is formed in the channel width direction of the transistor 10d. The oxide 230c is provided so as to cover the top and side surfaces of the oxide 230b. The insulator 250 is formed so as to cover the top and side surfaces of the oxide 230b via the oxide 230c. The conductor 260 is provided on the oxide 230c and the insulator 250. , which is provided to cover the top and side surfaces of oxide 230b.

[0133] The insulator 250 functions as a gate insulating film, and the conductor 260 functions as a gate electrode. The oxide 230b also functions as a channel forming region of the transistor 10d. and a region 231 (region 23) that functions as a source region or a drain region. The channel forming region has an oxide 230c. The slits may be formed as follows.

[0134] In addition, in the channel width direction of the transistor 10d, the bottom surface of the insulator 224 is used as a reference. When the oxide 230b is removed, the bottom surface of the conductor 260 in the region that does not overlap with the oxide 230b is covered with the oxide 230. The conductor 260 that functions as a gate electrode is preferably lower than the bottom surface of the channel. The side and top surfaces of the oxide 230b in the hole formation region are covered with the oxide 230c and the insulator 250. By using a structure in which the conductor 260 covers the entire region 234 of the oxide 230b, the electric field of the conductor 260 is generated over the entire region 234 of the oxide 230b. This increases the on-state current of the transistor 10d and improves the frequency characteristics. In the region where the oxide 230b and the conductor 260 do not overlap, The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 10 nm or less. 0 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less m or less.

[0135] At least one of the oxide 230b and the oxide 230c is made of a crystalline metal oxide. Specifically, it is preferable that at least the oxide 230b and the oxide 230c are One of the layers is preferably a single-crystal oxide semiconductor or a CAAC-OS.

[0136] Although the oxide 230b is illustrated as a single layer, it may have a laminated structure. When the oxide 230b has a two-layer laminated structure, the lower layer of the oxide 230b is in contact with the insulator 224, and the oxide The upper layer of the oxide 230b is in contact with the oxide 230c. The impurities are introduced into the oxide 230b from the structure formed below the lower layer of the oxide 230b. Diffusion can be suppressed.

[0137] Here, an enlarged view of the region 54 of the oxide 230b shown in FIG. 10(B) is shown in FIG. 10(D). The region 55 of the oxide 230c shown in FIG. 10(B) is shown in FIG. 10(E). , oxide 230b and oxide 230c are In-M-Zn oxides having a CAAC structure. is.

[0138] As described above, when the oxide 230b is a CAAC-OS, the oxide 230b has The c-axis of the crystal is oriented in the normal direction to the surface on which the oxide 230b is formed or the film surface, and The -b plane is approximately parallel to the surface on which the oxide 230b is formed or the film surface. In the region 54 of the oxide 230b shown in FIG. 10(D), the c-axis of the crystal of the oxide 230b is The direction of the (c-axis) is the vertical direction of the paper. The ab plane is parallel to the left-right direction of the paper and the normal direction to the paper.

[0139] The c-axis of the crystal of the CAAC-OS is approximately perpendicular to the surface on which the CAAC-OS is formed. The ab plane is aligned perpendicularly to the CAAC-OS film surface. When a crystalline metal oxide is used for the oxide 230c, the oxide 23 shown in FIG. In the 0c region 55, the direction of the c-axis of the crystal of the oxide 230c is The ab plane of the crystal of the oxide 230c is the vertical direction of the paper. direction and the normal direction to the paper surface.

[0140] From the above, it is found that the oxide 230b is active on the dashed line X5-X6 in FIG. 10(B). The c-axis direction of the crystals of the oxide 230c is different from the c-axis direction of the crystals of the oxide 230c.

[0141] [Carrier transmission model 2] Here, the oxide 230b and the oxide 230c are stacked in the transistor. Rear transmission will be explained using the carrier transmission model explained above.

[0142] FIG. 10C shows the transistor 10d shown in FIGS. 10A and 10B. , X5-X6. FIG. 10(C) shows the state where a positive potential is applied to the gate electrode. The oxide 230b and the oxide 230c are made of metal oxides having the same conduction band minimum energy. Here is an example.

[0143] On the dashed line X5-X6 shown in FIG. 10(B), inside the oxide 230b, The ab plane of the crystal of the oxide 230b is approximately parallel to the substrate surface. The energy of the conduction band minimum of the oxide 230b on the dashed line indicated by X6 is constant. In addition, inside the oxide 230b, the electric field is oriented in the ab-plane direction of the crystal of the oxide 230b. In addition, the electric field inside the oxide 230b is stronger than that applied to the surface of the oxide 230b. Therefore, the bending of the conduction band minimum inside the oxide 230b is small.

[0144] On the other hand, in the oxide 230c, an electric field is generated in the c-axis direction of the crystal of the oxide 230c. Furthermore, the electric field generated by oxide 230c is greater than the electric field applied inside oxide 230b. Therefore, the band bending in the oxide 230c is large (see the dotted line in FIG. 10(C)). In addition, on the dashed line indicated by X5-X6, the ab plane of the crystal of the oxide 230c is is approximately perpendicular to the substrate surface. Therefore, as shown in FIG. 10(C), On the dashed line, the conduction band minimum of the oxide 230c is different from the conduction band minimum of the InO layer ( The conduction band minimum originating from the (M,Zn)O layers appears alternately.

[0145] At this time, the carriers injected from the source pass through the oxide 230c, which has a lower conduction band edge. Furthermore, carriers are transported between the source and drain. From the above, the main The carrier transmission path is the InO layer of oxide 230b or the InO layer of oxide 230c. become.

[0146] If the carriers are too concentrated, repulsion occurs between them due to Coulomb force, In the case of metal oxides with layered crystals, the As shown in the figure, there are multiple InO layers, which are the main carrier transmission paths, and therefore multiple carriers Therefore, the concentration of carriers is reduced and the carriers are dispersed among the InO layers. Therefore, repulsion due to Coulomb force is unlikely to occur, and carrier transmission is not inhibited.

[0147] The oxide 230c has a metal oxide with a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. Metal oxides with a small difference between the energy of the vacant level and the energy of the bottom of the conduction band may be used. By doing so, the probability that carriers can move to the gate electrode and the gate insulating film is can be reduced.

[0148] 9 and 10, the oxide 230c is illustrated as a single layer, but it may have a laminated structure. For example, when the oxide 230c has a two-layer laminate structure, the lower layer of the oxide 230c is an oxide The upper layer of the oxide 230c is in contact with the insulator 250. The lower layer of the oxide 230c is made of a metal oxide having the same composition as the oxide 230b. The upper layer of 0c is preferably made of a metal oxide having a larger band gap than the oxide 230b. By adopting such a structure, carriers can move to the gate electrode and the gate insulating film. Alternatively, the upper layer of oxide 230c may suppress the diffusion of oxygen. When the oxide 230b and the oxide 230c have a function, the oxide in the lower layer of the oxide 230b and the oxide in the lower layer of the oxide 230c form a gate insulating film. Alternatively, the diffusion of the oxide 230c to the gate electrode can be suppressed. When the layer has a function of suppressing the diffusion of impurities, it is formed above the upper layer of the oxide 230c. The diffusion of impurities from the structure formed by the oxide 230c to the lower layer of the oxide 230b is suppressed. It is possible.

[0149] The above-described examples of the transistor configuration and the modified examples may be appropriately combined with each other. It can be used.

[0150] As described above, a semiconductor device including a transistor with large on-state current can be provided. Furthermore, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, fluctuations in electrical characteristics are suppressed, resulting in stable electrical characteristics and improved reliability. In addition, a semiconductor device having a transistor with low off-state current can be provided. It is possible to provide a semiconductor device.

[0151] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments and examples. It can be used in combination with other methods as appropriate.

[0152] (Embodiment 2) Hereinafter, an example of a specific structure of the semiconductor device described in the above embodiment will be described with reference to FIGS. This will be explained using FIG.

[0153] <Configuration Example 1 of Semiconductor Device> 11A to 11C illustrate a transistor 200 according to one embodiment of the present invention, and 1A and 1B are a top view and a cross-sectional view of a transistor 200 and its surroundings.

[0154] FIG. 11A is a top view of a semiconductor device including a transistor 200. 1(B) and 11(C) are cross-sectional views of the semiconductor device. 11(A) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 11(A), and is a cross-sectional view of the transistor 20 11(A) is also a cross-sectional view of the channel length direction of 0. 4 is a cross-sectional view of the portion indicated by the dashed dotted line in the channel width direction of the transistor 200. In the top view of FIG. 11(A), some elements have been omitted for clarity. do.

[0155] The semiconductor device of one embodiment of the present invention includes a transistor 200 and an insulator serving as an interlayer film. 214, an insulator 280, an insulator 274, and an insulator 281. The conductor 240 (conductor 240a, and conductor 240b). An insulator 241 (insulator 241a and insulator 241b) is provided thereon.

[0156] In addition, the side walls of the openings of the insulators 254, 280, 274, and 281 An insulator 241 is provided in contact with the first conductor of the conductor 240, and the first conductor of the conductor 240 is provided in contact with the side surface of the insulator 241. The second conductor of the conductor 240 is provided further inside. The height of the upper surface of the transistor 200 and the height of the upper surface of the insulator 281 can be made to be approximately the same. In FIG. 00, a first conductor of the conductor 240 and a second conductor of the conductor 240 are stacked. However, the present invention is not limited to this configuration. The structure may be a single layer or a laminated structure of three or more layers. If they have such structures, they may be distinguished by assigning ordinal numbers in the order of their formation.

[0157] [Transistor 200] As shown in FIG. 11, transistor 200 includes an insulating layer disposed on a substrate (not shown). The insulating member 216 is made of a conductive material 205 disposed so as to be embedded in the insulating member 216. 16 and the conductor 205, and an insulator 222 disposed on the insulator 222. and an oxide 230 (oxide 230a, oxide 230b and oxide 230c) and an insulator 25 disposed on the oxide 230. 0, and a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250. b), and conductors 242a and 242b in contact with a portion of the top surface of oxide 230b; A part of the top surface of the insulator 222, a side surface of the insulator 224, a side surface of the oxide 230a, and the oxide 230 the side of conductor 242b, the side of conductor 242a, the top surface of conductor 242a, the side of conductor 242b, and and an insulator 254 disposed in contact with the upper surface of the conductor 242b.

[0158] Conductor 260 functions as the gate electrode of the transistor, and conductors 242a and The body 242b functions as a source electrode or a drain electrode, respectively. In 00, a conductor 260 that functions as a gate electrode is formed on an insulator 280 or the like. The conductor 260 is formed in a self-aligned manner so as to fill the opening. conductor 260 is aligned in the region between conductor 242a and conductor 242b. It can be positioned reliably without any trouble.

[0159] The conductor 260 is made up of a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a has a bottom surface 60b. It is preferable that the casing is arranged so as to wrap around the sides. The upper surface of the conductor 260 is approximately flush with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Note that although the conductor 260 in the transistor 200 has a two-layer structure, However, the present invention is not limited to this. For example, even if the conductor 260 has a single-layer structure, Alternatively, it may have a laminated structure of three or more layers.

[0160] The insulators 222, 254, and 274 are hydrogen (e.g., hydrogen atoms, hydrogen It is preferable that the insulating material has a function of suppressing the diffusion of at least one of molecules. 222, insulator 254, and insulator 274 are oxygen (e.g., oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 , insulator 254, and insulator 274 have higher hydrogen and oxygen content than insulator 224, respectively. Preferably, one or both of the insulators have low permeability. The insulator 274 is more permeable to one or both of hydrogen and oxygen than the insulator 250, respectively. The insulators 222, 254, and 274 are each an insulator It is preferable that the permeability to one or both of hydrogen and oxygen is lower than that of the insulator 280 .

[0161] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b disposed on the insulator 224. and an oxide 230b disposed on the oxide 230b, at least a portion of which is oxide. It is preferable that the oxide 230c is in contact with the upper surface of the oxide 230b. As shown in (C), in the channel width direction of the transistor 200, the oxide 230c It is preferable that the oxide 230b is provided so as to cover the top and side surfaces of the oxide 230b.

[0162] Here, oxide 230, insulator 250, conductor 260, insulator 224, and conductor 2 05 is the transistor 10 or the transistors 10a to 10c shown in the above embodiment. This corresponds to the configuration of the transistor 10d.

[0163] In the transistor 200, a region where a channel is formed (hereinafter, referred to as a channel forming region) ) and in the vicinity thereof, oxide 230a, oxide 230b, and oxide 2 30c are stacked, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230a and oxide 230b, The structure may be a two-layer structure of the material 230b and the oxide 230c, or a laminated structure of four or more layers. In addition, each of the oxide 230a, the oxide 230b, and the oxide 230c may be 2 It may have a laminated structure of more than one layer.

[0164] For example, the oxide 230c may be a multilayer structure consisting of a first oxide and a second oxide on the first oxide. In the case of a layered structure, the first oxide has a composition similar to that of the oxide 230b, and the second oxide has a composition similar to that of the oxide 230c. The oxide of 2 may have a similar composition to oxide 230a.

[0165] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c) are added with a metal oxide (hereinafter It is preferable to use a semiconductor material other than a metal oxide semiconductor (also called an oxide semiconductor).

[0166] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be deposited using a sputtering method or the like, making them suitable for highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0167] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium one or more selected from the group consisting of aluminum, tantalum, tungsten, magnesium, etc. Metal oxides are preferably used. In particular, the element M is aluminum, gallium, yttrium, Alternatively, tin may be used. In addition, the oxide 230 may be an In-Ga oxide or an In-Zn oxide. Alternatively, Ga—Zn oxide or Ga—Zn oxide may be used.

[0168] As described above, the oxide 230 corresponds to the oxide 230 shown in the previous embodiment. The oxide 230 including the channel forming region of the transistor 200 is formed of a crystalline metal oxide. It is preferable to use the crystals of the metal oxide. It is preferable that the first layer and the second layer have a crystal structure in which they are alternately stacked. It is also preferable that the first layer has a wider band gap than the second layer. Examples of crystalline metal oxides include single-crystal oxide semiconductors and CAAC-OS. Crystalline metal oxides can improve carrier transmission. The mobility of the metal oxide is increased, and the on-state current of a transistor using the metal oxide is increased. As a result, the electrical characteristics of the transistor can be improved.

[0169] Furthermore, as described above, at least one of the oxide 230b and the oxide 230c is It is preferable to use a crystalline metal oxide. Specifically, oxide 230b and oxide At least one of 230c is a single-crystal oxide semiconductor or a CAAC-OS. Here, FIG. 11C shows the channel of the transistor 200, similar to FIG. 10B. Therefore, for the region 54 of the oxide 230b shown in FIG. The corresponding region has the crystal structure shown in FIG. 10(D) and the oxide 230c shown in FIG. 10(B). The region corresponding to the region 55 has the crystal structure shown in FIG. Since the model 200 satisfies the schematic band diagram shown in FIG. 10(C), This can prevent rear transmission from being suppressed.

[0170] 11(B), a portion of the oxide 230c is positioned near the interface between the oxide 230c and the insulator 274. It is preferable that the region where the oxide 230 is formed and the channel forming region of the oxide 230 are physically separated from each other. In the vicinity of the interface between the oxide 230c and the insulator 274, the trap state density may be high. Therefore, the region located near the interface between the oxide 230c and the insulator 274 and the oxide The physical distance between the channel forming region of the object 230 and the transistor 200 is increased. Fluctuations in characteristics can be suppressed and reliability can be improved.

[0171] In addition, a transistor using an oxide semiconductor has an insufficient region in a channel formation region of the oxide semiconductor. The presence of impurities and oxygen vacancies can cause fluctuations in electrical characteristics and reduce reliability. Furthermore, if oxygen vacancies are present in the channel formation region of an oxide semiconductor, Therefore, oxygen vacancies in the channel formation region are unlikely to occur. For example, the oxide 230c or the insulator 250 is preferably as small as possible. Oxygen can be supplied to the oxide 230 via the electrode or the like to compensate for the oxygen deficiency. Transistors that suppress fluctuations in characteristics, have stable electrical characteristics, and have improved reliability. A star can be provided.

[0172] Also, the oxide 230 is provided on the substrate 230 so as to be in contact with the oxide 230, and functions as a source electrode and a drain electrode. The elements contained in the conductor 242 (conductor 242a and conductor 242b) are oxides. When the oxide 230 has a function of absorbing oxygen, the oxide 230 is formed between the conductor 242 or between the oxide 230 and the conductor 242. In some cases, a low resistance region may be formed in part near the surface of the oxide 230. In the low resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered oxygen vacancies act as donors. This may function as a carrier to increase the carrier density.

[0173] 11B is an enlarged view of a part of the transistor 200 shown in FIG. 12A. As shown in FIG. 12A, a conductor 242 is provided on and in contact with the oxide 230. The oxide 230 has a low resistance region at the interface with the conductor 242 and its vicinity. 243 (region 243a and region 243b) may be formed. , a region 234 which functions as a channel formation region of the transistor 200 and a small region 243 and a region 231 (region 2) that functions as a source region or a drain region. 31a, and region 231b). Even when the region 243 is not shown, a similar region 243 may be formed.

[0174] The region 243a and the region 243b are formed in the vicinity of the conductor 242 of the oxide 230b. In this example, the electrons are diffused in the depth direction, but the present invention is not limited to this. The regions 243a and 243b are appropriately selected according to the desired electrical characteristics of the transistor. Furthermore, in the oxide 230, the boundaries of the respective regions can be clearly detected. The concentrations of elements detected within each region are not limited to gradual changes from region to region. Furthermore, the color may change continuously (also called gradation) within each region.

[0175] As shown in FIG. 11B, the insulator 254 is formed between the conductor 242a and the conductor 24 conductor 242a and the conductor 242b, and the conductors other than the upper surface of conductor 242a and the side surfaces of conductor 242b facing each other. The side surfaces of the conductive body 242a and the conductive body 242b and the side surfaces of the oxide 230a and the oxide 230b are It is preferable that the surface of the insulating member 224 contacts the insulating member 222, the side surface of the insulating member 224, and a part of the upper surface of the insulating member 222. As a result, the insulator 280 is formed by the insulator 254, the insulator 224, the oxide 230a, and oxide 230b. Therefore, hydrogen and the like contained in insulator 280 and the like impurities from being mixed into the insulator 224, the oxide 230a, and the oxide 230b. It is possible.

[0176] The insulator 274 is formed on each of the conductor 260, the insulator 250, and the oxide 230c. The transistor 200 of one embodiment of the present invention is in contact with the surface as shown in FIG. As shown, the insulator 274 and the insulator 250 are in contact with each other. By doing so, impurities such as hydrogen contained in the insulator 281 etc. are prevented from being mixed into the insulator 250. Therefore, the electrical characteristics and signal quality of the transistor can be improved. This can suppress the adverse effects on reliability.

[0177] 12(A), the bottom surface of the insulator 224 is used as a reference, and the area overlapping the area 234 is The height of the bottom surface of the conductor 260 in the region is the height of the conductor 242a and the conductor 242b. For example, the height of the upper surface of the area overlapping with the area 234 may be lower than the height of the upper surface of the area overlapping with the area 234. The height of the bottom surface of the conductor 260 and the height of the top surfaces of the conductors 242a and 242b are The difference in height between the first and second electrodes is 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less.

[0178] 11C is an enlarged view of a part of the transistor 200 shown in FIG. 12B. As in the previous embodiment, the insulating layer 201 is formed in the channel width direction of the transistor 200. The area where the conductor 260 and the oxide 230b do not overlap is determined based on the bottom surface of the body 222. Preferably, the height of the bottom surface of the conductor 260 is lower than the height of the bottom surface of the oxide 230b. A conductor 260 functioning as a gate electrode is formed on the side and the oxide 230b of the channel forming region. The upper surface of the conductive material 2 is covered with the oxide 230c and the insulator 250. 60 to the entire region 234 of the oxide 230b. The oxide 230 can increase the on-current of the gate 200 and improve the frequency characteristics. a and oxide 230b, and conductor 260 in the region where they do not overlap. If the difference between the height of the bottom surface and the height of the bottom surface of the oxide 230b is T2, T2 is 0 nm or less. At most 100 nm, preferably 3 nm to 50 nm, more preferably 5 nm or more It should be 20nm or less.

[0179] 12B, in the channel width direction of the transistor 200, The oxide 230c in the region that does not overlap with the insulator 224 is the oxide 230b, the oxide 230a, and the insulator 224. It is preferable that at least a part of the insulating material 222 is in contact with the insulating material 222. The oxygen contained in the oxide 230c passes through the insulator 224 and reaches the outside of the transistor 200. In addition, the oxide 230b and the oxide 230a can be prevented from diffusing. Preventing oxygen from diffusing through the insulator 224 to the outside of the transistor 200 In addition, the area of ​​the insulator 224 is reduced, and therefore the amount of oxygen taken up by the insulator 224 is reduced. The amount of oxygen supplied to the oxide 230 can be reduced. The oxygen contained in the oxide 230c is efficiently converted into the oxide 230b and the oxide 230a. Therefore, the resistance of the oxide 230 in the region 234 can be prevented from decreasing. Therefore, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the electrical characteristics can be stabilized. At the same time, reliability can be improved.

[0180] In addition, by adopting the above-mentioned configuration, impurities such as hydrogen contained in the insulator 224 are oxidized. In other words, the oxide 230 is prevented from being mixed in the substance 230. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and stable electrical characteristics can be obtained. The structure has the oxide 230 and can improve reliability. b, and removing the insulator 224 in areas that do not overlap with the oxide 230a. It is possible.

[0181] Also, the oxide 230b and the insulator 224 in the area not overlapping with the oxide 230a are removed. As a result, as shown in FIG. 12B, in the channel width direction of the transistor 200, , with the bottom surface of the insulator 222 as a reference, the oxide 230a and the oxide 230b, and the conductor 2 The height of the bottom surface of the conductor 260 in the region where the oxide 230b does not overlap with the conductor 260 is Therefore, the on-current of the transistor 200 is increased. , the frequency characteristics can be improved.

[0182] As described above, a semiconductor device including a transistor with large on-state current can be provided. Furthermore, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, fluctuations in electrical characteristics are suppressed, resulting in stable electrical characteristics and improved reliability. In addition, a semiconductor device having a transistor with low off-state current can be provided. It is possible to provide a semiconductor device.

[0183] The following describes in detail the configuration of a semiconductor device including a transistor 200 according to one embodiment of the present invention. This article explains:

[0184] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. The conductor 205 is preferably embedded in the insulators 214 and 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, The average surface roughness (Ra) of the upper surface of 205 is 1 nm or less, preferably 0.5 nm or less, more preferably This allows the insulating layer formed on the conductor 205 to be 224, and the oxide 230a, the oxide 230b, and the oxide 230c are formed. The crystallinity can be improved.

[0185] Here, the conductor 260 functions as a first gate (also called a top gate) electrode. The conductor 205 may also serve as a second gate (also called a back gate) electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. By changing the threshold voltage of the transistor 200 independently of the applied voltage, In particular, applying a negative potential to the conductor 205 can control the voltage (Vth). This makes it possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 is more effective than not applying a negative potential. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0186] As shown in FIG. 11(A), the conductor 205 is a channel-type oxide 230. In particular, as shown in FIG. 11(C), the conductor 205 The oxide 230 also extends beyond the end portion intersecting with the channel width direction. That is, it is preferable that the oxide 230 is formed on the outer side of the side surface in the channel width direction. It is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator.

[0187] With the above configuration, the electric field of the conductor 260 functioning as the first gate electrode and the The electric field of the conductor 205, which acts as the gate electrode of the semiconductor 2, causes the channel shape of the oxide 230 to change. The composite region can be electrically surrounded.

[0188] As shown in FIG. 11(C), the conductor 205 is extended to function as a wiring. However, the present invention is not limited to this, and a conductive material that functions as a wiring may be provided under the conductive material 205. The conductor 205 does not necessarily have to be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors. That's fine.

[0189] The conductor 205 is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a single layer, it may be a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0190] Also, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitric oxide are present under the conductor 205. It has the function of suppressing the diffusion of impurities such as elementary molecules (N2O, NO, NO2, etc.) and copper atoms. Alternatively, a conductor that is impervious to the impurities may be provided. The film has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc. (the film has a function of suppressing the diffusion of at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to provide a conductor. The function of suppressing the diffusion of oxygen is to suppress either one or all of the above impurities or the above oxygen. This function is to suppress the spread of

[0191] By using a conductor having a function of suppressing oxygen diffusion under the conductor 205, It is possible to prevent the conductor 205 from being oxidized and the conductivity from decreasing. Examples of conductive materials having a controlling function include tantalum, tantalum nitride, ruthenium, and It is preferable to use ruthenium oxide or the like for the conductive layer 205. In general, the conductive material may be a single layer or a multilayer.

[0192] The conductor 205 can be formed by sputtering, chemical vapor deposition (CVD), or the like. Vapor Deposition (Vapor Deposition), Molecular Beam Epitaxy (MBE) Microbeam Epitaxy (Pulse Laser Deposition (PLD) d Laser Deposition) method or Atomic Layer Deposition (ALD) method This can be done using a method such as Layer Deposition.

[0193] In this embodiment, the conductor 205 is made of, for example, tantalum nitride, titanium nitride, tungsten, or the like. A laminated film in which a conductive film is formed in that order can be used.

[0194] The insulator 214 disposed on the substrate (not shown) prevents impurities such as water and hydrogen from entering the substrate. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion from the side into the transistor 200. Therefore, the insulator 214 is preferably a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or the like. Suppresses the diffusion of impurities such as nitrogen oxide molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use an insulating material that has the function of preventing the impurities from penetrating. has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). It is preferable to use an insulating material that is permeable to oxygen (the above-mentioned oxygen is less likely to permeate).

[0195] For example, the insulator 214 is preferably made of aluminum oxide, silicon nitride, or the like. This allows impurities such as water and hydrogen to flow from the substrate side to the transistor rather than the insulator 214. Diffusion to the insulator 200 side can be suppressed. This can prevent oxygen from diffusing toward the substrate side of the insulator 214.

[0196] The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 214 is, for example, Alternatively, aluminum oxide formed by sputtering can be used.

[0197] The insulator 216 disposed on the insulator 214 functions as an interlayer film. The insulator 280 and the insulator 281 disposed on the insulating layer 54 also function as interlayer films. Here, the insulators 216, 280, and 281 functioning as interlayer films are It is preferable that the dielectric constant is lower than that of the insulator 214. For example, the insulator 216 and the insulator 217 can reduce the parasitic capacitance between the wirings. 80, and as the insulator 281, silicon oxide, silicon oxynitride, silicon nitride oxide , silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and Silicon oxide doped with nitrogen, silicon oxide having vacancies, or the like may be used as appropriate.

[0198] The insulator 216 may have a laminated structure. In any case, an insulator similar to the insulator 214 is provided at the portion in contact with the side surface of the conductor 205. With this configuration, the oxygen contained in the insulator 216 can The conductor 205 can prevent the insulator 21 from being oxidized. 6 can be prevented from absorbing oxygen.

[0199] The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 216 is, for example, Alternatively, a silicon oxynitride film formed by a CVD method can be used.

[0200] The insulator 222 and the insulator 224 function as gate insulators.

[0201] Here, it is preferable that the insulator 224 in contact with the oxide 230 releases oxygen by heating. In this specification, the oxygen released by heating may be referred to as excess oxygen. For example, The insulator 224 may be made of silicon oxide, silicon oxynitride, or the like as appropriate. By providing an insulator in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced, The reliability of the transistor 200 can be improved.

[0202] Specifically, an oxide film from which part of the oxygen is released by heating is used as the insulator 224. The oxide film that releases oxygen by heating is preferably a TDS (Thermal Desiccant) film. The desorption of oxygen in terms of oxygen atoms was analyzed by O2 desorption spectroscopy (O2 desorption spectroscopy). The separation is 1.0 x 10 18 atoms / cm 3 or more, preferably 1.0 × 10 19 atom s / cm 3 More preferably, 2.0 × 10 19 atoms / cm 3 or more, or 3 .0×10 20 atoms / cm 3 The oxide film is as above. The surface temperature of the film is 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower. The lower range is preferred.

[0203] The insulator 224 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 224 is, for example, Silicon oxynitride film formed by CVD can be used. In the transistor 200 shown in FIG. 1, the insulator 224 is configured to have an island shape. For example, the insulator 224 may cover the entire surface of the insulator 222. It can also be made into a

[0204] The insulator 222 prevents impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side. For example, the insulator 222 is preferably an insulating material. It is preferable that the hydrogen permeability is lower than that of the insulator 224. Therefore, by surrounding the insulator 224, oxide 230, etc., impurities such as water and hydrogen are Diffusion from the outside into the insulator 224 and the oxide 230 can be suppressed.

[0205] Furthermore, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). The insulator 222 preferably has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of atoms and impurities, so that the oxygen contained in the oxide 230 is In addition, the conductor 205 is preferably made of an insulator 224 or This can prevent the oxide 230 from reacting with oxygen.

[0206] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The diffusion of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230 is prevented. The insulator 222 functions as a layer that suppresses the electric field. Hafnium oxide is preferably used. For example, the insulator 222 is used as a gate insulating film. In this case, by using hafnium oxide for the insulator 222, the interface is more stable than with aluminum oxide. The level density can be reduced in some cases.

[0207] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride or silicon nitride may be laminated on the insulator. .

[0208] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT These include so-called high-k materials such as (Ba,Sr)TiO3 or (Ba,Sr)TiO3 (BST). As miniaturization and high integration of transistors progress, If the gate insulator is made thinner, problems such as leakage current may occur. By using a high-k material as an insulator, the physical thickness can be maintained. This makes it possible to reduce the gate potential during transistor operation.

[0209] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 222 is, for example, Alternatively, hafnium oxide formed by ALD can be used.

[0210] As shown in FIG. 11C, the insulator 222 is formed in a region where it does not overlap with the oxide 230b. In some cases, the thickness of the oxide film in the insulator 222 may be thinner than that of the other regions. The thickness of the region not overlapping with the object 230b is determined when forming an opening in the insulator 280 or the like. , the thickness of which can function as an etching stopper film, or which can function as an insulator 216 or a conductive film. It is preferable that the film thickness is sufficient so that the surface of the conductive material 205 is not exposed.

[0211] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. For example, an insulator similar to the insulator 224 may be provided below the insulator 222. stomach.

[0212] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from structures formed above oxide 230c into oxide 230b can be suppressed.

[0213] The oxide 230 has a layered structure made of oxides with different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the constituent elements are preferably The atomic ratio of element M in the oxide 230b is It is preferable that the atomic ratio of the metal oxide used for the oxide 230a is larger than that of the element M. In the oxide 230b, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxide used, the atomic ratio of In to the element M is It is preferable that the atomic ratio of In to the element M in the metal oxide is larger than that of In. Oxide 230c is a metal oxide that can be used for oxide 230a or oxide 230b. Things can be used.

[0214] Moreover, it is preferable that the oxide 230b and the oxide 230c have crystallinity. For example, it is preferable to use CAAC-OS, which will be described later. The oxides used have few impurities and defects (oxygen vacancies, etc.), high crystallinity, and a dense structure. Therefore, the oxygen from the oxide 230b by the source electrode or the drain electrode This can prevent the oxide 230b from being pulled out even when heat treatment is performed. Since oxygen extraction can be reduced, the transistor 200 can be fabricated with high efficiency. It is stable over a wide temperature range (the so-called thermal budget).

[0215] In addition, the conduction band minimums of the oxides 230a and 230c are greater than the conduction band minimum of the oxide 230b. It is preferable that the oxide 230a and the oxide 230b are closer to the vacuum level than the lower end. Preferably, the electron affinity of the oxide 230c is smaller than the electron affinity of the oxide 230b. In this case, the oxide 230c uses a metal oxide that can be used for the oxide 230a. Specifically, in the metal oxide used for the oxide 230c, it is preferable that the constituent elements The atomic ratio of element M is the atomic ratio of element M in the constituent elements of the metal oxide used for oxide 230b. It is preferable that the atomic ratio of M is larger than that of M. In addition, the metal oxide used for the oxide 230c is In the metal oxide used for the oxide 230b, the atomic ratio of the element M to In is It is preferable that the atomic ratio of element M to In is larger than that of element M. In the metal oxides used, the atomic ratio of In to element M is It is preferable that the atomic ratio of In to M in the metal oxide is larger than that of In.

[0216] Also, the oxide 230c is formed on the oxide 230c1 and the oxide 23 on the oxide 230c1. In the case of a stacked structure including oxide 230a and oxide 230c2, the conduction band The edge is preferably closer to the vacuum level than the lower edge of the conduction band of the oxide 230b and the oxide 230c1. In other words, the electron affinity of the oxide 230a and the oxide 230c2 is preferably It is preferable that the electron affinity is smaller than that of the oxide 230b and the oxide 230c1. In this case, the oxide 230c2 is made of a metal oxide that can be used for the oxide 230a. The material 230c1 is preferably a metal oxide that can be used for the oxide 230b. stomach.

[0217] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and the The conduction band edge at the junction of the oxide 230c and the silicon dioxide 230c changes continuously or is called a continuous junction. In order to achieve this, the interface between the oxide 230a and the oxide 230b , and the defect levels of the mixed layer formed at the interface between oxide 230b and oxide 230c. It is better to lower the density.

[0218] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen (as the main component), a mixed layer with low defect level density can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide The oxide 230a and the oxide 230c include In-Ga-Zn oxide, Ga-Zn oxide, Gallium oxide may also be used. In the case of forming a laminated structure with 230c2, for example, In-Ga-Zn oxide and the In-G Layered structure of Ga-Zn oxide on a-Zn oxide, or In-Ga-Zn oxide, A laminated structure of gallium oxide on the In-Ga-Zn oxide can be used. Then, the laminated structure of the In-Ga-Zn oxide and the oxide not containing In was formed as oxide 23 It may also be used as 0c.

[0219] Specifically, the oxide 230a is composed of In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide with an atomic ratio of In:Ga:Zn=1:1:0.5 may be used. , as oxide 230b, In:Ga:Zn=4:2:3 [atomic ratio], or In:G A metal oxide having an atomic ratio of Al:Zn=3:1:2 may be used. As the atomic ratio, In:Ga:Zn=1:3:4, In:Ga:Zn=4:2:3 atomic ratio], Ga:Zn=2:1 [atomic ratio], or Ga:Zn=2:5 [atomic ratio] In addition, as a specific example of the case where the oxide 230c has a laminated structure, The atomic ratios are In:Ga:Zn=4:2:3 and In:Ga:Zn=1:3:4. In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn= 2:1 [atomic ratio], In:Ga:Zn=4:2:3 [atomic ratio], and Ga :Zn=2:5[atomic ratio], In:Ga:Zn=4:2:3[atomic ratio] and a laminated structure with gallium oxide.

[0220] At this time, the main path of the carriers is the oxide 230b or the oxide 230c. Alternatively, the oxide 230c may have a stacked structure including the oxide 230c1 and the oxide 230c2. In this case, not only the oxide 230b but also the oxide 230c1 becomes the main path of the carriers. By configuring the oxide 230a and the oxide 230c as described above, the oxide 23 At the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c Therefore, the influence of interface scattering on carrier conduction can be reduced. The transistor 200 has a high on-state current and high frequency characteristics. When the oxide 230c has a laminated structure, the oxide 230b and the oxide 230c can be laminated. In addition to the effect of reducing the defect level density at the interface with the oxide 230c, It is expected that the diffusion of the constituent elements of the insulating material 250 to the insulating material 250 side can be suppressed. The oxide 230c has a laminated structure, and an oxide not containing In is positioned above the laminated structure. Therefore, it is possible to suppress the diffusion of In into the insulator 250. Because it functions as a gate insulator, if In gets mixed into the insulator 250, etc., the transistor Therefore, by forming the oxide 230c into a laminated structure, it is possible to improve reliability. It is therefore possible to provide a semiconductor device with a high resistance.

[0221] The oxide 230 is preferably a metal oxide that functions as a semiconductor. For example, The metal oxide for the region 234 has a band gap of 2 eV or more, preferably 2.5 eV or more. It is preferable to use a metal oxide having a large band gap of at least 100 eV. By using such a material, the off-state current of the transistor can be reduced. By using a resistor, a semiconductor device with low power consumption can be provided.

[0222] The oxide 230a, the oxide 230b, and the oxide 230c are formed by sputtering. This can be done by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. When forming a film by sputtering, oxygen or It is preferable to use a mixed gas of nitrogen and rare gas. This can improve the crystallinity of the oxide film.

[0223] In this embodiment, the oxide 230a is, for example, In:Ga:Zn=1:3:4[ The film was formed by sputtering using an In-Ga-Zn oxide target with a [atomic ratio]. The oxide 230b may be, for example, In: Using an In-Ga-Zn oxide target with an atomic ratio of Ga:Zn = 4:2:4.1 Metal oxides formed by sputtering can be used. For example, In-Ga with an atomic ratio of In:Ga:Zn=4:2:4.1 is used as 30c1. -Metal oxide film formed by sputtering using a Zn oxide target The oxide 230c2 may be, for example, In:Ga:Zn=1:3: 4 [atomic ratio] In-Ga-Zn oxide target was used for sputtering. A deposited metal oxide can be used.

[0224] On the oxide 230b, a conductor 242 is formed, which functions as a source electrode and a drain electrode. The thickness of the conductor 242 is, for example, For example, it may be 1 nm or more and 50 nm or less, and preferably 2 nm or more and 25 nm or less.

[0225] The conductor 242 may be aluminum, chromium, copper, silver, gold, platinum, tantalum, or nickel. Titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, Magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from rontium and lanthanum, or an alloy containing the above metal elements Alternatively, it is preferable to use an alloy of the above-mentioned metal elements. tantalum, titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum, an oxide containing lanthanum and nickel, or the like. Tantalum oxide, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Nitrides containing strontium, ruthenium oxide, ruthenium nitride, and oxides containing strontium and ruthenium The oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. This is preferable because it is a material that maintains its conductivity even when absorbed.

[0226] The conductor 242 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the conductor 242 is, for example, Alternatively, tantalum nitride formed by sputtering can be used.

[0227] The insulator 254, like the insulator 214, is a material that prevents impurities such as water and hydrogen from penetrating the insulator 280. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion from the side into the transistor 200. For example, it is preferable that the insulator 254 has a lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIG. 11(B), the insulator 254 is disposed on the upper and side surfaces of the conductor 242a. , the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, It is preferable that the insulating material 224 contacts the side surface of the insulating material 224. 280 is separated from the insulator 224 and the oxide 230 by the insulator 254 As a result, the hydrogen contained in the insulator 280 is transferred to the conductor 242a, the conductor 242b, and the oxide. The oxide 230 extends from the top or sides of the insulator 224 to the oxide 230. Therefore, the transistor 200 has good electrical characteristics and reliability. can give sex.

[0228] Furthermore, the insulator 254 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). Preferably, the rim 254 has a lower oxygen permeability than the insulator 280 or the insulator 224 .

[0229] The insulator 254 is preferably formed by sputtering. The insulating film of the insulator 224 is formed by sputtering in an atmosphere containing oxygen. Oxygen can be added to the area adjacent to the body 254. This allows oxygen to be released from the area. Oxygen can be supplied to the oxide 230 through the insulator 224. 54 has the function of suppressing the upward diffusion of oxygen, and oxygen is isolated from the oxide 230. The insulator 222 can prevent oxygen from diffusing downward. By having the function of suppressing diffusion, it is possible to prevent oxygen from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel forming region of the oxide 230. This reduces the oxygen vacancy in the oxide 230 and prevents the transistor from becoming normally on. It can be controlled.

[0230] The insulator 254 may be, for example, an oxide of one or both of aluminum and hafnium. It is preferable to form an insulator containing an oxide of aluminum or hafnium. Insulators containing both oxides include aluminum oxide, hafnium oxide, and aluminum and It is preferable to use oxides containing hafnium (hafnium aluminate) and the like. In this case, the insulator 254 is preferably deposited using an ALD method. Since this is a film forming method with good coating properties, unevenness of the insulator 254 does not cause discontinuities. This can be prevented.

[0231] In this way, the insulator 254 having a barrier property against hydrogen prevents the insulator 224 and By covering the insulator 224 and the oxide 230, the insulator 280 is insulated from the insulator 224 and the oxide 230. This prevents impurities such as hydrogen from entering the transistor 200 from the outside. This can prevent the transistor 200 from becoming unstable, thereby providing the transistor 200 with good electrical characteristics and reliability. It is possible.

[0232] The insulator 254 may be, for example, an insulator containing aluminum nitride. The insulator 254 has a composition formula of AlNx (x is a real number greater than 0 and less than or equal to 2, preferably It is preferable to use a nitride insulator that satisfies the following condition: x is a real number greater than 0.5 and less than or equal to 1.5. This allows the film to have excellent insulation and thermal conductivity, This can improve the heat dissipation performance of the heat generated when the transistor 200 is driven. Aluminum titanium nitride, titanium nitride, etc. can also be used as 254. In this case, by forming the film using the sputtering method, oxidizing gas such as oxygen or ozone is used in the film formation gas. This is preferable because it allows film formation without using highly reactive gases. Silicon nitride oxide or the like can also be used.

[0233] The insulator 254 may have a multi-layer structure of two or more layers. 4, the first layer is formed using the sputtering method in an oxygen-containing atmosphere, and then the second layer is formed using the ALD method. The ALD method is a film formation method with good coating properties. Therefore, it is possible to prevent the formation of discontinuities due to the unevenness of the first layer. When the edge 254 has a multi-layer structure of two or more layers, the multi-layer structure may be made of different materials. For example, silicon oxide, silicon oxynitride, silicon nitride oxide or silicon nitride, As a laminated structure with an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen In addition, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, For example, an insulator containing oxides of one or both of aluminum and hafnium is used. It is possible.

[0234] The insulator 250 functions as a gate insulator. The insulator 250 is preferably made of silicon oxide or silicon oxynitride. , silicon oxynitride, silicon nitride, silicon oxide with fluorine addition, carbon-added oxide silicon oxide, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, etc. In particular, silicon oxide and silicon oxynitride are stable to heat. This is preferable.

[0235] The insulator 250 is made of an insulator that releases oxygen when heated, similar to the insulator 224. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing the oxide 230c in contact with the upper surface thereof, the region 234 of the oxide 230b is effectively In addition, like the insulator 224, the water in the insulator 250 can be supplied with oxygen. It is preferable that the concentration of impurities such as silicon is reduced. It is preferable that the upper limit is 20 nm or less.

[0236] The insulator 250 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done using an LD method or the like. In this embodiment, the insulator 250 is, for example, Alternatively, a silicon oxynitride film formed by a CVD method can be used.

[0237] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 can be suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0238] The metal oxide may function as a part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, It is preferable to use a metal oxide, which is a high-k material with a high relative dielectric constant. By making the insulation layer of the insulation layer 250 and the metal oxide, it is possible to improve the thermal stability. Therefore, the physical properties of the gate insulator can be improved. It is possible to reduce the gate potential applied during transistor operation while maintaining the film thickness. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. do.

[0239] The metal oxide may also function as a part of the first gate. For example, The oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In this case, the conductor 260 is formed by sputtering, and the metal oxide This is called OC (Oxide Carbon Dioxide). The electrode can be called a conductor.

[0240] By including the metal oxide, the influence of the electric field from the conductor 260 is not weakened. This can improve the on-current of the transistor 200. The physical thickness of the metal oxide maintains the distance between the conductor 260 and the oxide 230. This makes it possible to suppress leakage current between the conductor 260 and the oxide 230. By providing a laminated structure of the insulator 250 and the metal oxide, the conductor 260 and the oxide the physical distance between the conductor 260 and the oxide 230, and the electric field strength from the conductor 260 to the oxide 230. can be easily adjusted appropriately.

[0241] Specifically, hafnium, aluminum, gallium, yttrium, zirconium, selected from tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. Metal oxides containing one or more of these metals can be used. aluminum oxide, which is an insulator containing oxides of one or both of aluminum and hafnium; Hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate ) is preferably used. By lowering the resistance of the metal oxide, it can be used as the metal oxide.

[0242] Although the conductor 260 is shown as having a two-layer structure in FIG. 11, it may have a single-layer structure or a three-layer structure. The above laminated structure may also be used.

[0243] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. (N2O, NO, NO2, etc.), conductive material with the function of suppressing the diffusion of impurities such as copper atoms It is preferable to use a material containing a small amount of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material that has the function of suppressing the diffusion of at least (i).

[0244] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can prevent the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum and nitride. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0245] In addition, since the conductor 260 also functions as wiring, a conductor with high conductivity should be used. For example, the conductor 260b is preferably made primarily of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure. For example, a laminated structure of titanium, titanium nitride and the above conductive material may be used.

[0246] The conductor 260 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the conductor 260a is, for example, For example, titanium nitride film formed by CVD is used, and the conductor 260b is made of, for example, C. Titanium nitride film formed by the VD method can be used.

[0247] The insulator 280 is connected to the insulator 222, the insulator 224, the oxide 230 through the insulator 254. and the conductor 242. For example, the insulator 280 may be silicon oxide, oxide, or the like. Silicon nitride, silicon oxide nitride, silicon oxide with fluorine addition, and carbon-added oxide silicon oxide, silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, etc. In particular, silicon oxide and silicon oxynitride are thermally stable. In particular, silicon oxide, silicon oxynitride, silicon oxide having vacancies, etc. These materials are preferred because they can easily form regions containing oxygen that is desorbed by heating. It's nice.

[0248] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. The top surface of the insulator 280 may be planarized.

[0249] The insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done using an LD method or the like. In this embodiment, the insulator 280 is, for example, Alternatively, a silicon oxynitride film formed by a CVD method can be used.

[0250] The insulator 274, like the insulator 214, prevents impurities such as water and hydrogen from entering from above. It is preferable that the insulator 2 functions as a barrier insulating film that suppresses diffusion into the insulator 280. As 74, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. is used. That's good enough.

[0251] The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 274 is, for example, Alternatively, aluminum oxide formed by sputtering can be used.

[0252] In addition, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. The insulator 281, like the insulator 224, has a low concentration of impurities such as water and hydrogen in the film. It is preferable that it is reduced.

[0253] The insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, or the like. This can be done by using an LD method or the like. In this embodiment, the insulator 281 is, for example, Alternatively, silicon nitride formed by CVD can be used.

[0254] Also, the insulating material 281, the insulating material 274, the insulating material 280, and the insulating material 254 are formed. The conductor 240a and the conductor 240b are placed in the opening. 240b are provided facing each other with the conductor 260 in between. The height of the upper surface of 240b may be flush with the upper surface of the insulator 281.

[0255] The side walls of the openings of the insulators 281, 274, 280, and 254 The insulator 241a is provided in contact with the first conductor of the conductor 240a. A conductor 242a is located at least partially on the bottom of the opening. , the conductor 240a contacts the conductor 242a. Similarly, the insulator 281, the insulator 274, the insulator An insulator 241b is provided in contact with the edge 280 and the side wall of the opening of the insulator 254, and The first conductor of the conductor 240b is formed in contact with the side surface of the opening. The conductor 242b is located at least in a part of the area where the conductor 240b is in contact with the conductor 242b. do.

[0256] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing the conductive material 240a and the conductive material 240b. 0b may have a laminated structure.

[0257] In addition, when the conductor 240 has a laminated structure, the oxide 230a, the oxide 230b, the conductor 242, insulator 254, insulator 280, insulator 274, and conductive material in contact with insulator 281. The body can be made of conductive materials that have the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, It is preferable to use ruthenium or the like. In addition, it is preferable to use a material that has a function of suppressing the permeation of impurities such as water and hydrogen. The conductive material having the function may be used in a single layer or a multilayer structure. The oxygen added to the insulator 280 is absorbed by the conductors 240a and 240b. In addition, impurities such as water and hydrogen contained in the layer above the insulator 281 can be prevented. is prevented from diffusing into the oxide 230 through the conductor 240a and the conductor 240b. It is possible.

[0258] The insulators 241a and 241b may be used, for example, as the insulator 254. The insulator 241a and the insulator 241b are made of an insulator 254. Since the insulator 280 is provided in contact with the conductor, impurities such as water and hydrogen contained in the insulator 280 can be easily absorbed by the conductor. 240a and the conductor 240b, the diffusion of the oxide 230 can be suppressed. In addition, oxygen contained in the insulator 280 is absorbed into the conductors 240a and 240b. It should be noted that the insulators 241a and 241b are formed by A The LD method or the CVD method can be used.

[0259] Although not shown, the conductive material 240a and the conductive material 240b are arranged in contact with each other on their upper surfaces. A conductor functioning as a wire may be disposed. The conductor functioning as a wiring may be made of tungsten. It is preferable to use a conductive material containing copper or aluminum as a main component. The conductor may have a laminated structure, for example, a layer of titanium, titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in the insulator. You may do so.

[0260] Although not shown, a thin film having a resistivity of 1.0×10 13 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more 5.0×10 14 It is preferable to provide an insulator having a resistivity of Ωcm or less on the conductor. By providing an insulator, the insulator can maintain insulation properties while The charge accumulated between the wiring of the conductor is dispersed, and the transistor and the transistor This is preferable because it can suppress the deterioration of characteristics and electrostatic breakdown of electronic devices having a transistor.

[0261] As described above, one embodiment of the present invention can provide a semiconductor device with large on-state current. According to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. According to one embodiment of the present invention, a semiconductor device with high productivity can be provided. It is possible.

[0262] <Materials for semiconductor devices> The following describes constituent materials that can be used in semiconductor devices.

[0263] The following materials are deposited by sputtering, CVD, MBE, PLD, and A This can be done using the LD method or the like.

[0264] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0265] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can suppress plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage does not occur. In addition, the thermal CVD method does not require the use of a metal oxide film, which increases the yield of semiconductor devices. Since no plasma damage occurs inside the film, a film with few defects can be obtained.

[0266] The ALD method is also a film formation method that can suppress plasma damage to the workpiece. Therefore, a film with few defects can be obtained. For this reason, films formed by ALD are more susceptible to impurities than those formed by other film formation methods. In some cases, the film contains more impurities such as carbon than the film formed by the method described above. The quantitative determination of This can be done using endoscopic imaging.

[0267] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0268] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0269] The constituent material may be processed using a lithography method. Dry etching or wet etching can be used. This method is suitable for microfabrication.

[0270] In the lithography method, first, the resist is exposed to light through a mask. The areas are removed or left behind using a developer to form a resist mask. By etching through a resist mask, conductors, semiconductors, insulators, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. A liquid immersion technique may be used, in which the substrate is exposed to light by filling the substrate with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the pattern is written directly on the resist, so the above-mentioned resist exposure mask is not required. The resist mask is used for dry etching such as ashing, and is also used for wet etching. Etching is performed, dry etching is performed followed by wet etching, or can be removed by wet etching followed by dry etching, etc. Cut.

[0271] In addition, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When a hard mask is used, an insulating film or a conductive film that will be the hard mask material is formed on the constituent material. Then, a resist mask is formed on the hard mask, and the hard mask material is etched. A hard mask of the desired shape can be formed. The etching of the constituent material is performed in a resist pattern. This may be done after removing the resist mask, or may be done with the resist mask left in place. In the latter case, the resist mask may disappear during etching. After etching, the hard mask may be removed by etching. If there is no effect on the subsequent process or if it can be used in the subsequent process, it is not necessary to remove the hard mask. There's no need to.

[0272] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0273] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate The semiconductor substrate may be a semiconductor such as silicon or germanium. Body substrate, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of zinc oxide, gallium oxide, etc. A semiconductor substrate having an insulating region inside the substrate, such as SOI (Silicon On Insulator) Conductive substrates include graphite substrates, metal substrates, and alloy substrates. substrates, conductive resin substrates, etc. Or, substrates with metal nitrides, metal oxides, etc. Furthermore, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, A substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate Alternatively, a substrate on which an element is provided may be used. The elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light emitting element, a recording element, and the like. There are memory elements, etc.

[0274] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0275] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0276] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0277] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies, or resin be.

[0278] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators having a function of controlling the temperature (insulator 214, insulator 222, insulator 254, and insulator By surrounding the transistor with a metal layer (such as 274), the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include porosity. Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators including titanium, hafnium, or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or thiamin oxide Metal oxides such as tantalum, aluminum nitride, titanium aluminum nitride, titanium nitride, and nitride Metal nitrides such as silicon oxide or silicon nitride can be used.

[0279] In addition, the insulator that functions as the gate insulator has a region containing oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, the oxide The oxygen deficiency of 230 can be compensated for.

[0280] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, Zirconium, Beryllium, Indium, Ruthenium, Iridium, Strontium Metal elements selected from ammonium, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel, or an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are resistant to oxidation or absorb oxygen. It is a material that maintains conductivity even after oxidation, and is therefore preferred. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, Silicide may also be used.

[0281] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0282] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0283] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0284] <<Metal oxides>> As the oxide 230, it is preferable to use a metal oxide that functions as an oxide semiconductor. Metal oxides applicable to the oxide 230 according to the present invention will be described below.

[0285] The metal oxide preferably contains at least indium or zinc. It is preferable that the alloy contains aluminum and zinc. It is preferable that the alloy contains boron, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0286] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M can be aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0287] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0288] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Non-single-crystal oxide semiconductors are, for example, CAAC-OS, polycrystalline These include crystalline oxide semiconductors, nc-OS, a-like OS, and amorphous oxide semiconductors. do.

[0289] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0290] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the lattice distortion. This is because the CAAC-OS crystals are grown in the ab-plane direction. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0291] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v It can also be called a metal oxide with low acancy. Metal oxides with CAAC-OS have stable physical properties. The metal oxides used are heat resistant and highly reliable.

[0292] Here, FIG. 13(A) shows the C observed by TEM from a direction roughly parallel to the sample surface. This shows a high-resolution TEM image of a cross section of AAC-OS. Correction (Spherical Aberration Corrector) function was used High-resolution TEM images using spherical aberration correction are specifically called Cs-corrected high-resolution TEM images. Cs-corrected high-resolution TEM images were obtained using, for example, an atomic resolution analytical electron microscope manufactured by JEOL Ltd. It can be observed using instruments such as the JEM-ARM200F.

[0293] From Figure 13(A), nanocrystals, which are regions where metal atoms are arranged in layers, can be confirmed. The size of a single nanocrystal can be 1 nm or more, or even 3 nm or more. The nanocrystals reflect the unevenness of the surface on which the CAAC-OS is formed or the top surface. It is parallel to the surface on which the AC-OS is formed or the upper surface.

[0294] 13(B) and 13(C) show CA images observed from a direction approximately perpendicular to the sample surface. Cs-corrected high-resolution TEM images of the AC-OS surface are shown in Figures 13(D) and 13(E). are the images obtained by image processing of Figure 13(B) and Figure 13(C), respectively. The processing method will be explained. First, the image in FIG. 13(B) is subjected to a fast Fourier transform (FFT). Then, an FFT image is obtained by performing Fourier Transform (FT). 2.8 nm based on the origin in the acquired FFT image -1 to 5.0 nm -1 Range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFF T: Inverse Fast Fourier Transform) processing The processed image is acquired. The image acquired in this way is called an FFT filtered image. The T-filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. 1 shows a lattice arrangement.

[0295] In Figure 13(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The dotted lines indicate the connection between the nanocrystals. The dashed line indicates a hexagonal shape, which indicates that the nanocrystals are hexagonal. In CAAC-OS, hexagonal lattice points are observed when observed by TEM from the c-axis direction. Therefore, the CAAC-OS is a layered crystal shown in FIG. The shape of the nanocrystal is not limited to a regular hexagonal shape, but may be non-hexagonal. It may also be a regular hexagon.

[0296] In FIG. 13(E), a grid is formed between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement. The dotted lines indicate the changes in the orientation of the child array, and the dashed lines indicate the changes in the orientation of the lattice array. Even near the dotted line, no clear grain boundaries can be seen. By connecting the surrounding lattice points around the center, a distorted hexagon, pentagon, or heptagon can be formed. In other words, it is clear that the formation of grain boundaries is suppressed by distorting the lattice arrangement. This is because the arrangement of oxygen atoms in CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because

[0297] In addition, Figure 14(A) shows a high-resolution TEM image of a cross section of CAAC-OS, which is different from that shown in Figure 13. Also, Figure 14(B) is a high-resolution TEM image of the cross section of Figure 14(A) that is further enlarged. The atomic arrangement is highlighted for ease of understanding.

[0298] Figure 14(C) shows the area surrounded by a circle (diameter approximately 4 mm) between AO and A' in Figure 14(A). From Figure 14(C), it is clear that the c-axis orientation is In addition, the c-axis orientation is different between A-O and O-A', so different graphs are formed. The c-axis angles between the A and A crystals are 14.3° and 16. 6°, 26.4°, and so on. Between these, the angle of the c-axis gradually changes to -18.3°, -17.6°, and -15.9°. It is clear that things are changing.

[0299] High-resolution TEM images of the cross section and the plane reveal that the nanocrystals of CAAC-OS It is clear that the crystals have an orientation.

[0300] From the above, it can be seen that the CAAC-OS has a c-axis orientation as shown in the above embodiment. and the c-axis is normal to the surface on which the CAAC-OS is formed or the film surface of the CAAC-OS. Therefore, it can be confirmed by the high-resolution TEM observation of the cross section mentioned above. Each layer of metal atoms arranged in a layered fashion is parallel to the ab plane of the nanocrystal.

[0301] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0302] Indium gallium oxide, a type of metal oxide containing indium, gallium, and zinc, is used. The IGZO nanocrystals mentioned above are stable. In particular, IGZO tends to have difficulty growing crystals in the atmosphere. , small crystals (e.g., crystals of several mm or several cm) are more likely to be formed than large crystals (here, crystals of several mm or several cm). For example, the nanocrystals mentioned above may be structurally more stable.

[0303] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0304] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0305] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0306] When alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed, Therefore, alkali metals or alkaline earth metals may be A transistor using the metal oxide in the channel formation region has normally-on characteristics. Therefore, the concentration of alkali metals or alkaline earth metals in the metal oxide is reduced. Specifically, it is preferable to use secondary ion mass spectrometry (SIMS). Al in metal oxides obtained by y Ion Mass Spectrometry The concentration of potassium metal or alkaline earth metal (obtained by SIMS) is 1 × 10 1 8 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0307] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electron carrier In addition, some of the hydrogen atoms may bond with the oxygen atoms that bond with the metal atoms, forming chiral ions. Therefore, metal oxides containing hydrogen can be used. Such a transistor is likely to have normally-on characteristics.

[0308] For this reason, it is preferable that the amount of hydrogen in the metal oxide is reduced as much as possible. is the hydrogen concentration obtained by SIMS in metal oxides, expressed as 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than 5x1 0 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than A metal oxide with sufficiently reduced impurities is used for the channel formation region of a transistor. By doing so, stable electrical properties can be imparted.

[0309] <Configuration Example 2 of Semiconductor Device> FIG. 15 shows a transistor 200A according to one embodiment of the present invention and a transistor 200A 1A and 1B are top and cross-sectional views of the periphery.

[0310] FIG. 15A is a top view of a semiconductor device including a transistor 200A. 15(B) and 15(C) are cross-sectional views of the semiconductor device. 15A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 15A, and is a cross-sectional view of the transistor 20 15(A) is also a cross-sectional view of the channel length direction of 0A. 1 is a cross-sectional view of a portion indicated by a dashed line in A4, and is a cross-section in the channel width direction of a transistor 200A. In the top view of Figure 15(A), some elements have been omitted for clarity. are.

[0311] In the semiconductor device shown in FIG. 15, the semiconductor device shown in <Configuration example 1 of the semiconductor device> The same reference numerals are used to designate structures having the same functions as those constituting the device.

[0312] The configuration of the semiconductor device will be described below with reference to FIG. The materials used for the semiconductor device are explained in detail in <Configuration example 1 of semiconductor device>. It is possible.

[0313] [Transistor 200A] As shown in FIG. 15, the transistor 200A is disposed on a substrate (not shown). an insulator 216, a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator An insulator 222 is disposed on the conductor 216 and on the conductor 205, and a and an oxide 230 (oxide 230a) disposed on the insulator 224. , oxide 230b, oxide 230c1, and oxide 230c2), and on the oxide 230 250 disposed on the insulator 250, and a conductor 260 (conductor 260a, and conductor 260b), and conductor 242a and conductor 260b in contact with a portion of the top surface of oxide 230b. a barrier film 244a disposed on the conductor 242a; and a conductive material 242b. a barrier film 244b disposed on a part of the upper surface of the insulator 222 and a side surface of the insulator 224; , the side of the oxide 230a, the side of the oxide 230b, the side of the conductor 242a, the barrier film 24 4a, the side of the conductor 242b, and the upper surface of the barrier film 244b. and an insulator 254 (insulator 254a and insulator 254b).

[0314] The insulator 254 is configured by laminating two layers of an insulator 254a and an insulator 254b. , and the oxide 230c is formed by stacking two layers of oxide 230c1 and oxide 230c2. The difference between the transistor 200 and the transistor 200 is the configuration. The differences will be explained below.

[0315] As shown in FIG. 15, the insulator 254 is made up of an insulator 254a and a For example, the insulator 254a is formed to prevent impurities such as water and hydrogen from being absorbed. However, it functions as a barrier film that prevents diffusion from the insulator 280 side to the transistor 200A. In addition, for example, the insulator 254b is formed by insulating the oxygen in the oxide 230. It is preferable to suppress the diffusion of the insulating layer 280 toward the insulating layer 280. This can prevent hydrogen from entering the channel formation region of the oxide 230. In addition, it is possible to prevent oxygen from being released from the channel forming region of the oxide 230. The insulator 254a is made of silicon nitride formed by sputtering. The insulator 254b may be made of aluminum oxide formed by ALD.

[0316] For example, the insulator 254a may be an insulating material having an excess oxygen region or an excess An insulating material that easily forms an excess oxygen region is used as the insulator 254b. It is preferable to use an insulating material that easily forms an oxygen region. a is a silicon oxide film formed by sputtering, and the insulator 254b is Therefore, it is possible to use aluminum oxide formed by sputtering. By laminating two layers, the excess oxygen in the insulator 254a is converted into the oxide 230. can be efficiently supplied to

[0317] If the insulator 254a contains excess oxygen, the barrier A barrier film 244b is provided in contact with the upper surface of the conductor 242b. The barrier film 244a and the barrier film 244b are preferably formed to prevent impurities such as water and hydrogen, and The oxide 230c and the insulator 250 have a function of suppressing the permeation of oxygen. Preventing excess oxygen in the conductive material from diffusing into the conductive material 242a and the conductive material 242b. In other words, excess oxygen in the surrounding area is used to oxidize the conductors 242a and 242b. Furthermore, it is possible to prevent the conductors 242a and 242b from being oxidized. This prevents the electrical resistance of the conductors 242a and 242b from increasing. The electrical resistance of a conductor can be measured using the two-terminal method. Cut.

[0318] The barrier film 244a and the barrier film 244b may be made of, for example, aluminum oxide, oxide, or the like. Magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide metal oxides such as tantalum oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and nitride oxide; Silicon oxide, silicon nitride, or the like may be used.

[0319] In addition, the barrier film 244a and the barrier film 244b are made of conductive material that is difficult for impurities to penetrate. A conductive material may be used for the barrier film 244a and the barrier film 244b. In this case, it is preferable to use a conductive material that is less likely to release or absorb oxygen. It is to be noted that the barrier film 244a and the barrier film 244b may not be provided.

[0320] The insulator 254 is not limited to a configuration in which the insulator 254a and the insulator 254b are stacked. Alternatively, the insulating layer 254 may be a single layer, or the insulating layer 254 may be a layer of the insulator 254a, the insulator 254b, and the insulator 254c. Three layers may be laminated. When three layers are laminated, for example, the insulator 25 4a: An insulating material that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. As the insulator 254b, an insulating material having an excess oxygen region is used, and as the insulator 25 For 4c, it is preferable to use an insulating material that has the function of suppressing the diffusion of oxygen. By using a three-layer stack, the excess oxygen in the insulator 254b is absorbed into the insulator 254a. Therefore, the diffusion of the insulating material 254c to the outside can be suppressed. The excess oxygen contained in the body 254b can be efficiently supplied to the oxide 230.

[0321] When the insulator 254 is configured to have two or more layers stacked, the insulating layer The combination of materials and the layering order can be designed appropriately depending on the desired transistor characteristics. stomach.

[0322] As shown in FIG. 15, the oxide 230c is composed of an oxide 230c1 and an oxide 230c and an oxide 230c2 disposed on the oxide 230c1. It is preferable that the metal oxide used in b contains at least one of the metal elements constituting the metal oxide, It is more preferable that all of the metal elements are contained. The defect level density at the interface with the oxide 230c2 can be reduced. The oxide 230c1 is preferably a metal oxide that inhibits oxygen diffusion or permeation. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, This can prevent oxygen contained in the insulator 280 from diffusing into the insulator 250. Therefore, the oxygen is easily supplied to the oxide 230 via the oxide 230c1.

[0323] Moreover, the oxide 230c1 and the oxide 230c2 preferably have crystallinity. It is more preferable that the oxide 230c2 has higher crystallinity than the oxide 230c1. It is preferable to use CAAC-OS as the oxide 230c1 and the oxide 230c2. Preferably, the c-axes of the crystals of the oxide 230c1 and the oxide 230c2 are the same as those of the oxide 230c1 and the oxide 230c2. 230c1 and the oxide 230c2 are oriented in a direction substantially perpendicular to the surface on which the oxide 230c1 is formed or the upper surface thereof. It is preferable that the CAAC-OS has a property of making it difficult for oxygen to move in the c-axis direction. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, The oxygen contained in the oxide 230c1 is prevented from diffusing into the insulator 250, and the oxygen is The oxide 230 can be efficiently supplied.

[0324] Specifically, the oxide 230c1 is a compound of In:Ga:Zn=4:2:3 [atomic ratio]. Metal oxide was used, and the oxide 230c2 was In:Ga:Zn=1:3:4 [atomic ratio In the metal oxide used for the oxide 230c2, the constituent elements The atomic ratio of In in the metal oxide used for oxide 230c1 is By making the atomic ratio smaller than that of In, the diffusion of In into the insulator 250 side is suppressed. Since the insulator 250 functions as a gate insulator, In is If the oxide 230c is mixed in the semiconductor layer, the transistor characteristics will be deteriorated. By adopting this structure, it is possible to provide a highly reliable semiconductor device.

[0325] The insulator 280 may also be configured to have a two-layer laminated structure. As described above, the insulator 280 is made up of an insulator 280a and an insulator 280b arranged on the insulator 280a. 80b, the insulator 280a preferably has an excess oxygen region. The insulator 280a is physically closer to the channel forming region of the oxide 230 than the insulator 280b. Because the distance is short, the oxygen contained in the insulator 280 is effectively transported to the channel forming region of the oxide 230. It can be supplied efficiently.

[0326] Specifically, the insulator 280a is a silicon oxide film formed by sputtering. and silicon oxynitride formed by CVD is used as the insulator 280b. Note that the transistor 200A has a structure in which the insulator 280 is stacked. However, the present invention is not limited to this. For example, the insulator 280 may be a single layer or a three layer The above-mentioned laminated structure may be used.

[0327] As shown in FIG. 15, an insulator 282 is provided between the insulator 274 and the insulator 281. The insulator 282 has a function of suppressing the diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to use an insulating film formed by sputtering or ALD. It is preferable to form a film of silicon nitride, aluminum oxide, or the like. By doing so, oxygen contained in the insulators 280 and 250 diffuses to the insulator 281 side. This can prevent this from happening.

[0328] <Configuration Example 3 of Semiconductor Device> FIG. 16 shows a transistor 200B according to one embodiment of the present invention and a transistor 200B 1A and 1B are top and cross-sectional views of the periphery.

[0329] FIG. 16A is a top view of a semiconductor device including a transistor 200B. 16(B) to 16(D) are cross-sectional views of the semiconductor device. 16A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 16A, and shows the transistor 200 FIG. 16(C) is also a cross-sectional view of the channel length direction of B. Also, FIG. 16(C) is a cross-sectional view of the channel length direction of B in FIG. 4 is a cross-sectional view of the portion indicated by the dashed line in the channel width direction of the transistor 200B. FIG. 16(D) is also a diagram of the portion indicated by the dashed line A5-A6 in FIG. 16(A). 1 is a cross-sectional view showing the vicinity of a region 243b that functions as a low-resistance region of a transistor 200B. In the top view of Figure 16(A), some elements have been omitted for clarity. are.

[0330] In the semiconductor device shown in FIG. 16, <Configuration Example 1 of Semiconductor Device> or <Semiconductor Device> The structures constituting the semiconductor device shown in the example 2 of the semiconductor device are designated by the same reference numerals. It is noted.

[0331] The configuration of the semiconductor device will be described below with reference to FIG. For the materials constituting the semiconductor device, see <Configuration example 1 of semiconductor device> or <Configuration example of semiconductor device> The materials described in detail in 2> can be used.

[0332] [Transistor 200B] As shown in FIG. 16, the transistor 200B is disposed on a substrate (not shown). an insulator 216, a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator An insulator 222 is disposed on the conductor 216 and on the conductor 205, and a and an oxide 230 (oxide 230a) disposed on the insulator 224. , oxide 230b, oxide 230c1, and oxide 230c2), and on the oxide 230 and a conductor 260 (conductor 260) disposed on the insulator 250. a, and conductor 260b), a part of the top surface of insulator 222, the side surface of insulator 224, and oxide The oxide 230b is disposed in contact with the side of the oxide 230a, the side of the oxide 230b, and the top surface of the oxide 230b. The insulating material 254 (insulator 254a and insulator 254b) is formed of an insulator 254a. On the upper surface of the oxide 230b, a region 243a and a region 243b are formed spaced apart from each other. It is being done.

[0333] Transistor 200B is similar to the transistors described above in that it does not include conductor 242. The following explains the differences from the above-mentioned transistor 200. Reveal.

[0334] As shown in FIG. 16(B), the region 243a and the region 243b sandwich the conductor 260. It is preferable that the upper surfaces of the insulating member 254 are in contact with the insulating member 254. The side surfaces of the region 243a and the region 243b on the conductor 260 side are the same as the side surfaces of the conductor 260. The region 243a and the region 243b are aligned with or overlap with the conductor 260. It is preferable.

[0335] In the transistor 200B shown in FIG. 16, for example, the carrier density of the oxide 230 By adding an element as a dopant that can increase the resistance and lower the , the region 243 (region 243a and region 243b) may be formed.

[0336] The dopant may be an element that forms an oxygen vacancy or an element that bonds with the oxygen vacancy. Representative examples of such elements include boron and phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, rare gases, etc. may also be used. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. Also, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, etc. Niobium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sodium, zirconium, beryllium, indium, ruthenium, iridium, strontium Add one or more metal elements selected from the group consisting of ruthenium, lanthanum, etc. Among the above, boron and phosphorus are preferred as dopants. , when phosphorus is used as a dopant, amorphous silicon, or low-temperature polysilicon This allows the use of equipment from the same production line, thereby reducing capital investment. The concentration of the above elements may be measured using SIMS or the like.

[0337] In particular, it is preferable to use an element that easily forms an oxide as the element to be added to the region 243. Representative examples of such elements include boron, phosphorus, aluminum, magnesium, and the like. The element added to the region 243 takes oxygen from the oxide 230 and forms the oxide. As a result, many oxygen vacancies occur in the region 243. When the hydrogen in the oxide 230 is bonded to the silicon dioxide, carriers are generated, resulting in an extremely low resistance region. Furthermore, since the element added to the region 243 exists in the region 243 in the form of a stable oxide, Even if a subsequent process requiring high temperatures is performed, the compound is unlikely to be desorbed from the region 243. That is, an element that easily forms an oxide is used as the element to be added to the region 243. This allows the formation of a region in the oxide 230 that is resistant to high resistance even after undergoing a high-temperature process.

[0338] Here, the concentration of the above element in the region 243 is the same as that in the region 243 where the oxide 230 is not formed. It is preferable that the concentration of the above elements in the region 2 is equal to or higher than that in the region 3. The amount of oxygen vacancies contained in 43 is the amount of oxygen vacancies in the part of the oxide 230 where the region 243 is not formed. It is preferable that the amount of the defect is equal to or greater than the amount of the defect. The carrier density is higher than that of the region 243 of the oxide 230 where the oxide 230 is not formed. , the resistance becomes lower.

[0339] Forming regions 243 in oxide 230 to function as source or drain regions. Thus, the region 243 can be formed without providing a source electrode and a drain electrode made of metal. A conductor 240 can be connected which acts as a plug.

[0340] Furthermore, when the region 243 is formed by adding the dopant in this way, the insulator 254a and The oxide 230b and the insulator 254b are also doped with dopants. 4a and insulator 254b have elements contained in the dopant. a and the insulator 254b have excess oxygen, the excess oxygen is transferred to the outside by the dopant. By forming such a region 243, the transistor The ON current of the 200B is increased, and the S value (Subthreshold Swing, SS This improves the frequency characteristics.

[0341] When the region 243 is formed by adding a dopant, for example, oxide 230c1, acid A dummy gate is formed at a position where the oxide 230c2, the insulator 250, and the conductor 260 are to be provided. Then, the dummy gate is used as a mask to add dopants. Therefore, the above elements are added to the region of the oxide 230 where the dummy gate does not overlap. A region 243 containing the ions can be formed.

[0342] As a method for adding dopants, ionization is performed by mass separating ionized source gases and adding them. ion injection method, ion doping method in which ionized source gas is added without mass separation, Mass separation can be performed by using methods such as ion implantation. When this is done, the ion species to be added and their concentrations can be strictly controlled. If separation is not performed, high concentration ions can be added in a short time. Alternatively, an ion doping method may be used, in which molecular clusters are generated and ionized. A dopant may also be referred to as an ion, a donor, an acceptor, an impurity, or an element. stomach.

[0343] In addition, an element that forms oxygen vacancies in the region 243 is added and heat treatment is performed, thereby forming a channel. The hydrogen contained in the region 234, which functions as a hole formation region, is transferred to the oxygen vacancy contained in the region 243. This gives the transistor 200B stable electrical characteristics, Reliability can be improved.

[0344] In FIG. 16, the oxide 230c is replaced with the oxide 23 The insulator 254 is shown as a stack of oxide 230c1 and oxide 230c2, and the insulator 254 is shown as a stack of insulators 254a and 254b. The stack of oxide 230c and insulator 254b is shown, but is not limited to this. It may be a single layer or a laminated structure of three or more layers.

[0345] <Configuration Example 4 of Semiconductor Device> FIG. 17 shows a transistor 200C according to one embodiment of the present invention and a transistor 200C 1A and 1B are top and cross-sectional views of the periphery.

[0346] FIG. 17A is a top view of a semiconductor device including a transistor 200C. 17(B) and 17(C) are cross-sectional views of the semiconductor device. 17A is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 17A, and is a cross-sectional view of the transistor 20 17(A) is also a cross-sectional view of the channel length direction of 0C. 10 is a cross-sectional view of the portion indicated by the dashed line in A4, and is a cross-section in the channel width direction of the transistor 200C. In the top view of Figure 17(A), some elements have been omitted for clarity. are.

[0347] In the semiconductor device shown in FIG. 17, the semiconductor device shown in <Configuration example 1 of the semiconductor device> The same reference numerals are used to designate structures having the same functions as those constituting the device.

[0348] The configuration of the semiconductor device will be described below with reference to FIG. The materials used for the semiconductor device are explained in detail in <Configuration example 1 of semiconductor device>. It is possible.

[0349] [Transistor 200C] As shown in FIG. 17, the transistor 200C is disposed on a substrate (not shown). an insulator 216, a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator An insulator 222 is disposed on the conductor 216 and on the conductor 205, and a and an oxide 230 (oxide 230a) disposed on the insulator 224. , oxide 230b, and oxide 230c), and an insulator 2 disposed on the oxide 230. 50, and a conductor 260 (conductor 260a and conductor 26) disposed on the insulator 250. 0b), and conductors 242a and 242b in contact with a portion of the top surface of oxide 230b. , a part of the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the oxide 23 The side of the conductor 242b, the side of the conductor 242a, the top surface of the conductor 242a, the side of the conductor 242b, an insulator 254 disposed in contact with the upper surface of the insulator 242b and a portion of the oxide 230c; and an insulator 273 disposed over the conductor 260.

[0350] The insulating layer 273 is formed on the oxide 230c, the insulating layer 250, and a portion of the conductor 260. The insulator 280 overlaps the oxide 230c, the insulator 250, and the conductor 26. The difference from the transistor 200 is that it is provided on The differences from Star 200 will be explained below.

[0351] In transistor 200C, conductor 260 is connected to conductor 242 via insulator 250. a and a region overlapping with the conductor 242b via the insulator 250. By forming the conductor 260 in this shape, the conductor 260 has a margin for alignment. Therefore, the region between the conductor 242a and the conductor 242b of the oxide 230 is The conductors 260 can be reliably overlapped to prevent the formation of offset regions.

[0352] The insulator 273, like the insulator 254, is made of oxygen (for example, oxygen atoms, oxygen molecules, etc.). It is preferable that the film has a function of suppressing the diffusion of at least one of the above oxygen (i.e., the film is less likely to transmit oxygen). For example, insulator 273 has a lower oxygen permeability than insulator 280 or insulator 224. By covering the conductor 260 with such an insulator 273, 60 can be prevented from being oxidized.

[0353] In addition, the insulator 273, like the insulator 254, is a material that prevents impurities such as water and hydrogen from It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion from the conductor 280 side to the conductor 260. For example, it is preferable that the insulator 273 has a lower hydrogen permeability than the insulator 224.

[0354] In FIG. 17, the insulator 273 covers the conductor 260 and is attached to the upper surface of the insulator 250. However, the present invention is not limited to this. For example, the insulator 273 may be The insulating layer 254 covers the insulating layer 260, the insulating layer 250, and the oxide layer 230c. That's fine.

[0355] The configurations and methods shown in the present embodiment may be the same as those shown in other embodiments and examples. It can be used in combination with other methods as appropriate.

[0356] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0357] [Storage device 1] FIG. 18 shows an example of a semiconductor device (memory device) using a capacitor according to one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is disposed above the transistor 300. The capacitor element 100 is provided above the transistor 300 and the transistor 200. The transistor 200 may be the same as the transistor described in the previous embodiment. Sta 200 etc. can be used.

[0358] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This allows the memory contents to be retained for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0359] In the semiconductor device shown in FIG. 18, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of transistor 300 and the other of the source and drain of transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0360] In addition, the memory device shown in FIG. 18 has a memory cell array arranged in a matrix. It can be configured.

[0361] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 serving as a gate electrode. 16, an insulator 315 serving as a gate insulator, and a semiconductor region consisting of a portion of the substrate 311 313, and low resistance regions 314a which function as source or drain regions, and low-resistance region 314b. The transistor 300 may be a p-channel or n-channel type. Either a panel type or a filter type may be used.

[0362] Here, the transistor 300 shown in FIG. 18 has a semiconductor region 313 ( The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may also be used. It is also called a FIN type transistor because it uses a convex part. In addition, the insulating layer may have an insulating material that functions as a mask for forming the convex portions. Here, we have shown a case where a protrusion is formed by processing a part of a semiconductor substrate, but it is also possible to process an SOI substrate. A semiconductor film having a convex shape may be formed by the above process.

[0363] The transistor 300 shown in FIG. 18 is an example, and the structure is not limited to this. Appropriate transistors may be used depending on the structure and driving method.

[0364] <Capacitor element 100> The capacitor 100 is provided above the transistor 200. Conductor 110 functions as the first electrode, conductor 120 functions as the second electrode, and It has an insulator 130 that functions as a conductor.

[0365] Also, for example, the conductor 112 provided on the conductor 240 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used in the capacitor 100, the transistor 200, and has a function as a plug or wiring electrically connected to the transistor 300.

[0366] In FIG. 18, the conductor 112 and the conductor 110 are shown as single-layer structures, but the present invention is not limited to this configuration. For example, a conductive material having a barrier property and a conductive material having a high conductivity may be used. Conductors with barrier properties between weak conductors and highly conductive conductors with good adhesion may form a highly conductive material.

[0367] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, nitride Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The material may be aluminum or the like, and may be provided as a laminated layer or a single layer.

[0368] For example, the insulator 130 may be made of a material with high dielectric strength such as silicon oxynitride and a material with high dielectric strength such as silicon oxynitride. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, which ensures sufficient capacitance. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0369] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium; oxide nitrides having silicon and hafnium; Nitrides containing ammonium.

[0370] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. silicon dioxide, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, silicon oxide with vacancies There are various types of resins, such as kon and resin.

[0371] <Wiring layer> Between each structure, a wiring layer including an interlayer film, wiring, plugs, etc. may be provided. In addition, multiple wiring layers can be provided depending on the design. Conductors that function as lines may have multiple structures collectively assigned the same symbol. In addition, in this specification and the like, the wiring and the plug electrically connected to the wiring are integrated. That is, when a part of the conductor functions as a wiring, or when a part of the conductor It may also function as a plug.

[0372] For example, on the substrate 311, an insulator 320, an insulator 322, an insulator 323, and an insulator 324 are provided as interlayer films. 4 and an insulator 326 are laminated in this order. The conductive material 316 is embedded in the insulator 320. , insulator 322, insulator 324, and insulator 326 are connected to the capacitive element 100 or the transformer. The conductive material 328 and the conductive material 330 are embedded in the insulating film 200. The conductor 328 and the conductor 330 function as plugs or wiring.

[0373] In addition, the insulator that functions as an interlayer film acts as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be subjected to chemical mechanical polishing (CMP) to improve flatness. The surface may be planarized by a planarization process using a CMP method or the like.

[0374] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In this case, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0375] On the insulator 354 and the conductor 356, the insulator 210, the insulator 212, the insulator 21 4, and an insulator 216 are laminated in this order. 12, insulator 214, and insulator 216 are provided with conductor 218 and transistor 200. The conductor 218 is embedded with a conductor (conductor 205) that constitutes a capacitance. As a plug or wiring electrically connecting to the element 100 or the transistor 300 Furthermore, an insulator 150 is provided on the conductor 120 and the insulator 130. It is being done.

[0376] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides that have insulating properties. Examples of such materials include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0377] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0378] For example, the insulators 212, 352, and 354 are made of insulators with low relative dielectric constants. For example, the insulator may be silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide silicon dioxide with added carbon and nitrogen, silicon dioxide with vacancies, resin, etc. Alternatively, the insulator may be made of silicon oxide, silicon oxynitride, or nitride. Silicon oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide Silicon oxide with carbon and nitrogen added or silicon oxide with vacancies, and resin It is preferable that the silicon oxide and silicon oxynitride have a laminated structure of It is thermally stable, so when combined with resin, it creates a laminated structure that is thermally stable and has a low dielectric constant. Examples of the resin include polyester, polyolefin, and polyamide. Examples include nylon, aramid, polyimide, polycarbonate, and acrylic.

[0379] In addition, the insulator 130 provided on the conductor 112 or the conductor 120, and the insulator 150 or both with a resistivity of 1.0 x 10 12 Ωcm or more 1.0×10 15 Ωc m or less, preferably 5.0 × 10 12 Ωcm or more 1.0×10 14 Ωcm or less, more preferred Or 1.0 x 10 13 Ωcm or more 5.0×10 13 It is preferable to use an insulator with a resistance of Ωcm or less. It is preferable that one or both of the insulators 130 and 150 have the above-mentioned resistivity. By using an insulator having such a structure, the insulator can maintain its insulating properties while preventing the transistor 200 from being damaged. Between the transistor 300, the capacitor 100, and the wirings of the conductor 112, the conductor 120, etc. Dispersing accumulated charge, transistor using the charge, memory device having the transistor As such an insulator, nitride is preferable because it can suppress the deterioration of characteristics and electrostatic breakdown. Silicon or silicon oxynitride can be used.

[0380] In addition, as an insulator having the above-mentioned resistivity, the insulator 140 is formed as a lower layer of the conductor 112. In this case, the insulator 140 may be formed on the insulator 281. Openings are formed in the insulator 281, the insulator 274, the insulator 280, the insulator 254, etc., and the openings The insulator 241 is formed in the opening, and the transistor 200 and the conductor 218 are electrically connected. The insulator 140 may be formed by forming a conductor 240 having a thickness of 1000 Å or less. The same materials as those in 50 can be used.

[0381] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulators 210, 350, etc. contain impurities such as hydrogen and oxygen. An insulator having a function of suppressing the transmission of light may be used.

[0382] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide Metal oxides such as silicon nitride oxide, silicon nitride, etc. can be used.

[0383] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as silicon, Silicides such as nickel silicide may also be used.

[0384] For example, conductor 328, conductor 330, conductor 356, conductor 218, conductor 110, The conductors 112, 120, etc. may be made of metal materials, alloy materials, or the like, which are made of the above-mentioned materials. Conductive materials such as metal nitride materials and metal oxide materials can be used as single layers or laminated layers. It is possible to use high-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity. It is preferable to use tungsten. Alternatively, aluminum, copper, etc. It is preferable to form the wiring from a low resistance conductive material. The resistance can be reduced.

[0385] <<Wiring or plug in a layer provided with an oxide semiconductor>> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In this case, the insulator having the excess oxygen region and an insulator having a barrier property is provided between the insulator having the excess oxygen region and a conductor provided on the insulator. It is preferable to provide such a function.

[0386] For example, in FIG. 18, an insulator 280 and an insulator 281 are provided between the conductor 240 and the insulator 281. It is preferable to provide an insulator 241. The insulator 241 is connected to the insulators 280 and 281 and the conductor. The insulator 280 and the insulator Absorption of oxygen contained in 281, that is, oxidation of the conductor 240, can be suppressed.

[0387] In other words, by providing the insulator 241, the excess oxygen contained in the insulator 280 is absorbed by the conductor 24 Furthermore, by having the insulator 241, it is possible to suppress the absorption of impurities. The diffusion of hydrogen, which is a substance, into the transistor 200 via the conductor 240 is suppressed. It is possible.

[0388] The insulator 241 has a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. It is advisable to use insulating materials with this property, such as aluminum oxide and hafnium oxide. It is preferable to use other oxides such as magnesium oxide, gallium oxide, and oxide. Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Metal oxides such as tantalum oxide, silicon nitride oxide, silicon nitride, etc. can be used. Cut.

[0389] The above is a description of the configuration example. By using this configuration, In semiconductor devices using transistors, the fluctuation of electrical characteristics is suppressed and reliability is improved. In addition, a transistor including an oxide semiconductor with high on-state current can be provided. In addition, a transistor including an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0390] [Storage device 2] FIG. 19 illustrates an example of a memory device using a semiconductor device according to one embodiment of the present invention. The memory device shown in FIG. 18 includes the transistor 200, the transistor 300, and the capacitor In addition to the semiconductor device having the capacitor 100, the semiconductor device also has a transistor 400.

[0391] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are connected to the source and the diode. and connect the source of transistor 400 to the second gate of transistor 200. In this configuration, when the second gate of the transistor 200 is held at a negative potential, The first gate-source voltage and the second gate-source voltage of the transistor 400 are In the transistor 400, the second gate voltage and the first gate voltage The drain current at 0V is very small, so the transistor 200 and the transistor Even if power is not supplied to the transistor 400, the negative potential of the second gate of the transistor 200 can be maintained for a long time. This allows the transistor 200 and the transistor 400 to be maintained. A storage device having the above structure can retain stored contents for a long period of time.

[0392] Therefore, in FIG. 19, the wiring 1001 is electrically connected to the source of the transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is The second gate of the transistor 200 is electrically connected to the second gate of the transistor 3. The gate of transistor 200 and the other of the source and drain of transistor 200 are connected to capacitance element 1 The wiring 1005 is electrically connected to one electrode of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the first gate of the transistor 400, and the wiring 1009 is electrically connected to the first gate of the transistor 400. is electrically connected to the second gate of the transistor 400, and the wiring 1010 is 400. Here, the wiring 1006, the wiring 1007, the wiring The wire 1008 and the wiring 1009 are electrically connected.

[0393] 19 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. 0 can control the second gate voltages of the plurality of transistors 200. It is preferable to provide fewer transistors 400 than transistors 200.

[0394] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. The conductor 460 (conductor 460a and conductor 460b) functions as a gate electrode. Conductor 405 functions as a gate electrode, insulator 222 functions as a gate insulator, and insulator 4 24a, insulator 424b, and insulator 450, and an acid having a region where a channel is to be formed. The oxide 430c, the conductor 442a functioning as either the source or the drain, and the oxide 4 31a, and oxide 431b, and conductor 4 serving as the other of the source or drain. 42b, oxide 432a, and oxide 432b, and conductor 440 (conductor 440a, and and conductor 440b).

[0395] In the transistor 400, the conductor 405 is formed in the same layer as the conductor 205. The insulator 424a and the insulator 424b are formed in the same layer as the insulator 224. The oxide 431a and oxide 432a are formed in the same layer as the oxide 230a. The conductor 431b and oxide 432b are formed in the same layer as the oxide 230b. 42 is formed in the same layer as the conductor 242. The oxide 430c is formed in the same layer as the oxide 230c. The insulator 450 is formed in the same layer as the insulator 250. 60 is formed in the same layer as the conductor 260 .

[0396] It should be noted that structures formed in the same layer can be formed simultaneously. For example, oxide 4 The oxide 30c can be formed by processing an oxide film that will become the oxide 230c.

[0397] The oxide 430c that functions as the active layer of the transistor 400 is the same as the oxide 230. Similarly, oxygen vacancies are reduced, and impurities such as water and hydrogen are reduced. The threshold voltage of the transistor 400 is increased, the off-current is reduced, and the second gate voltage and When the first gate voltage is 0V, the drain current can be made very small.

[0398] <<Dicing line>> In the following, a large-area substrate is divided into individual semiconductor elements to form multiple semiconductor devices. Dicing lines (scribe lines, dividing lines) are provided when extracting chips. The dividing method is as follows: First, grooves (dicing lines) for dividing the semiconductor elements are formed on the substrate, and then the dicing In some cases, the substrate is cut by a grinder and divided (divided) into a plurality of semiconductor devices.

[0399] The transistor 200 described in the previous embodiment and the transistor shown in this embodiment At the outer edge of 400, as shown in FIG. 19, the insulator 254 and the insulator 222 come into contact. Therefore, the area where the insulator 254 and the insulator 222 contact each other is set as a dicing line. When designing the dicing line, the degree of freedom in designing the dicing line can be increased. The insulator 222 and the insulator 254 may be formed using the same material and method. By providing the insulating material 254 and the insulating material 255 using the same material and method, adhesion can be improved. For example, it is preferable to use aluminum oxide.

[0400] With this structure, the insulator 222 and the insulator 254 form a transistor 200, and can encapsulate the transistor 400. Insulator 222, and The body 254 has a function of suppressing the diffusion of oxygen, hydrogen, and water. The substrate is divided into multiple chips by dividing it into circuit regions where semiconductor elements shown in Even if the substrate is processed into a chip, impurities such as water and hydrogen can enter from the side of the divided substrate, causing damage to the transistor. Therefore, diffusion to the transistor 200 and the transistor 400 can be prevented.

[0401] In addition, this structure allows excess oxygen in the insulator 224 to migrate to the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 can be prevented from diffusing to the outside. The oxide on which the channel of the transistor 200 or the transistor 400 is formed is The oxygen is supplied to the transistor 200 or the transistor 400. This reduces the oxygen vacancies in the oxide in which the channel is formed. The oxide on which the channel in transistor 200 or transistor 400 is formed is then subjected to a defect-level An oxide semiconductor having low potential density and stable characteristics can be obtained. The fluctuation of the electrical characteristics of the transistor 200 or the transistor 400 is suppressed, and the reliability is improved. It can be raised.

[0402] This embodiment mode may be appropriately combined with the configurations described in other embodiment modes and examples. It is possible to implement.

[0403] (Fourth embodiment) In this embodiment, a semiconductor device using an oxide according to one embodiment of the present invention will be described with reference to FIGS. 20 and 21. A transistor used as a conductor (hereinafter, sometimes referred to as an OS transistor) and a capacitor The following describes a storage device to which the device is applied (hereinafter, sometimes referred to as an OS memory device). The OS memory device includes at least a capacitance element and an OS transistor that controls charging and discharging of the capacitance element. The off-state current of an OS transistor is extremely small. The OS memory device has excellent retention characteristics and can function as a non-volatile memory. .

[0404] <Storage device configuration example> FIG. 20A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1 411, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 142 0, column circuitry 1430, output circuitry 1440, and control logic circuitry 1460. do.

[0405] The column circuitry 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write The precharge circuit has a function of precharging the wiring. The amplifier has the function of amplifying the data signal read from the memory cell. The lines are wirings connected to memory cells in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal RDA TA to the outside of the storage device 1400. It has a decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0406] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 The high power supply voltage (VDD) for the 11 and the high power supply voltage (VIL) for the memory cell array 1470 are The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data signal WDATA is input to the write circuit. do.

[0407] The control logic circuit 1460 receives externally input control signals (CE, WE, R E) to generate control signals for the row decoder and column decoder. The control signal WE is a write enable signal, and the control signal R E is a read enable signal. The signal is not limited to this, and other control signals may be input as required.

[0408] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0409] In FIG. 20A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. Although an example in which the film is formed on a surface has been shown, the present embodiment is not limited to this. For example, as shown in FIG. 20B, the memory cell array 1411 is provided on a part of the peripheral circuit 1411. 70 may be provided so as to overlap the memory cell array 1470. For example, In this way, a sense amplifier may be provided.

[0410] FIG. 21 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0411] [DOSRAM] 21A to 21C show examples of circuit configurations of memory cells in a DRAM. In this case, a DRAM using a memory cell of one OS transistor and one capacitor element type is called DOSRA. M (registered trademark) (Dynamic Oxide Semiconductor R&D It is sometimes called om Access Memory. The filter 1471 includes a transistor M1 and a capacitance element CA. 1 has a gate (sometimes called a top gate) and a back gate.

[0412] The first terminal of the transistor M1 is connected to the first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0413] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used to apply a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0414] Furthermore, the memory cells MC are not limited to the memory cells 1471, and the circuit configuration may be changed. For example, the memory cell MC can be configured as a memory cell 1472 shown in FIG. In addition, the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be configured as the memory cell 14 shown in FIG. As shown in 73, a transistor with a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with a resistor M1.

[0415] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This makes it possible to make the leakage current of the transistor M1 very small. The transistor M1 allows the data to be retained for a long time, reducing the frequency of refreshing the memory cells. In addition, the refresh operation of the memory cells can be made unnecessary. In addition, since the leakage current is very small, the memory cells 1471 and 147 2. The memory cell 1473 can store multi-value data or analog data. do.

[0416] In addition, in the DOSRAM, as described above, the memory cell array 1470 is overlapped with the By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0417] [NOSRAM] 21(D) to 21(G) show the structure of a gain cell type memory cell having two transistors and one capacitor. A circuit configuration example is shown in FIG. 21D. A memory cell 1474 shown in FIG. 21D includes a transistor M2 and The transistor M2 is a top gate. In this specification, etc., The memory cell has a gain cell type memory cell using an OS transistor as the transistor M2. The memory device is NOSRAM (Nonvolatile Oxide Semiconductor It is sometimes called EEPROM (RAM).

[0418] The first terminal of the transistor M2 is connected to the first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of transistor B is connected to the line CAL. The first terminal of transistor M3 is connected to the line R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to the first terminal of the capacitance element CB.

[0419] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL functions as the second wiring of the capacitance element CB. It functions as a wiring for applying a predetermined potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the The threshold voltage can be increased or decreased.

[0420] Furthermore, the memory cells MC are not limited to the memory cells 1474, and the circuit configuration may be changed as appropriate. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be the memory cell shown in FIG. Like the 1476, it is a single-gate transistor, i.e., it does not have a back gate. The memory cell may be configured with a transistor M2. As shown in FIG. 21G, the memory cell 1477 has a wiring WBL and a wiring RBL. The wiring BIL may be integrated.

[0421] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as the transistor M2, and the transistor 300 is used as the transistor M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by the transistor M2. Since the memory cells can be maintained at the same level, the frequency of refreshing the memory cells can be reduced. Furthermore, the refresh operation of the memory cells can be eliminated. Since the memory cell 1474 is always small, it can store multi-value data or analog data. The same applies to memory cells 1475 to 1477.

[0422] The transistor M3 is a transistor having silicon in the channel forming region (hereinafter referred to as The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. The field effect mobility may be higher than that of a read transistor. A Si transistor may be used as the transistor M3 that functions as a By using a Si transistor for transistor M3, a transistor can be stacked on top of transistor M3. Since the memory cell can be provided with the transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0423] The transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M3, the memory cell array 1470 is The circuit can be constructed using only transistors.

[0424] FIG. 21(H) shows an example of a gain cell type memory cell with three transistors and one capacitor. The memory cell 1478 shown in FIG. 21(H) includes transistors M4 to M 6 and a capacitor CC. The capacitor CC is provided as appropriate. is electrically connected to the wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. The wiring GNDL is a wiring that applies a low level potential. The wiring 478 may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

[0425] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0426] The transistors M5 and M6 are n-channel Si transistors. Alternatively, the transistors M4 to M5 may be p-channel Si transistors. The transistor M6 may be an OS transistor. In this case, the memory cell array 1470 is configured as an n-type transistor. The circuit can be constructed using only transistors.

[0427] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor M4 is a transistor 200, and the transistors M5 and M6 are transistors M1 and M2. The transistor 300 can be used as the capacitor element CC, and the capacitor element 100 can be used as the capacitor element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be reduced. The flow can be very small.

[0428] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are These circuits, and the wiring and circuits connected to the circuits, The arrangement or function of road elements etc. may be changed, deleted or added as required.

[0429] The structure shown in this embodiment mode may be combined as appropriate with structures shown in other embodiment modes, examples, etc. It can be used as such.

[0430] (Embodiment 5) In this embodiment, a chip 1200 on which the semiconductor device of the present invention is mounted is shown in FIG. A chip 1200 is implemented with multiple circuits (systems). The technology of integrating multiple circuits (systems) on a single chip is called system-on-chip ( It is sometimes called System on Chip (SoC).

[0431] As shown in FIG. 22(A), the chip 1200 includes a CPU (Central Processor). ssing Unit) 1211, GPU (Graphics Processing a memory controller 1212, one or more analog calculation units 1213, and one or more memory controllers 1214. controller 1214, one or more interfaces 1215, one or more networks It has a work circuit 1216 and the like.

[0432] The chip 1200 is provided with bumps (not shown), and as shown in FIG. 22(B), Printed Circuit Board (PCB) 1201 No.1 The first surface of the PCB 1201 is connected to the second surface. It is provided and connected to the motherboard 1203.

[0433] The motherboard 1203 is equipped with memory devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be provided with a DOSR as shown in the previous embodiment. For example, the flash memory 1222 may be configured as The NOSRAM shown in FIG.

[0434] The CPU 1211 preferably has multiple CPU cores. It is preferable that the CPU 1211 and the GPU 1 have multiple GPU cores. Each of the CPs 212 may have a memory for temporarily storing data. The memory common to U1211 and GPU1212 is provided on chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU1212 is also suitable for parallel calculation of large amounts of data, and is ideal for image processing and multiply-and-accumulate operations. The GPU 1212 can be used as an image processing circuit or By providing a multiply-and-accumulate circuit, image processing and multiply-and-accumulate operations can be performed with low power consumption. This becomes possible.

[0435] In addition, the CPU 1211 and GPU 1212 are mounted on the same chip, The wiring between the CPU1211 and GPU1212 can be shortened, and Data transfer from CPU 1211 to GPU 1212, memory After the data transfer between the GPUs and the calculations in GPU1212, the GPU1212 transfers the data to CPU12. The calculation results can be transferred to 11 at high speed.

[0436] The analog calculation unit 1213 includes an A / D (analog / digital) conversion circuit and a D / A (digital The analog calculation unit 1213 has one or both of a digital / analog conversion circuit. The product-sum calculation circuit may be provided in the

[0437] The memory controller 1214 is a circuit that functions as a controller for the DRAM 1221. , and a circuit that functions as an interface to the flash memory 1222.

[0438] The interface 1215 includes a display device, a speaker, a microphone, a camera, a computer, and the like. The controller has an interface circuit with external devices such as a This includes devices such as mice, keyboards, and game controllers. USB (Universal Serial Bus), HDMI (registered trademark) High-Definition Multimedia Interface) You can be there.

[0439] The network circuit 1216 is a LAN (Local Area Network) or the like. It may also have a circuit for network security. stomach.

[0440] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the manufacturing process can be increased. This eliminates the need for a soldering iron, and the chip 1200 can be produced at low cost.

[0441] A PCB 1201 on which a chip 1200 having a GPU 1212 is mounted, a DRAM 122 1 and a motherboard 1203 provided with a flash memory 1222. It can be called module 1204.

[0442] The GPU module 1204 includes a chip 1200 using SoC technology. Its size can be reduced. Also, it has excellent image processing capabilities, making it suitable for smart devices. Phones, tablets, laptops, portable (portable) game consoles, etc. It is suitable for use in portable electronic devices. Deep neural networks (DNNs), convolutional neural networks (CNN), recurrent neural network (RNN), autoencoder, deep Boltzmann It can implement techniques such as deep belief networks (DBM) and deep belief networks (DBN). Therefore, the chip 1200 is an AI chip, or the GPU module 1204 is an AI system module. It can be used as a module.

[0443] The structure shown in this embodiment mode may be combined as appropriate with structures shown in other embodiment modes, examples, etc. It can be used as such.

[0444] (Embodiment 6) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, computers include tablet computers, notebook computers, desktop computers, This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment may be used in a memory card (for example, an SD card). Various removable drives such as flash drives, USB flash drives, and SSDs (Solid State Drives) This is applied to removable storage devices. Figure 23 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed and used in various storage devices and removable memory.

[0445] 23A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, the controller chip 1106 is installed. The semiconductor device shown in the embodiment can be incorporated.

[0446] Figure 23(B) is a schematic diagram of the external appearance of an SD card, and Figure 23(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into such a device.

[0447] FIG. 23(D) is a schematic diagram of the external appearance of the SSD, and FIG. 23(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DOSRAM chip may be used. By providing the memory chip 115, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 4 or the like.

[0448] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments, examples, etc. It is possible to do this.

[0449] (Embodiment 7) A semiconductor device according to one aspect of the present invention is a processor such as a CPU or a GPU, or a chip. FIG. 24 shows a processor such as a CPU or a GPU according to one embodiment of the present invention. Specific examples of electronic devices equipped with the chip are shown below.

[0450] <Electronic devices and systems> A GPU or chip according to one embodiment of the present invention can be mounted in various electronic devices. Examples of electronic devices include television sets, desktop or notebook computers, Personal computers, computer monitors, digital signage Signage: Digital signage), pachinko machines and other large game machines. In addition to electronic devices with large screens, digital cameras, digital video cameras, digital photos Examples include frames, mobile phones, portable game consoles, personal digital assistants, and sound reproduction devices. Furthermore, by providing an integrated circuit or a chip according to one embodiment of the present invention in an electronic device, Artificial intelligence can be installed in the sub-devices.

[0451] The electronic device according to one embodiment of the present invention may include an antenna. By doing so, it is possible to display images, information, etc. on the display unit. If the device has a secondary battery, the antenna may be used for contactless power transmission.

[0452] The electronic device according to one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation Number, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power (including the ability to measure radiation, flow rate, humidity, gradient, vibration, odor or infrared) It may have.

[0453] The electronic device of one embodiment of the present invention can have various functions. (still images, videos, text images, etc.) on the display, touch panel function, calendar Functions such as displaying date and time, running various software (programs) functions, wireless communication functions, and functions to read programs or data recorded on recording media. It can have functions, etc. Figure 24 shows an example of an electronic device.

[0454] [mobile phone] FIG. 24(A) illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551. It is provided for 0.

[0455] The information terminal 5500 uses a chip according to one embodiment of the present invention to perform a function using artificial intelligence. It is possible to run applications that utilize artificial intelligence. For example, the application recognizes conversations and displays the conversation contents on the display unit 5511. The display unit 5511 recognizes characters, figures, etc. input by the user on the touch panel. and applications to be displayed on the display unit 5511, applications that perform biometric authentication such as fingerprints and voiceprints, etc. Applications, etc.

[0456] [Information terminal] 24(B) shows a desktop information terminal 5300. The information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard. It has a code 5303.

[0457] The desktop information terminal 5300 is one of the features of the present invention, similar to the information terminal 5500 described above. By applying the chip of the present invention, it is possible to execute applications using artificial intelligence. Examples of applications that use artificial intelligence include design support software. , writing correction software, automatic menu generation software, etc. By using the laptop information terminal 5300, new artificial intelligence can be developed.

[0458] In the above, a smartphone and a desktop information terminal are used as examples of electronic devices. As shown in Figure 24(A) and (B), the smartphone and desktop It is possible to apply information terminals other than personal information terminals, such as smartphones and desktops. Examples of information terminals other than personal information terminals include PDAs (Personal Digital Assistants). Assistant), notebook information terminals, and workstations.

[0459] [electric appliances] FIG. 24(C) shows an electric refrigerator-freezer 5800, which is an example of the electric appliance. The refrigerator 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like. do.

[0460] By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, artificial intelligence By utilizing artificial intelligence, an electric refrigerator-freezer 5800 can be realized. The Electric Refrigerator-Freezer 5800 is a refrigerator-freezer that can be used to store food and drink. It has a function to automatically generate menus based on the expiration date of ingredients, and a function to automatically generate menus based on the expiration date of ingredients stored in the electric refrigerator-freezer 5800. It can have a function to automatically adjust the temperature to suit the ingredients being cooked.

[0461] In this example, an electric refrigerator-freezer was described as an electrical appliance, but other electrical appliances may also be used. Examples include vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, and induction cookers. , water dispenser, heating and cooling appliances including air conditioners, washing machines, dryers, Examples include audiovisual equipment.

[0462] [Game consoles] FIG. 24(D) shows a portable game machine 5200, which is an example of a game machine. The computer 5200 includes a housing 5201, a display unit 5202, buttons 5203, and the like.

[0463] By applying the GPU or chip of one embodiment of the present invention to the portable game console 5200, It is possible to realize a portable game machine 5200 with low power consumption. Since heat generation from the circuit can be reduced, the circuit itself, peripheral circuits, and The impact on the module can be reduced.

[0464] Furthermore, by applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, This makes it possible to realize a portable game machine 5200 with artificial intelligence.

[0465] Originally, the progress of the game, the behavior of the creatures that appear in the game, the phenomena that occur in the game, etc. The expression is determined by the program that the game has, but the portable game machine 520 By applying artificial intelligence to 0, it becomes possible to express things that are not limited to game programs. For example, the questions asked by the player, the progress of the game, and events occurring during the game The timing of the occurrence, the words and actions of the characters appearing in the game, etc. are limited to the game program. It is possible to express it by changing it without changing the color.

[0466] In addition, when playing games that require multiple players on the handheld game console 5200, artificial intelligence This allows you to create anthropomorphic game players, so you can turn your opponents into AI. By using multiple game players, you can play the game alone.

[0467] In FIG. 24(D), a portable game machine is shown as an example of a game machine. The game machine to which the GPU or chip of the present invention is applied is not limited to this. Examples of game machines that can use PU or chips include home-use stationary game machines, Arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.), sports facilities Examples include pitching machines for batting practice that are installed in the facility.

[0468] [Moving object] The GPU or chip of one embodiment of the present invention is used in automobiles, which are moving objects, and in the vicinity of the driver's seat of the automobile. can be applied to.

[0469] FIG. 24(E1) shows an automobile 5700 as an example of a moving object, and FIG. 24(E2) shows an automobile FIG. 24(E2) is a diagram showing the area around the windshield in the interior of a vehicle. Display panels 5701, 5702, and 5703 attached to the board Also shown is a display panel 5704 mounted on the pillar.

[0470] The display panels 5701 to 5703 display a speedometer, a tachometer, It provides various information by displaying the driving distance, fuel gauge, gear status, air conditioning settings, etc. In addition, the display items and layout displayed on the display panel can be adjusted by the user. It can be changed as needed to suit your taste, enhancing the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0471] The display panel 5704 is connected to an imaging device (not shown) provided on the outside of the automobile 5700. By projecting images from the pillars, it is possible to complement the blind spots (fields of view) blocked by the pillars. That is, an image from an imaging device provided on the outside of the automobile 5700 can be displayed. This will help to compensate for blind spots and increase safety. By displaying the image, safety checks can be performed more naturally and without any discomfort. The light 5704 can also be used as a lighting device.

[0472] The GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, e.g. For example, the chip can be used in the autonomous driving system of the automobile 5700. The chip can be used in systems that provide road guidance, risk prediction, etc. Display panel 57 The display panels 5701 to 5704 are configured to display information such as road guidance and risk prediction. Good too.

[0473] In the above description, an automobile is used as an example of a moving body. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, These include vehicles such as drones, airplanes, and rockets. Applying the chip of one aspect of the present invention to a moving object and providing it with a system that utilizes artificial intelligence can be done.

[0474] [Broadcasting System] The GPU or chip according to one aspect of the present invention can be applied to a broadcasting system.

[0475] FIG. 24(F) shows a schematic diagram of data transmission in a broadcasting system. 24(F) shows how radio waves (broadcast signals) transmitted from a broadcasting station 5680 are transmitted to televisions in each home. The diagram shows the path the signal takes to reach the TV receiver (TV) 5600. The broadcast signal received by the antenna 5650 is transmitted to the receiving device (not shown). It is sent to the TV5600 via

[0476] In FIG. 24(F), the antenna 5650 is a UHF (Ultra High Frequency) The antenna shown is a BS 110°CS antenna. Antennas, CS antennas, etc. can also be applied.

[0477] Radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and radio tower 5670 The received radio wave 5675A is amplified and radio wave 5675B is transmitted. By receiving radio waves 5675B with Na 5650, you can watch terrestrial TV broadcasts on TV 5600. The broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 24(F), but may be any other type of broadcasting system. It may also be satellite broadcasting using an industrial satellite, data broadcasting via optical fiber lines, or the like.

[0478] The above-described broadcasting system applies the chip according to one aspect of the present invention to broadcast using artificial intelligence. The broadcasting station 5680 transmits broadcast data to the TV 5600 in each home. When the encoder is activated, the broadcast data is compressed and the antenna 5650 receives the broadcast data. When the data is received, the decoder of the receiving device included in the TV 5600 converts the broadcast data into By using artificial intelligence, for example, the compression method of the encoder can be Recognizing display patterns contained in displayed images in motion compensation prediction, which is one of the methods It is also possible to perform intra-frame prediction using artificial intelligence. For example, low-resolution broadcast data is received and then displayed on the TV5600 with high resolution. When displaying the broadcast data, the decoder may perform up-conversion or other operations to restore the broadcast data. Image interpolation can be performed.

[0479] The AI-based broadcasting system described above is expected to be a key component of the ultra-high definition television broadcasting system, which will see an increase in the amount of broadcast data. It is suitable for revision (UHDTV: 4K, 8K) broadcasting.

[0480] In addition, as an application of artificial intelligence on the TV5600 side, for example, By using such a configuration, the recording device By having AI learn user preferences, it can automatically record programs that match the user's preferences. It can be depicted.

[0481] Electronic devices described in the present embodiment, functions of the electronic devices, application examples of artificial intelligence, and their effects etc. can be appropriately combined with descriptions of other electronic devices.

[0482] This embodiment may be implemented in appropriate combination with the configurations described in other embodiments, examples, etc. It is possible to do this. [Example]

[0483] In this example, a semiconductor device according to one embodiment of the present invention is a transistor shown in FIGS. 9 and 10. A transistor (hereinafter referred to as sample 1) having a configuration similar to that of the transistor 10d was fabricated. The semiconductor device was observed under a scanning transmission electron microscope (STEM). The results of observations using a transmission electron microscope Explain the results.

[0484] First, the structure of sample 1 will be described. As shown in FIGS. 9 and 10, sample 1 is a substrate. An insulator 224 disposed on a plate (not shown) and an oxide disposed on the insulator 224. 230b, an oxide 230c disposed on the oxide 230b, and an oxide 230c disposed on the oxide 230c. The insulating layer 250 has an insulator 250 disposed thereon, and a conductor 260 disposed on the insulator 250 . Although not shown in FIGS. 9 and 10, Sample 1 is a transistor 2 shown in FIG. Similar to 00, the oxide 230a is located between the insulator 224 and the oxide 230b. The conductor 260 is a laminated film of a conductor 260a and a conductor 260b.

[0485] The insulator 224 was made of silicon oxynitride with a film thickness of 35 nm.

[0486] The oxide 230a is an In film having a thickness of 5 nm, which is formed by DC sputtering. The oxide 230a was formed using In:Ga:Zn=1 An oxide target with an atomic ratio of 3:4 was used, and 45 sccm of oxygen gas was used as the deposition gas. The deposition pressure was set to 0.7 Pa (measured by a miniature gauge MG-2 manufactured by Canon Anelva). The film formation power was 500 W, the substrate temperature was 200°C, and the target-substrate The distance between the plates was 60 mm.

[0487] The oxide 230b is a 15 nm thick I film formed by DC sputtering. The oxide 230b was formed using an n-Ga-Zn oxide. An oxide target with an atomic ratio of 4:2:4.1 was used, and argon gas was used as the deposition gas. The film formation pressure was 0.7 Pa (Canon Anelva) using 30 sccm of nitrogen and 15 sccm of oxygen gas. The measurement was performed using a miniature gauge MG-2 manufactured by Epson Corporation. The temperature was set to 200° C., and the target-substrate distance was set to 60 mm.

[0488] The oxide 230c is a laminated film. The In-Ga-Zn oxide film was formed using the coating method and had a thickness of 5 nm. The lower layer of the object 230c was formed by an acid of In:Ga:Zn=4:2:4.1 [atomic ratio]. A nitride target was used, and 45 sccm of oxygen gas was used as the deposition gas, with the deposition pressure at 0. 7 Pa (measured using a miniature gauge MG-2 manufactured by Canon Anelva), and the film was formed. The power was set to 500 W, the substrate temperature to 200°C, and the target-substrate distance to 60 mm. Ta.

[0489] In addition, a film formed by DC sputtering as the upper layer of the oxide 230c A 5 nm thick In-Ga-Zn oxide was used. , using an oxide target of In:Ga:Zn=1:3:4 [atomic ratio], other film formation conditions was the same as oxide 230a.

[0490] The insulator 250 was made of silicon oxynitride with a film thickness of 10 nm. Titanium nitride with a thickness of 5 nm was used as the conductor 260a. We used

[0491] The sample 1 having the above-mentioned configuration has a channel length of 200 nm and a channel width of 60 nm. Like the transistor 200, Sample 1 has the following features in addition to the above structure: Furthermore, the insulator 214, the insulator 216, the conductor 205, the insulator 222, the conductor 242, the insulator The insulating member 254, the conductor 240, the insulator 280, the insulator 274, and the insulator 281 are included. do.

[0492] The prepared sample 1 was analyzed using the JEOL "JEM-ARM200F" at an accelerating voltage of The voltage was set to 200 kV, and cross-sectional TEM images were taken in Cs-TEM mode. The photographed result is shown in FIG. 25. FIG. 25 shows the channel in the vicinity of the channel forming region of the oxide 230. This is a cross-sectional TEM image in the width direction.

[0493] Furthermore, Fig. 26 shows enlarged cross-sectional TEM images of regions A to F shown in Fig. 25. Region A includes oxide 230c that is in contact with the top surface of oxide 230b. Region B includes oxide 230c that is in contact with the top surface of oxide 230b. Region C includes oxide 230c in contact with the top edge of oxide 230b. Region D includes oxide 230c that contacts the side of insulator 224. Region E includes oxide 230c. Region E includes oxide 230c that is in contact with the top surface of insulator 224. Region F also includes oxide 230b.

[0494] In the regions A to E shown in FIGS. 25 and 26(A) to 26(E), the oxide 230 c was formed with a very thin film thickness of about 2 to 5 nm. 26(E), the oxide 230c has a layered structure in any region. The arrows shown in Figures 26(A) to 26(E) indicate the direction of the CAAC-OS. , the arrow indicates a direction approximately perpendicular to the oxide film 230c. This roughly coincides with the normal direction of the layered crystal, that is, the c-axis direction of the CAAC-OS. , the CAAC-OS of the oxide 230c is formed on the surface on which the oxide 230c is formed or the oxide 230c It can be seen that the molecules are aligned along the unevenness of the film surface.

[0495] As shown in Figures 25 and 26(F), the layered crystals also have an insulating The oxide 230b is arranged approximately parallel to the upper surface of the oxide 230b. It can be seen that the oxide 230b is arranged along the surface on which it is formed or along the film surface.

[0496] From the above, in sample 1, region F corresponding to region 54 in FIG. 10(B) is 10(B) has a crystal structure shown in FIG. 10(E), and a region C corresponding to the region 55 in FIG. 10(B) has a crystal structure shown in FIG. It is assumed that Sample 1 has a crystalline structure. Therefore, Sample 1 has the schematic band shown in FIG. Since the model in the diagram is satisfied, it is thought that the suppression of carrier transmission can be prevented. can be.

[0497] At least a part of the configurations, methods, etc. shown in the present embodiment are described in this specification. The present invention can be implemented in appropriate combination with the embodiment modes and examples. [Example]

[0498] In this example, the crystal structure of a metal oxide according to one embodiment of the present invention was evaluated. Specifically, a high-angle scattering annular dark-field scanning transmission electron microscope (STEM) was used to measure the metal oxide-formed sample 2. Mirror(HAADF-STEM:High-Angle Annular Dark Fie ld Scanning Transmission Electron Micros cope) images and energy dispersive X-ray spectroscopy (EDX) Elemental analysis was performed using transversive X-ray spectroscopy. Ta.

[0499] First, a method for preparing Sample 2 will be described.

[0500] Sputtered as metal oxides onto yttria-stabilized zirconia (YSZ) substrates In-Ga-Zn oxide was deposited to a thickness of 100 nm by the method. For the deposition of the oxide, an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1 was used. The oxygen gas flow rate was set to 30 sccm, the pressure was set to 0.4 Pa, and the DC power supply was set to 200 W. The substrate temperature was set to 300°C.

[0501] Next, a heat treatment was carried out. The heat treatment was carried out in an oxygen-containing atmosphere at a temperature of 1200°C for 1 Time processing was performed.

[0502] In this way, Sample 2 was prepared.

[0503] A HAADF-STEM image of the prepared sample 2 was acquired. Acquisition of HAADF-STEM image An atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. was used for the analysis.

[0504] The brightness of a point observed in a HAADF-STEM image is a function of the atomic number of the atom corresponding to that point. In other words, the points corresponding to atoms with higher atomic numbers are whiter. In In-Ga-Zn oxide, the atomic number is In The largest is Ga and Zn, and the smallest is O. The brightness of the points corresponding to Ga and Zn is higher than that of In. The brightness of the points corresponding to O is very low and appears darker than the points corresponding to In. It can be difficult to locate O because it is so low.

[0505] The right side of Figure 27 shows a cross-sectional HAADF-STEM image of sample 2. The vertical direction of the paper is the metal The normal direction of the oxide formation surface (YSZ substrate surface), and the left-right and normal directions of the paper. is a direction parallel to the surface on which the metal oxide is formed (the surface of the YSZ substrate).

[0506] The cross-sectional HAADF-STEM image shown on the right side of Figure 27 shows that the metal oxide formed on sample 2 It was confirmed that a layered structure was formed. Also, points with different brightness were observed. The points with relatively high brightness correspond to In, and the points with relatively low brightness correspond to Ga or It is estimated that the point corresponds to Zn. In addition, points with similar brightness are located in the left and right directions of the paper. The rows of relatively bright spots aligned horizontally on the paper surface are called In The relatively low brightness points aligned horizontally on the paper are the (Ga,Zn)O layer. It is estimated that there are rows of relatively bright points aligned in the left and right directions of the paper, and rows of relatively bright points aligned in the left and right directions of the paper. The rows of low intensity dots aligned horizontally on the paper surface were observed alternating with the rows of low intensity dots aligned vertically on the paper surface. Therefore, in the metal oxide formed in Sample 2, the InO layer and the (Ga, Zn)O layer were stacked. It was confirmed that a layered structure was formed.

[0507] Next, elemental analysis of sample 2 was performed using EDX. The process of measuring while doing so and evaluating the area in two dimensions is sometimes called EDX area analysis. From the EDX area analysis, data on linear regions are extracted and the distribution of atomic concentrations within the regions is evaluated. The evaluation of the sample is sometimes called EDX analysis.

[0508] The elemental analysis equipment used was an energy dispersive X-ray analyzer JED manufactured by JEOL Ltd. A Si drift detector was used to detect the X-rays emitted from the sample. Used.

[0509] The cross-sectional HAADF-STEM image shown on the right side of Figure 27 was taken in the same area. The results of the EDX analysis are shown on the left side of FIG. 27. In the left side of FIG. 27, the vertical axis is the normal to the surface on which the metal oxide is to be formed (YSZ substrate surface) from the reference position (0 nm). The horizontal axis indicates the distance in the direction (nm). Shows the composition ratio [atomic%].

[0510] From Figure 27, the row with relatively high brightness points aligned horizontally on the page has the highest ratio of In. The relatively low brightness points are located to the left and right of the page. The columns aligned in the direction of the SiO2 layer are (Ga,Zn)O layers because the proportion of Ga or Zn is high. In addition, the relatively low brightness points aligned horizontally on the paper also indicate that the 15atom The detection of about mic% In indicates that In is mixed in the (Ga,Zn)O layer. It was confirmed that:

[0511] From the above, in the In-Ga-Zn oxide, the InO layer and the (Ga, Zn)O layer are stacked. A layered structure was confirmed.

[0512] The configurations, methods, etc. shown in this example may be at least partially similar to other examples described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. [Example]

[0513] In this example, the operating frequency was estimated for the DOSRAM shown in the fourth embodiment.

[0514] "Allowable voltage fluctuation," one of the specifications required for DOSRAM, is the capacity of DOSRAM. The DOSR is the tolerance for the amount of change in the voltage applied to the capacitance element after data is written. The "data retention time" of AM is the amount of fluctuation in the voltage applied to the capacitance element of DOSRAM. This is the time required to reach the allowable voltage fluctuation. In this example, the "allowable voltage fluctuation" is set to 0. 2V, and the "data retention time" is the voltage applied to the capacitance element (retention capacitance 3.5fF) until the data This is the time required for the voltage to drop by 0.2 V from the state after writing. If the data retention time of OSRAM is 1 hour, the voltage applied to the capacitance element of the OSRAM is This means that it takes 1 hour for the voltage to drop by 0.2V after writing data. .

[0515] The data retention time of DOSRAM is determined by the cutoff voltage of the transistors in the DOSRAM. Here, the cut-off current of a transistor depends on the magnitude of the gate current of the transistor. Port voltage V G = 0V, the drain current I D (hereinafter referred to as Icut) For example, the data retention characteristics of DOSRAM can be If the data retention time of DOSRAM depends only on the size of the Icut of the DOS register, It is inversely proportional to the size of Icut of the transistors in the SRAM.

[0516] If the Icut of the transistors in the DOSRAM is known, The data retention time is the amount of charge lost from the capacitor during data retention (the retention capacity of the capacitor (3. 0.7fC), which is equivalent to the product of the capacitance (0.5fF) and the voltage drop across the capacitance element (0.2V). It can be calculated by dividing by Icut. By setting the retention time and dividing the charge amount 0.7 fC by the retention time, DOSRAM The value of Icut required for the transistor (hereinafter referred to as Icut0) is estimated. If the target retention time is 1 hour, the Icut required for the transistor is is approximately 200 zA (200 x 10 -21 A) Icut0 shown in Figure 28 is 200z By adjusting the back gate voltage so that A is obtained, it is possible to obtain high data retention characteristics and In this embodiment, a DOSRAM having a high operating frequency over a wide temperature range can be obtained. We evaluated the relationship between the back gate voltage and the operating frequency of DOSRAM.

[0517] In estimating the operating frequency of DOSRAM, the transistors shown in Figs. A transistor (hereinafter referred to as sample 3) having the same configuration as the transistor 10d was fabricated, and its voltage was measured. In this example, the parameters necessary for estimation were extracted from the electrical characteristics. Assuming that transistor 10d is used as transistor M1, the operating frequency of DOSRAM is estimated. It was.

[0518] First, the structure of sample 3 will be described. As shown in FIGS. 9 and 10, sample 3 is An insulator 224 disposed on a plate (not shown) and an oxide disposed on the insulator 224. 230b, an oxide 230c disposed on the oxide 230b, and an oxide 230c disposed on the oxide 230c. The insulating layer 250 has an insulator 250 disposed thereon, and a conductor 260 disposed on the insulator 250 . Although not shown in FIGS. 9 and 10, Sample 3 is a transistor 2 shown in FIG. Similar to 00, the oxide 230a is located between the insulator 224 and the oxide 230b. The conductor 260 is a laminated film of a conductor 260a and a conductor 260b.

[0519] The insulator 224 was made of silicon oxynitride with a film thickness of 35 nm.

[0520] The oxide 230a is an In film having a thickness of 5 nm, which is formed by DC sputtering. The oxide 230a was formed using In:Ga:Zn=1 An oxide target with an atomic ratio of 3:4 was used, and 45 sccm of oxygen gas was used as the deposition gas. The deposition pressure was set to 0.7 Pa, the deposition power was set to 500 W, and the substrate temperature was set to 200°C. The distance between the target and the substrate was set to 60 mm.

[0521] The oxide 230b is a 20 nm thick I film formed by DC sputtering. The oxide 230b was formed using an n-Ga-Zn oxide. An oxide target with an atomic ratio of 4:2:4.1 was used, and argon gas was used as the deposition gas. The deposition pressure was 0.7 Pa and the deposition power was 5 The power was set to 100 W, the substrate temperature was set to 200° C., and the distance between the target and the substrate was set to 60 mm.

[0522] The oxide 230c is an In film having a thickness of 5 nm, which is formed by DC sputtering. The oxide 230c was formed using In:Ga:Zn=4 An oxide target with an atomic ratio of 2:4.1 was used, and oxygen gas was used for 45 seconds. ccm, the deposition pressure was 0.7 Pa, the deposition power was 500 W, and the substrate temperature was 130 ° C., and the distance between the target and the substrate was 60 mm.

[0523] The insulator 250 was made of silicon oxynitride with a film thickness of 8 nm. Titanium nitride with a film thickness of 10 nm was used as the conductor 260b. We used

[0524] Sample 3 having the above-described configuration has a channel length of 0.37 μm and a channel width of 0.24 μm. Note that Sample 3 is a transistor having the above structure, similar to the transistor 200. In addition, the insulator 214, the insulator 216, the conductor 205, the insulator 222, the conductor 24 2, insulator 254, conductor 240, insulator 280, insulator 274, insulator 281, etc. do.

[0525] Next, in sample 3, the I D -V G Measurements were taken. D -V G measurement The drain potential V D to +1.08V, and the source potential V S to 0V, Port potential V G The back gate voltage was swept from -1.0V to +3.3V. V BG The measurement was performed at -7.1 V. The measurement temperature was three levels: -40°C, 27°C, and 85°C. Specifically, a 5-inch square substrate on which the transistor to be measured is formed is heated to each of the temperatures mentioned above. The I of the transistor is fixed on the set thermo chuck. D -V G Measurements were carried out. Furthermore, measurements were carried out on three elements at each measurement temperature.

[0526] Obtained I D -V G From the curve, the transistor shift voltage (Vsh) and subthreshold voltage The threshold swing value (S value) was calculated. Vsh is the I D - V G In a curve, the tangent at the point on the curve where the slope is maximum is I D =1pA direct current V crossing a line G Also, S value is the drain voltage at a constant value. This refers to the amount of change in gate voltage in the subthreshold region that changes the current by one order of magnitude.

[0527] As described in the second embodiment, the transistor 10d has a channel formation region formed of a metal oxide A transistor using a metal oxide in the channel formation region is, for example, Compared to transistors that use Si in the hole formation region, the leakage current in the non-conducting state is extremely low. Therefore, the transistors using metal oxide in the channel formation region have Therefore, it may be difficult to detect Icut. Since it was difficult to measure the actual D -V G Vsh and Sval obtained from the curve From ue, Icut was estimated by extrapolation using equation (1). As shown, the off-state current of the transistor is V G = 0V according to the S value. D is assumed to be monotonically decreasing.

[0528]

number

[0529] Next, the I of transistor 10d D -V S Measurements were taken.

[0530] Here, a method for estimating the DOSRAM operating frequency will be explained. The frequency is the reciprocal of the data write cycle time of DOSRAM. The data write cycle time is set based on the charging time of the capacitance element of the DOSRAM. In this embodiment, the data write cycle time of the DOSRAM is The time equivalent to 40% of the DOSRAM operating frequency (the inverse of the DOSRAM operating frequency) is The time was set to the charging time of the quantum element.

[0531] The operating frequency of DOSRAM depends on the charging time of the capacitance element of DOSRAM. Therefore, when estimating the DOSRAM operating frequency, the capacitance element of the DOSRAM must be considered first. In this embodiment, the charge time of the DOSRAM is known in advance. The state in which a potential of 0.52V or more is applied to the storage capacitor (3.5fF) is called the "charge" state. Therefore, in this embodiment, the data write operation of the DOSRAM is defined as "a state in which the data is written to the DOSRAM." The time from when the operation starts until the potential applied to the capacitor element reaches 0.52V is This corresponds to the charging time of the capacitance element in the SRAM.

[0532] The charging time of the capacitance element of DOSRAM is , I of the transistors in DOSRAM D Therefore, in this embodiment, It is assumed that the transistors in the DOSRAM are affected when writing data to the DOSRAM. The potential (see FIG. 29A) of the transistor according to one embodiment of the present invention (L / W=0. 37 / 0.24μm) to reproduce the DOSRAM data write operation. , the I of the transistor at this time D FIG. 29(A) shows the capacitance element of FIG. It is assumed that data is written to CA through transistor M1. D is the drain. where G represents the gate and S represents the source. The source potential of transistor Tr1 (voltage applied to the capacitance element Cs) is V S By turning on the transistor Tr1, And the current I D Specifically, the gate voltage of the transistor The drain potential Vg is set to +2.97V, the drain potential Vd is set to +1.08V, and the source potential V S From 0V By sweeping the voltage from +1.2V to +1.2V, the transistorD Measurement was performed. Back gate voltage V BG The measurement was performed at -7.1 V. The measurement was performed at three temperatures: -40°C, 27°C, and 85°C.

[0533] The DOSRAM has a channel length (L) of 60 nm and a channel width (W) of 60 nm. A configuration including a transistor and a capacitance element with a storage capacitance of 3.5 fF was assumed. I obtained from transistor 10d (L / W=0.37μm / 0.24μm) D The value of The size of the transistor (L / W=60 / 60nm) assumed to be used in DOSRAM is used as a compensation. Corrected.

[0534] DOSRAM starts charging and V S is the write determination voltage V CS Charging is complete when it reaches This time is the charging time t W (See Figure 29(B)). The charge stored in the capacitance element of the storage capacitance Cs [F] is Q [C], and the charging time is t W [sec ], and the potential applied to the capacitance element by charging is V CS (=Vs) [V], DOSRAM has The drain current of the transistor is I D When [A] is used, the following formula is used between each parameter. The relationship (2) holds.

[0535]

number

[0536] By modifying equation (2), the charging time t W The following formula (3) (see Figure 29(C)).

[0537]

number

[0538] In this example, Cs in formula (3) is 3.5 fF, V CS +0.52V to the aforementioned I D -V S The measured I D Substituting the above, the charging time t W Calculate Ta.

[0539] The operating frequency f and charging time t of the storage device 1400 W The relationship can be expressed by equation (4) .

[0540]

number

[0541] In equation (4), A is a coefficient. Since the time required for writing is estimated to be 40%, in this embodiment, coefficient A is set to 0.4. The operating frequency f was calculated using the above formula.

[0542] In sample 3, the D when the power supply voltage was 3.3 V and the back gate voltage was -7.1 V The operating frequency of the OSRAM is shown in Fig. 30 and Fig. 31. In Fig. 30, the horizontal axis is the temperature (T The vertical axis indicates the operating frequency [MHz]. In 1, the horizontal axis is the inverse of the temperature (1000 / Temperature) [K -1 ] The horizontal axis represents the operating frequency [MHz]. As shown in Figs. 30 and 31, the higher the temperature, the As shown in Figure 31, the operating frequency increases as the By extrapolating the frequency, it is estimated that the operating frequency at 200°C will be 1 GHz or more. It was stolen.

[0543] From the above, it is possible to use metal oxide in the channel formation region of the transistor in DOSRAM. By doing so, we found that the higher the temperature, the higher the operating frequency of the DOSRAM.

[0544] The configurations, methods, etc. shown in this example may be at least partially similar to other examples described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. [Example]

[0545] In this example, we evaluated the temperature dependence of the carrier concentration and Hall mobility of metal oxides. Specifically, the Hall effect was measured at different temperatures for Sample 4, which was a metal oxide film. The carrier concentration and Hall effect of the metal oxide at each temperature were measured using the results. The mobility was calculated.

[0546] Here, the Hall effect measurement is performed by applying a voltage perpendicular to the direction of the current to an object through which a current is flowing. By applying a magnetic field, an electromotive force appears in the direction perpendicular to both the current and the magnetic field. This method utilizes the results to measure electrical properties such as carrier density, mobility, and resistivity. Here, the Hall effect was measured using the Van der Pauw method. lResiTest manufactured by Toyo Corporation was used to measure the effectiveness.

[0547] First, a method for preparing Sample 4 will be described.

[0548] Silicon nitride is deposited on a glass substrate to a thickness of 400 nm. A silicon oxynitride film was formed to a thickness of 50 nm.

[0549] Next, a sputtered metal oxide film was applied to the silicon oxynitride. An In-Ga-Zn oxide film was formed to a thickness of 35 nm by the etching method. The oxide film was formed using an oxide target with an atomic ratio of In:Ga:Zn=1:1:1. The argon gas flow rate was 20 sccm, the oxygen gas flow rate was 10 sccm, and the pressure was 0. The pressure was 4 Pa, the DC power supply was 200 W, and the substrate temperature was 300°C.

[0550] Next, a heat treatment was carried out at a temperature of 450°C for 1 hour in a nitrogen-containing atmosphere. Then, the material was treated in an atmosphere containing oxygen and nitrogen at 450°C for 1 hour. went.

[0551] In this way, Sample 4 was prepared.

[0552] For the prepared sample 4, the temperature range from 159°C to 239°C was changed in increments of approximately 10°C. All effect measurements were performed.

[0553] FIG. 32(A) shows the change in carrier concentration of the metal oxide with respect to the measurement temperature. , the reciprocal of the measured temperature (1000 / Temperature) [K -1 ] and the vertical axis indicates the Carrier concentration of metal oxide [cm -3 ] is shown.

[0554] From Figure 32(A), the smaller the reciprocal of the measurement temperature (the higher the measurement temperature), the more the catalytic activity of the metal oxide It was found that the carrier concentration increased.

[0555] FIG. 32(B) shows the transition of the Hall mobility of the metal oxide with respect to the measurement temperature. The horizontal axis is the reciprocal of the measurement temperature (1000 / Temperature) [K -1 ] and vertical The axis represents the Hall mobility of the metal oxide [cm 2 / (V·s)].

[0556] From Figure 32(B), the smaller the reciprocal of the measurement temperature (the higher the measurement temperature), the more the H It was found that the mobility of all

[0557] From the above, it was confirmed that the higher the temperature, the higher the mobility of metal oxides tends to be.

[0558] The configurations, methods, etc. shown in this example may be at least partially similar to other examples described in this specification. The present invention can be implemented in appropriate combination with the embodiments and examples. [Explanation of symbols]

[0559] 10: transistor, 10a: transistor, 10b: transistor, 10c: transistor sta, 10d: transistor, 51: region, 52: region, 53: region, 54: region, 55 : area, 100: capacitance element, 110: conductor, 112: conductor, 120: conductor, 130 : insulator, 140: insulator, 150: insulator, 200: transistor, 200A: transistor 200B: transistor, 200C: transistor, 205: conductor, 210: Insulator, 212: Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224: Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 23 0c: oxide, 230c1: oxide, 230c2: oxide, 231: region, 231a: region area, 231b: area, 234: area, 240: conductor, 240a: conductor, 240b: conductor Conductor, 241: insulator, 241a: insulator, 241b: insulator, 242: conductor, 242 a: conductor, 242b: conductor, 243: region, 243a: region, 243b: region, 24 4a: Barrier film, 244b: Barrier film, 250: Insulator, 254: Insulator, 254a: Insulator Insulator, 254b: Insulator, 254c: Insulator, 260: Conductor, 260a: Conductor, 26 0b: conductor, 273: insulator, 274: insulator, 280: insulator, 280a: insulator, 280b: insulator, 281: insulator, 282: insulator, 300: transistor, 311: Substrate, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 315: insulating region Insulator, 316: conductor, 320: insulator, 322: insulator, 324: insulator, 326: insulator Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator Insulator, 356: Conductor, 400: Transistor, 405: Conductor, 424a: Insulator, 4 24b: insulator, 430c: oxide, 431a: oxide, 431b: oxide, 432a: Oxide, 432b: oxide, 440: conductor, 440a: conductor, 440b: conductor, 4 42: Conductor, 442a: Conductor, 442b: Conductor, 450: Insulator, 460: Conductor , 460a: conductor, 460b: conductor, 1001: wiring, 1002: wiring, 1003: Wiring, 1004: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring, 1009: Wiring, 1010: Wiring

Claims

1. a crystalline metal oxide; A transistor having a gate, a source, and a drain, the crystalline metal oxide has a first layer and a second layer; the first layer has a wider bandgap than the second layer; the first layer and the second layer form a crystal lattice; As the temperature increases, the crystalline metal oxide increases the thickness of the first layer in the c-axis direction, A transistor in which, as the temperature increases, the thickness of the second layer in the c-axis direction of the crystalline metal oxide decreases.

2. In claim 1, the crystalline metal oxide comprises a first metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide; The first metal oxide, the second metal oxide, and the third metal oxide each have the first layer and the second layer.

3. In claim 2, A transistor in which the first layer of the second metal oxide and the second layer of the second metal oxide are each arranged approximately parallel to a surface on which the second metal oxide is to be formed.

Images