Anomaly detection device

Abstract

To provide an abnormality detection device capable of detecting minute processing abnormalities and predicting failure of the entire device by detecting minute processing abnormalities.SOLUTION: An abnormality detection device 2 that detects a processing abnormality in a semiconductor wafer W that is heat-treated in a heat treatment device 160 includes a lower radiation thermometer 20 that measures the temperature of the semiconductor wafer W during heat treatment, a processing information acquisition unit 90 (each sensor) that obtains a plurality of pieces of processing information having a correlation with the temperature measured by the lower radiation thermometer 20, and a detection unit 32c that divides heat treatment of the semiconductor wafer W into a plurality of phases (heat treatment phases F1 to 7), and detects a processing abnormality of the semiconductor wafer W on the basis of a plurality of learning models created for each of a plurality of phases (heat treatment phases F1 to 7) on the basis of the temperature and the processing information.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to an anomaly detection device that detects processing anomalies in thin precision electronic substrates (hereinafter simply referred to as "substrates") such as semiconductor wafers that are heat-treated in a heat treatment device. [Background technology]

[0002] Patent Document 1 discloses an anomaly detection device that detects processing anomalies in substrates undergoing heat treatment. Patent Document 1 describes a device that detects damage to a semiconductor wafer by measuring the temperature of the top and / or bottom surfaces of the semiconductor wafer during the cooling period of the semiconductor wafer. This device achieves detection of damage to the semiconductor wafer by the difference between the value of an estimated cooling model parameter and the value obtained from temperature measurement data of the semiconductor wafer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-536284 Summary of the Invention [Problem to be solved by the invention]

[0004] In an apparatus such as that described in Patent Document 1, which detects anomalies by comparing the difference between the model parameter value and the actual measured value and determining whether the difference is within a threshold range, it has been difficult to detect processing anomalies with slight changes. For example, it has been difficult to detect a decrease in the output of one of the lamps that is a heat source for heating a substrate.

[0005] In response to this, attempts have been made to develop devices that detect abnormalities by comparing reference values ​​and actual measured values ​​for lamp output. However, even with such devices, it is difficult to distinguish between noise and a change of a few degrees in substrate temperature or a change of a few percent in lamp output.

[0006] The present invention has been made in view of the above-mentioned problems, and aims to provide an anomaly detection device that can detect minute processing anomalies and predict failure of the entire device by detecting minute processing anomalies. [Means for solving the problem]

[0007] In order to solve the above problem, the invention of claim 1 is an abnormality detection device that detects processing abnormalities of a substrate being heat-treated in a heat treatment device, a chamber for accommodating the substrate; a preheating unit for irradiating the substrate accommodated in the chamber with light to preheat the substrate; and a main heating unit for irradiating the substrate with light to bring the substrate to a processing temperature; a thermometer that measures the temperature of the substrate during heat treatment; a processing information acquisition unit that acquires a plurality of pieces of processing information that are correlated with the temperature measured by the thermometer; and a detection unit that divides the heat treatment of the substrate into a plurality of phases and detects a processing abnormality of the substrate based on a plurality of learning models created for each of the plurality of phases based on the temperature and the processing information. The plurality of pieces of processing information include two or more parameters selected from the group consisting of the temperature of the quartz parts in the chamber, the temperature of the wall surface of the chamber, the power supplied to the preheating unit, the intensity of light from the preheating unit, and the amount of processing gas supplied to the inside of the chamber. It is characterized by:

[0009] Also, claims 2 The invention is 1 In the anomaly detection device according to the present invention, the plurality of phases include at least a phase in which the temperature is increased by the preheating unit, a phase in which the temperature is maintained constant by the preheating unit, and a phase in which the temperature of the substrate is decreased after heating by the preheating unit and the main heating unit is completed.

[0010] Also, claims 3 The invention of claim 1 or claim 2 In this anomaly detection device, the detection unit detects a processing anomaly by comparing predicted values ​​obtained from the learning model with actual measured values ​​related to the plurality of processing information for each of the plurality of phases.

[0011] Also, claims 4 The invention is 3 In the anomaly detection device according to the present invention, the detection unit determines that a processing anomaly has occurred when the actual measurement value deviates from the predicted value obtained from the learning model by more than a predetermined threshold.

[0012] Also, claims 5 The invention is 4 The abnormality detection device according to the present invention is characterized in that it further comprises an alarm issuing unit that issues an alarm when the detection unit detects a processing abnormality. [Effects of the Invention]

[0013] Claim 1 , claim 3, and claim 4 According to the invention described in the above, processing abnormalities of substrates are detected based on a plurality of learning models created for each of a plurality of phases, thereby making it possible to detect minor processing abnormalities and to predict failures of the entire device based on the detection of minor processing abnormalities.

[0014] Claim 2 According to the invention described above, the preheating section is divided into characteristic phases, so that a learning model can be created for each characteristic phase.

[0015] Claim 5 According to the invention described in the above, since the alarm unit that issues an alarm when a processing abnormality is detected is provided, the operator of the device can smoothly detect the processing abnormality. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a cross-sectional view schematically showing the configuration of a heat treatment apparatus according to a first embodiment. [Figure 2] FIG. 2 is a perspective view showing the overall appearance of the holding portion. [Figure 3] FIG. [Figure 4] FIG. 2 is a cross-sectional view of a susceptor. [Figure 5] FIG. [Figure 6] FIG. [Figure 7] FIG. 2 is a plan view showing the arrangement of a plurality of halogen lamps in the halogen heating unit. [Figure 8] FIG. 2 is a functional block diagram illustrating an electrical configuration of a heat treatment apparatus including an abnormality detection device. [Figure 9] 1 is a table showing the phases used when creating a learning model in the first embodiment. [Figure 10] 10 is a flowchart illustrating a processing procedure for creating a learning model by the anomaly detection device. [Figure 11] 10 is a flowchart showing a procedure for detecting a processing abnormality by the abnormality detection device. [Figure 12] 10 is a table showing the phases used when creating a learning model in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following embodiments, detailed features are shown for technical explanation, but they are merely examples and are not necessarily essential features for enabling the embodiments to be implemented.

[0018] The drawings are schematic, and for the sake of convenience, components may be omitted or simplified as appropriate. Furthermore, the relative sizes and positions of components shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. Hatching may also be used in drawings such as plan views that are not cross-sectional views to facilitate understanding of the embodiments.

[0019] In the following description, the same components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions of them may be omitted to avoid duplication.

[0020] Furthermore, in the following description, when a certain component is described as "comprising," "including," or "having," unless otherwise specified, this is not an exclusive expression that excludes the presence of other components.

[0021] Furthermore, in the following description, even if ordinal numbers such as "first" or "second" are used, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and are not limited to the order that may result from these ordinal numbers.

[0022] Furthermore, in the following description, expressions indicating relative or absolute positional relationships, such as "in one direction," "along one direction," "parallel," "orthogonal," "center," "concentric," or "coaxial," unless otherwise specified, include cases where the positional relationship is strictly indicated and cases where the angle or distance is displaced within a tolerance or within a range where equivalent functionality is obtained.

[0023] Furthermore, in the following description, expressions indicating an equal state, such as "same," "equal," "uniform," or "homogeneous," unless otherwise specified, include cases indicating an exact equal state, as well as cases where there is a difference within a tolerance or within a range where the same level of functionality is obtained.

[0024] Furthermore, in the following description, terms that indicate specific positions or directions, such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back," may be used; however, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and have no relation to the positions or directions when actually implemented.

[0025] Furthermore, in the following explanation, when "the upper surface of ..." or "the lower surface of ..." is written, it includes not only the upper surface or lower surface of the target component itself, but also a state in which another component is formed on the upper surface or lower surface of the target component. In other words, for example, when it is written as "Part B provided on the upper surface of Part A," it does not prevent another component "Part C" from being interposed between Part A and Part B.

[0026] First Embodiment The abnormality detection device for a heat treatment apparatus according to the first embodiment will be described below.

[0027] <Configuration of Heat Treatment Device 160> FIG. 1 is a cross-sectional view schematically showing the configuration of a heat treatment apparatus 160 according to the first embodiment.

[0028] As shown in FIG. 1, the heat treatment apparatus 160 of this embodiment is an apparatus that heats a disk-shaped semiconductor wafer W as a substrate by irradiating the semiconductor wafer W with light.

[0029] The size of the semiconductor wafer W to be processed is not particularly limited, but is, for example, φ300 mm or φ450 mm (φ300 mm in this embodiment).

[0030] The heat treatment apparatus 160 includes a chamber 161 that accommodates a semiconductor wafer W, a flash heating unit 5 incorporating multiple flash lamps FL as a main heating unit, and a halogen heating unit 4 incorporating multiple halogen lamps HL as a preheating unit. The flash heating unit 5 is provided above the chamber 161, and the halogen heating unit 4 is provided below it. The heat treatment apparatus 160 also includes a control unit 3 that controls the halogen heating unit 4, the flash heating unit 5, and the various operating mechanisms provided in the chamber 161 to perform heat treatment on the semiconductor wafer W. In this embodiment, the control unit 3 includes an abnormality detection device 2 that detects abnormalities in the heat treatment apparatus 160. In this embodiment, the halogen heating unit 4 includes multiple halogen lamps HL, but arc lamps or light-emitting diodes (LEDs) may be used instead of the halogen lamps HL. With the above-described configuration, the semiconductor wafer W is heated while housed in the chamber.

[0031] The plurality of flash lamps FL emit flashes of light to heat the semiconductor wafer W. The plurality of halogen lamps HL heat the semiconductor wafer W continuously.

[0032] The heat treatment apparatus 160 also includes, inside the chamber 161, a holder 7 that holds the semiconductor wafer W in a horizontal position, and a transfer mechanism 10 that transfers the semiconductor wafer W between the holder 7 and the outside of the apparatus.

[0033] The chamber 161 is closed by an upper chamber window 63 made of quartz attached to the top surface of the chamber housing (chamber side portion 61).

[0034] The upper chamber window 63 that constitutes the ceiling of the chamber 161 is a disk-shaped member made of quartz, and functions as a quartz window that transmits the light emitted from the flash heating unit 5 into the chamber 161.

[0035] The lower chamber window 64 that forms the floor of the chamber 161 is also a disk-shaped member made of quartz, and functions as a quartz window that transmits light from the halogen heating unit 4 into the chamber 161 .

[0036] Furthermore, a reflecting ring 68 is attached to the upper part of the inner wall surface of the chamber side part 61, and a reflecting ring 69 is attached to the lower part. Both the reflecting ring 68 and the reflecting ring 69 are formed in an annular shape.

[0037] The upper reflecting ring 68 is attached by fitting it from the top side of the chamber side part 61. On the other hand, the lower reflecting ring 69 is attached by fitting it from the bottom side of the chamber side part 61 and fastening it with screws (not shown). In other words, both the reflecting ring 68 and the reflecting ring 69 are detachably attached to the chamber side part 61.

[0038] The inner space of the chamber 161, that is, the space surrounded by the upper chamber window 63, the chamber housing (chamber side portion 61), and the reflecting ring 68, is defined as a heat treatment space 65.

[0039] By attaching the reflecting ring 68 and the reflecting ring 69 to the chamber side part 61, a recess 62 is formed on the inner wall surface of the chamber 161. In other words, the recess 62 is formed by the central part of the inner wall surface of the chamber side part 61 where the reflecting ring 68 and the reflecting ring 69 are not attached, the lower end surface of the reflecting ring 68, and the upper end surface of the reflecting ring 69.

[0040] The recess 62 is formed in a circular ring shape along the horizontal direction on the inner wall surface of the chamber 161, and surrounds the holder 7 that holds the semiconductor wafer W. The chamber side portion 61 and the reflecting ring 68 and the reflecting ring 69 are made of a metal material (e.g., stainless steel) that has excellent strength and heat resistance.

[0041] Furthermore, a transfer opening (furnace port) 66 is formed in the chamber housing (chamber side portion 61) for carrying the semiconductor wafer W into and out of the chamber 161. The transfer opening 66 can be opened and closed by a gate valve 162. The transfer opening 66 is connected to the outer circumferential surface of the recess 62.

[0042] Therefore, when the gate valve 162 opens the transfer opening 66, the semiconductor wafer W can be carried into and out of the heat treatment space 65 through the transfer opening 66 and the recess 62. When the gate valve 162 closes the transfer opening 66, the heat treatment space 65 in the chamber 161 becomes an airtight space.

[0043] An upper radiation thermometer 25 and a lower radiation thermometer 20 are attached to the outer wall surface of the chamber side portion 61 at positions where through holes 61a and 61b are provided. The through hole 61a is a cylindrical hole for guiding infrared light radiated from the upper surface of a semiconductor wafer W held on a susceptor 74 (described later) to the upper radiation thermometer 25. The through hole 61b is a cylindrical hole for guiding infrared light radiated from the lower surface of the semiconductor wafer W held on the susceptor 74 (described later) to the lower radiation thermometer 20. The through holes 61a and 61b are inclined with respect to the horizontal direction so that the axes of the through holes intersect with the main surface of the semiconductor wafer W held on the susceptor 74. A transparent window 26 made of calcium fluoride material that transmits infrared light in a wavelength range that can be measured by the upper radiation thermometer 25 is attached to the end of the through hole 61a facing the heat treatment space 65. Furthermore, a transparent window 21 made of barium fluoride material that transmits infrared light in the wavelength range that can be measured by the lower radiation thermometer 20 is attached to the end of the through hole 61b facing the heat treatment space 65.

[0044] The upper radiation thermometer 25 is installed diagonally above the semiconductor wafer W held on the susceptor 74, and measures the temperature of the upper surface by receiving infrared light emitted from the upper surface of the semiconductor wafer W. The infrared sensor 29 provided in the upper radiation thermometer 25 has an InSb (indium antimonide) optical element so as to be able to respond to the sudden temperature change on the upper surface of the semiconductor wafer W at the moment when the flash light is irradiated.

[0045] Meanwhile, lower radiation thermometer 20 is installed diagonally below semiconductor wafer W held on susceptor 74 and receives infrared light emitted from the underside of semiconductor wafer W to measure the temperature of the underside. Lower radiation thermometer 20 is equipped with infrared sensor 24, which measures the temperature of the underside of semiconductor wafer W. Temperature sensors 91, 92, 93, 94, and 95 are also installed in chamber 161. Of each of temperature sensors 91, 92, 93, 94, and 95, temperature sensor 91 measures susceptor 74, temperature sensor 92 measures the upper chamber window 63, temperature sensor 93 measures the lower chamber window 64, temperature sensor 94 measures the atmosphere inside the chamber, and temperature sensor 95 measures the wall surface of chamber 161.

[0046] Furthermore, gas supply holes 81 are formed in the upper part of the inner wall of the chamber 161 to supply processing gas to the heat treatment space 65. The gas supply holes 81 are formed at a position above the recessed portion 62, and may be provided in the reflecting ring 68. The gas supply holes 81 are connected to a gas supply pipe 83 via a buffer space 82 formed in an annular shape inside the side wall of the chamber 161.

[0047] The gas supply pipe 83 is connected to a processing gas supply source 85. A valve 84 is inserted in the gas supply pipe 83. When the valve 84 is opened, the processing gas is supplied from the processing gas supply source 85 to the buffer space 82. A flow meter 98 is connected downstream of the valve 84, and the flow rate of the processing gas passing through the valve 84 is measured by the flow meter 98.

[0048] The processing gas that has flowed into the buffer space 82 spreads within the buffer space 82, which has a smaller fluid resistance than the gas supply holes 81, and is supplied from the gas supply holes 81 into the heat treatment space 65. The processing gas may be an inert gas such as nitrogen (N2), or a reactive gas such as hydrogen (H2) or ammonia (NH3) (nitrogen in this embodiment).

[0049] Meanwhile, a gas exhaust hole 86 is formed in the lower part of the inner wall of the chamber 161 to exhaust gas from the heat treatment space 65. The gas exhaust hole 86 is formed at a position lower than the recess 62, and may be provided in the reflecting ring 69. The gas exhaust hole 86 is connected to a gas exhaust pipe 88 via a buffer space 87 formed in an annular shape inside the side wall of the chamber 161. The gas exhaust pipe 88 is connected to an exhaust mechanism 190. A valve 89 is inserted in the path of the gas exhaust pipe 88. When the valve 89 is opened, the gas in the heat treatment space 65 is exhausted from the gas exhaust hole 86 through the buffer space 87 to the gas exhaust pipe 88.

[0050] The gas supply holes 81 and the gas exhaust holes 86 may be provided in multiple numbers along the circumferential direction of the chamber 161, or may be slit-shaped. The process gas supply source 85 and the exhaust mechanism 190 may be mechanisms provided in the heat treatment device 160, or may be utilities of a factory where the heat treatment device 160 is installed.

[0051] A gas exhaust pipe 191 for discharging gas from the heat treatment space 65 is also connected to the tip of the transfer opening 66. The gas exhaust pipe 191 is connected to an exhaust mechanism 190 via a valve 192. By opening the valve 192, the gas in the chamber 161 is exhausted through the transfer opening 66.

[0052] 2 is a perspective view showing the overall appearance of the holder 7. The holder 7 is configured to include a base ring 71, a connecting portion 72, and a susceptor 74. The base ring 71, the connecting portion 72, and the susceptor 74 are all made of quartz. In other words, the entire holder 7 is made of quartz.

[0053] The base ring 71 is an arc-shaped quartz member with a portion missing from the annular shape. This missing portion is provided to prevent interference between the base ring 71 and a transfer arm 11 of the transfer mechanism 10, which will be described later. The base ring 71 is placed on the bottom surface of the recess 62, and is supported by the wall surface of the chamber 161 (see FIG. 3). A plurality of connecting portions 72 (four in this embodiment) are erected on the upper surface of the base ring 71 along the circumferential direction of the annular shape. The connecting portions 72 are also quartz members, and are fixed to the base ring 71 by welding.

[0054] The susceptor 74 is supported from below by four connecting portions 72 provided on the base ring 71. Fig. 3 is a plan view of the susceptor 74. Fig. 4 is a cross-sectional view of the susceptor 74.

[0055] The susceptor 74 includes a holding plate 75, a guide ring 76, and a plurality of support pins 77. The holding plate 75 is a substantially circular, flat member made of quartz. The diameter of the holding plate 75 is larger than the diameter of the semiconductor wafer W. That is, the holding plate 75 has a larger planar size than the semiconductor wafer W.

[0056] A guide ring 76 is installed on the periphery of the upper surface of the holding plate 75. The guide ring 76 is an annular member having an inner diameter larger than the diameter of the semiconductor wafer W. For example, if the diameter of the semiconductor wafer W is φ300 mm, the inner diameter of the guide ring 76 is φ320 mm.

[0057] The inner periphery of the guide ring 76 is formed into a tapered surface that widens upward from the holding plate 75. The guide ring 76 is made of quartz, the same as the holding plate 75.

[0058] The guide ring 76 may be welded to the upper surface of the holding plate 75, or may be fixed to the holding plate 75 by a separately processed pin or the like. Alternatively, the holding plate 75 and the guide ring 76 may be processed as an integrated member.

[0059] An area of ​​the upper surface of the holding plate 75 that is inside the guide ring 76 is a flat holding surface 75a that holds the semiconductor wafer W. A plurality of support pins 77 are provided on the holding surface 75a of the holding plate 75. In this embodiment, a total of 12 support pins 77 are provided in an annular shape at intervals of 30° along a circumference concentric with the outer circumferential circle of the holding surface 75a (the inner circumferential circle of the guide ring 76).

[0060] The diameter of the circle on which the 12 support pins 77 are arranged (the distance between opposing support pins 77) is smaller than the diameter of the semiconductor wafer W, and if the diameter of the semiconductor wafer W is φ300 mm, it is φ210 mm to φ280 mm. Three or more support pins 77 are provided. Each support pin 77 is made of quartz.

[0061] The plurality of support pins 77 may be provided on the upper surface of the holding plate 75 by welding, or may be machined integrally with the holding plate 75 .

[0062] Returning to FIG. 2, four connecting portions 72 erected on the base ring 71 are fixed to the peripheral edge of the holding plate 75 of the susceptor 74 by welding. That is, the susceptor 74 and the base ring 71 are fixedly connected by the connecting portions 72. The base ring 71 of the holding portion 7 is supported on the wall surface of the chamber 161, and the holding portion 7 is thereby attached to the chamber 161. When the holding portion 7 is attached to the chamber 161, the holding plate 75 of the susceptor 74 is in a horizontal position (a position in which the normal line coincides with the vertical direction). That is, the holding surface 75a of the holding plate 75 is in a horizontal plane.

[0063] The semiconductor wafer W carried into the chamber 161 is placed and held in a horizontal position on the upper side of the susceptor 74 of the holder 7 attached to the chamber 161. At this time, the semiconductor wafer W is supported by twelve support pins 77 erected on the holding plate 75, and is supported from below by the susceptor 74. More precisely, the upper ends of the twelve support pins 77 contact the lower surface (rear surface) of the semiconductor wafer W to support the semiconductor wafer W.

[0064] The twelve support pins 77 have a uniform height (the distance from the upper end of the support pin 77 to the holding surface 75a of the holding plate 75), so that the twelve support pins 77 can support the semiconductor wafer W in a horizontal position.

[0065] Furthermore, the semiconductor wafer W is supported by a plurality of support pins 77 at a predetermined distance from the holding surface 75a of the holding plate 75. The thickness of the guide ring 76 is greater than the height of the support pins 77. Therefore, the guide ring 76 prevents the semiconductor wafer W supported by the plurality of support pins 77 from shifting in the horizontal direction.

[0066] 2 and 3, an opening 78 is formed in the holding plate 75 of the susceptor 74, penetrating vertically. The opening 78 is provided so that the lower radiation thermometer 20 can receive radiant light (infrared light) emitted from the lower surface (rear surface) of the semiconductor wafer W. That is, the lower radiation thermometer 20 receives the light radiated from the lower surface (rear surface) of the semiconductor wafer W through the opening 78 and the transparent window 21 (attached to the through-hole 61b) of the chamber housing (chamber side portion 61), thereby measuring the temperature of the semiconductor wafer W.

[0067] Furthermore, the holding plate 75 of the susceptor 74 is provided with four through holes 79 through which lift pins 12 of the transfer mechanism 10 (described later) penetrate to transfer the semiconductor wafer W.

[0068] Fig. 5 is a plan view of the transfer mechanism 10. Fig. 6 is a side view of the transfer mechanism 10. The transfer mechanism 10 includes two transfer arms 11. The transfer arms 11 have an arc shape that fits along the generally annular recess 62.

[0069] Two lift pins 12 are erected on each transfer arm 11. The transfer arms 11 and the lift pins 12 are made of quartz. Each transfer arm 11 can be rotated by a horizontal movement mechanism 13. The horizontal movement mechanism 13 moves the pair of transfer arms 11 horizontally between a transfer operation position (position indicated by a solid line in FIG. 5) where the pair of transfer arms 11 transfer the semiconductor wafer W to the holder 7 and a retracted position (position indicated by a two-dot chain line in FIG. 5) where the pair of transfer arms 11 do not overlap the semiconductor wafer W held by the holder 7 in a plan view.

[0070] The horizontal movement mechanism 13 may be one that rotates each transfer arm 11 using an individual motor, or one that uses a link mechanism to rotate a pair of transfer arms 11 in unison using a single motor.

[0071] Furthermore, the pair of transfer arms 11 are moved up and down together with the horizontal movement mechanism 13 by the lifting mechanism 14. When the lifting mechanism 14 raises the pair of transfer arms 11 to the transfer operation position, a total of four lift pins 12 pass through through holes 79 (see FIGS. 2 and 3) formed in the susceptor 74, and the upper ends of the lift pins 12 protrude from the upper surface of the susceptor 74. Meanwhile, when the lifting mechanism 14 lowers the pair of transfer arms 11 to the transfer operation position to remove the lift pins 12 from the through holes 79, and the horizontal movement mechanism 13 moves the pair of transfer arms 11 to open them, each transfer arm 11 moves to the retracted position.

[0072] The retracted position of the pair of transfer arms 11 is directly above the base ring 71 of the holder 7. Since the base ring 71 is placed on the bottom surface of the recess 62, the retracted position of the transfer arms 11 is inside the recess 62. An exhaust mechanism (not shown) is also provided near the location where the drive parts (horizontal movement mechanism 13 and lifting mechanism 14) of the transfer mechanism 10 are provided, and is configured to exhaust the atmosphere around the drive parts of the transfer mechanism 10 to the outside of the chamber 161.

[0073] Returning to Figure 1, the flash heating unit 5 provided above the chamber 161 is configured to include a light source consisting of multiple (30 in this embodiment) xenon flash lamps FL inside a housing 51, and a reflector 52 provided to cover the light source from above.

[0074] Furthermore, a lamp light emission window 53 is attached to the bottom of the housing 51 of the flash heating unit 5. The lamp light emission window 53, which forms the floor of the flash heating unit 5, is a plate-shaped quartz window made of quartz. When the flash heating unit 5 is installed above the chamber 161, the lamp light emission window 53 faces the upper chamber window 63. The flash lamp FL irradiates flash light from above the chamber 161 through the lamp light emission window 53 and the upper chamber window 63 into the heat treatment space 65. A light intensity sensor 96 is attached to the lamp light emission window 53, and the light intensity sensor 96 detects the amount of light emitted from the flash lamp FL.

[0075] The multiple flash lamps FL are each a rod-shaped lamp having a long cylindrical shape, and are arranged in a plane so that their longitudinal directions are parallel to each other (i.e., along the horizontal direction) along the main surface (surface) of the semiconductor wafer W held by the holder 7. Therefore, the plane formed by the arrangement of the flash lamps FL is also a horizontal plane.

[0076] The flash lamp FL comprises a rod-shaped glass tube (discharge tube) filled with xenon gas and having an anode and a cathode connected to a capacitor at both ends, and a trigger electrode attached to the outer surface of the glass tube.

[0077] Xenon gas is an electrical insulator, so even if a charge is stored in the capacitor, no electricity flows through the glass tube under normal conditions. However, when a high voltage is applied to the trigger electrode to break down the insulation, the electricity stored in the capacitor flows instantaneously through the glass tube, exciting the xenon atoms or molecules and causing light to be emitted.

[0078] In such flash lamps FL, electrostatic energy stored in a capacitor is converted into extremely short light pulses of 0.1 to 100 milliseconds, which allows them to emit much stronger light than continuous light sources such as halogen lamps HL. In other words, flash lamps FL are pulsed lamps that emit light instantaneously for an extremely short period of time, less than one second. The light emission time of flash lamps FL can be adjusted by the coil constant of the lamp power supply that supplies power to the flash lamp FL.

[0079] Furthermore, reflector 52 is provided above the multiple flash lamps FL so as to cover them entirely. The basic function of reflector 52 is to reflect the flash light emitted from the multiple flash lamps FL toward the heat treatment space 65. Reflector 52 is made of an aluminum alloy plate, and its top surface (the surface facing the flash lamps FL) is roughened by blasting.

[0080] The halogen heating unit 4, which is provided below the chamber 161, has a plurality of halogen lamps HL (40 in this embodiment) built into the inside of the housing 41. The halogen heating unit 4 heats the semiconductor wafer W by irradiating light from the plurality of halogen lamps HL from below the chamber 161 through the lower chamber window 64 into the heat treatment space 65. A light intensity sensor 97 is attached to the top of the housing 41, and the light intensity sensor 97 detects the amount of light irradiated from the halogen lamps HL.

[0081] 7 is a plan view showing the arrangement of multiple halogen lamps HL in the halogen heating unit 4. The 40 halogen lamps HL are arranged in two rows, upper and lower. Twenty halogen lamps HL are arranged in the upper row, which is closer to the holder 7, and another 20 halogen lamps HL are arranged in the lower row, which is farther from the holder 7 than the upper row.

[0082] Each halogen lamp HL is a rod-shaped lamp having a long cylindrical shape. The 20 halogen lamps HL in both the upper and lower rows are arranged so that their longitudinal directions are parallel to each other (i.e., along the horizontal direction) along the main surface (front surface) of the semiconductor wafer W held by the holder 7. Therefore, the plane formed by the arrangement of the halogen lamps HL in both the upper and lower rows is a horizontal plane.

[0083] 7, the halogen lamps HL are arranged more densely in the region facing the periphery of the semiconductor wafer W held by the holder 7 on both the upper and lower tiers than in the region facing the center of the semiconductor wafer W. That is, on both the upper and lower tiers, the halogen lamps HL are arranged at a shorter pitch in the periphery of the lamp arrangement than in the center. This allows a greater amount of light to be irradiated onto the periphery of the semiconductor wafer W, which is prone to temperature drop during heating due to light irradiation from the halogen heating unit 4.

[0084] 1, a voltage is applied to each of the multiple halogen lamps HL from a power supply unit 49, causing the halogen lamp HL to emit light. The power supply unit 49 individually adjusts the power supplied to each of the multiple halogen lamps HL under the control of the control unit 3. In other words, the power supply unit 49 can individually adjust the emission intensity of each of the multiple halogen lamps HL arranged in the halogen heating unit 4.

[0085] The lamp group consisting of the halogen lamps HL on the upper row and the lamp group consisting of the halogen lamps HL on the lower row are arranged so as to intersect in a grid pattern. That is, a total of 40 halogen lamps HL are arranged so that the longitudinal direction of the 20 halogen lamps HL arranged on the upper row and the longitudinal direction of the 20 halogen lamps HL arranged on the lower row are perpendicular to each other.

[0086] The halogen lamp HL is a filament-type light source that emits light by passing electricity through a filament placed inside a glass tube, causing it to become incandescent. The glass tube is filled with an inert gas such as nitrogen or argon, to which a small amount of halogen element (iodine, bromine, etc.) has been added. By adding halogen element, it is possible to set the filament temperature to a high temperature while suppressing filament breakage.

[0087] Therefore, halogen lamps HL have the characteristics of having a longer lifespan than ordinary incandescent light bulbs and being able to continuously irradiate strong light. In other words, halogen lamps HL are continuously lit lamps that emit light for at least one second or more. Furthermore, because the halogen lamps HL are rod-shaped lamps, they have a long lifespan, and arranging the halogen lamps HL horizontally improves the radiation efficiency toward the semiconductor wafer W above. Also, within the housing 41 of the halogen heating unit 4, a reflector 43 is provided below the two-tiered halogen lamps HL (FIG. 3). The reflector 43 reflects the light emitted from the multiple halogen lamps HL toward the heat treatment space 65.

[0088] The heat treatment apparatus 160 is also equipped with various cooling structures to prevent excessive temperature rises in the halogen heating unit 4, flash heating unit 5, and chamber 161 due to the thermal energy generated by the halogen lamps HL and flash lamps FL during heat treatment of the semiconductor wafer W. For example, a water-cooled pipe (not shown) is provided in the wall of the chamber 161. The halogen heating unit 4 and flash heating unit 5 have an air-cooled structure that dissipates heat by creating a gas flow inside. Air is also supplied to the gap between the upper chamber window 63 and the lamp light emission window 53 to cool the flash heating unit 5 and upper chamber window 63.

[0089] Next, a description will be given of the processing operation in the heat treatment apparatus 160. The processing procedure for the semiconductor wafer W described below progresses as the control unit 3 controls each operating mechanism of the heat treatment apparatus 160.

[0090] First, prior to processing of semiconductor wafers W, valve 84 for supplying gas is opened, and exhaust valve 89 is also opened to start supplying and exhausting gas to and from chamber 161. When valve 84 is opened, nitrogen gas is supplied to heat treatment space 65 through gas supply hole 81. Furthermore, when valve 89 is opened, gas within chamber 161 is exhausted through gas exhaust hole 86. As a result, nitrogen gas supplied from the upper part of heat treatment space 65 within chamber 161 flows downward and is exhausted from the lower part of heat treatment space 65.

[0091] Furthermore, by opening the valve 192, the gas inside the chamber 161 is also exhausted from the transfer opening 66. Furthermore, an exhaust mechanism (not shown) also exhausts the atmosphere around the drive unit of the transfer mechanism 10. Note that, during the heat treatment of the semiconductor wafer W in the heat treatment device 160, nitrogen gas is continuously supplied to the heat treatment space 65, and the supply amount is changed as appropriate depending on the treatment process.

[0092] Next, the gate valve 162 is opened to open the transfer opening 66, and a semiconductor wafer W to be processed is carried into the heat treatment space 65 in the chamber 161 by a transfer robot outside the apparatus through the transfer opening 66. At this time, there is a risk that the atmosphere outside the apparatus may be drawn in as the semiconductor wafer W is carried in, but since nitrogen gas is continuously supplied to the chamber 161, the nitrogen gas flows out from the transfer opening 66, making it possible to minimize the drawing in of such external atmosphere.

[0093] The semiconductor wafer W carried in by the transfer robot advances to a position directly above the holder 7 and stops there. Then, the pair of transfer arms 11 of the transfer mechanism 10 move horizontally from the retracted position to the transfer operation position and rise, causing the lift pins 12 to pass through the through holes 79 and protrude from the upper surface of the holding plate 75 of the susceptor 74 to receive the semiconductor wafer W. At this time, the lift pins 12 rise to a position higher than the upper ends of the support pins 77.

[0094] After the semiconductor wafer W is placed on the lift pins 12, the transfer robot exits the heat treatment space 65, and the transfer opening 66 is closed by the gate valve 162. Then, the pair of transfer arms 11 descend, transferring the semiconductor wafer W from the transfer mechanism 10 to the susceptor 74 of the holder 7, where it is held from below in a horizontal position. The semiconductor wafer W is supported by a plurality of support pins 77 erected on the holding plate 75 and held on the susceptor 74. The semiconductor wafer W is held on the holder 7 with its front surface, which is the surface to be processed, facing upward. A predetermined gap is formed between the back surface (the main surface opposite to the front surface) of the semiconductor wafer W supported by the plurality of support pins 77 and the holding surface 75a of the holding plate 75. The pair of transfer arms 11, which have descended to below the susceptor 74, are retracted to a retracted position, i.e., inside the recess 62, by the horizontal movement mechanism 13.

[0095] After the semiconductor wafer W is held from below in a horizontal position by the susceptor 74 of the holder 7, which is made of quartz, the 40 halogen lamps HL of the halogen heating unit 4 are turned on all at once to begin preheating (assisted heating). The halogen light emitted from the halogen lamps HL passes through the lower chamber window 64 and the susceptor 74, both of which are made of quartz, and is irradiated onto the underside of the semiconductor wafer W. The semiconductor wafer W is preheated by being irradiated with light from the halogen lamps HL, and its temperature rises. Note that the transfer arm 11 of the transfer mechanism 10 is retracted inside the recess 62, so it does not interfere with heating by the halogen lamps HL.

[0096] The temperature of the semiconductor wafer W, which is heated by the light irradiation from the halogen lamps HL, is measured by the lower radiation thermometer 20. The measured temperature of the semiconductor wafer W is transmitted to the control unit 3. The control unit 3 controls the output of the halogen lamps HL while monitoring whether the temperature of the semiconductor wafer W, which is heated by the light irradiation from the halogen lamps HL, has reached a predetermined preheating temperature T1 (see FIG. 9). That is, the control unit 3 feedback-controls the output of the halogen lamps HL based on the value measured by the lower radiation thermometer 20 so that the temperature of the semiconductor wafer W becomes the preheating temperature T1.

[0097] After the temperature of the semiconductor wafer W reaches the preheating temperature T1, the control unit 3 temporarily maintains the semiconductor wafer W at the preheating temperature T1. Specifically, when the temperature of the semiconductor wafer W measured by the lower radiation thermometer 20 reaches the preheating temperature T1, the control unit 3 adjusts the output of the halogen lamps HL to maintain the temperature of the semiconductor wafer W at approximately the preheating temperature T1.

[0098] By performing preheating using the halogen lamps HL in this manner, the temperature of the entire semiconductor wafer W is uniformly raised to the preheating temperature T1. During preheating using the halogen lamps HL, the temperature of the peripheral portion of the semiconductor wafer W, where heat dissipation is more likely, tends to be lower than that of the central portion, but the arrangement density of the halogen lamps HL in the halogen heating unit 4 is higher in the region facing the peripheral portion of the semiconductor wafer W than in the region facing the central portion. As a result, a greater amount of light is irradiated onto the peripheral portion of the semiconductor wafer W, where heat dissipation is more likely, and the in-plane temperature distribution of the semiconductor wafer W during the preheating stage can be made uniform.

[0099] When a predetermined time has elapsed since the temperature of the semiconductor wafer W reached the preheating temperature T1, the flash lamps FL of the flash heating unit 5 irradiate the surface of the semiconductor wafer W held on the susceptor 74 with flash light. At this time, part of the flash light emitted from the flash lamps FL heads directly into the chamber 161, and the other part is reflected by the reflector 52 before heading into the chamber 161, and the semiconductor wafer W is flash-heated by the irradiation of these flash lights.

[0100] Flash heating is performed by irradiating a flash of light (flash of light) from flash lamps FL, which can raise the surface temperature of the semiconductor wafer W in a short time. That is, the flash of light irradiated from the flash lamps FL is an extremely short, intense flash of light with an irradiation time of approximately 0.1 milliseconds to 100 milliseconds, in which electrostatic energy previously stored in a capacitor is converted into an extremely short light pulse. The surface temperature of the semiconductor wafer W flash-heated by the irradiation of the flash of light from the flash lamps FL instantaneously rises to a processing temperature of 1000°C or higher and then rapidly drops.

[0101] After the flash heating process is completed, the halogen lamps HL are turned off after a predetermined time has elapsed. This causes the temperature of the semiconductor wafer W to rapidly decrease from the preheating temperature T1. The temperature of the semiconductor wafer W during this decrease is measured by the lower radiation thermometer 20, and the measurement result is transmitted to the control unit 3. The control unit 3 monitors, based on the measurement result of the lower radiation thermometer 20, whether the temperature of the semiconductor wafer W has decreased to a predetermined temperature. After the temperature of the semiconductor wafer W has decreased to or below the predetermined temperature, the pair of transfer arms 11 of the transfer mechanism 10 again move horizontally from the retracted position to the transfer operation position and rise, causing the lift pins 12 to protrude from the upper surface of the susceptor 74 and receive the heat-treated semiconductor wafer W from the susceptor 74. Next, the transfer opening 66, which had been closed by the gate valve 162, is opened, and the semiconductor wafer W placed on the lift pins 12 is removed from the chamber 161 by a transfer robot external to the apparatus, completing the heat treatment of the semiconductor wafer W.

[0102] <Configuration of anomaly detection device 2> FIG. 8 is a functional block diagram showing the electrical configuration of a heat treatment apparatus 160 including an anomaly detection device 2. The heat treatment apparatus 160 includes a control unit 3, an input unit 15, and a display unit 16. The control unit 3 includes a processor such as a CPU. The control unit 3 also includes an anomaly detection device 2. The control unit 3 controls, for example, the flash heating unit 5 and the halogen heating unit 4. The input unit 15 includes input devices such as a keyboard, a pointing device, and a touch panel. The input unit 15 also includes a communication module for communicating with a host computer. The display unit 16 includes, for example, a liquid crystal display, and displays various information under the control of the control unit 3.

[0103] The CPU of the control unit 3 executes a predetermined processing program to perform processing in the heat treatment device 160. For example, the control unit 3 controls the halogen heating unit 4 and the flash heating unit 5 to heat-treat the semiconductor wafer W at a set temperature. The control unit 3 also includes a memory unit 31, a calculation unit 32, and an alarm issuing unit 33. The memory unit 31 includes a storage device such as a solid-state memory device and a hard disk drive. The calculation unit 32 includes a relationship information analysis unit 32a, a learning model creation unit 32b, and a detection unit 32c, which will be described in detail later. The learning model creation unit 32b, the detection unit 32c, and the alarm issuing unit 33 are included in the anomaly detection device 2. The relationship information analysis unit 32a, the learning model creation unit 32b, the detection unit 32c, and the alarm issuing unit 33 are functional processing units realized by the CPU of the control unit 3 executing a predetermined processing program. The processing details of the relationship information analysis unit 32a, the learning model creation unit 32b, the detection unit 32c, and the alarm issuing unit 33 will be described in more detail later.

[0104] 1 again, upper radiation thermometer 25 includes an infrared sensor 29 that measures the temperature of the top surface (front surface) of semiconductor wafer W. Infrared sensor 29 sends a detection signal generated in response to received light to control unit 3, which then calculates the temperature of the top surface of semiconductor wafer W. Similarly, lower radiation thermometer 20 includes an infrared sensor 24 that measures the temperature of the bottom surface (rear surface) of semiconductor wafer W. Infrared sensor 24 sends a detection signal generated in response to received light to control unit 3, which then calculates the temperature of the bottom surface of semiconductor wafer W.

[0105] The control unit 3 of the heat treatment apparatus 160 acquires the temperature of the semiconductor wafer W as well as a plurality of pieces of processing information that are correlated with the temperature of the semiconductor wafer W. Examples of this processing information include the temperature of the quartz parts in the chamber 161 (e.g., the temperature of the susceptor 74, the temperature of the upper chamber window 63, and the temperature of the lower chamber window 64), the temperature of the wall surface of the chamber 161, the amount of power supplied to the halogen heating unit 4 (or each halogen lamp HL), the amount of light irradiated from the halogen heating unit 4 (or each halogen lamp HL), the amount of processing gas supplied into the chamber 161, and the amount of light irradiated from the flash heating unit 5 (or each flash lamp FL).

[0106] These pieces of processing information are acquired by sensors S1 to S9 serving as processing information acquisition unit 90. For example, the temperature of susceptor 74 is acquired by temperature sensor 91 (FIG. 1) (sensor S1 in FIG. 8), the temperature of upper chamber window 63 is acquired by temperature sensor 92 (FIG. 1) (sensor S2 in FIG. 8), the temperature of lower chamber window 64 is acquired by temperature sensor 93 (FIG. 1) (sensor S3 in FIG. 8), the temperature of the atmosphere inside chamber 161 is acquired by temperature sensor 94 (FIG. 1) (sensor S4 in FIG. 8), and the temperature of the wall surface of chamber 161 is acquired by temperature sensor 95 (FIG. 1) (sensor S5 in FIG. 8). The amount of power supplied to the halogen heating unit 4 (or each halogen lamp HL) is measured by an ammeter 49a (FIG. 1) (sensor S6 in FIG. 8) connected to the power supply unit 49, the amount of light emitted from the halogen heating unit 4 (or each halogen lamp HL) is measured by a light intensity sensor 97 (FIG. 1) (sensor S7 in FIG. 8), the amount of process gas supplied to the chamber 161 is measured by a flow meter 98 (FIG. 1) (sensor S8 in FIG. 8) connected to the gas supply pipe 83, and the amount of light emitted from the flash heating unit 5 (or each flash lamp FL) is measured by a light intensity sensor 96 (FIG. 1) (sensor S9 in FIG. 8). This information can also be used as processing information for creating a learning model. The processing information obtained by the sensors S1 to S9 of the processing information acquisition unit 90 preferably includes two or more parameters selected from the above. Other information may be used as processing information as long as it is correlated with the temperature of the semiconductor wafer W. The processing information obtained by the sensors S1 to S9 may be excluded.

[0107] Whether or not the processing information has a correlation with the temperature of the semiconductor wafer W is determined by the relationship information analysis unit 32a, which analyzes the relationship between the temperature of the semiconductor wafer W and the processing information. The relationship information analysis unit 32a determines whether or not the information acquired from each sensor has a correlation with the temperature of the semiconductor wafer W, and whether the correlation is high or low. Information determined by the relationship information analysis unit 32a to have a high correlation with the temperature of the semiconductor wafer W is adopted as processing information by the learning model creation unit 32b. On the other hand, processing information determined to have no or only a low correlation with the temperature of the semiconductor wafer W may be excluded from the processing information in the learning model creation unit 32b.

[0108] In this embodiment, the learning model creation unit 32b creates a learning model that represents the relationship between the temperature of the semiconductor wafer W and the actual measurement values ​​(output values ​​of each sensor) obtained by the processing information acquisition unit 90 (each sensor). When creating the learning model, first, learning data that indicates the relationship between the temperature of the semiconductor wafer W and each actual measurement value is acquired based on the temperature of the semiconductor wafer W and the actual measurement values ​​obtained from each of the two or more sensors. Then, the acquired learning data is used to optimize the weighting coefficients and the like for each actual measurement value. In this manner, the learning model is created.

[0109] 9 is a table showing the phases used when creating a learning model in this embodiment. In FIG. 9, the horizontal axis represents time, one vertical axis (left side (data indicated by the solid line in the table)) represents temperature, and the other vertical axis (right side (data indicated by the dotted line in the table)) represents the heat treatment phase.

[0110] In this embodiment, when creating a learning model, the learning model creation unit 32b divides the heat treatment of the semiconductor wafer W into multiple phases to create the learning model. The multiple phases preferably include at least a phase in which the temperature of the semiconductor wafer W is increased by the halogen heating unit 4, a phase in which the temperature of the semiconductor wafer W is maintained constant by the halogen heating unit 4, and a phase in which the temperature of the semiconductor wafer W is decreased after heating by the halogen heating unit 4 and the flash heating unit 5 is completed. This is because these heat treatment phases are considered to be characteristic phases in the quality control of the semiconductor wafer W. Note that FIG. 9 shows the temperature of the underside of the semiconductor wafer W, and in this embodiment, the relationship information analysis unit 32a employs processing information that is correlated with the temperature of the underside of the semiconductor wafer W.

[0111] In this embodiment, the heat treatment phases are divided into seven sections, as indicated by dotted lines in FIG. 9. In this embodiment, the divisions are based on the difference in the intensity of light from the halogen heating unit 4. The heat treatment phases in this embodiment are divided into seven sections. Specifically, in FIG. 9, the sections are divided into a section from t0 to t1 (heat treatment phase F1), a section from t1 to t2 (heat treatment phase F2), a section from t2 to t3 (heat treatment phase F3), a section from t3 to t4 (heat treatment phase F4), a section from t4 to t5 (heat treatment phase F5), a section from t5 to t6 (heat treatment phase F6), and a section from t6 to t7 (heat treatment phase F7). The set intensity of light from the halogen heating unit 4 differs in each of these heat treatment phases. That is, the amount of power (indicated by the ammeter 49a) supplied from the power supply unit 49 to the halogen heating unit 4 differs. The learning model creation unit 32b creates a learning model for each of the above-described phases. The division of the phases as described above differs depending on the recipe for the heat treatment.

[0112] The detection unit 32c detects a processing abnormality of the semiconductor wafer W based on the multiple learning models created by the learning model creation unit 32b. More specifically, the detection unit 32c detects a processing abnormality of the semiconductor wafer W based on the difference between the actual measurement value obtained by the processing information acquisition unit 90 (each sensor) and the predicted value calculated using the learning model. The detection unit 32c detects a processing abnormality by comparing the predicted value obtained from the learning model with the actual measurement value related to the multiple processing information for each of multiple phases. The detection unit 32c detects a processing abnormality of the semiconductor wafer W based on the difference between the actual measurement value obtained by the processing information acquisition unit 90 (each sensor) and the predicted value calculated using the learning model. At this time, the magnitude of the difference between the actual measurement value obtained by the processing information acquisition unit 90 (each sensor) and the predicted value calculated using the learning model is calculated as the degree of abnormality. The degree of abnormality is related to the magnitude of the correlation between the temperature of the semiconductor wafer W and the processing information. When the correlation is large, the degree of abnormality is determined to be high even if the difference is small, and when the correlation is small, the degree of abnormality is determined to be low even if the difference is large.

[0113] As described above, the detection unit 32c detects a change in the relationship between the temperature of the semiconductor wafer W and the actual measurement value obtained by the processing information acquisition unit 90 (each sensor). This detects a sign of a malfunction in the heat treatment device 160. Furthermore, the detection unit 32c determines that a processing abnormality has occurred when the actual measurement value deviates from the predicted value obtained from the learning model by more than a predetermined threshold.

[0114] The alarm issuing unit 33 issues an alarm when the detection unit 32c detects the above-mentioned processing abnormality, and causes the display unit 16 to display an alarm indicating that there is a failure or a sign of a failure.

[0115] <Learning model creation flow for anomaly detection device 2> The flow of creating a learning model of the heat treatment device 160 and detecting a processing abnormality in the abnormality detection device 2 will be described below.

[0116] Fig. 10 is a flowchart showing the processing procedure for creating a learning model by the anomaly detection device 2. Fig. 11 is a flowchart showing the processing procedure for detecting a processing anomaly by the anomaly detection device 2.

[0117] 10, in order for the anomaly detection device 2 to create a learning model, first, the temperature of the semiconductor wafers W, which will serve as training data, is measured (step ST1). The temperature measurement is performed on multiple semiconductor wafers W. Next, similar to the temperature measurement, each piece of processing information, which will serve as training data, is acquired by each sensor (processing information acquisition unit 90) installed in the heat treatment device 160 (step ST2). The acquisition of each piece of processing information is also performed during the processing of multiple semiconductor wafers W.

[0118] The temperature data and each processing information acquired in steps ST1 and ST2 as training data are separated into heat treatment phases shown in Fig. 9 and stored in the storage unit 31 (step ST3). Next, the learning model creation unit 32b creates a learning model for each of the heat treatment phases F1 to F7 based on the temperature and each processing information. A learning model for the temperature data separated into heat treatment phases is created, and a learning model for each processing information separated into heat treatment phases is also created (step ST4).

[0119] As described above, the anomaly detection device 2 of this embodiment creates a learning model divided into heat treatment phases, enabling comparison of predicted and measured values ​​for each heat treatment phase. It is believed that during the heat treatment of semiconductor wafers W, different relationships between the temperature of the semiconductor wafers W and other processing information are established in each heat treatment phase, each with its own unique characteristics. Under these conditions, if different relationships are identified for each heat treatment phase, even slight changes in the heat treatment can be detected. Therefore, the anomaly detection device 2 of this embodiment enables detection of subtle processing anomalies, which was difficult with conventional technology. For example, it is possible to detect a decrease in the output of one of the lamps used as a heat source for heating the substrate. It is also possible to distinguish between a few degrees of change in substrate temperature or a few percent of change in lamp output and noise. As a result, the anomaly detection device 2 of this embodiment is able to detect subtle processing anomalies and predict signs of equipment-wide failure based on the detection of subtle processing anomalies, compared to when a learning model is created for the entire heat treatment of semiconductor wafers W.

[0120] Next, in order for the anomaly detection device 2 to detect a processing anomaly, first, the temperature of the semiconductor wafer W being processed is measured (step ST11). Next, each sensor (processing information acquisition unit 90) acquires each piece of processing information (step ST12).

[0121] The temperature data of the semiconductor wafer W and each piece of processing information acquired in steps ST11 and ST12 are separated into heat treatment phases (heat treatment phases F1 to F7) shown in Fig. 9 and stored in the storage unit 31 (step ST13). The temperature data and each piece of processing information stored in the storage unit 31 are used in the following processing as actual measured values.

[0122] Next, the calculation unit 32 calculates predicted values ​​of the learning model for the temperature of the semiconductor wafer W and each piece of processing information (step ST14). The calculated predicted values ​​are compared with the actual measured values ​​stored in step ST13 (step ST15). That is, the anomaly detection device 2 compares the predicted values ​​obtained from the learning model with the actual measured values ​​for each piece of processing information for each of the heat treatment phases (heat treatment phases F1 to F7).

[0123] It is determined whether the difference between the predicted value and the actual measured value compared in step ST15 is equal to or greater than a preset threshold value (step ST16). The threshold value is set for each piece of processing information, and further set for each phase. This threshold value may be calculated when creating the learning model. If it is determined in step ST16 that the difference between the predicted value and the actual measured value is less than the threshold value, it is determined that there is no processing abnormality (step ST17). If it is determined that there is no processing abnormality, the next semiconductor wafer W is processed.

[0124] On the other hand, if it is determined in step ST16 that the difference between the predicted value and the actual measured value is equal to or greater than the threshold, it is determined that a processing abnormality exists (step ST18). A determination that a processing abnormality exists is made when the difference is equal to or greater than the threshold in any heat treatment phase for any of the processing information. If the difference is equal to or greater than the threshold in any heat treatment phase for any of the processing information, it is determined that the correlation between the temperature and the processing information has been destroyed. The degree of the destruction of the correlation is also evaluated at the same time. Here, the degree of the destruction is evaluated by the ratio between the effective correlation coefficient in the learning model calculated by the relationship information analyzer 32a and the correlation coefficient in the actual measured values. Therefore, if the value of the effective correlation coefficient in the learning model is low (in the case of processing information that is considered to have a low correlation), a change in the correlation coefficient in the actual measured values ​​may not be determined to be an abnormality.

[0125] If it is determined in step ST18 that there is a processing abnormality, an alarm is issued by the alarm issuing unit 33 of the abnormality detection device 2 (step ST19). The greater the magnitude of the damage, the stronger the alarm that is issued. Also, if processing abnormalities are determined consecutively in multiple heat treatment phases for multiple pieces of processing information, a stronger alarm may be issued. To issue an alarm, for example, the alarm issuing unit 33 displays on the display unit 16 that there is a malfunction or a sign of a malfunction. In response to such an alarm, the processing of the semiconductor wafer W may be stopped.

[0126] As described above, the anomaly detection device 2 detects a processing anomaly by comparing predicted values ​​obtained from the learning model with actual measured values ​​related to a plurality of pieces of processing information for each of a plurality of phases.

[0127] Second Embodiment Next, a second embodiment of the present invention will be described. The configuration of a heat treatment apparatus 260 and the processing procedure for semiconductor wafers W in the second embodiment are the same as those in the first embodiment. As shown in FIG. 8, the second embodiment has the same electrical configuration as the first embodiment. The control unit 203 includes a memory unit 31, a calculation unit 232, and an alarm unit 33. The calculation unit 232 includes a relationship information analysis unit 32a, a learning model creation unit 232b, and a detection unit 32c. The learning model creation unit 232b, the detection unit 32c, and the alarm unit 33 are included in the anomaly detection device 202.

[0128] Fig. 12 is a table showing the phases used when creating a learning model in the second embodiment. In Fig. 12, the horizontal axis represents time, and the vertical axis (left side (data indicated by the solid line in the table)) represents temperature.

[0129] In the second embodiment, when a learning model is created, the learning model creation unit 232b creates the learning model by dividing the heat treatment of the semiconductor wafer W into multiple phases. In the second embodiment, the heat treatment is divided into heat treatment phases that are separated by the time periods indicated by t11 to t17 in FIG.

[0130] While the heat treatment phases in the first embodiment are divided into sections based on the intensity of light from the halogen heating unit 4, the heat treatment phases in the second embodiment are divided into sections based on the temperature range of the underside of the semiconductor wafer W. In the second embodiment, the sections are divided based on the difference in the intensity of light from the halogen heating unit 4. The heat treatment phases in the second embodiment are divided into five sections. More specifically, in FIG. 12, the sections are divided into a section from t10 to t11 (heat treatment phase F11), a section from t11 to t12 (heat treatment phase F12), a section from t12 to t13 (heat treatment phase F13), and a section from t13 to t14 (heat treatment phase F14). In each of these heat treatment phases, the temperature range measured by the lower pyrometer 20 differs. For example, heat treatment phase F11 is the period from the start of heating by the halogen heating unit 4 to the time when the temperature of the semiconductor wafer W begins to rise; heat treatment phase F12 is the period during which the semiconductor wafer W is heated to the preheating temperature T1 by the halogen heating unit 4 (the period during which the temperature is raised by the halogen heating unit 4); heat treatment phase F13 is the period during which the semiconductor wafer W is maintained at a constant preheating temperature T1 by heating by the halogen heating unit 4; and heat treatment phase F14 is the period during which the temperature of the semiconductor wafer W drops due to a decrease in the output of the halogen heating unit 4 after heating by the flash heating unit 5 ends (the period during which the temperature of the semiconductor wafer W drops after heating by the halogen heating unit 4 and flash heating unit 5 ends).

[0131] In the second embodiment, the acquired temperature data of the semiconductor wafer W and each piece of processing information are separated into heat treatment phases (heat treatment phases F11 to F14) shown in Fig. 12 and stored in the storage unit 31. Then, the anomaly detection device 202 in the second embodiment compares predicted values ​​obtained from the learning model with actual measured values ​​for each piece of processing information, for each piece of processing information, for each of the heat treatment phases (heat treatment phases F11 to F14).

[0132] <Effects of the above-described embodiments> Next, examples of effects obtained by the above-described embodiments will be described. Note that in the following description, the effects will be described based on the specific configurations exemplified in the above-described embodiments, but these may be replaced with other specific configurations exemplified in the present specification as long as the same effects are obtained.

[0133] Furthermore, the replacement may be made across multiple embodiments, i.e., configurations shown as examples in different embodiments may be combined to produce the same effect.

[0134] The anomaly detection device 2 (202) according to the embodiment described above is an anomaly detection device 2 (202) that detects a processing anomaly in a semiconductor wafer W that is being heat-treated in the heat treatment device 160. The anomaly detection device 2 (202) includes a lower radiation thermometer 20 that measures the temperature of the semiconductor wafer W during heat treatment, a processing information acquisition unit 90 (each sensor) that acquires a plurality of pieces of processing information that are correlated with the temperature measured by the lower radiation thermometer 20, and a detection unit 32c that divides the heat treatment of the semiconductor wafer W into a plurality of phases (heat treatment phases F1 to 7 or heat treatment phases F11 to 14) and detects a processing anomaly in the semiconductor wafer W based on a plurality of learning models created for each of the plurality of phases (heat treatment phases F1 to 7 or heat treatment phases F11 to 14) based on the temperature and the processing information.

[0135] With this configuration, it is possible to detect substrate processing abnormalities based on multiple learning models created for each of the multiple phases (heat treatment phases F1 to F7 or heat treatment phases F11 to F14). This makes it possible to detect subtle processing abnormalities and to predict failures of the entire heat treatment apparatus 160 (260) based on the detection of subtle processing abnormalities, compared to when abnormalities are detected using learning models created without dividing the process into multiple phases.

[0136] The heat treatment apparatus 160 (260) also includes a chamber 161 that accommodates a semiconductor wafer W, a halogen heating unit 4 that irradiates the semiconductor wafer W accommodated in the chamber 161 with light to preheat the semiconductor wafer W, and a flash heating unit 5 that irradiates the semiconductor wafer W with light to bring the semiconductor wafer W to a processing temperature. The plurality of processing information includes two or more parameters selected from the group consisting of the temperature of quartz parts in the chamber 161 (e.g., the temperature of the susceptor 74, the upper chamber window 63, and the lower chamber window 64), the temperature of the chamber wall surface, the power supplied to the halogen heating unit 4, the intensity of light from the halogen heating unit 4, and the amount of processing gas supplied into the chamber 161.

[0137] According to this configuration, the plurality of processing information includes two or more parameters that are considered to have a high correlation with the temperature of the semiconductor wafer W, thereby improving the accuracy of detecting processing abnormalities.

[0138] The multiple phases (heat treatment phases) include at least a phase in which the temperature is increased by the halogen heating unit 4 (heat treatment phase F12 in the second embodiment), a phase in which the temperature is maintained constant by the halogen heating unit 4 (heat treatment phase F13 in the second embodiment), and a phase in which the temperature of the semiconductor wafer W is decreased after heating by the halogen heating unit 4 and the flash heating unit 5 is completed (heat treatment phase F14 in the second embodiment).

[0139] According to this configuration, a learning model is created for each heat treatment phase that is considered to be a characteristic phase in the quality control of semiconductor wafers W, thereby improving the accuracy of detecting processing abnormalities.

[0140] In addition, the detection unit 32c compares predicted values ​​obtained from the learning model with actual measured values ​​of multiple processing information (e.g., the temperature of the quartz parts inside the chamber 161, the temperature of the chamber wall, the power supplied to the halogen heating unit 4, the intensity of light from the halogen heating unit 4, and the amount of processing gas supplied into the interior of the chamber 161) for each of multiple phases (heat treatment phases F1 to 7 or heat treatment phases F11 to 14) to detect processing abnormalities.

[0141] According to this configuration, the magnitude of the abnormality is determined based on the magnitude of the correlation between the temperature of the semiconductor wafer W and the processing information, thereby improving the accuracy of detecting processing abnormalities.

[0142] Furthermore, the detection unit 32c determines that a processing abnormality has occurred when the actual measurement value deviates from the predicted value obtained from the learning model by more than a predetermined threshold.

[0143] The system further includes an alarm unit 33 that issues an alarm when the detection unit 32c detects a processing abnormality.

[0144] With this configuration, the operator of the heat treatment device 160 (260) can smoothly detect any abnormality in the heat treatment device.

[0145] <Modifications of the above-described embodiments> In the embodiments described above, the material, composition, dimensions, shape, relative positional relationship, or implementation conditions of each component may also be described, but these are merely examples in all aspects and are not limited to those described in this specification.

[0146] Therefore, countless variations and equivalents not shown as examples are contemplated within the scope of the technology disclosed in the present specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component in at least one embodiment and combining it with a component in another embodiment.

[0147] In the above-described embodiment, the calculation unit 32 (232) is configured to include the relationship information analysis unit 32a and the learning model creation unit 32b (232b), but this is not limited to this. The calculation unit 32 (232) may not include the relationship information analysis unit 32a, and instead, a relationship between the temperature of the semiconductor wafer W and the processing information that has been analyzed (or set) in advance may be stored in the memory unit 31. Furthermore, the calculation unit 32 (232) may not include the learning model creation unit 32b, and instead, a learning model that has been created in advance may be stored in the memory unit 31. The calculation unit 32 (232) may then be configured to calculate a predicted value based on this stored learning model.

[0148] Similarly, in the above-described embodiment, the anomaly detection device 2 (202) is configured to include the learning model creation unit 32b (232b), but this is not limited to this. The anomaly detection device 2 (202) may not include the learning model creation unit 32b (232b), and instead, a pre-created learning model may be stored in the memory unit 31. The anomaly detection device 2 (202) may then be configured to detect processing anomalies in semiconductor wafers W based on this stored learning model.

[0149] Furthermore, in the above-described embodiment, the calculation unit 32 (232) (anomaly detection device 2 (202)) is configured to include the detection unit 32c, but this is not limiting. The calculation unit 32 (232) (anomaly detection device 2 (202)) may not include the detection unit 32c, and the function of the detection unit 32c may be provided in a cloud that can remotely access the heat treatment device 160 (260). In this case, the actual measurement values ​​obtained by the processing information acquisition unit 90 (each sensor) and the measurement values ​​by the lower radiation thermometer 20 (or / and upper radiation thermometer 25) may be transmitted to the cloud, where they are calculated and the result of the processing anomaly is received by the control unit 3 (203). In this case, the actual measurement values ​​obtained by the processing information acquisition unit 90 (each sensor) and the measurement values ​​by the lower radiation thermometer 20 (or / and upper radiation thermometer 25) may be stored in the cloud. The entire function of the control unit 3 (203) may be provided in the cloud. Furthermore, the configuration may be such that the function of the detector 32c is provided so that it can access (transmit and receive) the heat treatment device 160 not only via the cloud but also via wire or wireless.

[0150] Furthermore, in the above-described embodiment, a plurality of pieces of processing information correlating with the temperature of the semiconductor wafer W measured by the lower pyrometer 20 are used to create the learning model, but the present invention is not limited to such processing information. A plurality of pieces of processing information correlating with the temperature of the top surface of the semiconductor wafer W measured by the upper pyrometer 25 may also be used to create the learning model. In this case, the learning model is created based on the temperature of the top surface of the semiconductor wafer W and the processing information. Therefore, processing abnormalities of the semiconductor wafer W can be detected even during periods (e.g., during soaking) when the state of the heat treatment device 160 (260) is stable and the influence of noise is considered small compared to other periods.

[0151] In addition, a plurality of pieces of processing information having a correlation with the temperatures of the bottom surface and top surface of the semiconductor wafer W measured by the lower radiation thermometer 20 and the upper radiation thermometer 25, respectively, may be used to create a learning model.

[0152] Furthermore, in the embodiments described above, when a material name is mentioned without any particular specification, unless a contradiction arises, it is assumed that the material in question may contain other additives, such as an alloy. [Explanation of symbols]

[0153] 2,202 Anomaly detection device 3,203 Control Unit 4 Halogen heating section 5 Flash heating section 6 chambers 7 Holding part 10 Transfer mechanism 11 Transfer arm 12 lift pins 13 Horizontal movement mechanism 14 Lifting mechanism 15 Input section 16 Display 20 Lower radiation thermometer 21,26 Transparent window 24,29 Infrared sensor 25 Upper radiation thermometer 31 Storage section 32,232 calculation section 32a Relationship Information Analysis Department 32b,232b Learning model creation section 32c Detection unit 33. Reporting Department 41,51 Case 43,52 Reflector 49 Power supply section 49a ammeter 53 Lamp light emission window 61 Chamber side 61a,61b through hole 62 recess 63 Upper chamber window 64 Lower chamber window 65 Heat Treatment Space 66 Transport opening 68,69 Reflective ring 71 Base Ring 72 Connecting part 74 Susceptor 75 Retaining Plate 75a Holding surface 76 Guide Ring 77 Support pin 78 Opening 79 Through Hole 81 Gas supply hole 82,87 Buffer space 83 Gas supply pipe 84, 89, 192 valves 85 Process gas supply source 86 Gas exhaust vent 88,191 Gas exhaust pipe 90 Processing information acquisition unit 91, 92, 93, 94, 95 Temperature sensors 96,97 Light sensor 98 Flow meter 160,260 Heat treatment equipment 161 Chamber 162 Gate valve 190 Exhaust mechanism F1, F2, F3, F4, F5, F6, F7, F11, F12, F13, F14 Heat treatment phase S1, S2, S3, S4, S5, S6, S7, S8, S9 sensors T1 Preheating temperature W Semiconductor wafer

Claims

1. An abnormality detection device that detects a processing abnormality of a substrate being heat-treated in a heat treatment device, a chamber for accommodating the substrate; a preheating unit that preheats the substrate by irradiating the substrate accommodated in the chamber with light; a main heating unit that irradiates the substrate with light to bring the substrate to a processing temperature; a thermometer for measuring the temperature of the substrate during heat treatment; a processing information acquisition unit that acquires a plurality of pieces of processing information that are correlated with the temperature measured by the thermometer; a detection unit that divides the heat treatment of the substrate into a plurality of phases, and detects a processing abnormality of the substrate based on a plurality of learning models created for each of the plurality of phases based on the temperature and the processing information; Equipped with The plurality of pieces of processing information include two or more parameters selected from the group consisting of the temperature of quartz parts in the chamber, the temperature of the wall surface of the chamber, the power supplied to the preheating unit, the intensity of light from the preheating unit, and the amount of processing gas supplied into the interior of the chamber.

2. The anomaly detection device according to claim 1, The plurality of phases include at least a phase in which the temperature is increased by the preheating unit, a phase in which the temperature is maintained constant by the preheating unit, and a phase in which the temperature of the substrate is decreased after heating by the preheating unit and the main heating unit is completed.

3. 3. The anomaly detection device according to claim 1, The detection unit is an anomaly detection device that detects processing anomalies by comparing predicted values ​​obtained from the learning model with actual measured values ​​related to the multiple pieces of processing information for each of the multiple phases.

4. The anomaly detection device according to claim 3, The detection unit is an anomaly detection device that determines that a processing anomaly has occurred when the actual measured value deviates from the predicted value obtained from the learning model by more than a predetermined threshold.

5. The anomaly detection device according to claim 4, The anomaly detection device further comprises an alarm unit that issues an alarm when the detection unit detects a processing anomaly.

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