Power Delivery Network for CFETs with Buried Power Rails

Abstract

The semiconductor device includes a first power rail, a first power input structure, a circuit, and a first middle-of-line rail. The first power rail is formed in a first rail opening in a first isolation trench on a substrate. The first power input structure is configured to connect to a first terminal of a power supply external to the semiconductor device and receive power from the power supply. The circuit is formed on the substrate by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers forming the circuit. The first middle-of-line rail is configured to supply power from the first power input structure to the first power rail, and the first power rail provides power to the circuit for operation.

Description

[Technical Field]

[0001] Related Applications This application claims the benefit of U.S. Non-provisional Application No. 16 / 659,251, filed October 21, 2019, the entire disclosure of which is incorporated herein by reference.

[0002] This disclosure generally describes embodiments relating to semiconductor devices and manufacturing processes. [Background technology]

[0003] Historically, the semiconductor industry has characterized transistors as two-dimensional (2D) circuits or fabrication because transistors are fabricated in a single plane, with wiring / metallization formed on top. Scaling efforts have significantly increased the number of transistors per unit area in 2D circuits. As traditional 2D scaling offers a rapidly declining return on investment, the semiconductor industry is turning to third dimensions to maintain node-to-node improvements in power-performance-area-cost (PPAC). A very promising approach to utilizing the vertical axis for transistor density improvements is a new device architecture known as the complementary field-effect transistor (CFET). In the CFET approach, a logic cell with an N-type and a P-type device is essentially folded, with one of the two devices, such as a P-type device, placed on top of the other, such as an N-type device, while sharing a common gate. Summary of the Invention [Problem to be solved by the invention]

[0004] By folding two complementary devices on top of each other and eliminating the substantial lateral space required between N-type and P-type devices, standard cell logic designs are placed in a domain where cell height is limited not by device width but by the cumulative width of the required wiring tracks. At the scaling limit, the cell height must accommodate four wiring tracks plus a robust power rail. Thus, when double-wide power rails are assumed to be wide enough to prevent voltage drop or electromagnetic coupling problems during power transmission, the minimum cell height is six wiring tracks (6T).

[0005] To further scale cell height while maintaining robust power delivery, the semiconductor industry is turning to buried power rails (BPRs). By moving the power rails below the device plane, it is possible to reduce the cell height to 5T (i.e., four wiring tracks for signaling plus one wiring track to accommodate line-end extensions and tip-to-tip spacing in densely packed cells).

[0006] Buried power rails (BPRs) will play an important role in paving the way for future advances at the end of 2D scaling by leveraging 3D stacking of transistors, but a new challenge has arisen: how to power the BPRs. Connecting the power rails located below the device plane with the power delivery network (PDN) located above the device requires a high-rise power connection. This power connection cannot be too small, as it risks creating a current pinch point, nor too large, as it risks interfering with dense cell placement.

[0007] As outlined above, a unique middle-of-line power delivery network approach is provided in the present disclosure that realizes the benefits of CFETs and BPRs, and further realizes the need for a robust, low resistance means of delivering power to the BPRs. [Means for solving the problem]

[0008] An aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a first power rail, a first power input structure, a circuit, and a first middle-of-line rail. The first power rail is formed in a first rail opening in a first isolation trench on a substrate. The first power input structure is configured to connect to a first terminal of a power supply external to the semiconductor device and receive power from the power supply. The circuit is formed on the substrate by layers between the first power rail and the first power input structure. The first middle-of-line rail is formed by one or more of the layers forming the circuit. The first middle-of-line rail is configured to supply power from the first power input structure to the first power rail, and the first power rail provides power to the circuit for operation.

[0009] Further, in some embodiments, the semiconductor device includes a second power rail, a second power input structure, and a second middle-of-line rail. The second power rail is formed in a second rail opening in a second isolation trench on the substrate. The second power rail is parallel to the first power rail. The second power input structure is configured to connect to a second terminal of the power supply and receive power from the power supply using the first power input structure. The second middle-of-line rail is formed by one or more of the layers forming the circuit. The second middle-of-line rail is parallel to the first middle-of-line rail, and the first and second middle-of-line rails are configured to supply power from the first and second input structures to the first and second power rails. The first and second power rails provide power to the circuit for operation.

[0010] In some embodiments, the circuit includes a row of cells of cell circuits having the same cell height, and the first middle-of-line rail includes a section within a power tap cell disposed in the row of cells, the power tap cell having the same cell height as the cell circuits.

[0011] In some embodiments, the first middle-of-line rail is formed by at least a layer used to form connections within the cell circuitry.

[0012] In one embodiment, the circuit includes a plurality of rows of cell circuits, and the first middle-of-line rail is formed from sections within power tap cells arranged in the plurality of rows of cells, respectively.

[0013] In some embodiments, the power tap cells are aligned in a column, and sections within each power tap cell are conductively connected to form a first middle-of-line rail.

[0014] In one embodiment, each section within a respective power tap cell is connected to the first power rail by at least a power via and to a metal rail by at least a contact.

[0015] In some embodiments, the first middle-of-line rail and the second middle-of-line rail are perpendicular to the first power rail and the second power rail.

[0016] In some embodiments, the circuit includes a first transistor disposed above a second transistor in a vertical direction perpendicular to a surface of the substrate, and in some embodiments, the first middle-of-line rail includes a first layer for forming a local interconnect in the first transistor, a second layer for forming a local interconnect in the second transistor, and a strap layer coupling the first layer and the second layer.

[0017] Aspects of the present disclosure also provide a method for fabricating a semiconductor device. For example, a buried power rail is formed in a rail opening in an isolation trench on a substrate. The buried power rail forms a BPR power delivery network in an embodiment. Active devices and a MOL power delivery network are then formed. In some embodiments, the MOL power delivery network includes a MIL rail and an M0 rail. In one embodiment, the MIL rail includes a top LI structure, a bottom LI structure, and a strap structure coupling the top LI structure and the bottom LI structure. The MIL rail is connected to the BPR by a short power via, and the MIL rail and M0 rail are connected by a top CD structure. Additionally, a top metal layer is formed, and via structures connecting wiring from different metal layers are also formed. A UML power delivery network is formed in the top metal layer. In one embodiment, power input pads are formed in the top metal layer.

[0018] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard industry practice, various features have not been drawn to scale. In fact, dimensions of various features may be arbitrarily increased or decreased for clarity of discussion. [Brief explanation of the drawings]

[0019] [Figure 1] 1 shows a diagram of a semiconductor device according to some embodiments of the present disclosure. [Figure 2] 1 illustrates a top view of a semiconductor device according to some embodiments of the present disclosure. [Figure 3] 1A-1C illustrate top and cross-sectional views of a power tap cell according to some embodiments of the present disclosure. [Figure 4] 1A-1C illustrate top and cross-sectional views of a power tap cell according to some embodiments of the present disclosure. [Figure 5] 1A-1C illustrate top and cross-sectional views of a logic cell according to some embodiments of the present disclosure. [Figure 6]1 shows a flowchart outlining an example process according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the disclosure, specific example components and configurations are described below. It should be understood that these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact with each other, or may include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact with each other. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purposes of brevity and clarity and does not, in itself, dictate a relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, spatial relationship terms such as "lower," "below," "lower side," "upper," "above," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as shown. The spatial relationship terms are intended to encompass different orientations of the device during use or operation in addition to the orientation shown in the figures. The device may be reoriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein may be similarly interpreted accordingly.

[0022] Aspects of the present disclosure provide a semiconductor device that uses buried power rails (BPRs) to reduce the height of standard cells for circuits, thereby reducing the footprint of the standard cells and the circuit. The BPRs form a BPR power delivery network for providing power to circuits such as logic circuits, analog circuits, and memory circuits within the semiconductor device. The semiconductor device further includes a plurality of power tap cells disposed with the standard cells in a plane for active devices. The power tap cells form a middle-of-line (MOL) power delivery network (PDN) in the semiconductor device. The MOL power delivery network is disposed between the BPR power delivery network and an upper metal layer (UML) power delivery network.

[0023] Typically, a semiconductor device includes multiple metal layers, such as eight metal layers designated M0 through M7. In some examples, metal layer M0 is typically used for connections within a standard cell, and metal layers M1 through M7 are above metal layer M0 and may be used for connections between different cells. In some embodiments, a MOL power distribution network is implemented using one or more layers of standard cells, such as M0, as local interconnects to form the MOL power distribution network. A UML power distribution network is formed by upper metal layers, such as metal layers M1 through M7. The MOL power distribution network interconnects the BPR power distribution network and the UML power distribution network.

[0024] The MOL power delivery network supports power injection from the UML power delivery network to the BPR power delivery network. For example, power is distributed from the UML power delivery network to the MOL power delivery network and from the MOL power delivery network to the BPR power delivery network. According to some aspects of the present disclosure, the MOL power delivery network is configured to minimize current congestion and power drops due to excessive resistance during power delivery. In one aspect of the present disclosure, the MOL power delivery network is configured to maximize the number of redundant connections between the UML power delivery network and the BPR power delivery network. In another aspect of the present disclosure, the MOL power delivery network forms an intermediate power supply rail positioned vertically to the BPR.

[0025] FIG. 1 shows a diagram illustrating a semiconductor device 100 according to some embodiments of the present disclosure. The semiconductor device 100 includes power input structures 101 and 102, a UML power delivery network 110, a MOL power delivery network 120, and a BPR power delivery network 190, which are coupled together. The MOL power delivery network 120 is formed in a layer forming active devices such as logic circuits, memory cells, etc., and is configured to support power injection from the UML power delivery network 110 to the BPR power delivery network 190. The BPR power delivery network 190 is configured to provide power to the active devices. In some embodiments, the logic circuits are implemented using standard cells, and the MOL power delivery network 120 is formed by a plurality of power tap cells. The power tap cells can be placed in a layout along with the standard cells during circuit and layout design.

[0026] It should be noted that semiconductor device 100 may be any suitable device, such as a semiconductor chip (or die), a semiconductor wafer having multiple semiconductor dies formed on the semiconductor wafer, a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips assembled on a package substrate, etc.

[0027] According to some aspects of the present disclosure, the semiconductor device 100 includes active devices such as logic circuits, analog circuits, and memory circuits. The active devices are formed in appropriately positioned and patterned layers. In some embodiments, the logic circuits are implemented using standard cells, such as inverter cells, NAND cells, and NOR cells, from a standard cell library. Each standard cell is configured to perform one or more operations. In some embodiments, the inverter cells are configured to perform a logical inversion operation, and thus generate an output having an inverted logical value of the input. For example, when the input has a binary logical value of "0," the output has a binary logical value of "1." When the input has a binary logical value of "1," the output has a binary logical value of "0." In some embodiments, the inverter cells are the smallest logic cells among the standard cells, and in some embodiments, occupy the smallest area. In some embodiments, the power tap cells are configured to have the same size as the inverter cells or a smaller size than the inverter cells.

[0028] In some embodiments, power input structures 101 and 102 are input pads configured to receive power from a power source (not shown) external to the semiconductor device. For example, the external power source may be V DD terminal and V SS It has a terminal V DD is used to represent the high voltage level side of a power supply such as 5V, 3V, or 1.5V, and V SS is used to represent the low voltage level side of the power supply, such as ground in the example. DD terminals, and the power supply input structure 102 is electrically coupled to the V SS In some embodiments, the power input structures 101 and 102 are formed from a top metal layer.

[0029] UML power distribution network 110 includes electrical connections in upper metal layers that are coupled to form a power distribution network. For example, semiconductor device 100 includes metal layers M0-M7 above the active devices, and UML power distribution network 110 includes several wires formed in metal layers M7-M1, including via connections that connect the wires in the different metal layers.

[0030] The buried power rails of the BPR power delivery network 190 are formed under physical devices (e.g., active devices, transistors) to allow for reduced cell lengths. For example, standard cells in a standard cell library are typically implemented as fixed-height, variable-width cells. The fixed height allows cells to be arranged in rows, facilitating the automated layout design process. In some embodiments, the row direction is referred to as the east-west direction, and the direction perpendicular to the east-west direction is referred to as the north-south direction. In this naming convention, M0 typically includes lines running in the east-west direction, while M1 has lines running in the north-south direction. Subsequent metal layers, in some embodiments, run perpendicular to the preceding metal layer.

[0031] By burying the power rails below the physical device, the cell height of a standard cell can be defined by the number of routing tracks or signal lines, rather than the combination of power rails and routing tracks. In some embodiments, the cell height can be easily scaled down by incorporating this concept from a cell height with 6.0 to 6.5 routing tracks (6.5T) to a cell height with 5.0 routing tracks (assuming the width of the power rails is equal to two or three times the width of the routing track lines), even though the number of actual routing tracks remains the same.

[0032] In the embodiment of FIG. DD and V SSThe active devices are provided with alternating parallel buried power rails, each extending in an east-west direction. In some embodiments, shallow trench isolation (STI) is used to isolate the active devices. The buried power rails may be housed either in the STI or in the bulk silicon and STI together, with the buried power rails buried below the plane of the layers forming the active devices. In some embodiments, rail openings may be formed in the STI and even in the bulk silicon, as disclosed in applicant's co-pending application Ser. No. 16 / 011,377, filed June 18, 2018, which is incorporated herein by reference in its entirety, and the rail openings may then be filled with a conductive metal material, such as copper, cobalt, aluminum, or ruthenium.

[0033] In some embodiments, the rows of standard cells are also in an east-west direction. The power rails may have a width that is relatively wider than the normal routing tracks, such as about two or three times the width of the routing tracks. In some implementations, adjacent rows of standard cells may be arranged in opposite directions to share a single power rail. For example, the standard cells in the first row are arranged in a north-south direction (e.g., V DD , V to the south SS ), and the standard cells in the second row are in the north-south direction (e.g., V DD , V to the north SS ) when the first row is north of the second row, V SS The power rail provides V to both the first and second row standard cells. SS may be provided.

[0034] 1, the power tap cells 120 are arranged with the standard cells in a row of cells. Note that in some embodiments, multiple power tap cells 120 may be arranged in a row of cells.

[0035] According to some aspects of the present disclosure, power tap cells 120 are formed in a device plane having active devices and include redundant connections for interfacing a UML power delivery network 110 above the device plane with a BPR power delivery network 190 located below the device plane. Additionally, power tap cells 120 help redistribute current loads using continuously coupled local interconnects while lowering overall resistance through highly redundant connections.

[0036] Specifically, power tap cell 120 includes a rail 150 formed by bonded local interconnects, which rail 150 is referred to as a bonded local interconnect (MLI) rail 150. In an embodiment, MLI rail 150 is formed from a top local interconnect (LI), a bottom LI, and a strap layer that secures the top LI to the bottom LI and continuously bonds the top LI to the bottom LI.

[0037] The MLI rail 150 is connected to the buried power rail using a short power via structure 160. In the example of Figure 1, the MLI rail 150 is in a north-south direction while the buried power rail 190 is in an east-west direction.

[0038] Additionally, power tap cell 120 includes a rail 130 formed on metal layer M0, which is referred to as M0 rail 130. M0 rail 130 is oriented east-west. M0 rail 130 is connected to wiring in metal layer M1 using, for example, a via referred to as V0, and to MLI rail 150 using a top contact to diffusion (CD) structure 140.

[0039] According to some aspects of the present disclosure, the components used in power tap cell 120 are similar to some components used to implement standard cells, and therefore power tap cell 120 can be fabricated using the same fabrication processes as active devices. In embodiments using a CFET approach, a logic standard cell has an N-type device (e.g., an N-type metal-oxide-semiconductor transistor, or NMOS transistor) and a P-type device (a P-type metal-oxide-semiconductor transistor, or PMOS transistor), where the N-type device is disposed above the P-type device and shares a common gate. In some embodiments, MLI rail 150 is formed in a manner similar to the drain connection of an inverter cell. In the case of an inverter cell, the drains of the N-type and P-type devices are connected. In embodiments, the drain connection of an inverter cell includes a top LI to the drain of the N-type device, a bottom LI to the drain of the P-type device, and a strap connection between the top LI and the bottom LI. Similarly, each of MLI rails 150 is formed from a top LI, a bottom LI, and a strap connection coupling the top LI and the bottom LI.

[0040] It should be noted that in some embodiments, additional masks and processes may be used to form the top and bottom LI strap connections and, therefore, to form the MIL rail 150.

[0041] The top LI, bottom LI, and strap connections of the MIL rail 150 may each be formed from any suitable conductive material or combination of conductive materials, such as copper, cobalt, or aluminum, ruthenium, titanium, doped polysilicon, etc.

[0042] Note that the standard cell may use several other components. For example, the standard cell may also include a top power via structure and a bottom CD structure. In some embodiments of the CFET, power is provided to the active devices from the BPR 190 using a power via structure. In an embodiment, the N-type device is positioned above the P-type device in a vertical direction perpendicular to the major surface of the substrate, and is connected to a buried power rail (e.g., V SS ) is connected to the N-type device using a high-power via structure and connected to a buried power rail (e.g., V DD ) are connected to the P-type using short power via structures. In some embodiments of the CFET, the metal layer M0 is connected to the active devices using contact to diffusion (CD) structures. In embodiments, the metal layer M0 may be connected to the N-type devices using top CD structures and to the P-type devices using bottom CD structures. In general, tall power via structures have higher resistance than short power via structures, and bottom CD structures have higher resistance than top CD structures. By using short power via structures and top CD structures in the MOL power delivery network 120, voltage drop during power delivery can be reduced.

[0043] 2 illustrates a top view of a semiconductor device 200 according to some embodiments of the present disclosure. The semiconductor device 200 is formed from patterns of various layers. Note that some layers, such as polysilicon layers, have been omitted in FIG. 2 for simplicity and clarity.

[0044] In the example of FIG. 2 , semiconductor device 200 includes three cell rows, referred to as cell row A, cell row B, and cell row C. The cell rows are oriented east-west and have the same height H. Each cell row includes multiple cells, such as logic standard cells and power tap cells. For example, cell row A includes inverter cell 201, power tap cell 221, and other logic cells 281 and 282. Cell row B includes inverter cell 202, power tap cell 222, and other logic cells 283 and 284. Cell row C includes inverter cell 203, power tap cell 223, and other logic cells 285 and 286. Power tap cells 221-223 occupy approximately the same footprint as the inverter cells.

[0045] In the embodiment of FIG. 2, the power tap cells 221-223 are aligned in a north-south direction, and each of the power tap cells 221-223 includes a section of a middle-of-line rail, and the sections are connected within the rail. For example, two MLI rails 250 and 255 are formed by connecting the sections in each of the power tap cells 221-223. Furthermore, the cells within a cell row are appropriately oriented, and cell row A and cell row B are aligned (e.g., V SS Cell row B and cell row C share BPR292 (for example, V DD Note that cell row A may share BPR 291 (e.g., for VDD) with its neighboring row to the north (not shown), and cell row C may share BPR 294 (e.g., for VSS) with its neighboring row to the south (not shown).

[0046] 2, the standard cell height can support four M0 rails. In power tap cells 221-223, M0 rail 230 may form multiple redundant connections with two MLI rails 250 and 255, respectively, and may couple the two MLI rails 250 and 255, respectively, to a UML power delivery network (not shown in FIG. 2). Details of semiconductor device 200 are described with reference to FIGS. 3-5.

[0047] 3 shows a top view 300A and a cross-sectional view 300B of the power tap cell 222 and the power tap cell 223, according to some embodiments of the present disclosure. The cross-sectional view 300B is taken along line BB' of the top view 300A.

[0048] In the embodiment of FIG. 3, BPRs 292 to 294 are arranged to extend in the east-west direction, and MLI rails 250 and 255 are arranged in the north-south direction perpendicular to BPRs 292 to 294.

[0049] The MLI rail 250 is formed by a top LI structure 251, a strap structure 252, and a bottom LI structure 253. The MLI rail 250 is connected to the BPR 293 by a short via structure 261. The MLI rail 250 is connected to the V DD It is connected to the M0 rail 231 for

[0050] In the embodiment of FIG. 3, each power tap cell has a V DD When power tap cells arranged in a cell row are connected as shown in FIG. 2, the power tap cells can redistribute the current load across the BPR, and the redundant connections can reduce the overall resistance.

[0051] 4 shows a top view 400A and a cross-sectional view 400B of power tap cell 221 and power tap cell 222, according to some embodiments of the present disclosure. Cross-sectional view 400B is taken along line CC' of top view 400A.

[0052] In the embodiment of FIG. 4, BPRs 291 to 293 are arranged to extend in the east-west direction, and MLI rails 250 and 255 are arranged in the north-south direction perpendicular to BPRs 291 to 293.

[0053] The MLI rail 255 is formed by a top LI structure 256, a strap structure 257, and a bottom LI structure 258. The MLI rail 255 is connected to the BPR 292 by a short via structure 262. The MLI rail 255 is connected to the V SS 2. The M0 rail 232 is connected to the M1 rail 232 for

[0054] In the example of Figure 4, each power tap cell includes a connection from the M0 rail for VSS to the BPR. When power tap cells arranged in a cell row are connected as shown in Figure 2, the power tap cells can redistribute the current load across the BPR, and the redundant connections can reduce the overall resistance.

[0055] 5 shows a top view 500A and two cross-sectional views 500B and 500C of logic cell 286 according to some embodiments of the present disclosure. Cross-sectional view 500B is taken along line D-D' through the source / drain region of the CFET, and cross-sectional view 500C is taken along line E-E' through the gate region of the CFET.

[0056] 5, an N-type device is formed above a P-type device in active structure 599. The source of the N-type device is connected to BPR 294 for VSS by top LI structure 259 and Thor power via 265, and the drain of the P-type device is connected to M0 rail 233 by bottom LI structure 254 and bottom CD 245.

[0057] 6 shows a flowchart outlining an example process for manufacturing a semiconductor device, such as semiconductor device 100 or semiconductor device 200. The process starts at S601 and proceeds to S610.

[0058] In S610, buried power rails are formed in rail openings in isolation trenches on the substrate, which in an embodiment form a BPR power delivery network.

[0059] At S620, active devices and a MOL power delivery network are formed. In some embodiments, the MOL power delivery network includes a MIL rail and an M0 rail. In some embodiments, the MIL rail includes a top LI structure, a bottom LI structure, and a strap structure coupling the top LI structure and the bottom LI structure. The MIL rail is connected to the BPR by a short power via, and the MIL rail and the M0 rail are connected by a top CD structure.

[0060] In S630, a top metal layer is formed, along with via structures connecting wiring from different metal layers. A UML power distribution network is formed in the top metal layer. In an embodiment, power input pads are formed in the top metal layer. The process then proceeds to S699, where it ends.

[0061] In the foregoing description, specific details have been set forth, such as the particular geometry of the processing system and descriptions of the various components and processes used therein. However, it should be understood that the technology herein may be practiced in other embodiments that deviate from these specific details, and that such details are for purposes of explanation and not limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding. Nevertheless, embodiments can be practiced without such specific details. Components having substantially the same functional configurations are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0062] To aid in understanding various embodiments, various techniques have been described as multiple discrete operations. The order of description should not be construed as to imply that these operations are necessarily order dependent. In fact, these operations need not be performed in the order presented. The operations described may be performed in a different order than in the described embodiments. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.

[0063] As used herein, "substrate" or "target substrate" refers generally to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device, particularly a semiconductor or other electronic device, and may be, for example, a base substrate structure such as a semiconductor wafer or a reticle, or a layer on or overlying a base substrate structure such as a thin film. Thus, substrate is not limited to any particular base structure, underlying layer or overlying layer, patterned or unpatterned, but rather is intended to include any such layer or base structure and any combination of layers and / or base structures. While the description may refer to a particular type of substrate, this is for illustrative purposes only.

[0064] Those skilled in the art will also appreciate that many variations can be made to the operation of the techniques described above and still achieve the same objectives of the present invention. Such variations are intended to be encompassed within the scope of the present disclosure. Accordingly, the above description of embodiments of the present invention is not intended to be limiting. Rather, any limitations to embodiments of the present invention are set forth in the following claims.

Claims

1. A semiconductor device comprising: a first power rail; a first power input structure configured to connect to a first terminal of a power source external to the semiconductor device to receive power from the power source; an active device formed between the first power rail and the first power input structure; a first middle-of-line rail formed by a plurality of layers, the first middle-of-line rail configured to supply the power from the first power input structure to the first power rail, the first power rail providing the power to the active devices for operation; Equipped with the active device includes a second transistor and a first transistor; the first transistor is disposed above the second transistor in a vertical direction, the vertical direction being parallel to a direction in which the active device is formed between the first power rail and the first power input structure; the first transistor is connected to the first power rail via a top local interconnect structure for connection with a source, and the second transistor is connected to a bottom local interconnect structure for connection with a drain; the first middle-of-line rail is flush with and at the same level as the top local interconnect structure and the bottom local interconnect structure.

2. moreover, a second power rail parallel to the first power rail; a second power input structure configured to connect to a second terminal of the power source and to receive the power from the power source using the second power input structure; a second middle-of-line rail formed by a plurality of layers, the second middle-of-line rail being parallel to the first middle-of-line rail, the first middle-of-line rail being configured to supply the power from the first power input structure to the first power rail, the second middle-of-line rail being configured to supply the power from the second power input structure to the second power rail, the first power rail and the second power rail providing the power to the active devices for operation; The semiconductor device of claim 1 , comprising:

3. the active device includes a row of cells of cell circuits having the same cell height; 2. The semiconductor device of claim 1, wherein the first middle-of-line rail includes a section within a power tap cell disposed in the row of cells, the power tap cell having the same cell height as the cell circuitry.

4. the active device includes a plurality of rows of cell circuits; The semiconductor device of claim 3 , wherein the first middle-of-line rails are formed from sections within power tap cells arranged in the plurality of rows of cells, respectively.

5. 5. The semiconductor device of claim 4, wherein the power tap cells are aligned in a column, and the sections within the respective power tap cells are conductively connected to form the first middle-of-line rail.

6. The semiconductor device of claim 4 , wherein the sections within the respective power tap cells are connected to the first power rail by at least power vias and to a metal rail by at least contacts.

7. 3. The semiconductor device of claim 2, wherein the first middle-of-line rail and the second middle-of-line rail are perpendicular to the first power rail and the second power rail when viewed from a stacking direction of the plurality of layers of the first middle-of-line rail.

8. 1. A method for manufacturing a semiconductor device, comprising: forming a first power rail; forming a first power input structure for coupling to a first terminal of a power source external to the semiconductor device to receive power from the power source; forming an active device between the first power rail and the first power input structure; the active device includes a second transistor and a first transistor; the first transistor is disposed vertically above the second transistor, the vertical direction being parallel to a direction in which the active devices are formed between the first power rail and the first power input structure; forming a first middle-of-line rail having a plurality of layers, the first middle-of-line rail supplying the power from the first power input structure to the first power rail, the first power rail providing the power to the active devices for operation; and the first transistor is connected to the first power rail via a top local interconnect structure for connection with a source, and the second transistor is connected to a bottom local interconnect structure for connection with a drain; a top layer of the first middle-of-line rail is at the same height and level as the top local interconnect structure; The method, wherein the bottom layer of the first middle-of-line rail is flush with and at the same level as the bottom local interconnect structure.

9. moreover, forming a second power rail parallel to the first power rail; forming a second power input structure coupled to a second terminal of the power source to receive the power from the power source; forming a second middle-of-line rail having a plurality of layers, the second middle-of-line rail being parallel to the first middle-of-line rail, the first middle-of-line rail being configured to supply the power from the first power input structure to the first power rail, the second middle-of-line rail being configured to supply the power from the second power input structure to the second power rail, the first power rail and the second power rail providing the power to the active devices for operation; The method of claim 8, comprising:

10. When viewed from the stacking direction of the plurality of layers of the first middle-of-line rail, 10. The method of claim 9, wherein the first and second middle-of-line rails are perpendicular to the first and second power rails.

11. The step of forming the active device and the first middle-of-line rail further comprises: forming rows of cell circuits having the same height; 9. The method of claim 8, wherein the first middle-of-line rail has a section at a power tap cell disposed in the row of cells, the power tap cell having the same cell height as the cell circuitry.

12. forming a plurality of rows of cell circuits, the rows including power tap cells arranged in the plurality of rows; forming the first middle-of-line rail using respective sections within the power tap cell; The method of claim 11 further comprising:

13. The method of claim 12 further comprising forming the power tap cells arranged in columns.

14. The method of claim 12 , wherein the sections within the respective power tap cells are connected to the first power rail by at least power vias and to a metal rail by at least contacts.

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