Capacitor including a stack of layers made of semiconductor materials with wide band gaps - Patents.com

Abstract

The invention relates to a capacitor (10) comprising a stack (1) of layers made of a semiconductor material with a band gap energy greater than 2.3 eV, the stack (1) of layers comprising an electrically insulating intermediate layer (3) having a resistivity greater than 10 kΩ·cm and containing a deep n- or p-type dopant creating an energy level greater than 0.4 eV from the conduction or valence band of the semiconductor material, and two contact layers (2a, 2b) having a resistivity less than or equal to 10 kΩ·cm and containing a dopant of a type opposite to the type of deep dopant of the intermediate layer (3), the two contact layers (2a, 2b) being arranged on either side of the intermediate layer (3) to form two junctions pn.

Description

[Technical Field]

[0001] The present invention relates to the field of microelectronic devices, and in particular to a capacitor comprising a stack of layers made of wide bandgap semiconductor materials. [Background technology]

[0002] Interest in wide bandgap semiconductors, such as silicon carbide, gallium nitride, or diamond, has grown significantly in recent years, as power devices and integrated power systems based on these materials can manage much higher power densities and have smaller active area dimensions compared to their conventional silicon analogues. They are increasingly being utilized in the manufacture of devices operating at high voltages and frequencies, particularly to meet the needs of growing electronics applications such as hybrid or electric vehicles.

[0003] In addition to active power devices, microelectronic circuits also require passive components such as capacitors capable of handling very high voltages (e.g., above 1000 V, or even above 3000 V) to form RC dampers that can eliminate voltage transients during switching between closed and open circuits, thus avoiding overload damage to the active devices.

[0004] Ceramic-insulator capacitors are known to withstand very high voltages. However, they have several drawbacks. First, their large size prevents them from being integrated as close as possible to active devices. The large distance between active and passive devices creates parasitic inductance, which becomes increasingly significant as switching frequencies increase. Additionally, these capacitors are not compatible with integration during cleanroom microelectronics fabrication of active devices. Finally, they operate within a limited temperature range, typically between room temperature and 125°C. Summary of the Invention [Problem to be solved by the invention]

[0005] The present invention aims to remedy all or some of the aforementioned drawbacks. The invention proposes a capacitor with fixed capacitance comprising a stack of layers made of wide bandgap semiconductors, which can withstand very high voltages, is reliable, has a constant capacitance value regardless of the applied voltage, has reduced dimensions and can operate over a wide temperature range, typically up to 300°C. The capacitor according to the invention is also compatible with microelectronic manufacturing methods and can therefore be monolithically co-integrated in the vicinity of active power devices. [Means for solving the problem]

[0006] The present invention relates to a capacitor comprising a stack of layers of semiconductor material having a bandgap energy greater than 2.3 eV, said stack of layers comprising: - an electrically insulating intermediate layer having a resistivity greater than 10 kΩ cm and containing n-type or p-type deep dopants that generate energy levels located more than 0.4 eV from the conduction or valence band of the semiconductor material; - two contact layers having a resistivity of less than 10 kΩ·cm and containing a dopant of a type opposite to the type of deep dopant of the intermediate layer, the two contact layers being electrically insulated from each other and disposed on either side of the intermediate layer to form two pn junctions.

[0007] According to other advantageous and non-limiting features of the present invention, alone or in any technically feasible combination: the two contact layers have a resistivity greater than 1 mΩ·cm, and the capacitor defines a capacitance with an integrated resistance to form an RC damper; The two contact layers have resistivities of 1 mΩ·cm or less, giving the capacitor pure capacitive properties. The capacitor includes two metal electrodes electrically connected to the two contact layers, respectively; Deep dopants are 1×10 14 / cm 3 ~1×10 21 / cm 3 present in the intermediate layer at a concentration of The intermediate layer has a thickness of 1 nm to 2 mm, preferably 500 nm to 50 μm, Each contact layer has a thickness of 5 nm to 50 μm, preferably 50 nm to 1 μm; the semiconductor material of the stack of layers is selected from silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), nitride-based ternary or quaternary alloys, boron nitride (BN), gallium oxide (Ga2O3) and diamond; The capacitor includes a support substrate on which the stack of layers is disposed; the support substrate is made of the same type of semiconductor material as the semiconductor material of the stack of layers; the semiconductor material forming the stack of layers is diamond, the deep dopant of the intermediate layer is n-type, the dopant of the contact layer is p-type and is boron atom; The deep dopant of the intermediate layer is a nitrogen atom, The semiconductor material forming the stack of layers is silicon carbide, the deep dopant in the intermediate layer is p-type and is a vanadium atom, and the dopant (shallow dopant) in the contact layer is n-type and is a nitrogen atom. [Brief explanation of the drawings]

[0008] Other features and advantages of the present invention will become apparent from the following detailed description of the invention which refers to the accompanying drawings.

[0009] [Figure 1] 1 is a diagram showing a first embodiment of a capacitor according to the present invention; [Figure 2] FIG. 2 shows a second embodiment of a capacitor according to the present invention.

[0010] The same reference numerals in the figures may be used for the same type of elements. The figures are schematic and not to scale for ease of reading. In particular, the thickness of layers along the z-axis is not to scale relative to the lateral dimensions along the x- and y-axes, and the relative thicknesses of layers therebetween are not necessarily respected in the figures. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention relates to a capacitor 10 comprising a stack 1 of layers made of semiconductor materials, known as wide bandgap materials, i.e. having a bandgap energy between the valence band and the conduction band greater than 2.3 eV. The semiconductor materials are in particular: Silicon carbide (SiC), for example 4H-SiC, with a band gap energy of 3.26 eV; - Gallium nitride (GaN), which has a bandgap energy of 3.4 eV; - aluminum nitride (AlN) with a band gap energy of 6.2 eV, - boron nitride (BN), which has a band gap energy of about 5.9 eV; - ternary or quaternary alloys based on nitrides, such as AlGaN, InGaN, etc. - gallium oxide (Ga2O3) with a band gap energy of 4.8 eV, and - Diamond has a band gap energy of 5.45 eV may be selected from:

[0012] The layer stack 1 of the capacitor 10 comprises three layers 2a, 2b, 3 made of wide bandgap semiconductor material, namely an intermediate layer 3 arranged between two contact layers 2a, 2b (FIGS. 1 and 2).

[0013] The contact layers 2a, 2b have a resistivity of less than 10 kΩ·cm. Depending on various aspects of the invention, they may have a resistivity of 10 Ω·cm or less, 1 Ω·cm or less, 10 mΩ·cm or less, or 1 mΩ·cm or less. To adjust the expected resistivity, the contact layers 2a, 2b are doped with n-type (donor) or p-type (acceptor) dopants that can increase the conductivity of the semiconductor material. They are intended to form (wholly or partially) the two metal armatures of the capacitor 10 and are therefore electrically isolated from each other.

[0014] As is well known per se, donors and acceptors are impurities (atoms) introduced into semiconductors, intentionally or unintentionally, where donors (n-type) can donate electrons to the conduction band or other levels within the band gap, and acceptors (p-type) can take in electrons from the valence band or other levels in the band gap.

[0015] Generally, a shallow donor is defined as one that can easily donate electrons to the conduction band of a semiconductor. This is related to the fact that the energy level in the band gap is slightly away from the conduction band. Therefore, a semiconductor heavily doped with shallow donors has conductive properties at room temperature due to the free electrons transferred to the conduction band by the donor. Similarly, a shallow acceptor is defined as one that has an energy level in the band gap slightly away from the valence band, so it can easily take in valence band electrons. Therefore, a semiconductor heavily doped with shallow acceptors has conductive properties at room temperature due to the free holes created in the valence band by the acceptor.

[0016] To achieve the expected resistivity range of the contact layers 2a, 2b, from 10 kΩ·cm to less than 1 mΩ·cm, the dopants introduced into those layers 2a, 2b are generally described as shallow dopants. However, certain dopants that are not typically considered shallow may be used to achieve the above resistivity. For example, in diamond, the ionization energy of the boron dopant is 0.38 eV for low dopant concentrations, and 5×10 20 / cm 3 The resistivity tends to 0 eV as the concentration increases until the insulator-metal transition is reached for doping of 0 eV. In this case, it is possible to achieve resistivities of less than 5 mΩ cm in diamond heavily doped with boron.

[0017] Hopping conduction also makes it possible to achieve low resistivity using dopants such as boron (acceptor) or phosphorus (donor) in diamond. To take advantage of this phenomenon, the boron concentration must be less than 1×10 19 / cm 3 ~5×10 20 / cm 3 and the phosphorus concentration must be 1 x 10 19 / cm 3 Greater than.

[0018] The semiconductor material of the contact layers 2a, 2b may have a polycrystalline structure, or preferably a monocrystalline structure, in order to reduce leakage (parasitics) and to provide a better interface with the intermediate layer 3 if it is itself monocrystalline.

[0019] The intermediate layer 3 is electrically insulating, ie has a resistivity greater than 10 kΩ·cm.

[0020] Advantageously, the resistivity of the intermediate layer 3 is as high as possible, for example greater than 1000 kΩ cm. It contains deep dopants, defined here as those that generate energy levels located above 0.4 eV of the conduction or valence band of the semiconductor material. The deep dopants of the intermediate layer 3 can be deep donors (n-type) or deep acceptors (p-type) specific to the nature of the semiconductor material.

[0021] Deep dopants are donors or acceptors with higher binding energies for electrons and holes, respectively, and therefore are not substantially ionized at room temperature. Compared with shallow donors and acceptors, the energy levels of deep donors and acceptors are deeper in the band gap, i.e., located farther from the conduction band and valence band, respectively. Therefore, the insulating properties of the intermediate layer 3 can be fully maintained in the presence of these deep dopants.

[0022] Preferably, for operation of the capacitor 10 above 150° C., deep dopants are selected that create energy levels located more than 1 eV from the valence band (acceptor) or conduction band (donor). For example, for diamond, 1×10 16 / cm 3 For deep dopant concentrations of about 1000 kΩ·cm, it is desirable for the ionization energy of the deep dopant to be greater than 1 eV, or up to 1.3 eV, to ensure a resistivity of the intermediate layer 3 of 1000 kΩ·cm or more for operation at 150° C. or 250° C., respectively.

[0023] Generally, deep dopants are 1×10 14 / cm 3 ~1×10 21 / cm 3 However, this concentration range may be more limited in the specific case of deep dopants, typically 1×10 14 / cm 3 ~1×10 18 / cm 3It should be noted that, indeed, above a certain concentration, certain deep dopants (such as phosphorus in diamond already mentioned above) can participate in electrical conduction by the phenomenon of conduction by hopping, which is undesirable in the intermediate layer 3.

[0024] The semiconductor material of the intermediate layer 3 may have a polycrystalline structure or preferably be monocrystalline to ensure good electrical insulation by avoiding leakage currents and premature breakdown that may be promoted by the presence of grain boundaries.

[0025] In the layer stack 1 of the capacitor 10 according to the invention, the dopants of the contact layers 2a, 2b are of the opposite type to the deep dopant type of the intermediate layer 3. As the two contact layers 2a, 2b are arranged on either side of the intermediate layer 3, the layer stack 1 therefore forms two pn junctions, one between the upper contact layer 2a and the intermediate layer 3 and the other between the lower contact layer 2b and the intermediate layer 3.

[0026] Thus, the capacitor 10 includes, in order, an upper contact layer 2a, a pn junction, an insulating intermediate layer 3, a pn junction, and a lower contact layer 2b. The pn junction prevents carrier injection from the contact layers 2a, 2b into the intermediate layer 3 through the contact layers 2a, 2b when a high voltage is applied to the capacitor 10. Such injection significantly degrades the insulating properties of the intermediate layer 3. The pn junction established between the contact layers 2a, 2b and the intermediate layer 3 provides the capacitor 10 of the present invention with great stability and excellent reliability. The capacitor effect is provided by the non-depleted zone of the intermediate layer 3 and by the two space charge zones of the two pn junctions, provided that the dopant in the intermediate layer 3 is deep enough to ensure electrical insulation at operating temperatures. At high operating temperatures (typically above 150°C), the overlap of the two space charge zones of the two pn junctions can be used to enhance the electrical insulation of the intermediate layer 3.

[0027] The capacitor 10 according to the present invention takes advantage of the presence of deep dopants in the intermediate layer 3, of the opposite type to the shallow dopants of the contact layers 2a, 2b, on the one hand to ensure the insulating properties (deep impurity properties) of said intermediate layer 3, and on the other hand to establish two pn junctions (deep impurities used as dopants) which provide a fixed capacitance value and give the capacitor 10 electrical insulation, stability and reliability.

[0028] The intermediate layer 3 may have a thickness (along the z-axis in the figure) of 10 nm to 2 mm, preferably 500 nm to 50 μm. Each of the contact layers 2a, 2b may have a thickness of 5 nm to 50 μm, preferably 50 nm to 1 μm.

[0029] According to a first example of a capacitor 10 according to the invention, the semiconductor material forming the stack of layers 1 is diamond. The deep dopants of the intermediate layer 3 are n-type (donor). They can be phosphorus atoms (P) or, preferably, nitrogen atoms (N). In diamond, phosphorus and nitrogen create deep levels in the band gap, 0.57 eV and 1.7 eV below the conduction band, respectively.

[0030] For example, the concentration of deep nitrogen donors is 3 × 10 19 / cm 3 and the intermediate layer 3 has a resistivity greater than 1000 kΩ cm. Alternatively, the concentration of the deep phosphorus donor is 1×10 15 / cm 3 The resistivity of the intermediate layer 3 is about 100 kΩ·cm.

[0031] The dopant in the contact layers 2a and 2b is boron (B), a p-type (acceptor) atom. In diamond, boron creates a level in the band gap, 0.38 eV above the valence band. However, as mentioned above, the ionization energy of boron decreases with increasing dopant concentration.

[0032] For example, 5 x 10 20 / cm 3For an acceptor concentration of about 5×10, the contact layers 2a, 2b have a resistivity of less than 5 mΩ·cm. 14 / cm 3 At an acceptor concentration of about 1 kΩ·cm, the contact layers 2a and 2b have a resistivity of about 1 kΩ·cm.

[0033] In this first example, a stack 1 of three layers 2a, 3, 2b defines a p / n / p type stack.

[0034] According to a second example of a capacitor 10 according to the invention, the semiconductor material forming the stack of layers is silicon carbide (SiC). The deep dopant of the intermediate layer 3 is vanadium (V) atoms, p-type. In SiC, vanadium creates a deep level in the band gap, 0.8 eV below the conduction band.

[0035] For example, the concentration of deep acceptors is 1×10 15 / cm 3 The intermediate layer 3 has a resistivity of greater than 100 kΩ·cm.

[0036] The shallow dopant in the contact layers 2a and 2b is nitrogen atom, n-type. In SiC, nitrogen creates a shallow level in the band gap, 0.08 eV below the conduction band. For example, 19 / cm 3 At a donor concentration of about 1000 .mu.m, the contact layer 3 has a resistivity of less than 20 m.OMEGA.cm.

[0037] In this second example, the stack 1 of three layers 2a, 3, 2b defines an n / p / n type stack.

[0038] Of course, these two examples are not exhaustive, and other wide-bandgap semiconductor materials can be implemented in the capacitor 10 of the present invention. A p / n / p or n / p / n stack can be used depending on the properties of the semiconductor material, particularly as a function of the type of deep and shallow dopants in that material. For connection to a circuit or another microelectronic component, the capacitor 10 advantageously includes two metal electrodes 4a, 4b electrically connected to the two contact layers 2a, 2b, respectively. These electrodes 4a, 4b are in ohmic contact with the layers 2a, 2b, allowing electrical connection of the capacitor 10 to the outside. Thus, each electrode 4a, 4b can be composed of one or more metal layers formed on the contact layers 2a, 2b. Of course, the connection between the two contact layers 2a, 2b and the outside can alternatively be performed by any other known means allowing electrical connection of the layers 2a, 2b.

[0039] The capacitor 10 according to the invention is part of the category of fixed capacitance non-polarized capacitors. Here, it is understood that the capacitance remains constant (i.e., has a variation of less than 10%, or even less than 1%) whatever the voltage applied to these armatures (contact layers 2a, 2b or electrodes 4a, 4b), which voltage may be greater than a few kV, greater than 1000 V, greater than 2000 V, or even greater. The two contact layers 2a, 2b (potentially with their electrodes 4a, 4b) form the two metallic armatures of the capacitor 10, separated by an insulating material (intermediate layer 3). When a voltage is applied between the two armatures, an electric field is formed in the insulating material (intermediate layer 3).

[0040] Capacitor 10 is defined by its capacitance C in Farads (F) as follows:

[0041]

number

[0042] where ε0 is the dielectric constant of a vacuum, ε r is the relative permittivity (intermediate layer 3), S is the surface area of ​​the metal armature, and d is the thickness of the intermediate layer 3.

[0043] Therefore, the value of capacitance C is - S, the larger S, the larger C, - d, the smaller d is, the larger C is; - ε r , ε r The larger is, the larger is C. There are dependencies such as:

[0044] Without being limited thereto, the lateral dimensions of the capacitor 10, which define the surface area S of the metal armature, can be between 10 μm and 10 mm.

[0045] In addition to these parameters, the capacitor 10 is limited by the maximum electric field that the intermediate layer 3 can withstand. Wide bandgap semiconductors are known to have very high maximum electric fields. For example, for SiC, this field is about 3 MV / cm, and for diamond, it is 10 MV / cm. This unique property of the intermediate layer 3 makes it possible to push back the limits of currently available capacitors.

[0046] According to the first aspect of the invention, the two contact layers 2a, 2b have a resistivity of 1 mΩ·cm or less, in which case the series resistance of the capacitor 10 is negligible (compared to other resistances of the circuit in which the capacitor 10 is incorporated), and the capacitor 10 then exhibits a purely capacitive behavior.

[0047] According to the second aspect of the invention, the two contact layers 2a, 2b have a resistivity greater than 1 mΩ·cm (and, recall, less than 10 kΩ·cm). The series resistance of the capacitor 10 becomes significant (compared to other resistances of the circuit in which it is incorporated) and can be adjusted to create an RC damper. The capacitor 10 then defines a capacitance with an integrated resistance, forming an RC damping device.

[0048] The following embodiments may be applied to one or other of the above aspects of the invention.

[0049] In the first embodiment of the capacitor 10 shown in FIG. 1, each electrode 4a, 4b is arranged on a major surface (in the (x,y) plane) of the stack of layers 1.

[0050] According to a second embodiment shown in Figure 2, the stack of layers 1 is arranged on a support substrate 5 included in the capacitor 10, which support substrate 5 typically forms a support for the growth of the layers of stack 1. The support substrate 5 may consist of the same type of semiconductor material as the semiconductor materials of the stack of layers 1, or it may consist of a different type of semiconductor material that allows the growth of the layers of stack 1.

[0051] The presence of this support substrate 5 changes the arrangement of the electrodes 4a, 4b. The electrode 4a is arranged on the free main surface of the top contact layer 2a. The bottom contact layer 4b has a surface in the plane (x, y) that is larger than the surfaces in the same plane of the other layers of the stack 1 (i.e. the intermediate layer 3 and the top contact layer 4a). The other electrode 4b can therefore be brought into contact with the bottom contact layer 2b on its periphery, which is free from the other layers of the stack 1 (FIG. 2).

[0052] Here, an example of the manufacturing method of the first and second embodiments will be described, in which diamond is selected as the semiconductor material.

[0053] (First embodiment) The starting point is a nitrogen (N)-rich type Ib diamond wafer obtained by high-pressure high-temperature (HPHT) techniques or chemical vapor deposition (CVD). This wafer has a 1×10 19 / cm 3 It has a concentration of deep donor N and has the expected insulating properties (resistivity greater than 10 kΩ·cm).

[0054] This wafer is then trimmed to the desired thickness, for example by grinding or laser cutting, to form the intermediate layer 3 .

[0055] The choice of thickness of the intermediate layer 3, for example 50 μm, determines the value of the capacitance.

[0056] The intermediate layer 3 is then treated in a conventional cleaning acid bath to remove contaminants such as graphite, metals, organic and inorganic materials. The deposition (growth) of highly conductive monocrystalline diamond layers (of p++ type) is carried out on both sides of the intermediate layer 3 to form the two contact layers 2a, 2b. The deposition can be carried out, for example, by hot filament (HF) or by microwave plasma (MP) CVD. The concentration of boron atoms B is 5×10 20 atm / cm 3 The thickness is, for example, 200 nm.

[0057] The next step consists in metallizing the surfaces of the contact layers 2a, 2b. For this, deposition of metals, titanium (Ti) followed by gold (Au), is carried out, for example, on the free surfaces of the two layers 2a, 2b, with a total thickness of 70 nm (30 nm Ti and 40 nm Au). Of course, other metals that form ohmic contacts may also be used. Next, annealing of the structure is carried out to promote the formation of carbides and to impart ohmic properties to the contacts. Annealing can be carried out for 1 hour at 450 °C under vacuum with a flow of inert gas, for example, argon, using a simple furnace or RTA system for rapid and controlled temperature increase.

[0058] A capacitor structure 10 according to the first embodiment of the invention is then obtained (FIG. 1), which has a very high voltage, typically up to several kV, and a capacitance of 1 pF / mm 2 Here, the contact layers 2a, 2b have a resistivity of less than 1 mΩ·cm, giving the capacitor 10 a purely capacitive nature (first aspect of the invention).

[0059] (Second embodiment) A starting support substrate 5 of any known type made of single crystal diamond is obtained by high pressure, high temperature (HPHT) techniques or chemical vapor deposition (CVD). A conventional acid bath clean is applied to the support substrate 5 to remove contaminants.

[0060] The growth of a highly conductive (p++ type) monocrystalline diamond layer is carried out on the support substrate 5, forming the lower contact layer 2b of the stack 1. The deposition can be carried out, for example, by hot filament (HF) or microwave plasma (MP) CVD. The concentration of boron atoms B is 5×10 20 atm / cm 3 The thickness is 200 nm. Next, the deposition (growth) of an electrically insulating, n-type (deep nitrogen dopant) monocrystalline diamond layer is carried out to form the intermediate layer 3. The concentration of deep donors is 1×10 19 atm / cm 3and the thickness of the intermediate layer 3 is about 1 μm. Finally, a new growth of a highly conductive (p++ type) single crystalline diamond layer is carried out on the intermediate layer 3 to form the upper contact layer 2 a of the stack 1 identical to the lower contact layer 2 b.

[0061] A mask, for example made of aluminum, is then deposited on the upper contact layer 2a to define a smaller than desired surface of the lower contact layer 2b. The unmasked parts of the upper contact layer 2a and the intermediate layer 3 can then be etched until the lower contact layer 2b is reached.

[0062] After removing the mask, metallization of the free surfaces of the contact layers 2a, 2b can be performed, for example, in two successive steps using a mask and / or lithographic techniques. To form ohmic contacts between each contact layer 2a, 2b and its electrodes 4a, 4b, titanium (Ti) and gold (Au) deposits, or other metals, can be applied. Each electrode 4a, 4b has a thickness of 70 nm. Annealing of the structure, for example as described in the first embodiment, is then performed to promote the formation of carbides and to provide ohmic contact properties.

[0063] According to a variant of the second embodiment, after the growth of the lower contact layer 2b, a metal mask is deposited on the surface of said layer 2b, which must be free of other layers of the stack 1. The intermediate layer 3 and the upper contact layer 2a are then produced by selective growth only on the defined surface (the central surface in FIG. 2). Removal of the mask and metallization can then be carried out as described above.

[0064] Whatever the variant used, a capacitor structure 10 according to the second embodiment of the invention is then obtained, which, regardless of the voltage applied to its terminals, is suitable for very high voltages, typically up to 1000 V, and has a capacitance of 0.05 nF / mm 2Here, the contact layers 2a, 2b have a resistivity of less than 1 mΩ·cm, giving the capacitor 10 a purely capacitive nature (first aspect of the invention).

[0065] According to a second aspect of the invention, in which the capacitor 10 forms an RC damping device, the contact layers 2a, 2b have a thickness of about 1 μm and a resistivity of 1 kΩ·cm (typically 5×10 14 / cm 3 (corresponding to a boron dopant concentration of about 0.05 nF / mm 2 With the same capacitance as above, it is possible to obtain a time constant of the RC damping circuit of 1 ns.

[0066] It should be noted that the second embodiment offers greater flexibility in terms of capacitance, since the thickness of the intermediate layer 3 (insulator) can be manufactured and adjusted more easily than the first embodiment.

[0067] The capacitor 10 according to the present invention can store high energy, typically voltages greater than 1000 V, greater than 3000 V, or even greater than 5000 V. It offers great stability of capacitance value over temperature over an extended temperature range from -30°C to 300°C. Temperature-induced leakage current is negligible.

[0068] The capacitor 10 is fabricated by microelectronic methods and is therefore amenable to monolithic co-integration with active components on the same chip.

[0069] The capacitor according to the invention constitutes a passive component that can be integrated into all power converters used, for example, in hybrid and / or electric vehicles, in aeronautics, in energy management, etc. When integrated into busbar and damping RC networks, it makes it possible to protect electrical circuits from component failure due to voltage spikes, typically exceeding 2000 V, generated during switching between closed and open circuits.

[0070] In general, a capacitor according to the present invention can be used to protect high voltage electrical circuits against voltage transients.

[0071] Naturally, the invention is not limited to the described embodiments and examples, and variations in implementation may be applied without departing from the scope of the invention as defined by the claims.

Claims

1. A capacitor (10) comprising a stack (1) of layers of semiconductor material having a bandgap energy greater than 2.3 eV, said stack (1) of layers comprising: an electrically insulating intermediate layer (3) having a resistivity greater than 10 kΩ cm and containing n-type or p-type deep dopants that create energy levels located more than 0.4 eV from the conduction or valence band of the semiconductor material; two contact layers (2a, 2b) having a resistivity of less than 10 kΩ cm and containing a dopant of a type opposite to the deep dopant of the intermediate layer (3), the two contact layers (2a, 2b) being electrically insulated from each other and arranged on either side of the intermediate layer (3) to form two pn junctions; A capacitor (10) comprising:

2. 2. The capacitor (10) of claim 1, wherein the two contact layers (2a, 2b) have a resistivity greater than 1 mΩ cm, and the capacitor (10) defines a capacitance with an integrated resistance to form an RC damper.

3. 2. The capacitor (10) of claim 1, wherein the two contact layers (2a, 2b) have a resistivity of 1 mΩ·cm or less, giving the capacitor (10) a purely capacitive property.

4. The deep dopant is 1×10 １４ / cm ３ ~1 x 10 ２１ / cm ３ The capacitor (10) according to any one of claims 1 to 3, wherein the metal oxide is present in the intermediate layer (3) at a concentration comprised within:

5. The intermediate layer (3) has a thickness of 10 nm to 2 mm, Each contact layer (2a, 2b) has a thickness of 5 nm to 50 microns; A capacitor (10) according to any one of claims 1 to 4.

6. A capacitor (10) as described in any one of claims 1 to 5, comprising a support substrate (5) on which the stack of layers (1) is arranged.

7. A capacitor (10) as described in any one of claims 1 to 6, wherein the semiconductor material of the stack of layers (1) is selected from silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), nitride-based ternary or quaternary alloys, boron nitride (BN), gallium oxide (Ga2O3), and diamond.

8. the semiconductor material forming the stack of layers (1) is diamond, The deep dopant of the intermediate layer (3) is n-type; The capacitor (10) according to any one of claims 1 to 6, wherein the dopants of the contact layers (2a, 2b) are p-type and are boron atoms (B).

9. The capacitor (10) of claim 8, wherein the deep dopant is a nitrogen atom (N).

10. the semiconductor material forming the stack of layers is silicon carbide (SiC); The deep dopant of the intermediate layer (3) is p-type and is a vanadium atom (V); 7. Capacitor according to any one of claims 1 to 6, wherein the dopants of the contact layers (2a, 2b) are n-type and are nitrogen atoms (N).

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