Hybrid Under-Bump Metallization Components

Abstract

To provide a method of fabricating a flip chip device that can eliminate oxide formation (e.g., oxidation) between various components of the flip chip device thereby facilitating improved electrical coupling between such components.SOLUTION: A device 100A that can facilitate hybrid under-bump metallization components comprises: an under-bump metallization component 124B that comprises a superconducting interconnect component (e.g., a second superconducting layer 106, a third superconducting layer 108, a solder bump 122, or the like) and a solder wetting component 112; and a solder bump coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component comprises a hermetically sealed superconducting interconnect component.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to superconducting devices, and more particularly to superconducting, mechanically robust under-bump metallization components fabricated on semiconductor substrates. [Background technology]

[0002] Quantum computing is the use of quantum mechanical phenomena, typically for the purpose of performing computational and information processing functions. Quantum computing can be seen in contrast to classical computing, which typically uses transistors and operates on binary values. That is, while classical computers can operate on bit values ​​that are either 0 or 1, quantum computers operate on qubits, which contain superpositions of both 0 and 1, and can entangle multiple qubits and use interference.

[0003] Quantum computing hardware can differ from classical computing hardware. In particular, quantum computing hardware typically comprises superconducting quantum circuits, which can be fabricated in semiconductor devices and employed in flip-chip mounted quantum devices that can be used in such quantum computing hardware. Such quantum computing hardware (e.g., superconducting quantum processors) can perform computational and information processing functions that are significantly more complex than those that can be performed by classical computing devices (e.g., general-purpose computers, special-purpose computers, etc.).

[0004] Challenges associated with designing such superconducting quantum circuits that may be implemented in flip-chip mounted quantum devices include, but are not limited to, providing superconducting and mechanically robust interconnections between the various components of such superconducting quantum circuits and / or flip-chip mounted quantum devices, as well as providing hermetically sealed superconducting interconnections between the various components of such circuits and / or devices. While existing superconducting quantum circuits and / or flip-chip mounted quantum devices attempt to overcome one or more of the challenges previously listed, such prior art circuits and / or devices either fail to do so or introduce design trade-offs, manufacturing trade-offs, or other issues, such as, for example, unreliable performance or excessive power consumption or both, or a combination thereof.

[0005] For example, some prior art superconducting quantum circuits and / or flip-chip mounted quantum devices provide superconducting interconnections between various components of such circuits and / or devices. Problems with such prior art include, but are not limited to, not providing hermetic superconducting interconnections and / or weak mechanical coupling between the various components of such circuits and / or devices. In another example, some prior art circuits and / or devices provide strong mechanical coupling between the various components of integrated circuits and / or flip-chip mounted devices. Problems with such prior art include, but are not limited to, not providing superconducting interconnections between the various components of such integrated circuits and / or flip-chip mounted devices and / or not providing hermetic superconducting interconnections between the various components of such integrated circuits and / or flip-chip mounted devices.

[0006] Therefore, there is a need in the art to address the aforementioned problems. Summary of the Invention

[0007] Viewed from a first aspect, the present invention provides a device including an under-bump metallization component including a superconducting interconnect component and a solder-wettable component, and a solder bump coupled to the superconducting interconnect component and the solder-wettable component.

[0008] Viewed from yet another aspect, the present invention provides a method that includes depositing solder on an under-bump metallization component and forming a superconducting interconnect component and an intermetallic layer on the under-bump metallization component based on the deposition.

[0009] Viewed from yet another aspect, the present invention provides a device including a substrate having a superconducting layer and an intermetallic layer, and a solder bump coupled to the superconducting layer and the intermetallic layer.

[0010] Viewed from yet another aspect, the present invention provides a device including a first under-bump metallization component including a superconducting interconnect component and an intermetallic compound layer, and a solder bump coupled to the superconducting interconnect component, the intermetallic compound layer, and the second under-bump metallization component.

[0011] Viewed from yet another aspect, the present invention provides a method including bonding a first under bump metallization component to a second under bump metallization component including a superconducting interconnect component and an intermetallic compound layer, and forming a hermetically sealed superconducting interconnect component on the first under bump metallization component based on the bonding.

[0012] The following presents a summary intended to provide a basic understanding of one or more embodiments of the present invention. This summary is not intended to identify key or critical elements or to delineate the scope of particular embodiments or the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a device, system, computer-implemented method, apparatus, and / or computer program product that facilitates hybrid under-bump metallization components is described.

[0013] According to one embodiment, a device can include an underbump metallization component including a superconducting interconnect component and a solder-wettable component. The device can further include solder bumps that can be coupled to the superconducting interconnect component and the solder-wettable component. An advantage of such a device is that it can facilitate superconducting interconnections between various components of a superconducting quantum circuit and / or flip-chip mounted quantum device, and robust mechanical coupling of those components.

[0014] In another embodiment, the superconducting interconnect component may comprise a hermetically sealed superconducting interconnect component, an advantage of which is that it may eliminate oxide formation (e.g., oxidation) between various components of the superconducting quantum circuit and / or flip-chip mounted quantum device that may be coupled by such a hermetically sealed superconducting interconnect component, thereby facilitating improved electrical coupling between such components.

[0015] According to one embodiment, a method includes depositing solder on an under-bump metallization component. The method may further include forming a superconducting interconnect component and an intermetallic compound layer on the under-bump metallization component based on such deposition. An advantage of such a method is that it may be employed to fabricate hybrid under-bump metallization components that can facilitate superconducting interconnections between and robust mechanical coupling of various components of superconducting quantum circuits and / or flip-chip mounted quantum devices.

[0016] In another embodiment, the method can further include forming a hermetically sealed superconducting interconnect component on the under-bump metallization component based on such deposition. An advantage of such a method is that it can be employed to fabricate hybrid under-bump metallization components that can eliminate oxide formation (e.g., oxidation) between various components of superconducting quantum circuits and / or flip-chip mounted quantum devices that may be coupled by such hermetically sealed superconducting interconnect component, thereby facilitating improved electrical coupling between such components.

[0017] According to one embodiment, a device can include a substrate including a superconducting layer and an intermetallic layer. The device can further include solder bumps that can be coupled to the superconducting layer and the intermetallic layer. An advantage of such a device is that it can facilitate superconducting interconnections between various components of a superconducting quantum circuit and / or flip-chip mounted quantum device, and robust mechanical coupling of those components.

[0018] In another embodiment, the superconducting layer may be sealed by at least one of an intermetallic layer or a solder bump. An advantage of such a device is that it may eliminate oxide formation (e.g., oxidation) between various components of a superconducting quantum circuit and / or flip-chip mounted quantum device that may be joined by such sealed superconducting layers, thereby facilitating improved electrical coupling between such components.

[0019] According to one embodiment, a device can include a first under-bump metallization component including a superconducting interconnect component and an intermetallic compound layer. The device can further include solder bumps that can be coupled to the superconducting interconnect component, the intermetallic compound layer, and the second under-bump metallization component. An advantage of such a device is that it can facilitate superconducting interconnections between and robust mechanical coupling of various components of a superconducting quantum circuit and / or flip-chip mounted quantum device.

[0020] In another embodiment, the superconducting interconnect component may comprise a hermetically sealed superconducting interconnect component, an advantage of which is that it may eliminate oxide formation (e.g., oxidation) between various components of the superconducting quantum circuit and / or flip-chip mounted quantum device that may be coupled by such a hermetically sealed superconducting interconnect component, thereby facilitating improved electrical coupling between such components.

[0021] According to one embodiment, a method includes bonding a first under-bump metallization component to a second under-bump metallization component including a superconducting interconnect component and an intermetallic compound layer. The method further includes forming a hermetically sealed superconducting interconnect component on the first under-bump metallization component based on such bonding. An advantage of such a method is that it can be employed to fabricate flip-chip devices that can facilitate superconducting interconnections between various components of such flip-chip devices and robust mechanical bonding of those components. Another advantage of such a method is that it can be employed to fabricate flip-chip devices that can eliminate oxide formation (e.g., oxidation) between various components of such flip-chip devices that can be bonded by such hermetically sealed superconducting interconnect components, thereby facilitating improved electrical bonding between such components.

[0022] Embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0023] [Figure 1] FIG. 1 is a side cross-sectional view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 2] FIG. 1 is a side cross-sectional view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 3] FIG. 1 is a top view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 4]FIG. 1 is a side cross-sectional view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 5] FIG. 1 is a side cross-sectional view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 6] FIG. 1 is a side cross-sectional view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 7] FIG. 1 is a side cross-sectional view of an exemplary non-limiting device facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 8] FIG. 1 is a flow diagram of an example non-limiting methodology that facilitates implementing a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 9] FIG. 1 is a flow diagram of an example non-limiting methodology that facilitates implementing a hybrid under-bump metallization component in accordance with one or more embodiments described herein. [Figure 10] FIG. 1 is a block diagram of an exemplary non-limiting operating environment that can facilitate one or more embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0024] The following detailed description is exemplary only and is not intended to limit the embodiments or the application and / or uses of the embodiments, nor is it intended to be bound by any express or implied information presented in the preceding "Background" or "Summary" sections or in the "Detailed Description" section.

[0025] One or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It will be apparent, however, that one or more embodiments may be practiced in various instances without these specific details.

[0026] Given the above-mentioned problems associated with existing superconducting quantum circuits and / or flip-chip mounted quantum devices, which do not facilitate both superconducting interconnections between various components of the superconducting quantum circuit and / or flip-chip mounted quantum device, and robust mechanical coupling of those components, the present disclosure provides implementations that provide a solution to this problem in the form of a hybrid under-bump metallization component that includes a superconducting interconnect component and an intermetallic compound layer. An advantage of such a device is that it can facilitate superconducting interconnections between various components of the superconducting quantum circuit and / or flip-chip mounted quantum device, and robust mechanical coupling of those components.

[0027] Furthermore, given the above-mentioned problem associated with existing superconducting quantum circuits and / or flip-chip mounted quantum devices of not having hermetically sealed superconducting interconnects between various components of the superconducting quantum circuit and / or flip-chip mounted quantum device and robust mechanical coupling of those components, the present disclosure may provide implementations that provide a solution to this problem in the form of a hybrid under-bump metallization component that includes a hermetically sealed superconducting interconnect component and an intermetallic compound layer. An advantage of such a device is that it may eliminate oxide formation (e.g., oxidation) between various components of the superconducting quantum circuit and / or flip-chip mounted quantum device that may be coupled by such hermetically sealed superconducting interconnect component, thereby facilitating improved electrical coupling between such components.

[0028] 1(A)-(D) illustrate one exemplary, non-limiting, multi-step fabrication sequence that may be performed to fabricate one or more embodiments of the present disclosure described herein and / or illustrated in the figures. For example, in accordance with one or more embodiments described herein, the non-limiting multi-step fabrication sequence illustrated in FIG. 1(A)-(D) may be performed to fabricate device 100D (shown in FIG. 1(D)), which may include under-bump metallization component 124B.

[0029] According to various embodiments, the present disclosure (e.g., device 100D, under-bump metallization component 124B, etc.) described and / or illustrated in the figures may comprise one or more components of a superconducting quantum circuit and / or superconducting quantum device (e.g., quantum computing device, quantum computing hardware, etc.). In some embodiments, the present disclosure (e.g., device 100D, under-bump metallization component 124B, etc.) described and / or illustrated in the figures may be fabricated in a semiconductor device using one or more techniques for fabricating integrated circuits.

[0030] As described below with reference to Figures 1(A)-(D), fabrication of various embodiments of the present disclosure (e.g., device 100D, under-bump metallization component 124B, etc.) described and / or illustrated herein may include a sequence of multiple steps, e.g., photolithographic and / or chemical processing steps, that facilitate the incremental creation of an electronics-based (e.g., microelectronics-based) system, device, component, or circuit, or combination thereof, on one or more substrate layers. For example, various embodiments of the present disclosure (e.g., device 100D, under-bump metallization component 124B, etc.) described herein and / or illustrated in the figures may be fabricated by employing techniques including, but not limited to, photolithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques, etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, etc.), evaporation techniques, sputtering techniques, plasma ashing techniques, thermal treatments (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, etc.), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical-mechanical planarization (CMP), backgrinding techniques, or another technique for manufacturing integrated circuits, or a combination thereof.

[0031] 1(A)-(D) , various embodiments of the present disclosure (e.g., device 100D, under bump metallization component 124B, etc.) described and / or illustrated herein may be fabricated using a variety of materials. For example, various embodiments of the present disclosure (e.g., device 100D, under bump metallization component 124B, etc.) described and / or illustrated herein may be fabricated using materials from one or more different material classes, including, but not limited to, conductive materials, semiconductor materials, superconducting materials, dielectric materials, polymeric materials, organic materials, inorganic materials, non-conductive materials, or other materials that may be utilized in one or more of the aforementioned techniques for fabricating integrated circuits, or combinations thereof.

[0032] 1A illustrates a cross-sectional side view of an exemplary, non-limiting device 100A for facilitating a hybrid under-bump metallization component according to one or more embodiments described herein. According to some embodiments, device 100A may include a substrate 102, a first superconducting layer 104, a second superconducting layer 106 (which may protect first superconducting layer 104 from oxidation), a third superconducting layer 108 (which may improve adhesion between second superconducting layer 106 and solder diffusion layer 110), a solder diffusion layer 110, or a solder wetting layer 112, or a combination thereof.

[0033] According to various embodiments, the substrate 102 can include a semiconductor material. For example, the substrate 102 can include silicon (Si), sapphire (e.g., aluminum oxide (Al2O3)), or another semiconductor material, or a combination thereof. For example, the substrate 102 can include silicon (Si), sapphire (e.g., aluminum oxide (Al2O3)), or another semiconductor material that can reduce the dielectric loss tangent at low temperatures, or a combination thereof.

[0034] In some embodiments, substrate 102 can have any thickness that ensures mechanical stability of all material layers and / or components coupled to substrate 102. For example, substrate 102 can be polished (e.g., by back-grinding) to a thickness (e.g., height) in the range of 10 micrometers (μm) to 1,000 μm.

[0035] According to various embodiments, the first superconducting layer 104 may include a superconducting material. For example, the first superconducting layer 104 may include niobium (Nb), aluminum (Al), rhenium (Re), tungsten (W), diamond, or another superconducting material, or a combination thereof.

[0036] In some embodiments, the first superconducting layer 104 may be coupled to the substrate 102. For example, the first superconducting layer 104 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to an upper surface of the substrate 102. In some embodiments, to facilitate such coupling, the first superconducting layer 104 may be deposited on the upper surface of the substrate 102. For example, the first superconducting layer 104 may be deposited on the upper surface of the substrate 102 by employing techniques including, but not limited to, physical vapor deposition (PVD), sputtering, evaporation, or another technique for depositing the first superconducting layer 104 on the substrate 102, as shown in FIG. 1(A). In some embodiments, the first superconducting layer 104 may be deposited on the substrate 102 (e.g., by PVD, sputtering, evaporation, etc.) such that the first superconducting layer 104 may have a thickness (e.g., height) in the range of, for example, 50 nanometers (nm) to 500 nm.

[0037] In some embodiments, the first superconducting layer 104 may comprise a superconducting interconnect component. For example, the first superconducting layer 104 may comprise a superconducting interconnect component that may couple (e.g., electrically, operatively, etc.) the substrate 102 to the second superconducting layer 106.

[0038] According to various embodiments, the second superconducting layer 106 can include a superconducting material. For example, the second superconducting layer 106 can include titanium nitride (TiN), niobium nitride (NbN), titanium niobium nitride (TiNbN), a silicide, or another superconducting material, or a combination thereof.

[0039] In some embodiments, the second superconducting layer 106 may be coupled to the first superconducting layer 104. For example, the second superconducting layer 106 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to the top surface of the first superconducting layer 104. In some embodiments, to facilitate such coupling, the second superconducting layer 106 may be deposited on the top surface of the first superconducting layer 104 without breaking vacuum, thereby preventing oxidation of the first superconducting layer 104. For example, the second superconducting layer 106 may be deposited on the top surface of the first superconducting layer 104 by employing techniques including, but not limited to, PVD, sputtering, evaporation, or another technique for depositing the second superconducting layer 106 on the first superconducting layer 104, or a combination thereof, as shown in FIG. 1(A). In some embodiments, the second superconducting layer 106 can be deposited (e.g., by PVD, sputtering, evaporation, etc.) over the first superconducting layer 104 such that the second superconducting layer 106 can have a thickness (e.g., height) in the range of, for example, 1 nm to 100 nm.

[0040] In some embodiments, the second superconducting layer 106 can comprise a superconducting interconnect component. For example, the second superconducting layer 106 can comprise a superconducting interconnect component that can couple (e.g., electrically, operatively, etc.) the first superconducting layer 104 to the third superconducting layer 108. In another example, the second superconducting layer 106 can comprise a superconducting interconnect component that can couple (e.g., electrically, operatively, etc.) the first superconducting layer 104 to the solder bumps 122 (e.g., as described below with reference to FIGS. 2(A)-(D)).

[0041] In some embodiments, the second superconducting layer 106 can comprise a wire bonding layer. For example, the second superconducting layer 106 can comprise a wire bonding layer that can couple (e.g., electrically, operatively, etc.) the first superconducting layer 104 to the third superconducting layer 108. In another example, the second superconducting layer 106 can comprise a wire bonding layer that can couple (e.g., electrically, operatively, etc.) the first superconducting layer 104 to a solder bump 122 (e.g., as described below with reference to FIGS. 2(A)-(D)).

[0042] In some embodiments, the second superconducting layer 106 can include an oxidation barrier layer. For example, the second superconducting layer 106 can include an oxidation barrier layer that can prevent oxidation of the first superconducting layer 104.

[0043] According to various embodiments, the third superconducting layer 108 may include a superconducting material, including, but not limited to, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), or another superconducting material, or a combination thereof.

[0044] In some embodiments, the third superconducting layer 108 may be coupled to the second superconducting layer 106. For example, the third superconducting layer 108 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to a top surface of the second superconducting layer 106. In some embodiments, to facilitate such coupling, the third superconducting layer 108 may be deposited on a top surface of the second superconducting layer 106. For example, the third superconducting layer 108 may be deposited on a top surface of the second superconducting layer 106 by employing techniques including, but not limited to, PVD, sputtering, evaporation, or another technique for depositing the third superconducting layer 108 on the second superconducting layer 106, or a combination thereof, as shown in FIG. 1(A). In some embodiments, the third superconducting layer 108 can be deposited (e.g., by PVD, sputtering, evaporation, etc.) on the second superconducting layer 106 such that the third superconducting layer 108 can have a thickness (e.g., height) in the range of, for example, 5 nm to 500 nm.

[0045] In some embodiments, the third superconducting layer 108 can comprise a superconducting interconnect component. For example, the third superconducting layer 108 can comprise a superconducting interconnect component that can couple (e.g., electrically, operatively, etc.) the second superconducting layer 106 to the solder diffusion layer 110 and / or the solder bumps 122, as described below with reference to Figures 1(C) and 1(D). In some embodiments, the third superconducting layer 108 can comprise an adhesion layer. For example, the third superconducting layer 108 can comprise an adhesion layer that can provide improved adhesion between the second superconducting layer 106 and the solder diffusion layer 110.

[0046] According to various embodiments, the solder diffusion layer 110 can include a material capable of reacting with a solder to form an intermetallic compound layer, where the solder diffusion layer 110 can be partially (but not completely) consumed by the reaction with the solder. For example, the solder diffusion layer 110 can include, but is not limited to, platinum (Pt), palladium (Pd), nickel (Ni), copper (Cu), indium (In), tin (Sn), or another metal capable of reacting with a solder (e.g., a solder bump 122, as described below with reference to FIG. 1C) to form an intermetallic compound layer (e.g., an intermetallic compound layer 120, as described below with reference to FIG. 1C)) but not completely consumed after the reaction with the solder (e.g., a portion of the solder diffusion layer 110 is still shown in FIG. 1C after the formation of the intermetallic compound layer 120).

[0047] In some embodiments, the solder diffusion layer 110 may be coupled to the third superconducting layer 108. For example, the solder diffusion layer 110 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to the top surface of the third superconducting layer 108. In some embodiments, to facilitate such coupling, the solder diffusion layer 110 may be deposited on the top surface of the third superconducting layer 108. For example, the solder diffusion layer 110 may be deposited on the top surface of the third superconducting layer 108 by employing techniques including, but not limited to, PVD, sputtering, evaporation, or another technique for depositing the solder diffusion layer 110 on the third superconducting layer 108, as shown in FIG. 1(A). In some embodiments, the solder diffusion layer 110 may be deposited on the third superconducting layer 108 (e.g., by PVD, sputtering, evaporation, etc.) such that the solder diffusion layer 110 may have a thickness (e.g., height) in the range of, for example, 5 nm to 1000 nm.

[0048] In some embodiments, the solder diffusion layer 110 can comprise an oxidation barrier layer. For example, the solder diffusion layer 110 can comprise an oxidation barrier layer that can prevent oxidation of the third superconducting layer 108. In some embodiments, the solder diffusion layer 110 can comprise a solder wetting layer that can react with a solder to form an intermetallic compound layer. For example, the solder diffusion layer 110 can comprise a solder wetting layer that can react with a solder (e.g., a solder bump 122 as described below with reference to FIG. 1(C)) to form an intermetallic compound layer (e.g., an intermetallic compound layer 120 as described below with reference to FIG. 1(C)).

[0049] According to several embodiments, the solder wetting layer 112 can include a solder wetting material that can react with and become incorporated into the molten solder. In some embodiments, the solder wetting layer 112 should not be oxidized before contacting the solder. For example, the solder wetting layer 112 can include gold (Au) and / or another solder wetting material that can react with and become incorporated into the molten solder (e.g., solder bump 122, as described below with reference to FIG. 1(C)) and enable the formation of an intermetallic compound layer between the solder bump 122 and the solder diffusion layer 110 (e.g., the solder wetting layer 112 of FIG. 1(B) is not shown in FIG. 1(C)). In some embodiments, the solder wetting layer 112 may be coupled to the solder spread layer 110. For example, the solder wetting layer 112 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to the top surface of the solder spread layer 110. In some embodiments, to facilitate such coupling, the solder wetting layer 112 may be deposited on the top surface of the solder spread layer 110. For example, the solder wetting layer 112 may be deposited on the top surface of the solder spread layer 110 by employing techniques including, but not limited to, PVD, sputtering, evaporation, or another technique for depositing the solder wetting layer 112 on the solder spread layer 110, as shown in FIG. 1(A). In some embodiments, the solder wetting layer 112 may be deposited on the solder spread layer 110 (e.g., by PVD, sputtering, evaporation, etc.) such that the solder wetting layer 112 may have a thickness (e.g., height) in the range of, for example, 5 nm to 1000 nm.

[0050] In some embodiments, the solder wetting layer 112 may comprise an oxidation barrier layer. For example, the solder wetting layer 112 may comprise an oxidation barrier layer that can prevent oxidation of the solder diffusion layer 110.

[0051] 1(B) illustrates a side cross-sectional view of an exemplary, non-limiting device 100B facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein are omitted for brevity. According to some embodiments, device 100B can include one or more channels 114, photoresist layers 116, openings 118, and / or under-bump metallization components 124A.

[0052] According to several embodiments, a channel 114 may be formed through the solder wetting layer 112 and the solder spreading layer 110 of device 100A to form device 100B. For example, the channel 114 may be formed through the solder wetting layer 112 and the solder spreading layer 110 such that the top surface of the third superconducting layer 108 is exposed (e.g., as shown in the embodiment illustrated in FIG. 1(B)). In some embodiments, the channel 114 may be formed through the solder wetting layer 112 and the solder spreading layer 110 by employing one or more photoresist, photomasking, patterning, and / or etching techniques on device 100A. For example, the channels 114 may be formed through the solder wetting layer 112 and the solder diffusion layer 110 by applying a photomask and / or photoresist to the top surface of the solder wetting layer 112 such that the desired geometric pattern of the channels 114 (e.g., the two-dimensional (2D) shape of the channels 114) is superimposed on the top surface of the solder wetting layer 112, and then etching (e.g., by RIE, dry etching, wet etching, etc.) the desired geometric pattern of the channels 114 through the solder wetting layer 112 and the solder diffusion layer 110 so that the top surface of the third superconducting layer 108 is exposed (e.g., as shown in the embodiment illustrated in FIG. 1(B)).

[0053] In some embodiments, the channel 114 can have a variety of shapes. For example, the shape of the channel 114 can be defined in a 2D plane extending along the X- and Z-axes of FIGS. 1A-1D, which 2D plane can be observed in a top view of the device 100B (e.g., as presented in the example embodiment shown in FIGS. 3A-3D). In some embodiments, the channel 114 can be etched through the solder wetting layer 112 and the solder spreading layer 110 in this manner to form shapes including, but not limited to, a ring, a square, a rectangle, a circle, a hexagon, an octagon, a diamond, or another shape defined in such a 2D plane extending along the X- and Z-axes of FIGS. 1A-1D, or a combination thereof.

[0054] According to various embodiments, the photoresist layer 116 can include various types of photoresist materials, including, but not limited to, dry film photoresist, liquid photoresist, or another type of photoresist, or a combination thereof.

[0055] In some embodiments, the photoresist layer 116 may be applied to the substrate 102 such that the photoresist layer 116 can form a wall structure surrounding (e.g., enclosing, containing, etc.) the various material layers deposited on the substrate 102 (e.g., the first superconducting layer 104, the second superconducting layer 106, the third superconducting layer 108, the solder diffusion layer 110, and / or the solder wetting layer 112). In some embodiments, the photoresist layer 116 may be applied to the substrate 102 such that the photoresist layer 116 can form a wall structure surrounding the various material layers deposited on the substrate 102 and the opening 118 (e.g., as shown in the embodiment illustrated in FIG. 1(B)). In some embodiments, the photoresist layer 116 may be applied to the substrate 102 such that the photoresist layer 116 can have a thickness (e.g., height) in the range of, for example, 10 μm to 200 μm.

[0056] According to various embodiments, the under bump metallization component 124A can comprise one or more material layers of the device 100B. For example, the under bump metallization component 124A can comprise the third superconducting layer 108, the solder diffusion layer 110, or the solder wetting layer 112, or a combination thereof.

[0057] 1(C) illustrates a side cross-sectional view of an exemplary, non-limiting device 100C facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for brevity. According to some embodiments, device 100C can include one or more intermetallic compound layers 120, solder bumps 122, or under-bump metallization components 124B, or combinations thereof.

[0058] According to several embodiments, molten solder, such as injection molded solder (IMS), can be injected onto device 100B and into channel 114 to form device 100C. For example, the IMS can be injected onto device 100B and into channel 114 by employing a fill head device (not shown in FIGS. 1A-1D) that can inject such IMS into opening 118 of device 100B to fill the volume enclosed by photoresist layer 116 (e.g., as shown in the embodiment illustrated in FIGS. 1B and 1C). In some embodiments, the IMS can include various types of solder materials. For example, the IMS can include solder materials including, but not limited to, indium (In), bismuth (Bi), tin (Sn), lead-tin (PbSn), indium-bismuth-tin alloy (InBiSn), indium-tin alloy (InSn), or another material, or a combination thereof. In some embodiments, the IMS may include a cryogenically compatible solder.

[0059] In some embodiments, injection of molten solder (e.g., IMS) onto device 100B and into channel 114 (e.g., as described above) can facilitate the formation of intermetallic layer 120. For example, solder wetting layer 112 and solder diffusion layer 110 can react with the IMS to facilitate the formation of intermetallic layer 120. For example, solder wetting layer 112 can include gold (Au) that can diffuse into the IMS, and solder diffusion layer 110 can include platinum (Pt), palladium (Pd), nickel (Ni), or another material that can react with, for example, indium (In) of the IMS to facilitate the formation of intermetallic layer 120, or a combination thereof.

[0060] In some embodiments, the molten solder (e.g., IMS), which may be injected onto device 100B and into channel 114 (e.g., as described above), can completely consume solder wetting layer 112, thereby facilitating the formation of intermetallic compound layer 120. For example, all of the material (e.g., Au) of solder wetting layer 112 can diffuse into the IMS, facilitating the formation of intermetallic compound layer 120. In some embodiments, the molten solder (e.g., IMS), which may be injected onto device 100B and into channel 114 (e.g., as described above), can partially consume solder diffusion layer 110, thereby further facilitating the formation of intermetallic compound layer 120. For example, a portion of the material (e.g., Pt, Pd, Ni, etc.) of solder diffusion layer 110 can react with the IMS (e.g., indium (In) in the IMS), facilitating the formation of intermetallic compound layer 120. In some embodiments, therefore, based on injection of an IMS onto device 100B and into channel 114 (e.g., as described above), intermetallic layer 120 may include materials such as, for example, an IMS, solder diffusion layer 110, solder wetting layer 112, or solder bump 122 that may be formed from an IMS (e.g., as described below), or a combination thereof.

[0061] In some embodiments, injection of molten solder (e.g., IMS) onto device 100B and into channel 114 (e.g., as described above) can facilitate the formation of solder bump 122. For example, IMS injected onto device 100B and into channel 114 can solidify as shown in FIG. 1(C), thereby facilitating the formation of solder bump 122 due to the surface tension of the IMS.

[0062] In some embodiments, injection of molten solder (e.g., IMS) onto device 100B and into channel 114 (e.g., as described above) can facilitate the formation of under bump metallization component 124B. For example, IMS injected onto device 100B and into channel 114 can facilitate the formation of intermetallic compound layer 120 (e.g., as described above). In this example, based on such formation of intermetallic compound layer 120, formation of under bump metallization component 124B can be completed, as under bump metallization component 124B can comprise third superconducting layer 108, solder diffusion layer 110, or intermetallic compound layer 120, or a combination thereof.

[0063] In some embodiments, the under-bump metallization component 124B can include a hybrid under-bump metallization component, which can include a mechanical interconnection component (e.g., a solder diffusion layer 110, a solder wetting layer 112, or an intermetallic compound layer 120, as described below) and a hermetically sealed superconducting interconnection component (e.g., by sealing the third superconducting layer 108 with a solder bump 122, as described below).

[0064] In some embodiments, the intermetallic compound layer 120 can constitute a mechanical interconnection component that can mechanically couple the solder bump 122 to one or more components of the device 100C. For example, the intermetallic compound layer 120 can mechanically couple the solder bump 122 to the third superconducting layer 108, the solder diffusion layer 110, the solder wetting layer 112, or the under-bump metallization component 124B, or a combination thereof. It should be understood that such a mechanical coupling can facilitate improved mechanical integrity of the device 100C (or device 100D, or both), which may be an advantage of the present disclosure over the prior art. It should also be understood that such a mechanical coupling can facilitate improved strength of the mechanical connection of the solder bump 122 to the under-bump metallization component 124B, thereby facilitating improved electrical coupling of such components (e.g., improved consistency of the electrical connection), which may be an advantage of the present disclosure over the prior art.

[0065] In some embodiments, the under-bump metallization component 124B can comprise a sealed superconducting interconnect component. For example, upon injection of an IMS onto the device 100B and into the channel 114 (e.g., as described above), the IMS filling the channel 114 can seal the top surface of the third superconducting layer 108, which can thereby constitute a sealed superconducting interconnect component (e.g., sealed by the solder bump 122). It should be understood that such sealing can prevent oxide formation (e.g., oxidation) between the third superconducting layer 108 and the solder bump 122, thereby facilitating improved electrical coupling of such a component, which can be an advantage of the present disclosure over the prior art.

[0066] 1(D) illustrates a side cross-sectional view of an exemplary, non-limiting device 100D facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0067] According to various embodiments, device 100D can include device 100C without photoresist layer 116. For example, upon solidification of the IMS to facilitate the formation of intermetallic layer 120 (e.g., as described above), solder bump 122, and / or under-bump metallization component 124B, photoresist layer 116 can be stripped from device 100C (e.g., by RIE, dry etching, wet etching, etc.) to form device 100D.

[0068] 2(A)-(D) illustrate an exemplary, non-limiting, multi-step fabrication sequence that may be performed to fabricate one or more embodiments of the present disclosure described herein and / or illustrated in the figures. For example, in accordance with one or more embodiments described herein, the non-limiting multi-step fabrication sequence illustrated in FIGS. 2(A)-(D) may be performed to fabricate device 200D (shown in FIG. 2(D)), which may include under-bump metallization component 204B.

[0069] According to various embodiments, the exemplary, non-limiting, multi-step fabrication sequence illustrated in Figures 2(A)-(D) may include alternative exemplary fabrication sequences to those described above with reference to Figures 1(A)-(D). For example, the fabrication sequence illustrated in Figures 2(A)-(D) may be implemented to fabricate alternative exemplary embodiments of devices 100A, 100B, 100C, or 100D, or combinations thereof (e.g., as described below).

[0070] 2A illustrates a side cross-sectional view of an exemplary, non-limiting device 200A that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0071] According to some embodiments, device 200A may comprise an alternative example embodiment of device 100A, where device 200A does not include solder wetting layer 112. Additionally or alternatively, in some embodiments, the manufacturing sequence described above with reference to FIG. 1(A) that may be performed to manufacture device 100A may also be performed to manufacture device 200A, where deposition of solder wetting layer 112 may be omitted from such manufacturing sequence to form device 200A.

[0072] 2(B) illustrates a side cross-sectional view of an exemplary, non-limiting device 200B facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0073] According to some embodiments, device 200B may include an alternative example embodiment of device 100B described above with reference to FIG. 1(B). In some embodiments, device 200B may include one or more channels 202. In some embodiments, device 200B may include a solder wetting layer 112 deposited on solder spreading layer 110 and second superconducting layer 106 (e.g., as shown in the embodiment depicted in FIG. 2(B)). In some embodiments, device 200B may include an under bump metallization component 204A, which may include an alternative example embodiment of under bump metallization component 124A of FIG. 1(B).

[0074] According to various embodiments, the channel 202 may include an alternative example embodiment of the channel 114 described above with reference to device 100B and FIG. 1(B), where the channel 202 may be formed through the solder spread layer 110 and the third superconducting layer 108 of device 200A to expose a top surface of the second superconducting layer 106. For example, the channel 202 may be formed through the solder spread layer 110 and the third superconducting layer 108 by applying a photomask and / or photoresist to the top surface of the solder spread layer 110 such that the desired geometric pattern of the channel 202 (e.g., a two-dimensional (2D) shape of the channel 202) is superimposed on the top surface of the solder spread layer 110, and etching (e.g., by RIE, dry etching, wet etching, etc.) the desired geometric pattern of the channel 202 through the solder spread layer 110 and the third superconducting layer 108 to expose the top surface of the second superconducting layer 106. In some embodiments, based on the formation of the channel 202, a solder wetting layer 112 may be deposited on the upper surface of the solder diffusion layer 110 and the upper surface of the second superconducting layer 106. For example, based on the formation of the channel 202, the solder wetting layer 112 may be deposited on the upper surface of the solder diffusion layer 110 and the upper surface of the second superconducting layer 106 by employing techniques including, but not limited to, PVD, sputtering, evaporation, or another technique for depositing the solder wetting layer 112 on the solder diffusion layer 110 and the second superconducting layer 106, or a combination thereof, as shown in FIG. 2(B). In some embodiments, the solder wetting layer 112 may be deposited on the solder diffusion layer 110 and the second superconducting layer 106 (e.g., by PVD, sputtering, evaporation, etc.) such that the solder wetting layer 112 can have a thickness (e.g., height) in the range of, for example, 5 nm to 1000 nm.

[0075] In some embodiments, the solder wetting layer 112 can comprise an oxidation barrier layer. For example, the solder wetting layer 112 can comprise an oxidation barrier layer that can prevent oxidation of the solder diffusion layer 110 and / or the second superconducting layer 106.

[0076] 2(C) illustrates a side cross-sectional view of an exemplary, non-limiting device 200C facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0077] According to some embodiments, device 200C may include an alternative embodiment of device 100C, where device 200C includes under bump metallization component 204B, which may include an alternative embodiment of under bump metallization component 124B of FIG. 1(C). Additionally or alternatively, in some embodiments, the fabrication sequence described above with reference to FIG. 1(C) that may be performed to fabricate device 100C may also be performed to fabricate device 200C. For example, molten solder (e.g., IMS) may be injected onto device 200B and into channel 202 to facilitate the formation of intermetallic compound layer 120, solder bump 122, and / or under bump metallization component 204B of device 200C.

[0078] In some embodiments, the intermetallic compound layer 120 of the under bump metallization component 204B can constitute a mechanical interconnect component that can mechanically couple the solder bump 122 to, for example, the second superconducting layer 106, the third superconducting layer 108, the solder spreading layer 110, the solder wetting layer 112, or the under bump metallization component 204B, or a combination thereof. In some embodiments, upon injection of an IMS onto the device 200B and into the channel 202 (e.g., as described above), the IMS filling the channel 202 can seal one or more sides of the third superconducting layer 108 and the top surface of the second superconducting layer 106, which can thereby constitute a hermetically sealed superconducting interconnect component (e.g., sealed by the solder bump 122).

[0079] 2(D) illustrates a side cross-sectional view of an exemplary, non-limiting device 200D facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0080] According to various embodiments, device 200D can include device 200C without photoresist layer 116. For example, upon solidification of the IMS to facilitate the formation of intermetallic layer 120 (e.g., as described above), solder bump 122, and / or under-bump metallization component 204B, photoresist layer 116 can be stripped from device 200C (e.g., by RIE, dry etching, wet etching, etc.) to form device 200D.

[0081] FIG. 3A illustrates a top view of an exemplary, non-limiting device 300A facilitating a hybrid under-bump metallization component according to one or more embodiments described herein. According to various embodiments, device 300A can include device 100B of FIG. 1B and device 200B of FIG. 2B, respectively, where, for clarity, photoresist layer 116 is not shown in FIG. 3A. In FIG. 3A, dashed line 304 indicates where cross-sectional side views of device 100A and device 100B would appear relative to device 300A.

[0082] Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0083] According to various embodiments, device 300A can include layer 302, which can include third superconducting layer 108 or solder wetting layer 112. For example, device 300A can include device 100B of FIG. 1(B), and in such an embodiment, layer 302 can include third superconducting layer 108. In another example, device 300A can include device 200B of FIG. 2(B), and in such an embodiment, layer 302 can include solder wetting layer 112.

[0084] 3(B) illustrates a top view of an exemplary, non-limiting device 300B facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. According to various embodiments, device 300B may include alternative embodiments of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or combinations thereof. Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0085] 3(C) illustrates a top view of an exemplary, non-limiting device 300C facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. According to various embodiments, device 300C may include an alternative embodiment of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or a combination thereof. Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0086] 3(D) illustrates a top view of an exemplary, non-limiting device 300D facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. According to various embodiments, device 300D may include alternative embodiments of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or combinations thereof. Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0087] In some embodiments, under bump metallization component 124B and / or under bump metallization component 204B may include hybrid under bump metallization components, devices, systems, and / or processes related to various technologies, such as quantum bit (qubit) technology, quantum circuit technology, superconducting circuit technology, circuit quantum electrodynamics (cQED) technology, quantum computing technology, quantum processor technology, superconductor device fabrication technology, semiconductor device fabrication technology, flip chip device technology, semiconductor device packaging technology, superconductor device packaging technology, quantum hardware technology, and / or other technologies.

[0088] In some embodiments, the under bump metallization component 124B and / or the under bump metallization component 204B may provide technical improvements to systems, devices, components, operable steps, or process steps, or combinations thereof, associated with the various technologies previously listed. For example, the under bump metallization component 124B and / or the under bump metallization component 204B may provide a hermetic superconducting interconnect (e.g., the second superconducting layer 106 and / or the third superconducting layer 108 hermetically sealed by the solder bump 122) that may prevent oxide formation (e.g., oxidation) between components coupled to such hermetically sealed superconducting interconnect (e.g., between the second superconducting layer 106 and / or the third superconducting layer 108 and the solder bump 122), thereby facilitating improved electrical coupling of such components. In another example, under-bump metallization component 124B and / or under-bump metallization component 204B may provide improved mechanical bonding of under-bump metallization component 124B and / or under-bump metallization component 204B with solder bump 122 (e.g., via solder spreading layer 110, solder wetting layer 112, and / or intermetallic compound layer 120). In this example, such improved mechanical bonding may facilitate improved mechanical integrity of a flip-chip device (e.g., a quantum bit (qubit) chip, quantum hardware, superconducting quantum processor, quantum computing device, etc.) including under-bump metallization component 124B and / or under-bump metallization component 204B.

[0089] In some embodiments, under-bump metallization component 124B and / or under-bump metallization component 204B may provide technical improvements to a processing unit associated with under-bump metallization component 124B and / or under-bump metallization component 204B. For example, improved electrical and mechanical coupling provided by under-bump metallization component 124B and / or under-bump metallization component 204B (e.g., as described above) may facilitate improved electrical connectivity required to execute the processing workload of a processing unit (e.g., a quantum processor) associated with under-bump metallization component 124B and / or under-bump metallization component 204B. In this example, such improved electrical connectivity may facilitate requiring fewer processing cycles to complete a given processing workload, thereby facilitating improved processing efficiency and / or performance of a processing unit (e.g., a superconducting quantum processor) including under-bump metallization component 124B and / or under-bump metallization component 204B, thereby reducing power consumption by such processing unit.

[0090] In some embodiments, underbump metallization component 124B and / or underbump metallization component 204B may employ hardware and / or software to solve problems that are not abstract and are highly technical in nature and cannot be performed as a series of mental activities by a human being. For example, underbump metallization component 124B and / or underbump metallization component 204B may facilitate sealing of superconducting interconnects that may be employed in flip-chip devices used to implement quantum computing devices that can process information and / or perform calculations based on quantum mechanical phenomena.

[0091] It should be understood that underbump metallization component 124B and / or underbump metallization component 204B may facilitate superconducting interconnect processes utilizing various combinations of electrical components, mechanical components, and circuitry (e.g., superconducting quantum circuits) that cannot be replicated or performed by the human intellect. For example, facilitating superconducting interconnections that can enable the operation of quantum computing devices (e.g., quantum processors, quantum computers, etc.) is an operation beyond the capabilities of the human intellect. For example, the amount of data processed by underbump metallization component 124B and / or underbump metallization component 204B over a particular period of time, the speed at which such data is processed, or the type of data processed, or a combination thereof, may be greater in amount, faster in speed, or different in data type than can be processed by the human intellect over the same period of time, or a combination thereof.

[0092] According to some embodiments, the under bump metallization component 124B and / or the under bump metallization component 204B may be fully operable (e.g., fully powered, fully running, etc.) to perform one or more other functions while also performing the above-referenced superconducting interconnect process. It should also be understood that performing such simultaneous multiple operations is beyond the capabilities of the human mind. It should also be understood that the under bump metallization component 124B and / or the under bump metallization component 204B may include information that is not manually obtainable by an entity such as a human user. For example, the type, amount, or variety, or combination thereof, of information included in the under bump metallization component 124B and / or the under bump metallization component 204B may be more complex than information manually obtainable by a human user.

[0093] 4A illustrates a side cross-sectional view of an exemplary, non-limiting device 400A that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0094] According to various embodiments, device 400A may include device 406 and device 200D of FIG. 2(D). In some embodiments, device 406 may include alternative example embodiments of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or combinations thereof. In some embodiments, device 406 may include a substrate 402, which may include substrate 102. In some embodiments, substrate 402 may include a quantum bit (qubit) chip.

[0095] In some embodiments, device 406 can include an under bump metallization component 404A, which can include an alternative example embodiment of under bump metallization component 204A of device 200B described above with reference to FIG. 2(B). In some embodiments, under bump metallization component 404A can be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to under bump metallization component 204B. For example, to facilitate such coupling of under bump metallization component 404A to under bump metallization component 204B, device 406 can be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D to form device 400B (e.g., as described below with reference to FIG. 4(B)).

[0096] FIG. 4(B) illustrates a side cross-sectional view of an exemplary, non-limiting device 400B that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein.

[0097] A repeated description of similar elements employed in other embodiments described herein has been omitted for the sake of brevity. According to various embodiments, device 400B can include an under bump metallization component 404B, which can include an alternative embodiment of under bump metallization component 204B.

[0098] According to various embodiments, device 400B may be formed by coupling (e.g., electrically, mechanically, operatively, chemically, etc.) device 406 to device 200D. For example, device 406 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D by employing a reflow soldering technique. For example, heat may be applied to solder bumps 122 of device 200D by a heat source (not shown in FIGS. 4A and 4B ) such that solder bumps 122 change from a solid state to a liquid state and / or semi-liquid state (e.g., a solder reflow state). In this example, based on performing such a reflow soldering technique, under-bump metallization components 404A of device 406 may be inserted into solder bumps 122, thereby facilitating the formation of under-bump metallization components 404B and device 400B. In this example, performing a reflow soldering technique and inserting the under-bump metallization component 404A into the solder bump 122 can facilitate the formation of the intermetallic layer 120 of the under-bump metallization component 404B as shown in the embodiment shown in FIG. 4(B).

[0099] In some embodiments, device 400B may include a flip-chip device, such as a flip-chip device including one or more hermetically sealed superconducting interconnect components (e.g., second superconducting layer 106, third superconducting layer 108, solder bumps 122, etc.) and / or one or more mechanical interconnect components (e.g., solder diffusion layer 110, solder wetting layer 112, intermetallic compound layer 120, solder bumps 122, etc.).

[0100] 5A illustrates a side cross-sectional view of an exemplary, non-limiting device 500A that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0101] According to various embodiments, device 500A may include device 502 and device 200D of FIG. 2(D). In some embodiments, device 502 may include an alternative embodiment of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or a combination thereof. In some embodiments, device 502 may include an under bump metallization component 504, which may include an alternative embodiment of under bump metallization component 204A of device 200B described above with reference to FIG. 2(B). In some embodiments, under bump metallization component 504 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to under bump metallization component 204B. For example, to facilitate such bonding of under bump metallization component 504 to under bump metallization component 204B, device 502 can be bonded (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D to form device 500B (e.g., as described below with reference to FIG. 5(B)).

[0102] 5(B) illustrates a side cross-sectional view of an exemplary, non-limiting device 500B facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0103] According to various embodiments, device 500B may be formed by coupling (e.g., electrically, mechanically, operatively, chemically, etc.) device 502 to device 200D. For example, device 502 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D by employing a cold welding technique (also referred to as contact welding). In this example, based on the implementation of such a cold welding technique, under-bump metallization component 504 of device 502 may be inserted and coupled to solder bumps 122, thereby facilitating the formation of device 500B and coupling (e.g., electrically, mechanically, operatively, chemically, etc.) of under-bump metallization component 504 to under-bump metallization component 204A.

[0104] In some embodiments, device 500B may include a flip-chip device, such as a flip-chip device including one or more hermetically sealed superconducting interconnect components (e.g., second superconducting layer 106, third superconducting layer 108, solder bumps 122, etc.) and / or one or more mechanical interconnect components (e.g., solder diffusion layer 110, solder wetting layer 112, intermetallic compound layer 120, solder bumps 122, etc.).

[0105] 5(C) illustrates a side cross-sectional view of an exemplary, non-limiting device 500C facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0106] According to various embodiments, device 500C may include device 506 and device 200D of FIG. 2(D). In some embodiments, device 506 may include an alternative embodiment of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or a combination thereof. In some embodiments, device 506 may include an under bump metallization component 508, which may include an alternative embodiment of under bump metallization component 204A of device 200B described above with reference to FIG. 2(B). In some embodiments, under bump metallization component 508 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to under bump metallization component 204B. For example, to facilitate such bonding of under bump metallization component 508 to under bump metallization component 204B, device 506 may be bonded (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D to form device 500D (e.g., as described below with reference to FIG. 5(D)).

[0107] FIG. 5(D) illustrates a side cross-sectional view of an exemplary, non-limiting device 500D that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein.

[0108] Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0109] According to various embodiments, device 500D may be formed by coupling (e.g., electrically, mechanically, operatively, chemically, etc.) device 506 to device 200D. For example, device 506 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D by employing a cold welding technique (also referred to as contact welding). In this example, based on the implementation of such a cold welding technique, under-bump metallization component 508 of device 506 is inserted and coupled to solder bumps 122, thereby facilitating the formation of device 500D and coupling (e.g., electrically, mechanically, operatively, chemically, etc.) of under-bump metallization component 508 to under-bump metallization component 204A.

[0110] In some embodiments, device 500D may include a flip-chip device, for example, device 500D may include one or more hermetically sealed superconducting interconnect components (e.g., second superconducting layer 106, third superconducting layer 108, solder bumps 122, etc.) and / or one or more mechanical interconnect components (e.g., solder diffusion layer 110, solder wetting layer 112, intermetallic compound layer 120, solder bumps 122, etc.).

[0111] FIG. 6(A) illustrates a side cross-sectional view of an exemplary, non-limiting device 600A that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein.

[0112] Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0113] According to various embodiments, device 600A can include device 602 and device 200D of FIG. 2(D). In some embodiments, device 602 can include an alternative embodiment of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or a combination thereof. In some embodiments, device 602 can include an underbump metallization component 604, which can include an alternative embodiment of underbump metallization component 204A of device 200B described above with reference to FIG. 2(B). In some embodiments, device 602, underbump metallization component 604, or both, can include stud bumps 606.

[0114] According to various embodiments, the stud bumps 606 may include a conductive material. For example, the stud bumps 606 may include gold (Au) and / or another conductive material. In some embodiments, the stud bumps 606 may be formed on the solder wetting layer 112 by employing, for example, a modified wire bonding process using a wire bonder or a stud bumping process (also referred to as stud bump bonding).

[0115] In some embodiments, under bump metallization component 604 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to under bump metallization component 204B. For example, to facilitate such coupling of under bump metallization component 604 to under bump metallization component 204B, device 602 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D to form device 600B (e.g., as described below with reference to FIG. 6(B)).

[0116] FIG. 6(B) illustrates a side cross-sectional view of an exemplary, non-limiting device 600B that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein.

[0117] Repeated descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0118] According to various embodiments, device 600B may be formed by coupling (e.g., electrically, mechanically, operatively, chemically, etc.) device 602 to device 200D. For example, device 602 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D by employing a cold welding technique (also referred to as contact welding). In this example, based on the implementation of such a cold welding technique, underbump metallization component 604 of device 602 is inserted and coupled to solder bump 122, thereby facilitating the formation of device 600B and coupling (e.g., electrically, mechanically, operatively, chemically, etc.) of underbump metallization component 604 to underbump metallization component 204A. It should be appreciated that stud bump 606 may act as an insulator during cold welding of device 602 to device 200D, further facilitating improved mechanical coupling of device 602 to device 200D.

[0119] In some embodiments, device 600B may include a flip-chip device, such as a flip-chip device including one or more hermetically sealed superconducting interconnect components (e.g., second superconducting layer 106, third superconducting layer 108, solder bumps 122, etc.) and / or one or more mechanical interconnect components (e.g., solder diffusion layer 110, solder wetting layer 112, intermetallic compound layer 120, solder bumps 122, stud bumps 606, etc.).

[0120] 7A illustrates a side cross-sectional view of an exemplary, non-limiting device 700A that facilitates a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0121] According to various embodiments, device 700A may include device 702 and device 200D of FIG. 2(D). In some embodiments, device 702 may include an alternative embodiment of device 100B of FIG. 1(B), device 200B of FIG. 2(B), or device 300A of FIG. 3(A), or a combination thereof. In some embodiments, device 702 may include an under bump metallization component 704, which may include an alternative embodiment of under bump metallization component 204A of device 200B described above with reference to FIG. 2(B). In some embodiments, device 702, under bump metallization component 704, or both, may include plated pedestals or posts 706.

[0122] According to various embodiments, the plated pedestals or pillars 706 may include a conductive material. For example, the plated pedestals or pillars 706 may include copper (Cu) and / or another conductive material. In some embodiments, the plated pedestals or pillars 706 may be formed on the solder wetting layer 112, for example, by employing an electroplating process.

[0123] In some embodiments, the under bump metallization component 704 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to the under bump metallization component 204B. For example, to facilitate such coupling of the under bump metallization component 704 to the under bump metallization component 204B, the device 702 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to the device 200D to form the device 700B (e.g., as described below with reference to FIG. 7(B)).

[0124] 7(B) illustrates a side cross-sectional view of an exemplary, non-limiting device 700B facilitating a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0125] According to various embodiments, device 700B may be formed by coupling (e.g., electrically, mechanically, operatively, chemically, etc.) device 702 to device 200D. For example, device 702 may be coupled (e.g., electrically, mechanically, operatively, chemically, etc.) to device 200D by employing a cold welding technique (also referred to as contact welding). In this example, based on the implementation of such a cold welding technique, under-bump metallization component 704 of device 702 is inserted and coupled to solder bumps 122, thereby facilitating the formation of device 700B and coupling (e.g., electrically, mechanically, operatively, chemically, etc.) of under-bump metallization component 704 to under-bump metallization component 204A. It should be appreciated that plated pedestals or posts 706 may act as insulators during cold welding of device 702 to device 200D, further facilitating improved mechanical coupling of device 702 to device 200D.

[0126] In some embodiments, device 700B may include a flip-chip device. For example, device 700B may include a flip-chip device including one or more hermetically sealed superconducting interconnect components (e.g., second superconducting layer 106, third superconducting layer 108, solder bumps 122, etc.) and / or one or more mechanical interconnect components (e.g., solder diffusion layer 110, solder wetting layer 112, intermetallic compound layer 120, solder bumps 122, plated pedestals or pillars 706, etc.). Figure 8 illustrates a flow diagram of an exemplary, non-limiting method 800 for facilitating the implementation of a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetition of descriptions of similar elements employed in other embodiments described herein has been omitted for brevity.

[0127] In some embodiments, method 800 may be performed by a computing system (e.g., operating environment 1000 shown in FIG. 10 and described below) and / or a computing device (e.g., computer 1012 shown in FIG. 10 and described below). In a non-limiting example embodiment, such a computing system (e.g., operating environment 1000) and / or such a computing device (e.g., computer 1012) may comprise one or more processors and one or more memory devices capable of storing executable instructions that, when executed by the one or more processors, can facilitate the performance of the operations described herein, including the non-limiting operations of method 800 shown in FIG. 8. As a non-limiting example, the one or more processors can facilitate the performance of the operations described herein (e.g., method 800) by managing or controlling one or more systems and / or equipment operable to perform semiconductor manufacturing.

[0128] At 802, solder (e.g., injection molten solder (IMS) and / or solder bumps 122) is deposited (e.g., by computer 1012) onto an under-bump metallization component (e.g., under-bump metallization component 124A, under-bump metallization component 124B, under-bump metallization component 204A, or under-bump metallization component 204B, or a combination thereof).

[0129] At 804, based on this deposition, a superconducting interconnect component (e.g., second superconducting layer 106, third superconducting layer 108, or solder bump 122, or a combination thereof) and an intermetallic layer (e.g., intermetallic layer 120) are formed (e.g., by computer 1012) on the under-bump metallization component.

[0130] In some embodiments, such depositing of operation 802 and forming of operation 804 may be performed (e.g., by computer 1012) by employing one or more integrated circuit fabrication techniques described above with reference to Figures 1(A)-(D) and / or 2(A)-(D). It should be appreciated that such depositing of operation 802 and forming of operation 804 may facilitate sealing of a superconducting interconnect component (e.g., by solder bumps 122) that may prevent oxide formation (e.g., oxidation) between a superconducting interconnect component (e.g., second superconducting layer 106, third superconducting layer 108, etc.) and another conductive component (e.g., solder bumps 122), thereby facilitating improved electrical coupling of such components. It should also be appreciated that such deposition of operation 802 and formation of operation 804 may facilitate improved mechanical integrity of the under-bump metallization component (e.g., under-bump metallization component 124A, under-bump metallization component 124B, under-bump metallization component 204A, or under-bump metallization component 204B, or a combination thereof) and improved strength of the mechanical connection of the under-bump metallization component to solder bump 122. It should further be appreciated that such sealing, improved electrical bonding, improved mechanical integrity, and improved mechanical interconnection as described above may be advantages of the present disclosure over the prior art.

[0131] 9 illustrates a flow diagram of an exemplary, non-limiting method 900 for facilitating the implementation of a hybrid under-bump metallization component in accordance with one or more embodiments described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0132] In some embodiments, method 900 may be performed by a computing system (e.g., operating environment 1000 shown in FIG. 10 and described below) and / or a computing device (e.g., computer 1012 shown in FIG. 10 and described below). In a non-limiting example embodiment, such a computing system (e.g., operating environment 1000) and / or such a computing device (e.g., computer 1012) may comprise one or more processors and one or more memory devices capable of storing executable instructions that, when executed by the one or more processors, can facilitate the performance of the operations described herein, including the non-limiting operations of method 900 shown in FIG. 9. As one non-limiting example, the one or more processors may facilitate the performance of the operations described herein (e.g., method 900) by managing or controlling one or more systems and / or equipment operable to perform semiconductor manufacturing.

[0133] At 902, a first under bump metallization component (e.g., under bump metallization component 404A, under bump metallization component 404B, under bump metallization component 504, under bump metallization component 508, under bump metallization component 604, or under bump metallization component 704, or a combination thereof) is bonded (e.g., by computer 1012) to a second under bump metallization component (e.g., under bump metallization component 124B or under bump metallization component 204B, or both) comprising a superconducting interconnect component (e.g., second superconducting layer 106, third superconducting layer 108, or solder bump 122, or a combination thereof) and an intermetallic compound layer (e.g., intermetallic compound layer 120).

[0134] At 904, based on this bonding, a sealed superconducting interconnect component (e.g., second superconducting layer 106 or third superconducting layer 108, or both, sealed by solder bumps 122) is formed (e.g., by computer 1012) on the first under-bump metallization component.

[0135] In some embodiments, such coupling of operation 902 and forming of operation 904 may be performed (e.g., by computer 1012) by employing one or more integrated circuit fabrication techniques (e.g., reflow soldering, cold welding, etc.) described above with reference to Figures 4(A) and (B), 5(A)-(D), 6(A) and (B), or 7(A) and (B), or combinations thereof. It should be appreciated that such coupling of operation 902 and forming of operation 904 may provide a flip-chip device including one or more hermetically sealed superconducting interconnect components (e.g., second superconducting layer 106, third superconducting layer 108, etc.) that can prevent oxide formation (e.g., oxidation) between the hermetically sealed superconducting interconnect component (e.g., second superconducting layer 106, third superconducting layer 108, etc.) and another conductive component (e.g., solder bumps 122), thereby facilitating improved electrical coupling of such components. It should also be appreciated that such bonding of operation 902 and formation of operation 904 can provide flip chip devices having improved mechanical integrity and improved strength of mechanical connections between various components of such flip chip devices (e.g., between a first underbump metallization component and solder bumps 122, between a second underbump metallization component and solder bumps 122, etc.) It should further be appreciated that such sealing, improved electrical bonding, improved mechanical integrity, and improved mechanical interconnections as described above can be advantages of the present disclosure over the prior art.

[0136] For ease of explanation, the methodologies (e.g., computer-implemented methods) described herein are depicted and described as a series of acts. It should be understood that the innovations are not limited by the depicted acts and / or the order of acts, e.g., acts can occur in various orders and / or simultaneously with other acts not presented or described herein. Moreover, not all depicted acts may be required to implement a methodology (e.g., computer-implemented method) described herein in accordance with the disclosed subject matter. In addition, those skilled in the art will appreciate that such a methodology could alternatively be represented as a series of interrelated states or events via a state diagram. Furthermore, it should be further understood that the methodologies (e.g., computer-implemented methods) disclosed below and throughout this specification can be stored on an article of manufacture to facilitate transporting and transferring such methodologies (e.g., computer-implemented methods) to a computer. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or computer-readable storage medium.

[0137] To provide context for various aspects of the disclosed subject matter, FIG. 10 and the following discussion are intended to provide an overview of a suitable environment in which various aspects of the disclosed subject matter may be implemented. FIG. 10 illustrates a block diagram of an exemplary, non-limiting operating environment that can facilitate one or more embodiments described herein. For example, operating environment 1000 can be used to implement exemplary, non-limiting method 800 of FIG. 8 or non-limiting method 900 of FIG. 9, or both, where both method 800 and method 900 facilitate the implementation of various embodiments of the present disclosure described herein. Repetitive descriptions of similar elements employed in other embodiments described herein have been omitted for the sake of brevity.

[0138] 10, a suitable operating environment 1000 for implementing various aspects of the present disclosure may include a computer 1012. The computer 1012 may also include a processing unit 1014, a system memory 1016, and a system bus 1018. The system bus 1018 couples system components, including but not limited to the system memory 1016, to the processing unit 1014. The processing unit 1014 may be any of a variety of available processors. Dual microprocessors and other multi-processor architectures may also be employed as the processing unit 1014. The system bus 1018 can be any of several types of bus structures, including a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MCA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), CardBus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), FireWire (IEEE 1394), and Small Computer Systems Interface (SCSI).

[0139] The system memory 1016 may also include volatile memory 1020 and nonvolatile memory 1022. A basic input / output system (BIOS), containing the basic routines for transferring information between elements within the computer 1012, such as during start-up, is stored in the nonvolatile memory 1022. The computer 1012 may also include removable and non-removable, volatile and non-volatile computer storage media. For example, FIG. 10 illustrates disk storage 1024. The disk storage 1024 may include devices such as, but not limited to, a magnetic disk drive, a floppy disk drive, a tape drive, a Jaz drive, a Zip drive, an LS-100 drive, a flash memory card, or a memory stick. The disk storage 1024 may also include storage media, either separately or in combination with other storage media. A removable or non-removable interface, such as interface 1026, is typically used to facilitate connection of the disk storage 1024 to the system bus 1018. 10 also illustrates software that acts as an intermediary between users and the basic computer resources described in suitable operating environment 1000. Such software may include, for example, an operating system 1028. Operating system 1028, which may be stored on disk storage 1024, operates to control and allocate resources of computer 1012.

[0140] System applications 1030 rely on the management of resources by operating system 1028 through program modules 1032 and program data 1034 stored, for example, in either system memory 1016 or disk storage 1024. It should be understood that various operating systems or combinations of operating systems may be used to implement the present disclosure. A user enters commands or information into computer 1012 through one or more input devices 1036. Input devices 1036 include, but are not limited to, pointing devices such as a mouse, trackball, stylus, or touch pad; keyboard; microphone; joystick; game pad; satellite dish; scanner; TV tuner card; digital camera; digital video camera; and webcam. These and other input devices connect to processing unit 1014 through system bus 1018 via one or more interface ports 1038. The one or more interface ports 1038 include, for example, serial ports, parallel ports, game ports, and a universal serial bus (USB). The one or more output devices 1040 use some of the same types of ports as the one or more input devices 1036. In this way, for example, a USB port can be used to provide input to the computer 1012 and output information from the computer 1012 to the output device(s) 1040. The output adapter 1042 is provided to indicate the presence of some output devices 1040 such as monitors, speakers, and printers, among other output devices 1040 that require special adapters. Examples of output adapters 1042 include, but are not limited to, video cards and sound cards, which provide a means of connection between the output device(s) 1040 and the system bus 1018. It should be noted that other devices and / or systems of devices, such as one or more remote computers 1044, provide both input and output capabilities.

[0141] The computer 1012 can operate in a networked environment using logical connections to one or more remote computers, such as one or more remote computers 1044. The one or more remote computers 1044 can be a computer, server, router, network PC, workstation, microprocessor-based device, peer device or other common network node, and can typically include many or all of the elements described relative to the computer 1012. For simplicity, only a memory storage device 1046 is shown, along with the one or more remote computers 1044. The one or more remote computers 1044 are logically connected to the computer 1012 through a network interface 1048 and then physically connected via a communication connection 1050. The network interface 1048 encompasses wired and / or wireless communication networks, such as local-area networks (LANs), wide-area networks (WANs), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, and Token Ring. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks such as Integrated Services Digital Networks (ISDN) and variations thereof, packet-switched networks, and Digital Subscriber Lines (DSL). One or more communications connections 1050 refer to the hardware / software employed to connect the network interface 1048 to the system bus 1018.Communications connection 1050 is shown within computer 1012 for clarity of explanation, but can also be external to computer 1012. The hardware / software for connecting to network interface 1048 can include, by way of example only, internal and external technologies such as modems, including regular telephone-grade modems, cable modems, and DSL modems, ISDN adapters, and Ethernet cards.

[0142] The present invention may be a system, method, apparatus, or computer program product, or any combination thereof, at any possible level of technical detail. The computer program product may include one or more computer-readable storage media containing computer-readable program instructions for causing a processor to perform aspects of the present invention. A computer-readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction-execution device. The computer-readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media may include portable floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves in which instructions are recorded, and any suitable combination thereof. As used herein, a computer-readable storage medium should not itself be construed as a transitory signal such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse passing through a fiber optic cable), or an electrical signal transmitted over a wire.The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to each computing / processing device or to an external computer or storage device over a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). This network may comprise copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface within each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage on a computer-readable storage medium within each computing / processing device. The computer readable program instructions for carrying out the operations of the present invention can be either assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk® or C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions can execute entirely on a user's computer, partially on a user's computer as a stand-alone software package, partially on each of the user's computer and a remote computer, or entirely on a remote computer or server.In the latter scenario, the remote computer can be connected to the user's computer over any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be to an external computer (e.g., over the Internet using an Internet service provider). In some embodiments, to carry out aspects of the invention, electronic circuitry, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute computer-readable program instructions to customize the electronic circuitry by utilizing state information of the computer-readable program instructions.

[0143] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions. These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to create a machine, such that the instructions, executed by a processor of the computer or other programmable data processing apparatus, create means for performing the functions / operations specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer-readable program instructions can also be stored on a computer-readable storage medium and can direct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner, such that the computer-readable storage medium on which the instructions are stored comprises an article of manufacture containing instructions for implementing aspects of the functions / operations specified in one or more blocks of the flowchart illustrations and / or block diagrams. Computer-readable program instructions may also be loaded into a computer, other programmable data processing apparatus, or other device such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / acts specified in one or more blocks of the flowcharts and / or block diagrams, thereby causing a series of operable operations to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process.

[0144] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing one or more specified logical functions. In some alternative implementations, the functions shown in the blocks may occur out of the order shown in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or in the reverse order, depending on the functionality involved. It will also be noted that each block in the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a special-purpose hardware-based system that performs the specified functions or operations or executes a combination of special-purpose hardware and computer instructions.

[0145] While the subject matter has been described above in the general context of computer-executable instructions for a computer program product executing on one or more computers, or both, those skilled in the art will recognize that the present disclosure may be combined with or implemented in conjunction with other program modules. Typically, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Furthermore, those skilled in the art will appreciate that the computer-implemented methods of the present invention may be practiced using other computer system configurations, including single-processor or multiprocessor computer systems, minicomputing devices, mainframe computers, as well as computers, handheld computing devices (e.g., PDAs, phones), and microprocessor-based or programmable consumer or industrial electronics. The illustrated aspects may also be practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communications network. However, some, if not all, aspects of the present disclosure may be practiced on standalone computers. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.

[0146] As used in this application, terms such as “component,” “system,” “platform,” and “interface” can refer to and / or include computer-related or operable machine-related entities that include one or more particular functions. The entities disclosed herein can be hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, or a computer, or combinations thereof. By way of example, both an application running on a server and the server can be a component. One or more components can reside within a process and / or a thread of execution, and a component can be localized on one computer or distributed between two or more computers. In another example, each component can execute from various computer-readable media having various data structures stored thereon. Components can communicate via local and / or remote processes, such as according to signals containing one or more data packets (e.g., data from one component to another component in a local or distributed system, or to other systems via signals over a network such as the Internet, or both). As another example, a component can be a device having a specific functionality provided by mechanical parts operated by electrical or electronic circuits, which in turn are operated by software or firmware applications executed by a processor. In such cases, the processor can be internal or external to the device and can execute at least a portion of the software or firmware application.As yet another example, a component can be a device that provides a particular function through electronic components that do not include mechanical parts, and those electronic components can include a processor or other means for executing software or firmware that provides at least some of the functionality of the electronic component. In one aspect, a component can emulate an electronic component through a virtual machine, for example, within a cloud computing system.

[0147] Additionally, the term "or" is intended to mean an inclusive "or," rather than an exclusive "or." That is, unless otherwise specified or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A, or X employs B, or X employs both A and B, then "X employs A or B" is satisfied in any of the foregoing cases. Furthermore, the articles "a" and "an" as used in this specification and the accompanying drawings should generally be construed to mean "one or more" unless otherwise specified or clear from context to refer to the singular form. As used herein, the terms "example" and / or "exemplary" are used to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. Additionally, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, and is not intended to exclude equivalent exemplary structures and techniques known to those skilled in the art.

[0148] As used herein, the term "processor" may refer to virtually any computing unit or device, including, but not limited to, a single-core processor, a single processor with software multithreading, a multi-core processor, a multi-core processor with software multithreading, a multi-core processor with hardware multithreading, a parallel platform, and a parallel platform with distributed shared memory. Furthermore, a processor may refer to an integrated circuit, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, a processor may utilize nanoscale architectures, such as, but not limited to, molecular and quantum dot-based transistors, switches, and gates, to optimize space utilization and improve performance of user equipment. A processor may be implemented as a combination of computing units. In this disclosure, terms such as "store," "storage," "data store," "data storage," "database," and substantially any other information storage component, relating to the operation and functionality of a component, are used to refer to a "memory component," an entity embodied in a "memory," or a component comprising a memory.It should be understood that the memory and / or memory components described herein can be either volatile or nonvolatile memory, or can include both volatile and nonvolatile memory. Examples of nonvolatile memory may include, but are not limited to, read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory may include RAM, which can function, for example, as external cache memory. For example, RAM is available in many forms, including, but not limited to, synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), Direct Rambus RAM (DRRAM), Direct Rambus Dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the memory components of the systems or computer-implemented methods disclosed herein are intended to comprise memory, including, but not limited to, these and any other suitable types of memory.

[0149] The foregoing includes merely exemplary systems and computer-implemented methods. Of course, for purposes of describing this disclosure, it is not possible to describe every conceivable combination of components or computer-implemented methods, but one of ordinary skill in the art will recognize that many other combinations and permutations of the present disclosure are possible. Furthermore, to the extent terms such as "including," "having," and "possessing" are used in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a similar manner to the term "comprising," as "comprising" is interpreted when used as a transitional term in a claim.

[0150] The descriptions of various embodiments are presented for illustrative purposes but are not intended to be exhaustive or limited to the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond those found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. providing an under-bump metallization component including at least one superconducting layer, a solder diffusion layer on the superconducting layer, and a solder wetting layer on the solder diffusion layer; depositing solder on the under-bump metallization component; forming an intermetallic compound layer between the solder and the solder diffusion layer based on the deposition; and forming the intermetallic compound layer includes consuming the solder wetting layer by reacting with the solder, and forming the intermetallic compound layer by reacting a portion of the solder diffusion layer with the solder; method.

2. providing an under-bump metallization component including at least one superconducting layer, a solder diffusion layer on the superconducting layer, and a solder wetting layer on the solder diffusion layer, the at least one superconducting layer having an exposed portion exposed by channels through the solder diffusion layer and the solder wetting layer; depositing solder within the channel and on the under bump metallization component; forming an intermetallic compound layer between the solder and the solder diffusion layer based on the deposition; And, forming a hermetically sealed superconducting interconnect component based on the deposition, the superconducting interconnect component including the at least one superconducting layer, the exposed portion of the at least one superconducting layer being hermetically sealed by the solder. and

3. Providing a second under-bump metallization component, the second under-bump metallization component including at least one second superconducting layer, a second solder diffusion layer on the second superconducting layer, and a second solder wetting layer on the second solder diffusion layer; and bonding the second under-bump metallization component onto the solder; 3. The method of claim 1 or 2, further comprising:

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