Semiconductor device manufacturing method

Abstract

To control the diffusion distance of magnesium in a GaN-based semiconductor substrate.SOLUTION: A method of manufacturing a semiconductor device includes the following steps of: injecting an inert element or an electron beam into a GaN-based semiconductor substrate; injecting magnesium into the GaN-based semiconductor substrate; and performing heat treatment on the GaN-based semiconductor substrate. A reference depth Dref calculated by a numerical expression of Dref=D1+140 nm from an injection depth D1 (nm) deepest at the step of injecting an inert element or an electron beam, is deeper than an injection depth D2 (nm) deepest at the step of injecting magnesium. After the heat treatment, the magnesium concentration is reduced toward a deeper side at a predetermined decrease rate and at a position of the reference depth Dref. The predetermined decrease rate is smaller than a such decrease rate that the magnesium concentration becomes 1 / 10 at around a depth of 300 nm.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device.

[0002] Patent Document 1 discloses a technique for forming a p-type semiconductor layer in a GaN-based semiconductor substrate. In this technique, magnesium is implanted into the GaN-based semiconductor substrate, and then the GaN-based semiconductor substrate is heat-treated. The heat treatment activates the magnesium inside the GaN-based semiconductor substrate. As a result, a p-type semiconductor layer is formed inside the GaN-based semiconductor substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2020-155468 Summary of the Invention [Problem to be solved by the invention]

[0004] During heat treatment to activate magnesium, magnesium diffuses inside a GaN-based semiconductor substrate. The diffusion distance of magnesium varies greatly depending on the heat treatment conditions, etc., making it difficult to control the diffusion distance of magnesium. For this reason, it was difficult to control the shape of the p-type semiconductor layer with the manufacturing method of Patent Document 1. This specification proposes a technology for controlling the diffusion distance of magnesium in a GaN-based semiconductor substrate more accurately than conventional techniques. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device includes the steps of implanting an inert element or an electron beam into a GaN-based semiconductor substrate, implanting magnesium into the GaN-based semiconductor substrate, and heat-treating the GaN-based semiconductor substrate after the steps of implanting the inert element or the electron beam and implanting magnesium are performed. A first implantation range, which is a range for implanting the inert element or the electron beam, and a second implantation range, which is a range for implanting magnesium, overlap on the surface of the GaN-based semiconductor substrate. A reference depth Dref, calculated from the deepest implantation depth D1 (nm) in the step of implanting the inert element or the electron beam using the formula Dref = D1 + 140 nm, is deeper than the deepest implantation depth D2 (nm) in the step of implanting magnesium. After the heat treatment, in the magnesium concentration distribution in the depth direction within the range where the first implantation range and the second implantation range overlap, the magnesium concentration at the reference depth Dref decreases at a predetermined decrease rate with increasing depth. The predetermined decrease rate is smaller than the decrease rate at which the magnesium concentration becomes 1 / 10 per 300 nm.

[0006] It should be noted that either the step of implanting an inert element or an electron beam into the GaN-based semiconductor substrate or the step of implanting magnesium into the GaN-based semiconductor substrate may be performed first. Furthermore, a GaN-based semiconductor substrate refers to a semiconductor substrate whose main component is GaN (i.e., gallium nitride). For example, the GaN-based semiconductor substrate may be made of GaN, AlGaN, InGaN, AlInGaN, or the like. Furthermore, a smaller decrease rate means that the magnesium concentration decreases at a more rapid rate. In other words, a smaller decrease rate means that the magnesium concentration decreases at a steeper slope. For example, the decrease rate at which the magnesium concentration decreases to 1 / 20 per 300 nm is smaller than the decrease rate at which the magnesium concentration decreases to 1 / 10 per 300 nm. The decrease rate is calculated using the following formula: -3 ) and the logarithm of the concentration P with base 10 is log 10 When P is used, dD / dlog 10P. That is, the reduction rate can be expressed as the logarithm of the depth D. 10 In other words, "the predetermined decrease rate is smaller than the decrease rate at which the magnesium concentration becomes 1 / 10 per 300 nm depth" is the value obtained by differentiating dD / dlog 10 This means that P<300. The inert element means an element that does not function as an acceptor or a donor when implanted into a GaN-based semiconductor substrate.

[0007] In the step of injecting an inert element or an electron beam into a GaN-based semiconductor substrate (hereinafter referred to as the first injection step), crystal defects are formed in the injection region. The crystal defects are formed at the depth where the inert element or the electron beam is injected and in the vicinity thereof. In the GaN-based semiconductor substrate, crystal defects are formed up to a position deeper than a reference depth Dref, where Dref = D1 + 140 nm, relative to the deepest injection depth D1 in the first injection step. At the reference depth Dref, the crystal defect density rapidly decreases toward the deeper side. In the step of injecting magnesium into the GaN-based semiconductor substrate (hereinafter referred to as the second injection step), magnesium is injected into a range shallower than the reference depth Dref. When the GaN-based semiconductor substrate is heat-treated after the first injection step and the second injection step, magnesium diffuses within the GaN-based semiconductor substrate. At this time, magnesium diffuses rapidly in the region where crystal defects were formed in the first injection step (i.e., the region shallower than the reference depth Dref). On the other hand, diffusion of magnesium is suppressed at the interface between the region where crystal defects were formed and the region where crystal defects were not formed. Therefore, if magnesium is sufficiently diffused in the region where crystal defects are formed in the heat treatment process, the edge of the magnesium diffusion region can be controlled to be near the position of the reference depth Dref. In this case, a distribution is obtained in which the magnesium concentration decreases at a very small rate as the depth increases at the position of the reference depth Dref. More specifically, the decrease rate of the magnesium concentration at the position of the reference depth Dref is smaller than the decrease rate at which the magnesium concentration becomes 1 / 10 per 300 nm depth. As described above, this manufacturing method can control the edge of the magnesium diffusion region to be near the position of the reference depth Dref, thereby suppressing variations in the diffusion distance of magnesium. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor device 10. [Figure 2] FIG. [Figure 3] An explanatory diagram of the N injection process. [Figure 4] 1 is a graph showing the N concentration distribution in the depth direction. [Figure 5] FIG. 2 is an explanatory diagram of the Mg injection step in Example 1. [Figure 6] FIG. 2 is a plan view of the Mg implantation range and the N implantation range when the GaN-based semiconductor substrate is viewed from above. [Figure 7] FIG. 2 is an explanatory diagram of the heat treatment process of Example 1. [Figure 8] 1 is a graph showing the Mg concentration distribution before a heat treatment process. [Figure 9] Graph showing Mg concentration distribution after a heat treatment process. [Figure 10] 1A to 1C are explanatory diagrams illustrating a process for forming a gate insulating film and a gate electrode. [Figure 11] 10 is a graph showing the Mg concentration distribution when the heat treatment temperature is changed. [Figure 12] FIG. 10 is an explanatory diagram of the Mg injection step in Example 2. [Figure 13] FIG. 10 is an explanatory diagram of a heat treatment process in Example 2. [Figure 14] FIG. 10 is an explanatory diagram of a step of removing the Mg-implanted region in Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0009] In the exemplary manufacturing method disclosed in the present specification, in the step of implanting an inert element or an electron beam, at least one of N, Ga, Ar, H, and He may be implanted into the GaN-based semiconductor substrate.

[0010] In the exemplary manufacturing method disclosed herein, the second implantation area may be included in the first implantation area on the surface. A dose DS1 in the step of implanting an inert element or an electron beam, an area S1 of the first implantation area, a dose DS2 in the step of implanting magnesium, and an area S2 of the second implantation area may satisfy the relationship DS1·S1>DS2·S2.

[0011] In one example of the manufacturing method disclosed in the present specification, the heat treatment may be performed at a temperature of 1300° C. or higher.

[0012] This configuration makes it possible to more reliably obtain the effect of suppressing the diffusion of Mg at the interface of the implanted region in the first implantation step.

[0013] In one example manufacturing method disclosed in this specification, after the heat treatment, a step of forming a gate electrode so that a range of the surface outside the second implantation range and inside the first implantation range becomes a channel region may be included.

[0014] The channel region refers to a semiconductor region in which an inversion layer (i.e., a channel) is formed when a potential equal to or greater than the gate threshold is applied to the gate electrode. With this configuration, a region with few crystal defects can be used as the channel region, thereby reducing the channel resistance.

[0015] In the exemplary manufacturing method disclosed herein, the magnesium concentration in the channel region may be 10% or more of the magnesium concentration in the region into which magnesium is implanted in the step of implanting magnesium.

[0016] In one example of the manufacturing method disclosed in the present specification, after the heat treatment, the method may further include a step of removing the region into which magnesium has been implanted in the step of implanting magnesium to expose a p-type region underneath, and a step of forming a gate electrode so that the exposed p-type region becomes a channel region.

[0017] According to this configuration, a region with few crystal defects can be used as the channel region, and the channel resistance can be reduced.

[0018] FIG. 1 shows a semiconductor device 10 manufactured by a manufacturing method according to the embodiment. The semiconductor device 10 includes a GaN-based semiconductor substrate 12. A drain layer 20, a drift layer 22, multiple body layers 24, and multiple source layers 26 are provided within the GaN-based semiconductor substrate 12. The drain layer 20 is an n-type layer and is disposed in an area including the bottom surface 12b of the GaN-based semiconductor substrate 12. The drift layer 22 is an n-type layer having a lower n-type impurity concentration than the drain layer 20. The drift layer 22 is disposed above the drain layer 20. The multiple body layers 24 are p-type layers and are disposed above the drift layer 22. Each body layer 24 is disposed in an area that partially includes the top surface 12a of the GaN-based semiconductor substrate 12. The body layers 24 are disposed at intervals. Hereinafter, the intervals between the body layers 24 are referred to as window portions 23. The drift layers 22 are disposed in the window portions 23. Within the window portion 23, the drift layer 22 extends to the top surface 12a. Each source layer 26 is an n-type layer and is disposed inside the corresponding body layer 24. Each source layer 26 is disposed in an area that partially includes the top surface 12a. Each source layer 26 is separated from the drift layer 22 by the corresponding body layer 24.

[0019] A gate insulating film 40, a gate electrode 42, an interlayer insulating film 44, and a source electrode 46 are provided on the upper surface of the GaN-based semiconductor substrate 12. The gate insulating film 40 extends from the upper surface of one source layer 26 to the upper surface of the other source layer 26. The gate insulating film 40 covers the upper surface of the body layer 24 and the upper surface of the drift layer 22 in the window portion 23 between the two source layers 26. The gate electrode 42 is disposed on top of the gate insulating film 40. The gate electrode 42 faces the source layer 26, the body layer 24, and the drift layer 22 in the window portion 23 via the gate insulating film 40. The interlayer insulating film 44 covers the gate electrode 42. The source electrode 46 covers the interlayer insulating film 44 and the upper surface 12a of the GaN-based semiconductor substrate 12. The source electrode 46 is electrically connected to each source layer 26 and each body layer 24.

[0020] A drain electrode 48 is provided on the lower part of the GaN-based semiconductor substrate 12. The drain electrode 48 is electrically connected to the drain layer 20.

[0021] When the semiconductor device 10 is in use, a higher potential is applied to the drain electrode 48 than to the source electrode 46. When a potential equal to or higher than the gate threshold is applied to the gate electrode 42, a channel is formed in the body layer 24 below the gate insulating film 40 (i.e., the surface portion of the body layer 24 between the window portion 23 and the source layer 26). Hereinafter, the portion of the body layer 24 where the channel is formed is referred to as the channel region 24a. When the channel is formed in the channel region 24a, electrons flow from the source layer 26 to the drain layer 20 via the channel and the drift layer 22, turning on the semiconductor device 10.

[0022] Next, a description will be given of a method for manufacturing the semiconductor device 10. First, a conventional method for manufacturing the semiconductor device 10 will be described.

[0023] (Conventional manufacturing method) The semiconductor device 10 is manufactured from a GaN-based semiconductor substrate including a drain layer 20. First, as shown in FIG. 2, a drift layer 22 is epitaxially grown on the drain layer 20. Next, Mg (i.e., magnesium) is implanted into the surface layer of the drift layer 22. Next, the GaN-based semiconductor substrate 12 is heat-treated to diffuse and activate the Mg within the GaN-based semiconductor substrate 12. Since Mg functions as a p-type impurity within the GaN-based semiconductor substrate 12, a p-type body layer 24 is formed within the area into which the Mg has diffused. Thereafter, as shown in FIG. 1, a source layer 26, a gate insulating film 40, a gate electrode 42, an interlayer insulating film 44, a source electrode 46, and a drain electrode 48 are formed by a conventionally known method. This completes the semiconductor device 10.

[0024] In conventional manufacturing methods, it is difficult to control the diffusion distance of Mg during the heat treatment process, which leads to the following problems:

[0025] The longer the diffusion distance of Mg, the thicker the body layer 24 and the longer the vertical length of the window portion 23. As the vertical length of the window portion 23 increases, the resistance of the window portion 23 increases, and the on-resistance of the semiconductor device 10 increases. Therefore, if the diffusion distance of Mg varies greatly, the resistance of the window portion 23 varies greatly, and the on-resistance of the semiconductor device 10 varies greatly.

[0026] Furthermore, if the diffusion distance of Mg is long, a small amount of Mg that diffuses below the body layer 24 may segregate at the interface between the drift layer 22 and the drain layer 20. If a Mg segregation layer is formed at the interface between the drift layer 22 and the drain layer 20, the on-resistance of the semiconductor device 10 increases. Therefore, if the diffusion distance of Mg varies greatly, the on-resistance of the semiconductor device 10 varies more due to the influence of the segregation layer.

[0027] Furthermore, the longer the diffusion distance of Mg, the lower the p-type impurity concentration in the surface layer of the body layer 24, and the lower the p-type impurity concentration in the channel region 24a. A low p-type impurity concentration in the channel region 24a lowers the gate threshold (i.e., the gate potential required to form a channel). Therefore, a large variation in the diffusion distance of Mg leads to a large variation in the gate threshold.

[0028] As described above, it is difficult to control the diffusion distance of Mg in conventional manufacturing methods, and as a result, the on-resistance and gate threshold of the semiconductor device 10 vary greatly.

[0029] (Manufacturing method of Example 1) In the manufacturing method of Example 1, the drift layer 22 is also epitaxially grown on the drain layer 20, as shown in FIG. 2 . Next, an N implantation step is performed. In the N implantation step, N (i.e., nitrogen) ions are implanted into the upper surface 12a of the GaN-based semiconductor substrate 12, as shown in FIG. 3 . Here, the N implantation range is limited using a mask (not shown). Hereinafter, the N implantation range in the upper surface 12a is referred to as an implantation range Rn. Here, N ions are implanted into a range of the upper surface 12a where the body layer 24 is to be formed. N ions are not implanted into a range of the upper surface 12a where the window portion 23 is to be formed. In this example, N ions are implanted multiple times while changing the N implantation energy En, so that N ions are implanted into the entire depth range corresponding to the body layer 24. By implanting N into the GaN-based semiconductor substrate 12 in this manner, an N-implanted region 24n is formed in the GaN-based semiconductor substrate 12. When N is implanted into the GaN-based semiconductor substrate 12, crystal defects are formed in the implanted region. Therefore, the N-implanted region 24n is a region in which crystal defects are formed by the N implantation step. In the GaN-based semiconductor substrate 12, under conditions that do not cause channeling (for example, a tilt angle of 7° and a twist angle of 15°), the acceleration energy En (keV) when implanting N and the N implantation depth Dn (nm) satisfy the relationship of the following mathematical formula: Dn=-4.03×10 -4 En 2 +1.41En-13.8 The implantation depth Dn is the average depth at which N stops. N implanted into the GaN-based semiconductor substrate 12 with the implantation energy En is distributed around the implantation depth Dn.

[0030] Graph G in FIG. 4 shows the concentration distribution of N implanted into the GaN-based semiconductor substrate 12 in the N implantation step. The horizontal axis of FIG. 4 shows the implantation depth, and the origin shows the position of the upper surface 12a. Note that, because the GaN-based semiconductor substrate 12 itself contains N, it is difficult to actually measure graph G, which shows the concentration distribution of the implanted N. Graph G is calculated based on the implantation energy En in the N implantation step. Furthermore, as described above, when N is implanted into the GaN-based semiconductor substrate 12, crystal defects are formed in the GaN-based semiconductor substrate 12. Graph G corresponds to the distribution of crystal defects formed in the GaN-based semiconductor substrate in the N implantation step.

[0031] As described above, in the N implantation step, N ions are implanted multiple times while changing the implantation energy En. Therefore, N is distributed at a relatively high and relatively uniform concentration in the surface layer of the GaN-based semiconductor substrate 12. The depth D1 in FIG. 4 indicates the deepest implantation depth in the N implantation step. The reference depth Dref in FIG. 4 is calculated using the formula Dref=D1+140 nm. As shown in FIG. 4, at the reference depth Dref, the N concentration rapidly decreases toward the deeper side. That is, at the reference depth Dref, the density of crystal defects rapidly decreases toward the deeper side. In this way, it is possible to calculate the reference depth Dref at which the N concentration rapidly decreases from the deepest implantation depth D1 in the N implantation step. In FIG. 3, the position of the reference depth Dref is shown as the bottom end of the N implantation region 24n.

[0032] Next, the Mg implantation process is performed. In the Mg implantation process, as shown in FIG. 5, Mg ions are implanted into the upper surface 12a of the GaN-based semiconductor substrate 12. Here, the Mg implantation range is limited using a mask (not shown). Hereinafter, the Mg implantation range within the upper surface 12a will be referred to as the implantation range Rmg. Herein, as shown in FIG. 6, Mg ions are implanted into the upper surface 12a so that the N implantation range Rn and the Mg implantation range Rmg overlap. In this embodiment, the implantation range Rmg is smaller than the implantation range Rn and is included within the implantation range Rn. Herein, Mg ions may be implanted multiple times while varying the Mg implantation depth, or Mg ions may be implanted to a fixed depth. By implanting Mg into the GaN-based semiconductor substrate 12 in this manner, an Mg-implanted region 24mg is formed within the GaN-based semiconductor substrate 12. Herein, as shown in FIG. 5, Mg ions are implanted at a position shallower than the reference depth Dref. Hereinafter, the deepest implantation depth in the Mg implantation process will be referred to as the implantation depth D2. As shown in FIG. 5, the implantation depth D2 is shallower than the reference depth Dref.

[0033] The amount of N implanted in the N implantation step can be equal to or greater than the amount of Mg implanted in the Mg implantation step. The amount of N implanted can be expressed as the product of the dose DS1 in the N implantation step and the area S1 of the implantation range Rn in the N implantation step. The amount of Mg implanted can be expressed as the product of the dose DS2 in the Mg implantation step and the area S2 of the implantation range Rmg in the Mg implantation step. That is, the amounts of N and Mg implanted can be adjusted to satisfy the relationship DS1·S1>DS2·S2.

[0034] After the N implantation step and the Mg implantation step are performed, a heat treatment step is performed. In this embodiment, the GaN-based semiconductor substrate 12 is heat-treated at a temperature of 1300°C or higher. When the GaN-based semiconductor substrate 12 is heat-treated, Mg diffuses and is activated inside the GaN-based semiconductor substrate 12. That is, Mg in the Mg-implanted region 24mg diffuses to its surroundings. Mg is easily diffused in the N-implanted region 24n. Furthermore, Mg diffusion is suppressed at the interface between the N-implanted region 24n and the region where N is not implanted. Therefore, as shown in FIG. 7, a p-type body layer 24 is formed in the N-implanted region 24n.

[0035] 8 and 9 show the Mg concentration distribution at the position of the line AA in FIG. 7. That is, FIGS. 8 and 9 show the Mg concentration distribution measured in the depth direction from the position where the N implantation range Rn and the Mg implantation range Rmg overlap. FIG. 8 shows the distribution before the heat treatment process, and FIG. 9 shows the distribution after the heat treatment process. Graphs A to C in FIGS. 8 and 9 show the Mg concentration distribution when the manufacturing method of Example 1 is performed. Graph G in FIGS. 8 and 9 shows the concentration distribution of N implanted in the N implantation process. That is, graph G in FIGS. 8 and 9 is equivalent to graph G in FIG. 4. Graph D in FIGS. 8 and 9 shows the Mg concentration distribution when the N implantation process is not performed as a comparative example. Graphs A to D show values ​​actually measured by experiments. As described above, graph G is a graph calculated based on the implantation energy En in the N implantation process.

[0036] As shown in Fig. 8, graph A shows the case where Mg is implanted at a high concentration into a narrow range in the surface layer during the Mg implantation process. Graph B shows the case where Mg is implanted at a lower concentration into a wider range than graph A during the Mg implantation process. Graph C shows the case where Mg is implanted at an even lower concentration into an even wider range than graph B during the Mg implantation process. Also, as shown in Fig. 8, before the heat treatment process, graphs C and D are approximately equal.

[0037] As shown in FIG. 9, after the heat treatment step, the Mg concentration is distributed relatively uniformly in the surface layer of the GaN-based semiconductor substrate 12 in all of the graphs A to C. The Mg concentration in the surface layer is approximately the same between the graphs A to C. This shows that Mg is sufficiently diffused in the N-implanted region 24n. In the vicinity of the reference depth Dref, the Mg concentration decreases rapidly so that the deeper the Mg concentration, the lower it becomes. The dashed line X in FIG. 9 indicates the rate of decrease at which the Mg concentration becomes 1 / 10 at a depth of 300 nm (i.e., the relationship between the depth D and the Mg concentration P is dD / dlog 10 In all of the graphs A to C, the Mg concentration decreases at a steeper slope than the dashed line X at the reference depth Dref. That is, in all of the graphs A to C, the decrease rate (i.e., dD / dlog 10 On the other hand, in graph D, the Mg concentration in the surface layer is lower than in graphs A to C. Also, in graph D, the gradient of the decrease in Mg concentration at the position corresponding to the reference depth Dref is gentler than that of dashed line X. That is, in graph D, the decrease rate dD / dlog 10 P is greater than 300 nm. Therefore, in the range deeper than the reference depth Dref, the Mg concentration is higher in graph D than in graphs A to C. That is, in graph D, Mg diffuses to a position deeper than in graphs A to C. As is clear from a comparison of graphs A to C with graph D, when the N implantation step is performed, the diffusion of Mg is suppressed at the position of the reference depth Dref (i.e., the position of the boundary of the N implanted region 24n). In this way, when a heat treatment step is performed after the N implantation step and the Mg implantation step, the diffusion of Mg into a region deeper than the reference depth Dref can be suppressed.

[0038] As described above, performing the heat treatment step after performing the N implantation step and the Mg implantation step suppresses the diffusion of Mg at the interface between the N implanted region 24n and the region where N is not implanted. Therefore, by controlling the implantation range Rn and implantation depth Dn in the N implantation step, the diffusion range of Mg can be controlled, and the formation range of the body layer 24 can be accurately controlled.

[0039] Next, as shown in FIG. 10 , a source layer 26 is formed by ion implantation. Next, a gate insulating film 40 is formed to cover the surface of the body layer 24 between the source layer 26 and the window portion 23. Next, a gate electrode 42 is formed on top of the gate insulating film 40. By forming the gate insulating film 40 and the gate electrode 42 in this manner, the surface portion of the body layer 24 between the source layer 26 and the window portion 23 becomes the channel region 24a. In FIG. 10 , the body layer 24 outside the Mg-implanted region 24mg is formed by Mg diffused from the Mg-implanted region 24mg. The Mg-implanted region 24mg contains many crystal defects formed when Mg is ion-implanted. On the other hand, the body layer 24 outside the Mg-implanted region 24mg has fewer crystal defects than the Mg-implanted region 24mg. By forming the body layer 24 outside the Mg-implanted region 24mg as the channel region 24a, the crystal defects in the channel region 24a can be reduced. Reducing the crystal defects in the channel region 24a can reduce the channel resistance. In this case, a portion of the Mg-implanted region 24mg having an Mg concentration of 10% or more can be used as the channel region 24a, thereby achieving suitable switching.

[0040] Thereafter, an interlayer insulating film 44, a source electrode 46, and a drain electrode 48 are formed, thereby completing the semiconductor device 10 shown in FIG.

[0041] As described above, according to the manufacturing method of Example 1, the diffusion distance of Mg can be accurately controlled, and the formation range of the body layer 24 can be accurately controlled. This reduces variations in the vertical length of the window portion 23, and reduces variations in the on-resistance of the semiconductor device 10. Furthermore, since Mg can be prevented from diffusing to the interface between the drift layer 22 and the drain layer 20, variations in the on-resistance due to the influence of the segregation layer can be suppressed. Furthermore, since the diffusion distance of Mg can be accurately controlled, the Mg concentration in the channel region 24a can be accurately controlled. This reduces variations in the gate threshold of the semiconductor device 10.

[0042] Even when a heat treatment process is performed after the N implantation process and the Mg implantation process, if the temperature or time of the heat treatment process is insufficient, the Mg diffusion distance may not be accurately controlled. For example, if the heat treatment process is insufficient, Mg does not sufficiently diffuse to the reference depth Dref, and the Mg diffusion suppression effect at the interface of the N implantation region 24n is not obtained. For example, FIG. 11 shows the concentration distribution when the heat treatment process is performed while changing the heat treatment temperature after the N implantation process and the Mg implantation process. As shown in FIG. 11, when the heat treatment temperature T is 1300°C, 1350°C, and 1460°C, Mg can be sufficiently diffused to the reference depth Dref. That is, in these cases, the Mg concentration decreases at the reference depth Dref with a steeper slope than the dashed line X. In contrast, when the heat treatment temperature T is 1250°C, Mg cannot be sufficiently diffused to the reference depth Dref. Therefore, in this case, the slope of the Mg concentration at the reference depth Dref is gentler than the dashed line X. That is, in this case, the effect of suppressing the diffusion of Mg at the interface of the N-implanted region 24n cannot be obtained. Therefore, in order to obtain the effect of suppressing the diffusion of Mg at the interface of the N-implanted region 24n, the GaN-based semiconductor substrate 12 can be heat-treated at a temperature of 1300°C or higher and lower than the melting point in the heat treatment step.

[0043] Example 2 In the manufacturing method of Example 2, an N implantation step is performed in the same manner as in Example 1, followed by an Mg implantation step as shown in FIG. 12. Here, Mg is implanted within a wider range of N implantation than in Example 1 (i.e., FIG. 5). Next, a heat treatment step is performed in the same manner as in Example 1, and a body layer 24 is formed in the N implantation region 24n as shown in FIG. 13. Next, the upper surface 12a of the GaN-based semiconductor substrate 12 is etched to remove the Mg implantation region 24mg, as shown in FIG. 14, exposing the body layer 24 below the Mg implantation region 24mg. Next, a source layer 26, a gate insulating film 40, a gate electrode 42, an interlayer insulating film 44, a source electrode 46, and a drain electrode 48 are formed in the same manner as in Example 1. This completes the semiconductor device 10.

[0044] In the manufacturing method of Example 2, the gate insulating film 40 and the gate electrode 42 are formed so that the body layer 24 exposed by removing the Mg-implanted region 24mg becomes the channel region 24a. According to the manufacturing method of Example 2, the body layer 24 outside the Mg-implanted region 24mg can be made into the channel region 24a, and crystal defects in the channel region 24a can be reduced. Therefore, the channel resistance can be reduced.

[0045] In the above-described Examples 1 and 2, N is implanted as an inert element into the GaN-based semiconductor substrate 12. However, at least one of N, Ga, Ar, H, and He may be implanted as the inert element. Also, instead of an inert element, an electron beam may be implanted (i.e., irradiated) into the GaN-based semiconductor substrate 12.

[0046] In addition, in the above-described first and second embodiments, the Mg implantation step is carried out after the inert element implantation step, but the inert element implantation step may be carried out after the Mg implantation step.

[0047] In the above-described first and second embodiments, the Mg implantation range Rmg was included in the inert element implantation range. However, as long as the Mg implantation range Rmg and the inert element implantation range at least partially overlap, the Mg implantation range Rmg may extend outside the inert element implantation range. Even with this configuration, the Mg diffusion distance can be controlled within the inert element implantation region.

[0048] The above-mentioned injection range Rn is an example of a first injection range, and the above-mentioned injection range Rmg is an example of a second injection range.

[0049] The following is a list of configurations of the technology disclosed in this specification. (Configuration 1) A method for manufacturing a semiconductor device, comprising: A step of implanting an inert element or an electron beam into a GaN-based semiconductor substrate; implanting magnesium into the GaN-based semiconductor substrate; a step of heat-treating the GaN-based semiconductor substrate after the step of implanting an inert element or an electron beam and the step of implanting magnesium are performed; and a first implantation range, which is an implantation range of an inert element or an electron beam, and a second implantation range, which is an implantation range of magnesium, overlap on a surface of the GaN-based semiconductor substrate; a reference depth Dref calculated from the deepest implantation depth D1 (nm) in the step of implanting an inert element or an electron beam by the formula Dref=D1+140 nm is deeper than the deepest implantation depth D2 (nm) in the step of implanting magnesium; After the heat treatment, in a distribution of magnesium concentration in a depth direction within a range where the first implantation range and the second implantation range overlap, the magnesium concentration at the position of the reference depth Dref decreases at a predetermined decrease rate as it goes deeper, the predetermined decrease rate is smaller than the decrease rate at which the magnesium concentration becomes 1 / 10 per 300 nm depth; Manufacturing method. (Configuration 2) 2. The manufacturing method according to configuration 1, wherein in the step of implanting an inert element or an electron beam, at least one of N, Ga, Ar, H, and He is implanted into the GaN-based semiconductor substrate. (Configuration 3) the second implanted area is included in the first implanted area on the surface; a dose DS1 in the step of implanting an inert element or an electron beam, an area S1 of the first implantation range, a dose DS2 in the step of implanting magnesium, and an area S2 of the second implantation range satisfy a relationship of DS1·S1>DS2·S2; Manufacturing method of configuration 1 or 2. (Configuration 4) 4. The method according to any one of aspects 1 to 3, wherein the heat treatment is carried out at a temperature of 1300° C. or higher. (Configuration 5) The manufacturing method according to any one of configurations 1 to 4, further comprising, after the heat treatment, forming a gate electrode such that a region of the surface outside the second implantation region and inside the first implantation region becomes a channel region. (Configuration 6) 6. The manufacturing method according to configuration 5, wherein the magnesium concentration in the channel region is 10% or more of the magnesium concentration in the region into which magnesium was injected in the step of injecting magnesium. (Configuration 7) a step of removing the region into which magnesium was implanted in the step of implanting magnesium after the heat treatment to expose the underlying p-type region; forming a gate electrode so that the exposed p-type region becomes a channel region; 5. The method according to any one of aspects 1 to 4, further comprising:

[0050] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0051] 12: GaN-based semiconductor substrate, 22: drift layer, 24: body layer, 24a: channel region, 24n: N-implanted region, 24mg: Mg-implanted region, 26: source layer, 40: gate insulating film, 42: gate electrode

Claims

1. A method for manufacturing a semiconductor device, comprising: A step of implanting an inert element or an electron beam into a GaN-based semiconductor substrate (12); implanting magnesium into the GaN-based semiconductor substrate; a step of heat-treating the GaN-based semiconductor substrate after the step of implanting an inert element or an electron beam and the step of implanting magnesium are performed; and a first implantation range (Rn) which is an implantation range of an inert element or an electron beam and a second implantation range (Rmg) which is an implantation range of magnesium overlap on a surface of the GaN-based semiconductor substrate; a reference depth Dref calculated from the deepest injection depth D1 (nm) in the step of injecting an inert element or an electron beam by the formula Dref=D1+140 nm is deeper than the deepest injection depth D2 (nm) in the step of injecting magnesium; after the heat treatment, in a distribution of magnesium concentration in a depth direction within a range where the first implantation range and the second implantation range overlap, the magnesium concentration at the position of the reference depth Dref decreases at a predetermined decrease rate as it goes deeper, the predetermined decrease rate is smaller than the decrease rate at which the magnesium concentration decreases to 1 / 10 per 300 nm depth, The method further includes forming a gate electrode (42) after the heat treatment so that a region of the surface outside the second implanted region and inside the first implanted region becomes a channel region (24a); a magnesium concentration in the channel region is 10% or more of a magnesium concentration in a region into which magnesium is injected in the step of injecting magnesium; Manufacturing method.

2. 2. The manufacturing method according to claim 1, wherein in the step of implanting an inert element or an electron beam, at least one of N, Ga, Ar, H, and He is implanted into the GaN-based semiconductor substrate.

3. the second implanted area is included in the first implanted area at the surface; a dose DS1 in the step of implanting an inert element or an electron beam, an area S1 of the first implantation range, a dose DS2 in the step of implanting magnesium, and an area S2 of the second implantation range satisfy a relationship of DS1·S1>DS2·S2; The method of claim 1 or 2.

4. The method according to claim 1 or 2, wherein the heat treatment is carried out at a temperature of 1300° C. or higher.

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