Common gate input circuit for III / VD mode buffer FET logic (BFL)

Abstract

The common gate input circuit of the III / VD mode buffer FET logic (BFL) drives the level shift section with maximum dynamic range, allowing it to set the proper voltage level for switching the BFL and decouple the switch point from the dynamic range. The common gate switching section includes a D mode FET (FET1) configured as a load and a D mode FET (FET2) configured as a common gate connected in series between a high power supply Vdd and a low power supply Vee1 (usually at ground potential). The gate electrode of FET2 is tied to Vee1 and the source electrode of FET2 is driven by an external digital signal. This eliminates the need for an additional power supply Vss, thus maximizing the dynamic range of the section switching between Vdd and Vee1 and decoupling the dynamic range from the switch point. The input level shift section shifts the data in to the source electrode of FET2 to shift the switch point and present a high input impedance.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of priority to U.S. Patent Application No. 17 / 655,356, filed March 17, 2022, which is incorporated by reference herein in its entirety.

[0002] The present invention relates to an input circuit for interfacing an external digital signal, typically CMOS TTL, to a III / V integrated circuit (IC) with D-mode buffer FET logic (BFL). [Background technology]

[0003] Highly integrated monolithic microwave integrated circuits (MMICs) formed from III / V materials such as gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP) are often used in phased array systems to perform multiple functions—switching, phase-shift control, attenuation control, and amplification—on a single chip. As shown in FIG. 1 , an MMIC chip 100 includes a D-mode buffer FET logic (BFL) 102 that provides, for example, a digital attenuator 104, a digital phase shifter 106, an RF amplifier 107, and an RF switch 108. An external digital controller 110 provides digital control signals 112 that control the FET logic circuitry. To reduce the number of external control lines required to perform these functions, input circuitry 114 is built into the III / V MMIC to perform "serial-in to parallel-out" conversion. This built-in conversion can accept a single external data control line input and convert it to multiple parallel output control signals within the III / V MMIC. External digital control signals are typically standard CMOS TTL levels (e.g., 5V CMOS, TTL, LVTTL, 2.5V, 1.8V). III / V MMICS based on depletion-mode (D-mode) FET technology preferably use buffered FET logic (BFL) for embedded digital circuits. Other III / V ICs also require input circuitry.

[0004] When converting digital signals from one type of device, here a digital controller, to a III / V MMIC, the signal must be compatible and sufficiently regenerated so that the second device can process such signals. Therefore, input circuit 114 must also provide a CMOS-to-III / V BFL interface to convert CMOS voltage levels (e.g., for 2.5TTL, logic 0 is 0-0.5V and logic 1 is 2-2.5V) to appropriately regulated D-mode III / V voltage levels (e.g., logic 0 is approximately 0.2V and logic 1 is 2.4V). To maximize signal regeneration, it is desirable to maximize the peak-to-peak voltage swing (e.g., dynamic range) given the limited available power supply. Input circuit 114 is typically incorporated into the MMIC prior to any logic gate function stage. The input circuit includes a switching section to maximize the dynamic range of the available power supply and a level-shifting function to set appropriate voltage levels for the III / V D-mode FETs.

[0005] D-mode FETs used in BFLs are "normally on" devices, requiring a negative gate-source voltage Vgs to place the transistor in an open-circuit or closed (non-conducting) state. A typical negative Vgs threshold can be -0.9 V, referred to as the "switch point." This negative gate-source voltage requirement can limit the amount of dynamic range available from a particular power supply, directly impacting the voltage noise margin of the logic input circuitry. This dynamic range limitation is a direct result of the "common-source" switching section within the core BFL cell. Examples of common-source input circuits are shown in Figure 10 of U.S. Patent No. 5,705,940, Figure 1 of U.S. Patent No. 5,286,985, and Chiara Ramella et al., "GaAs-Based Serial-Input-Parallel-Output Interfaces for Microwave Core-Chips," Electronics 2021, 10, 3020, pp. 1-16.

[0006] 2A-2C show a typical embodiment of a buffer logic FET inverter 200 for interfacing an external CMOS digital signal with a D-mode III / V BFL. In this example, the voltage level at Data In 202 is between 0 and 0.5V for a logic 0 and between 2 and 2.5V for a logic 1. The voltage level at Data Out 204 (which switches the D-mode III / V FET) is approximately 0.2V (ideally 0V at ground potential) for a logic 0 and 1.5V for a logic 1. Inverter 200 includes a common-source switching section 206 that inverts and switches Data In 202 to accommodate the dynamic range of the available power supply, and a level-shifting section 208 that sets the appropriate voltage level at Data Out 204.

[0007] The common-source switching section 206 includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common-source switch connected in series between a high power supply voltage Vdd (e.g., 4 V) and a low power supply voltage Vee (e.g., ground). More specifically, the drain electrode of load FET1 is coupled to Vdd, and its gate-source connection is coupled to the drain of common-source FET2 at intermediate output 210. Data In 202 is sent to the gate electrode of common-source FET2. The gate electrode presents a high input impedance to an external digital controller, limiting the amount of current required to drive the input circuit. For this reason, it is common to bias the drain and source electrodes of common-source FET2 while driving the gate electrode. An additional power supply voltage Vss (e.g., 1.5 V) is applied to the source electrode of common-source FET2. Vss is typically derived from the existing power supply voltage using a diode or voltage divider. Vss is required to generate a negative Vgs to turn off FET2 when Data In is a logic 0 (0 to 0.5 V). For example, if Data In is 0.5V, then Vgs = -1V, which is enough to turn the FET off. If Data In is a logic 1 (2 to 2.5V), then Vgs will be positive and FET2 will remain on.

[0008] 2B, when Data In is logic 0, common source FET2 is off, no current flows through load FET1, and intermediate output voltage 212 at intermediate output 210 is pulled up to Vdd (e.g., 4V). When Data In is logic 1, common source FET2 is on, pulling intermediate output voltage 212 down to Vss (e.g., 1.5V). As shown, when Vss is not needed and the logic state is inverted, the dynamic range 214 of the common source switching section is limited to a maximum of 2.5V instead of 4V.

[0009] Switch point 216 is a point determined by the threshold Vgs (the point at which FET2 stops conducting current) and an additional power supply Vss. In this example, switch point 216 is 1.5V (Vss) plus the Vgs threshold (-0.9V), which is 0.6V. Below 0.6V (the logic 0 range of Data In), FET2 is off. Switch point 216 is effectively set by the value of Vss. The minimum switch point, or minimum Vss, is determined by the upper limit of the logic 0 range of Data In. In this example, logic 0 of Data In is 0 to 0.5V. The maximum value of 0 is less than the switch point. If a higher switch point and a higher Vss are needed (or desired), this would further reduce the dynamic range 214 for a given high power supply Vdd. The combination of switch points and dynamic range can complicate or limit the design to properly switch between various external digital logic such as 5V CMOS, TTL, LVTTL, 2.5V, and 1.8V, which have different high-voltage supplies and different switching regions.

[0010] Referring again to FIG. 2A, level shift section 208 includes a D-mode FET (FET3) configured as a source follower, N series-connected diodes Dn, and a D-mode FET (FET4) configured as a current source. The drain electrode of FET3 is coupled to a high power supply, Vdd. The gate electrode of FET3 is coupled to an intermediate output 210, and the voltage at the source of FET3 tracks the intermediate output voltage 212. The N diodes Dn level-shift this voltage by N diode drops (e.g., N*0.6V) to generate low and high output voltage levels 218 for Data Out 204 at the drain electrode of current source FET4. In another embodiment, diodes Dn and FET4 can be replaced with load resistors. Typically, the low output voltage level for output logic 0 is driven to a low power supply (e.g., ground potential). To achieve this, a diode drop must exceed Vss. In this case, N=3 diodes are used to drive Data Out Logic 0 to ground. This necessarily reduces the output voltage level for Logic 1 by the same amount. As a result, as shown in Figure 2C, the dynamic range 220 of the inverter 200 is further limited, in this case to 1.5V. The inverter cannot support the higher voltage level for logic 1 and still provide the lower voltage level at ground potential for logic 0. Summary of the Invention

[0011] The following is a summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description and claim definitions that are presented later.

[0012] The present invention provides an input circuit for III / VD mode buffer FET logic (BFL) that maximizes the dynamic range provided by a common gate switching section, drives an output level shift section to set the appropriate voltage level to switch the BFL, and decouples the switch point from the dynamic range. Increasing the dynamic range of the high-gain common gate switching section mitigates the impact of noise in the level shift section on degrading noise performance. Decoupling the switch point from the dynamic range allows the switch point to be set to accommodate a range of different voltages in the input logic level without degrading the dynamic range. Unlike typical switch configurations, the common gate input circuit is not inverting.

[0013] This is accomplished in a III / V IC where the common-gate switching section includes a D-mode FET (FET1) configured as a load and another D-mode FET (FET2) configured as a common gate connected in series between a high power supply, Vdd, and a low power supply, Vee1 (usually ground). The gate electrode of FET2 is tied to Vee1, and the source electrode of FET2 is driven by an external digital signal. This eliminates the need for an additional power supply, Vss, thereby maximizing the dynamic range of the section that switches Vdd and Vee1, and decoupling the dynamic range from the switch point.

[0014] The input level shifting section can shift the Data In voltage level applied to the source electrode of FET2 to shift the switch point and / or present a high input impedance. In one embodiment, the level shifting section includes a D-mode FET configured as a source follower, M series-connected diodes, and a D-mode FET configured as a current source. The gate electrode of the source follower presents a high input impedance to the digital input signal, and the M series-connected diodes shift the switch point. In another embodiment, the source follower is omitted, and the digital input signal is directly coupled to the M series-connected diodes to shift the switch point.

[0015] These and other features and advantages of the present invention will be apparent to those skilled in the art from the following detailed description of the preferred embodiment, taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0016] [Figure 1] As previously mentioned, this is a block diagram of a III / V IC including a D-mode BFL and input circuitry that converts external logic signals to voltage levels suitable for driving III / V D-mode FETs. [Figure 2A] As described above, an embodiment of an input inverter including a common source switching section and a source follower level shifter and a dynamic range of switching voltages is shown. [Figure 2B] As described above, an embodiment of an input inverter including a common source switching section and a source follower level shifter and a dynamic range of switching voltages is shown. [Figure 2C] As described above, an embodiment of an input inverter including a common source switching section and a source follower level shifter and a dynamic range of switching voltages is shown. [Figure 3A]1 illustrates a first embodiment of an input inverter including a common gate switching section with its source electrode directly coupled to the input logic signal and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 3B] 1 illustrates a first embodiment of an input inverter including a common gate switching section with its source electrode directly coupled to the input logic signal and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 3C] 1 illustrates a first embodiment of an input inverter including a common gate switching section with its source electrode directly coupled to the input logic signal and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 4A] 1 illustrates a second embodiment of an input inverter including a common gate switching section whose source electrode is coupled to an input logic signal through a high impedance input level shifter, and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 4B] 1 illustrates a second embodiment of an input inverter including a common gate switching section whose source electrode is coupled to an input logic signal through a high impedance input level shifter, and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 4C] 1 illustrates a second embodiment of an input inverter including a common gate switching section whose source electrode is coupled to an input logic signal through a high impedance input level shifter, and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 5A] 1 illustrates a second embodiment of an input inverter including a common gate switching section whose source electrode is coupled to an input logic signal through a high impedance input level shifter, and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 5B]1 illustrates a second embodiment of an input inverter including a common gate switching section whose source electrode is coupled to an input logic signal through a high impedance input level shifter, and a source follower level shifter, and the dynamic range of the switched voltage. [Figure 5C] 1 illustrates a second embodiment of an input inverter including a common gate switching section whose source electrode is coupled to an input logic signal through a high impedance input level shifter, and a source follower level shifter, and the dynamic range of the switched voltage. DETAILED DESCRIPTION OF THE INVENTION

[0017] The present invention provides an input circuit for III / VD mode buffer FET logic (BFL) that maximizes the dynamic range provided by a common-gate switching section, drives a level-shift section to set the appropriate voltage level for switching the BFL, and decouples the switch point from the dynamic range. Increasing the dynamic range of the high-gain common-gate switching section mitigates the impact of noise in the level-shift section on degraded noise performance. Decoupling the switch point from the dynamic range allows the switch point to be set to accommodate a range of different voltages in the input logic level without degrading the dynamic range. Unlike typical switch configurations, the common-gate input circuit is not inverting.

[0018] This is achieved in a III / V IC in which the common-gate switching section includes a D-mode FET (FET1) configured as a load and another D-mode FET (FET2) configured as a common gate connected in series between a high power supply, Vdd, and a low power supply, Vee1 (usually ground). The gate electrode of FET2 is tied to Vee1, and the source electrode of FET2 is driven by an external digital signal. This eliminates the need for an additional power supply, Vss, thereby maximizing the dynamic range of the section that switches Vdd and Vee1, and allowing the dynamic range to be decoupled from the switch point. The input level-shift section shifts the data in to the source electrode of FET2, shifting the switch point and allowing it to present a high input impedance.

[0019] 3A-3C, in an embodiment, input circuit 300 interfaces external digital signals, e.g., standard CMOS levels, e.g., 5V CMOS, TTL, LVTTL, 2.5V, and 1.8V, with a D-mode III / V BFL. In this example, the voltage level of Data In 302 is 0-0.5V for a logic 0 and 2-2.5V for a logic 1. The voltage level of Data Out 304 (which switches the D-mode III / V FET) is approximately 0.2V (ideally 0V at ground potential) for a logic 0 and 2.6V for a logic 1. Non-inverting input circuit 300 includes a common-gate switching section 306 that switches Data In 302 to maximize the dynamic range of the available power supply, and a level-shifting section 308 that sets the appropriate voltage level of Data Out 304.

[0020] Common-gate switching section 306 includes a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common-gate switch connected in series between a high power supply voltage Vdd (e.g., 4 V) and a low power supply voltage Vee (e.g., ground). More specifically, the drain electrode of load FET1 is connected to Vdd, and its gate-source connection is coupled to the drain of common-source FET2 at intermediate output 310. The gate electrode of FET2 is connected to Vee1 (e.g., ground). Data In 302 is routed to the source electrode of common-source FET2. The source electrode presents a low input impedance to an external digital controller, much lower than the impedance seen from the gate electrode. This requires a higher current level to drive the source electrode, which is not a standard practice.

[0021] The gate-source voltage Vgs required to switch the common-gate FET2, specifically a negative Vgs<0.9V, can be achieved without requiring an additional supply voltage on the gate electrode. For example, if Data In is 0.5V, then Vgs=-0.5V, which is insufficient to turn FET2 off, so FET2 remains normally on. If Data In is a logic 1 (2-2.5V), then Vgs is less than -2V, and FET2 is off.

[0022] As shown in FIG. 3B, when Data In is a logic 1, common-gate FET2 is off, no current flows through load FET1, and intermediate output voltage 312 at intermediate output 310 is pulled up to Vdd (e.g., 4V). When Data In is a logic 0, common-gate FET2 is on, pulling intermediate output voltage 312 down to near ground. As shown, the dynamic range 314 of the common-source switching section approximates the rail-to-rail voltage range between the positive power supply Vdd and ground. When Data In's logic 0 voltage is in the range of 0 to 0.5V, common-gate FET2 is not fully on, and output voltage 312 does not fully reach ground.

[0023] Switch point 316 is the point determined by the threshold Vgs (the point at which FET2 stops conducting current). In this example, switch point 316 is 0V (ground potential) plus the Vgs threshold (-0.9V), which is 0.9V. Below 0.9V (the logic 0 range for Data In), FET2 remains on. Switch point 316 is decoupled from ground potential.

[0024] Referring again to FIG. 3A, level shift section 308 includes a D-mode FET (FET3) configured as a source follower, N series-connected diodes Dn, and a D-mode FET (FET4) configured as a current source. The drain electrode of FET3 is coupled to the high power supply Vdd. The gate electrode of FET3 is coupled to the intermediate output 310, and the voltage at the source of FET3 tracks the intermediate output voltage 312. The N diodes Dn level-shift this voltage by N diode drops (e.g., N*0.6V) to generate low and high output voltage levels 318 for Data Out 304 at the drain electrode of current source FET4. N can be 0, 1, or multiple. In another embodiment, diodes Dn and FET4 can be replaced with load resistors. Typically, the low output voltage level for output logic 0 is driven to a low power supply (e.g., ground potential). To achieve this, a diode drop must exceed Vss. In this case, N=3 diodes are used to drive Data Out logic 0 to ground. This necessarily reduces the output voltage level for logic 1 by the same amount. As a result, the dynamic range 320 of the input 300 is 2.6 V, as shown in Figure 2C. For the same supply voltage Vdd, the common-gate input circuit 300 supports a higher dynamic range than a common-source inverter.

[0025] The diodes in III / V ICs can be fabricated as standard pn junction diodes or can be used as D-mode FETs configured as diodes.

[0026] An input level shifter can be placed between Data In and the source electrode of common-gate FET2 to shift the switch point (without affecting the dynamic range of the common-gate switching section) and to present a high input impedance to Data In, reducing the current requirements to drive the input circuit. For brevity, the description of the input circuit will not be repeated and similar reference numerals will be used as for the input circuit shown in Figure 3A.

[0027] 4A-4C, in an embodiment, input circuit 400 includes an input level shifter 402 disposed between Data In 302 and the source electrode of common-gate FET2 to shift the switch point 404 from 0.9V to 2.1V, presenting a high input impedance to Data In 302 (e.g., an external digital controller) and reducing the amount of current required to drive the input circuit. Input level shifter 402 is a source-follower network including a D-mode FET (FET5) having its drain electrode connected to Vdd, a gate electrode driven by Data In, and a source electrode coupled to M series-connected diodes Dm (M is 0, 1, or multiple), and a D-mode FET (FET6) connected to ground potential as a current source and having its drain electrode connected to the source electrode of common-gate FET2. The impedance seen by the gate electrode of FET5 is much higher than the impedance seen by the source electrode of FET2 to the Data In signal and the external digital controller. The source follower helps to maintain signal integrity and its output can drive the low impedance load created by the source of common gate FET2.

[0028] As shown in Figure 4B, M series-connected diodes offset the switch point from the inherent Vgs of FET2 by M*Vdiode. In this case, M=2, and the switch point is 0.9V + 2*0.6 = 2.1V. A logic 0 on Data In puts FET5 into a low-current state, causing the follower output to move toward ground, but not reach ground because FET5 is not fully cutoff. The source voltage of FET2 is low, so FET2 remains on, pulling the intermediate voltage 406 at the intermediate output 310 toward ground. Because switch point 404 has been pushed to 2.1V, a logic 0 on Data In between 0 and 0.5V can turn on common-gate FET2 and pull the intermediate voltage 406 toward ground. A logic 1 at data in increases the current in FET5, raising the potential at the drain of current source FET6, which now raises the voltage at the source electrode of common-gate FET2, turning FET2 off and forcing the intermediate voltage 406 toward the high power supply, Vdd. The number of diodes, M, is selected from zero to several to reinforce the low logic state caused by incomplete shutoff of FET5. The dynamic range 407 of the common-gate switching section generally ranges from the high power supply, Vdd, to ground potential. As shown in FIG. 4C, the output level shifter shifts the low voltage 408 and high voltage 410 for data to approximately 2.6 V, again approximately ground potential. The input level shifter affects the switch point and input impedance, but does not affect the dynamic range 407 of the switching section or the dynamic range 412 of the input circuit.

[0029] 5A-5C, in an embodiment, an input circuit 500 includes an input level shifter 502 disposed between Data In 302 and the source electrode of common-gate FET2, which shifts a switch point 504 from 0.9 V to 2.1 V. The input level shifter 502 includes M series-connected diodes Dm connected to Data In 302 in series with a D-mode FET (FET5) as a current source to ground, whose drain electrode is connected to the source electrode of common-gate FET2.

[0030] As shown in FIG. 4B, a logic 0 at Data In turns off the series-connected diode Dm, and FET5 operates in linear, or low-resistance, mode, keeping the voltage at the source of FET2 low. Common-gate FET2 remains on, pulling the intermediate voltage 506 at the intermediate output 310 toward ground. A logic 1 data signal turns on the series-connected diode, saturating FET5, which increases the voltage at the source electrode of common-gate FET2, turning FET2 off and forcing intermediate voltage 506 to move toward the high power supply, Vdd. This input level shifter configuration provides a lower input impedance during a logic high state, but is more effective at reaching a logic low because the diodes are off. The M series-connected diodes offset the switch point from the intrinsic Vgs of FET2 by M*Vdiode. In this case, M=2, and the switch point is 0.9V + 2*0.6 = 2.1V. As shown in FIG. 5C, the output level shifter shifts the data low voltage 508 and high voltage 510 to approximately 2.6V, which is roughly ground potential, as before.

[0031] Other configurations of input level shifters for offsetting the switch point and / or increasing the input impedance to the input circuit are contemplated within the scope of the present invention. While several illustrative embodiments of the invention have been shown and described, numerous variations and alternative embodiments will occur to those skilled in the art. Such variations and alternative embodiments are contemplated and can be made without departing from the scope of the invention, as defined in the appended claims.

Claims

1. 1. A III / V integrated circuit (III / V IC), comprising: a depletion-mode (D-mode) field-effect transistor (FET) formed on a substrate composed of III / V semiconductor material; 1. An input circuit for silicon CMOS technology having an input configured to receive digital logic signals 0 and 1 as a low input voltage and a high input voltage, respectively, said input circuit comprising: a common gate switching section including a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate switch connected in series between a high power supply Vdd and a low power supply Vee1, the common gate switch remaining on in response to a low input voltage below a switch point and turning off in response to a high input voltage above a switch point, the common gate switching section switching an intermediate output voltage between the gate and source electrodes of FET1 and the drain electrode of FET2 over a dynamic range spanning Vdd to Vee1; and the input circuit including a D-mode FET (FET3) configured as a source follower and an output level shifter including a load configured to shift down the intermediate voltage to low and high output voltages compatible with the switching of the D-mode FET at the circuit output; and one or more buffer FET digital logic circuits coupled to the circuit output, each of the buffer FET digital logic circuits comprising a D-mode FET configuration responsive to digital logic signals 0 and 1 at the low output voltage and the high output voltage to be output; the FET2 has a drain electrode coupled to the gate-source connection of FET1 at the intermediate output where the intermediate voltage is switched, a gate electrode coupled to Vee1, and a source electrode coupled to a circuit input; the nominal switch point is the voltage at the source electrode of FET2 that reaches the negative gate-source voltage Vgs required to turn FET2 off; an input level shifter between the input and the source electrode of FET2 configured to shift the nominal switch point with a positive offset; the input level shifter includes a D-mode FET (FET5) configured as a source follower having a gate electrode coupled to the input, a drain coupled to Vdd, and a source connected through M series-connected diodes to a D-mode FET (FET6) configured as a current source, the gate electrode of FET5 presenting a high input impedance to digital logic signals, and the positive offset being the voltage drop across the M series-connected diodes; The drain electrodes of FET1, FET3, and FET5 are all connected to Vdd. III / V integrated circuits.

2. The III / V integrated circuit of claim 1 , wherein the III / V semiconductor material is selected from one of GaAs, GaN, and InP.

3. 10. The III / V integrated circuit of claim 1, wherein the III / V IC is a monolithic microwave IC (MMIC), and the one or more buffer FET digital logic circuits include one or more of a digital attenuator, a digital phase shifter, an RF amplifier, and an RF switch.

4. The III / V integrated circuit of claim 1, wherein the load of the output level shifter includes N series-connected diodes and a D-mode FET (FET4) configured as a current source.

5. 2. The III / V integrated circuit of claim 1, wherein the low power supply Vee1 is equal to or less than ground potential.

6. 2. The III / V integrated circuit of claim 1, wherein the source electrode of FET2 is directly connected to the input, and the switch point is the voltage at the source electrode of FET2 that reaches the negative gate-source voltage Vgs required to turn FET2 off.

7. The III / V integrated circuit of claim 1 , wherein the input level shifter and the output level shifter are independent.

8. The III / V integrated circuit of claim 1 , wherein the shifted switch point is greater than a downward level shift of the output level shifter.

9. 2. The III / V integrated circuit of claim 1, wherein the input level shifter comprises M series connected diodes between the input and a D-mode FET configured as a current source, wherein in response to a digital logic signal of 0, the M series connected ones are turned off and conduct no current, presenting a high input impedance, and in response to a digital logic signal of 1, the M series connected diodes are turned on and conduct current, thereby reducing the high input impedance, and the positive offset is the voltage drop across the M series connected diodes.

10. 1. A III / V integrated circuit (III / V IC), comprising: a depletion-mode (D-mode) field-effect transistor (FET) formed on a substrate composed of a III / V semiconductor material selected from GaAs, GaN, and InP; 1. An input circuit having an input configured to receive digital signals 0 and 1 as a low input voltage and a high input voltage, respectively, compatible with Si CMOS technology, said input circuit comprising: a common gate switching section including: a D-mode FET (FET1) configured as a load coupled to a high power supply voltage Vdd; and a D-mode FET (FET2) configured as a common gate switch having a drain electrode connected to a gate-source connection of the load at an intermediate output, a gate electrode connected to a ground potential, and a source electrode coupled to a circuit input, the common gate switch remaining on in response to a low input voltage below a switch point and turning off in response to a high input voltage above a switch point to switch an intermediate voltage at the intermediate output connected to the drain electrode of FET2 over a dynamic range spanning Vdd to ground; the input circuit including a D-mode FET (FET3) configured as a source follower and an output level shifter including a load configured to shift down the intermediate voltage to low and high output voltages compatible with the switching of the D-mode FET at the circuit output; and one or more buffer FET digital logic circuits coupled to the circuit output, each of the buffer FET digital logic circuits comprising a D-mode FET configuration responsive to digital logic signals 0 and 1 at the low output voltage and the high output voltage to be output; the FET2 has a drain electrode coupled to the gate-source connection of FET1 at the intermediate output where the intermediate voltage is switched, a gate electrode coupled to Vee1, and a source electrode coupled to a circuit input; the nominal switch point is the voltage at the source electrode of FET2 that reaches the negative gate-source voltage Vgs required to turn FET2 off; an input level shifter between the input and the source electrode of FET2 configured to shift the nominal switch point with a positive offset; the input level shifter includes a D-mode FET (FET5) configured as a source follower having a gate electrode coupled to the input, a drain coupled to Vdd, and a source connected through M series-connected diodes to a D-mode FET (FET6) configured as a current source, the gate electrode of FET5 presenting a high input impedance to digital logic signals, and the positive offset being the voltage drop across the M series-connected diodes; The drain electrodes of FET1, FET3, and FET5 are all connected to Vdd. The III / V integrated circuit.

11. the nominal switch point is the voltage at the source electrode of FET2 that reaches the negative gate-source voltage Vgs required to turn FET2 off; 11. The III / V integrated circuit of claim 10, further comprising an input level shifter between the input and the source electrode of FET2 configured to shift the nominal switch point with a positive offset.

12. 1. A III / V integrated circuit (III / V IC), comprising: a depletion-mode (D-mode) field-effect transistor (FET) formed on a substrate composed of III / V semiconductor material; an input configured to receive digital signals 0 and 1 as low and high input voltages, respectively, for silicon CMOS technology; and a common gate switching section including a D-mode FET (FET1) configured as a load and a D-mode FET (FET2) configured as a common gate switch connected in series between a high power supply Vdd and a low power supply Vee1, the common gate switching section having a source electrode that remains on in response to a low input voltage below a switch point and turns off in response to a high input voltage above the switch point, switching an intermediate output voltage between the gate electrode and source electrode of FET1 and the drain electrode of FET2 over a dynamic range extending from Vdd to Vee1; the FET2 has a drain electrode coupled to the gate-source connection of FET1 at the intermediate output where the intermediate voltage is switched, a gate electrode coupled to Vee1, and a source electrode coupled to a circuit input; the nominal switch point is the voltage at the source electrode of FET2 that reaches the negative gate-source voltage Vgs required to turn FET2 off; an input level shifter between the input and the source electrode of FET2 configured to shift the nominal switch point with a positive offset; the input level shifter includes a D-mode FET (FET5) configured as a source follower having a gate electrode coupled to the input, a drain coupled to Vdd, and a source connected through M series-connected diodes to a D-mode FET (FET6) configured as a current source, the gate electrode of FET5 presenting a high input impedance to digital logic signals, and the positive offset being the voltage drop across the M series-connected diodes; The drain electrodes of FET1, FET3, and FET5 are all connected to Vdd. III / V integrated circuits.

13. 13. The III / V integrated circuit of claim 12, wherein FET2 has a drain coupled to the gate-source connection of FET1 at an intermediate output where the intermediate voltage is switched, a gate electrode coupled to Vee1, and the source electrode coupled to a circuit input.

14. the nominal switch point is the voltage at the source electrode of FET2 that reaches the negative gate-source voltage Vgs required to turn FET2 off; 13. The III / V integrated circuit of claim 12, further comprising an input level shifter between the input and the source electrode of FET2 configured to shift the nominal switch point with a positive offset.

15. 15. The III / V integrated circuit of claim 14, wherein the input level shifter presents an input impedance to the input that is higher than the impedance looking into the source electrode of FET2.

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