PLL circuit and transmission system

Abstract

A PLL circuit (1) for generating an output clock signal is provided with: a selection circuit (70) for selecting one of a plurality of clock signals as a reference clock signal for the PLL circuit (1); and a control circuit (75) for temporarily reducing the divider ratio of a frequency divider (3) that generates a feedback clock signal with which the reference clock signal is to be compared, when switching the selection of the reference clock signal. For example, the control circuit (75) may temporarily mask a detection result from a phase comparator (40) in the PLL circuit (1) when switching the selection of the reference clock signal.

Description

[Technical Field]

[0001] The present disclosure relates to a PLL circuit and a transmission system capable of switching a reference clock signal. [Background technology]

[0002] Patent Document 1 proposes a PLL (Phase Locked Loop) circuit capable of switching a reference clock signal, in which there is no phase shift between the reference clock signal and the comparison clock signal when the reference clock signal is switched, a stable output is obtained even when the reference clock signal is switched, and the PLL circuit can be realized with a simple configuration. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-243980 Summary of the Invention [Problem to be solved by the invention]

[0004] However, according to Patent Document 1, there are cases where the phase difference between the reference clock signal and the comparison clock signal does not disappear when the reference clock signal is switched, which can cause frequency fluctuations.

[0005] Therefore, an object of the present disclosure is to provide a PLL circuit and a transmission system that suppress frequency fluctuations when switching a reference clock signal. [Means for solving the problem]

[0006] In order to achieve the above object, a PLL circuit according to one aspect of the present disclosure is a PLL circuit that generates an output clock signal, and includes: a selection circuit that selects one of a plurality of clock signals as a reference clock signal for the PLL circuit; and a control circuit that, when switching the selection of the reference clock signal, temporarily reduces a division ratio of a frequency divider that generates a feedback clock signal to be compared with the reference clock signal. The control circuit resets the frequency divider when switching the selection of the reference clock signal, and the period during which the frequency division ratio is temporarily reduced is one cycle or multiple cycles of the feedback clock signal immediately after the reset of the frequency divider is released. .

[0007] Furthermore, a transmission system according to one embodiment of the present disclosure includes the above-described PLL circuit, a converter that converts parallel data into serial data in synchronization with the output clock signal, and a transmission driver that outputs the serial data to a communication line.

[0008] These general or specific aspects may be realized as a system, a method, or an integrated circuit, or may be realized as any combination of a system, a method, or an integrated circuit. [Effects of the Invention]

[0009] According to the PLL circuit and transmission system of the present disclosure, it is possible to suppress frequency fluctuations when switching the reference clock signal. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a PLL circuit according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of the switching circuit in FIG. [Figure 3] FIG. 3 is a circuit diagram showing an example of the configuration of the frequency divider in FIG. [Figure 4] FIG. 4 is a circuit diagram showing an example of the configuration of the synchronization circuit in FIG. [Figure 5] FIG. 5 is a circuit diagram showing an example of the configuration of the phase comparator in FIG. [Figure 6] FIG. 6 is a time chart showing an example of the operation of the frequency divider of FIG. [Figure 7]FIG. 7 is a time chart showing an example of the operation of the PLL circuit according to the embodiment. [Figure 8] FIG. 8 is a circuit diagram showing a modification of the phase comparator of FIG. [Figure 9] FIG. 9 is a circuit diagram showing another modified example of the phase comparator of FIG. [Figure 10] FIG. 10 is a block diagram illustrating an example of a configuration of a transmission system according to an embodiment. [Figure 11] FIG. 11 is a block diagram showing the configuration of a PLL circuit in the prior art. [Figure 12] FIG. 12 is a time chart showing the operation that may occur in the prior art. [Figure 13] FIG. 13 is an explanatory diagram showing frequency fluctuations that can occur in clock switching operations of the prior art. [Figure 14] FIG. 14 is an explanatory diagram showing frequency fluctuations suppressed in clock switching operations. DETAILED DESCRIPTION OF THE INVENTION

[0011] (Findings that formed the basis of this disclosure) The present inventors have found that the following problems occur with the PLL circuit of the prior art described in the "Background Art" section. Fig. 11 is a diagram showing the configuration of a PLL circuit of the prior art. This PLL circuit corresponds to Fig. 1 of Patent Document 1. Fig. 12 is a time chart showing operations that may occur when the reference clock signal in Fig. 11 is switched.

[0012] In Figure 12, the clock switching signal is a signal that instructs switching of the reference clock signal. The reference clock signal is a signal output from the selector to the phase comparator. The comparison clock signal is a signal output from the frequency divider to the phase comparator. The reset signal is a signal output from the timing generator to the frequency divider.

[0013] 12, while the clock switching signal is at low level, clock A is selected as the reference clock signal and the system is in a locked state. After the clock switching signal changes from low to high, the reference clock signal is switched from clock A to clock B.

[0014] The reset signal is asserted (a negative logic pulse is output) at the timing of the first edge of the reference clock signal after switching (the rising edge in Figure 12), clearing the divider counter. The divider counter operation stops for the pulse width of the reset signal (the time it is at L level). A phase difference occurs between the reference clock signal and the comparison clock signal for the duration of this pulse width.

[0015] Even if clock A and clock B have the same frequency, this phase difference is transmitted to the voltage-controlled oscillator VCXCO via the filter, causing frequency fluctuations.

[0016] Furthermore, if the frequency divider is provided with a synchronization circuit that synchronizes the reset release timing (that is, the rising edge timing of the reset pulse) with the output clock signal, the reset release timing will be delayed, further increasing the phase difference.

[0017] Furthermore, as shown in the dashed circle in Figure 12, if the reference clock signal is stopped for a long period during clock switching, unnecessary clock pulses may occur in the comparison clock signal during the stopped period. These unnecessary clock pulses can cause large fluctuations in frequency.

[0018] FIG. 13 is an explanatory diagram showing frequency fluctuations that can occur during clock switching operations in the prior art. As shown in the figure, a frequency fluctuation ΔF occurs when switching the reference clock signal. In an example of a typical PLL circuit prior to Patent Document 1, ΔF can be as large as 30,000 ppm. In the PLL circuit of Patent Document 1, it is thought that the frequency fluctuation ΔF can be reduced to less than 30,000 ppm, but the above-mentioned problems remain.

[0019] In recent years, there has been a demand to further reduce the frequency fluctuation Δf (Δf<<ΔF) when switching the reference clock signal, as shown in Figure 14. For example, the USB4 (Universal Serial Bus 4) standard requires Δf=1400 ppm or less.

[0020] Therefore, the present disclosure provides a PLL circuit and a transmission system that suppress frequency fluctuations when switching a reference clock signal.

[0021] In order to solve the above problem, a PLL circuit according to one embodiment of the present disclosure is a PLL circuit that generates an output clock signal, and includes a selection circuit that selects one of a plurality of clock signals as a reference clock signal for the PLL circuit, and a control circuit that, when switching the selection of the reference clock signal, temporarily reduces the division ratio of a divider that generates a feedback clock signal to be compared with the reference clock signal.

[0022] Furthermore, a transmission system according to one embodiment of the present disclosure includes the above-described PLL circuit, a converter that converts parallel data into serial data in synchronization with the output clock signal, and a transmission driver that outputs the serial data to a communication line.

[0023] These general or specific aspects may be realized as a system, a method, an integrated circuit, or a computer program, or may be realized as any combination of a system, a method, an integrated circuit, or a computer program.

[0024] Hereinafter, an embodiment of a PLL circuit and a transmission system according to an aspect of the present disclosure will be specifically described with reference to the drawings.

[0025] It should be noted that the embodiments described below each illustrate a comprehensive or specific example of the present disclosure. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims that represent the highest concept are described as optional components.

[0026] (Embodiment) [1.1 PLL circuit configuration] First, the configuration of a PLL circuit according to an embodiment will be described.

[0027] 1 is a block diagram showing an example of the configuration of a PLL circuit 1 according to an embodiment. The PLL circuit 1 in the figure includes a voltage-controlled oscillator 2, a frequency divider 3, a phase comparator 40, a low-pass filter 6, and a switching circuit 7.

[0028] The voltage controlled oscillator 2 is called a VCO (Voltage controlled oscillator), and generates an output clock signal VCLK by oscillating at a frequency according to a control voltage from the low-pass filter 6 .

[0029] The frequency divider 3 divides the output clock signal VCLK and outputs the divided result to the phase comparator 40 as a feedback clock signal FB. The frequency divider 3 is reset by the reset signal NRST and enters a stopped state. Furthermore, while the division ratio switching signal CHG is asserted, the frequency divider 3 changes the division ratio and starts division. Here, the division ratio is N when the frequency of the output clock signal VCLK is multiplied by 1 / N. N may be a positive integer.

[0030] The phase comparator 40 detects the phase difference between the reference clock signal REF and the feedback clock signal FB output from the frequency divider 3. To this end, the phase comparator 40 includes, for example, a PFD 4 and a CP5.

[0031] A PFD4 (Phase Frequency Detector 4) detects the phase difference and frequency difference between the reference clock signal REF and the feedback clock signal FB. Hereinafter, the phase difference and the frequency difference will not be particularly distinguished from each other and will simply be referred to as the phase difference.

[0032] CP5 (Charge Pump 5) outputs or inputs a current according to the detected phase difference.

[0033] The low-pass filter 6 outputs a control voltage corresponding to the detected phase difference to the voltage-controlled oscillator 2. Specifically, the low-pass filter 6 generates the control voltage by converting the current output from or input to the CP5 into a smoothed voltage.

[0034] The switching circuit 7 is a circuit that switches the reference clock signal REF in accordance with the clock switching signal, and therefore includes a selection circuit 70 and a control circuit 75.

[0035] The selection circuit 70 selects one of the multiple clock signals in response to the clock switching signal and outputs it to the phase comparator 40 as the reference clock signal REF. In the figure, two examples of the multiple clock signals are shown: a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 may be clock signals with the same frequency but different phases, such as a recovered clock or other clock. Here, the recovered clock is a clock signal recovered in accordance with the timing of changes in the received serial data.

[0036] The control circuit 75 performs control to temporarily reduce the division ratio of the frequency divider 3 when switching the selection of the reference clock signal REF. Furthermore, the control circuit 75 performs control to temporarily mask the detection result of the phase comparator 40 when switching the selection of the reference clock signal REF.

[0037] Temporarily reducing the division ratio in the frequency divider 3 temporarily shortens the period of the feedback clock signal FB. For example, if the first edge timing of the feedback clock signal FB from the frequency divider 3 is slightly delayed relative to the first edge timing of the reference clock signal REF immediately after switching, it is possible to match the edge timing of the next period of both the reference clock signal REF and the feedback clock signal FB. As a result, it is possible to suppress frequency fluctuations in the output clock signal VCLK caused by switching the reference clock signal REF.

[0038] Regarding the masking control, when switching the selection of the reference clock signal, it is possible that an extra clock pulse of one of the reference clock signal and the feedback clock signal is erroneously output, but the phase difference caused by this extra pulse can be masked.

[0039] [1.2 Configuration of switching circuit] Next, a specific configuration of the switching circuit 7 will be described.

[0040] Fig. 2 is a circuit diagram showing an example of the configuration of the switching circuit 7 in Fig. 1. In Fig. 2, the switching circuit 7 includes a selection circuit 70 and a control circuit 75.

[0041] The selection circuit 70 includes a logic circuit 71, an AND circuit 72, an AND circuit 73, and an OR circuit 74. In the figure, the clock switching signal is a signal that indicates one of the first clock signal CLK1 and the second clock signal CLK2 at a low level and indicates the other at a high level.

[0042] The logic circuit 71 receives the clock switching signal, first clock signal CLK1, and second clock signal CLK2, and drives either the first clock selection signal 1SEL or the second clock selection signal 2SEL to a high level, i.e., active. However, immediately after the clock switching signal changes, i.e., immediately after issuing an instruction to switch the reference clock signal REF, the logic circuit 71 provides a non-selection period in which both the first clock selection signal 1SEL and the second clock selection signal 2SEL are temporarily set to a low level. This non-selection period is provided to prevent or prevent the generation of glitch noise from the OR circuit 74 due to the switching of the reference clock signal REF. Here, a glitch is an unintended, short, whisker-like pulse. Furthermore, if this pulse adversely affects subsequent circuits, it is called glitch noise.

[0043] The AND circuit 72 outputs the logical AND of the first clock signal CLK1 and the first clock selection signal 1SEL. That is, the AND circuit 72 outputs the first clock signal CLK1 when the first clock selection signal 1SEL is at a high level, and outputs a low level without outputting the first clock signal CLK1 when the first clock selection signal 1SEL is at a low level.

[0044] The AND circuit 73 outputs the logical AND of the second clock signal CLK2 and the second clock selection signal 2SEL. That is, when the second clock selection signal 2SEL is at a high level, the AND circuit 73 outputs the second clock signal CLK2, and when the second clock selection signal 2SEL is at a low level, the AND circuit 73 does not output the second clock signal CLK2 but outputs a low level.

[0045] The OR circuit 74 outputs the logical sum of the output of the AND circuit 72 and the output of the switching circuit 7. The OR circuit 74 outputs one of the first clock signal CLK1 and the second clock signal CLK2 as the reference clock signal REF. However, during the non-selection period, the OR circuit 74 does not output either the first clock signal CLK1 or the second clock signal CLK2, but outputs a low level.

[0046] The control circuit 75 includes an XOR circuit 76, a flip-flop 77, a flip-flop 78, and an inversion circuit 79. As a result, the control circuit 75 generates various control signals for performing control to temporarily reduce the division ratio and control to temporarily mask the detection result of the phase comparator 40.

[0047] The XOR circuit 76 performs an exclusive OR operation on the first clock selection signal 1SEL and the second clock selection signal 2SEL. The output of the XOR circuit 76 is input to the reset terminals of the flip-flops 77 and 78. As a result, the XOR circuit 76 resets the flip-flops 77 and 78 when both the first clock selection signal 1SEL and the second clock selection signal 2SEL become low level. In other words, the XOR circuit 76 resets the flip-flops 77 and 78 during the non-selection period, and releases the reset state when either the first clock selection signal 1SEL or the second clock selection signal 2SEL becomes high level. The XOR circuit 76 may be substituted with an OR circuit.

[0048] A high level is always input to the D input terminal of the flip-flop 77. The reference clock signal REF is input to the clock input terminal of the flip-flop 77. The output signal of the XOR circuit 76 is input to the reset input terminal of the flip-flop 77. As a result, the Q output terminal of the flip-flop 77 changes from high to low at the start of the non-selection period, and changes to high at the first rising edge of the reference clock signal REF after the non-selection period ends. This signal at the Q output terminal is output to the frequency divider 3 as the reset signal NRST.

[0049] The D input terminal of flip-flop 78 is connected to the Q output terminal of flip-flop 77, and receives the reset signal NRST. The inverted clock input terminal of flip-flop 78 receives the reference clock signal REF. The reset input terminal of flip-flop 78 receives the output signal of XOR circuit 76. As a result, the Q output terminal of flip-flop 78 changes from high to low at the start of the non-selection period, and at the first falling edge of the reference clock signal REF after the end of the non-selection period, flip-flop 78 receives the reset signal NRST from the D input terminal and outputs it from the Q output terminal. The signal at this Q output terminal is output to phase comparator 40 as mask signal NMSK.

[0050] The inverting circuit 79 inverts the mask signal NMSK and outputs the inverted signal to the frequency divider 3 as the frequency division ratio switching signal CHG.

[0051] The operations performed by the various signals in FIG. 2 will be described later with reference to FIG.

[0052] [1.3 Divider Configuration] Next, a more specific configuration of the frequency divider 3 will be described.

[0053] Fig. 3 is a circuit diagram showing an example of the configuration of the frequency divider 3 in Fig. 1. Fig. 4 is a circuit diagram showing an example of the configuration of the synchronization circuit 30 in Fig. 3.

[0054] 3, the frequency divider 3 includes a synchronization circuit 30 and a counter-type frequency divider circuit 31. The counter-type frequency divider circuit 31 includes a counter 32 and a comparator 33.

[0055] The synchronization circuit 30 is a circuit that synchronizes the reset signal NRST with the output clock signal VCLK, and therefore includes an inverting circuit 34, a flip-flop 35, and a flip-flop 36 in the configuration example of FIG.

[0056] The inverter circuit 34 inverts the output clock signal VCLK and outputs the inverted signal to the clock input terminals of the flip-flops 35 and 36 .

[0057] The flip-flop 35 takes in and holds the reset signal NRST at the rising edge of the inverted signal from the inverting circuit 34 (that is, at the falling edge of the output clock signal VCLK), and outputs the held signal from the Q output terminal.

[0058] The flip-flop 36 receives and holds the signal from the Q output terminal of the flip-flop 35 at the rising edge of the inverted signal from the inversion circuit 34 (i.e., at the falling edge of the output clock signal VCLK), and outputs the held signal from the Q output terminal. The signal output from the Q output terminal of the flip-flop 36 is output to the counter 32 as the counter reset signal NRES. The counter reset signal NRES is a signal obtained by delaying the reset signal NRST by two clock periods of the output clock signal VCLK. In other words, the counter reset signal NRES is a signal obtained by synchronizing the reset signal NRST with the output clock signal VCLK.

[0059] The counter-type frequency divider circuit 31 divides the output clock signal VCLK by N and outputs the feedback clock signal FB. The counter-type frequency divider circuit 31 includes a counter 32 and a comparator 33 in the example of FIG.

[0060] The counter 32 counts the number of clock pulses of the output clock signal VCLK.

[0061] Comparator 33 compares the count value of counter 32 with division ratio N and initializes counter 32 when they match. When division ratio switching signal CHG is asserted, comparator 33 determines whether the count value matches the division ratio (Nm) specified by division ratio setting signal mSET. Here, m is an integer corresponding to the time difference between the edge timing of reference clock signal REF immediately after switching and the start timing of frequency divider 3 immediately after reset is released. In the configuration example of FIG. 3, m corresponds to the time difference between the rising edge of reset signal NRST and the rising edge of counter reset signal NRES, and corresponds to two clocks of output clock signal VCLK (m=2). In this way, frequency divider 3 performs frequency division operation at division ratio (Nm) when division ratio switching signal CHG is asserted.

[0062] [1.4 Phase comparator configuration] Next, a more specific configuration of the phase comparator 40 will be described.

[0063] Fig. 5 is a circuit diagram showing an example of the configuration of the phase comparator 40 in Fig. 1. The phase comparator 40 in Fig. 5 includes a PFD 4 and a CP5.

[0064] The PFD 4 includes a flip-flop 41, a flip-flop 42, and a NAND circuit 43.

[0065] In the reset state and immediately after the reset is released, the flip-flop 41 outputs a low level from the Q output terminal. In states other than the reset state, the flip-flop 41 receives and holds a high level at the D input terminal at the timing of the rising edge of the reference clock signal REF, and outputs a high level from the Q output terminal as an UP signal.

[0066] In the reset state and immediately after the reset is released, the flip-flop 42 outputs a low level from the Q output terminal. In states other than the reset state, the flip-flop 42 receives and holds a high level at the D input terminal at the timing of the rising edge of the feedback clock signal FB, and outputs a high level from the Q output terminal as a DOWN signal.

[0067] The NAND circuit 43 outputs an output signal, which is the inverted logical product of the UP signal, the DOWN signal, and the mask signal NMSK, to the reset input terminal of the flip-flop 41 and the reset input terminal of the flip-flop 42. When the mask signal NMSK is at a high level (i.e., not masked), the NAND circuit 43 does not reset the flip-flops 41 and 42 unless both the UP signal and the DOWN signal are at a high level, and resets the flip-flops 41 and 42 unless both the UP signal and the DOWN signal are at a high level. As a result, when the rising edge of the reference clock signal REF is earlier than the rising edge of the feedback clock signal FB, a pulse width corresponding to the phase difference appears in the UP signal, and a negligibly short pulse appears in the DOWN signal. Conversely, when the rising edge of the reference clock signal REF is later than the rising edge of the feedback clock signal FB, a negligibly short pulse appears in the UP signal, and a pulse width corresponding to the phase difference appears in the DOWN signal. On the other hand, when the mask signal NMSK is at a low level, the flip-flops 41 and 42 are reset. Therefore, when the mask signal NMSK is at a low level, both the UP signal and the DOWN signal are masked.

[0068] The CP5 includes a current source 51, a switch 52, a switch 53, and a current source .

[0069] The current source 51 and the switch 52 supply the current ICP corresponding to the pulse width of the UP signal to the low-pass filter 6. At this time, the current ICP flows from the CP5 to the low-pass filter 6. As a result, the UP signal has the effect of increasing the frequency of the output clock signal VCLK via the low-pass filter 6 and the voltage-controlled oscillator 2.

[0070] The switch 53 and the current source 54 draw a current ICP corresponding to the pulse width of the DOWN signal from the low-pass filter 6. At this time, the current ICP flows from the low-pass filter 6 to the CP5. As a result, the DOWN signal has the effect of lowering the frequency of the output clock signal VCLK via the low-pass filter 6 and the voltage-controlled oscillator 2.

[0071] [2. Operation] The operation of the PLL circuit 1 according to the embodiment configured as above will now be described.

[0072] First, an example of the operation of the frequency divider 3 will be described.

[0073] Figure 6 is a time chart showing an example of the operation of the frequency divider of Figure 3. The figure shows the division ratio switching signal CHG, the feedback clock signal FB, and the timing of switching the division ratio. Assume that a rising edge of the feedback clock signal FB occurs at the count start timing of the frequency division operation.

[0074] As shown at times t0 and t3, when the division ratio switching signal CHG is at a low level at the count start timing, the division operation starts with a division ratio of N.

[0075] As shown at times t1 and t2, when the division ratio switching signal CHG is at a high level at the start of counting, the frequency division operation starts with a division ratio (Nm), where m is specified by the division ratio setting signal mSET.

[0076] In this way, the frequency divider 3 switches the frequency division ratio depending on the level of the frequency division ratio switching signal CHG at the count start timing.

[0077] If the frequency divider 3 is reset during the period from time t0 to t1, the frequency dividing operation is stopped during the period from time t0 to t1, and no pulse of the feedback clock signal FB is output.

[0078] Next, an example of the operation of the PLL circuit 1 will be described.

[0079] FIG. 7 is a time chart showing an example of the operation of the PLL circuit according to the embodiment.

[0080] During the period from time t1 to t5, the first clock signal CLK1 is selected by the selection circuit 70 and output as the reference clock signal REF. During this period, the reference clock signal REF and the feedback clock signal FB are in a locked state in phase, and both the UP signal and the DOWN signal have negligibly short pulse widths.

[0081] At time t4, the clock switching signal changes from low to high, indicating that the reference clock signal REF should be switched from the first clock signal CLK1 to the second clock signal CLK2.

[0082] In response to the change in the clock switching signal during the period from time t5 to t7, the selection circuit 70 sets both the first clock selection signal 1SEL and the second clock selection signal 2SEL to low level, which is a non-selection period.

[0083] At time t5, both the first clock selection signal 1SEL and the second clock selection signal 2SEL change to low level, and the output of the reference clock signal REF stops. The control circuit 75 activates the mask signal NMSK, the reset signal NRST, and the division ratio switching signal CHG.

[0084] During the period from time t5 to t7, i.e., the non-selection period, the reference clock signal REF is not output. After time t7 when the second clock selection signal 2SEL is asserted, the second clock signal CLK2 is selected and output.

[0085] During the period from time t5 to t10, the mask signal NMSK becomes active. During this period, neither the UP signal nor the DOWN signal is masked in the phase comparator 40 and is not output. As a result, the UP signal indicating the phase difference from time t8 to t9 is masked. The very short DOWN signal between times t8 and t9 is also masked.

[0086] During the period from time t5 to time t8, the reset signal NRST becomes active, causing the frequency divider 3 to stop its frequency division operation.

[0087] During the period from time t5 to t10, the division ratio switching signal CHG becomes active. The division operation of the frequency divider 3 that starts during this period changes the division ratio. In the figure, the division ratio is changed from N to (Nm).

[0088] During the period from time t6 to t9, the counter reset signal NRES becomes active. At time t9, the counter reset signal NRES becomes inactive, and the frequency division operation with the frequency division ratio (Nm) starts.

[0089] At time t9, the frequency divider 3 begins dividing by a division ratio (Nm), generating a rising edge in the feedback clock signal FB. Here, m=2, and m corresponds to the time difference between the rising edge of the reset signal NRST and the rising edge of the counter reset signal NRES. Therefore, at time t11, when the first cycle of the frequency division by a division ratio (Nm) is completed, the phase difference between the reference clock signal REF and the feedback clock signal FB approaches zero. At this point, the PLL circuit 1 is in a locked state, and frequency fluctuations are significantly suppressed.

[0090] At time t11, the division ratio switching signal CHG is not active, so that the division operation with the division ratio N starts.

[0091] At time t12, one cycle of the frequency division operation with a division ratio of N is completed, and the phase difference between the reference clock signal REF and the feedback clock signal FB becomes 0. At this point, the PLL circuit 1 remains locked, and frequency fluctuations are significantly suppressed.

[0092] In this way, in the operation example of FIG. 7, as shown in FIG. 14, it is possible to suppress frequency fluctuations when switching clocks.

[0093] 7 shows an example in which m=2, but m=1 may also be used. When m=1, a phase difference equivalent to one cycle of the output clock signal VCLK remains at time t11 in FIG. 7, and the phase difference is considered to become 0 at time t12. Even in this case, a locked state is achieved at time t12, so frequency fluctuations can be sufficiently suppressed. In this way, m may correspond to the time difference between the rising edge of the reset signal NRST and the rising edge of the counter reset signal NRES, or may correspond to a time shorter than this time difference.

[0094] The phase comparator 40 may have the configuration shown in FIG. 8 or FIG. 9 instead of that shown in FIG. 5. In FIG. 5, the mask signal NMSK indirectly masks the UP signal, the DOWN signal, and the current ICP by resetting the flip-flops 41 and 42. In FIG. 8, the mask signal NMSK directly masks the UP signal and the DOWN signal. In FIG. 9, the mask signal NMSK directly masks the current ICP.

[0095] [3. Transmission System] Next, a transmission system according to an embodiment will be described.

[0096] 10 is a block diagram showing an example of the configuration of a transmission system according to an embodiment of the present invention, which includes a PLL circuit 1, a parallel-serial converter 11, and a transmission driver 12.

[0097] The PLL circuit 1 may have the same configuration as that shown in Fig. 1. For example, one of the first clock signal CLK1 and the second clock signal CLK2 is a recovered clock, and the other is another clock.

[0098] The parallel-serial converter 11 is a shift register that loads parallel data and outputs it as serial data in synchronization with the output clock signal VCLK from the PLL circuit 1 .

[0099] The transmission driver 12 outputs the serial data output from the parallel-serial converter 11 to a communication line.

[0100] As described above, the PLL circuit according to the embodiment is a PLL circuit that generates an output clock signal, and includes a selection circuit that selects one of a plurality of clock signals as a reference clock signal for the PLL circuit, and a control circuit that, when switching the selection of the reference clock signal, temporarily reduces the division ratio of a divider that generates a feedback clock signal that is compared with the reference clock signal.

[0101] This suppresses frequency fluctuations in the output clock signal caused by switching the reference clock signal. Temporarily reducing the division ratio temporarily shortens the period of the feedback clock signal. For example, if the first edge of the feedback clock signal from the frequency divider is slightly delayed relative to the first edge of the reference clock signal immediately after switching, it is possible to synchronize the edge timings of the next periods of both the reference clock signal and the feedback clock signal.

[0102] Here, the control circuit may temporarily mask the detection result of a phase comparator in the PLL circuit when switching the selection of the reference clock signal.

[0103] According to this, if an extra pulse of one of the reference clock signal and the feedback clock signal is erroneously output when the selection of the reference clock signal is switched, the phase difference caused by the extra pulse can be masked. Also, if glitch noise occurs in the reference clock signal when the selection of the reference clock signal is switched, the phase difference caused by the glitch noise can be masked. As a result, frequency fluctuations can be suppressed when the selection of the reference clock signal is switched.

[0104] Moreover, the PLL circuit according to the embodiment includes an oscillator that generates an output clock signal, a frequency divider that divides the output clock signal, a phase comparator that detects the phase difference between a reference clock signal and a feedback clock signal output from the frequency divider, a filter circuit that outputs a control signal to the oscillator according to the detected phase difference, a selection circuit that selects one of a plurality of clock signals and outputs it to the phase comparator as the reference clock signal, and a control circuit that temporarily reduces the division ratio of the frequency divider when switching the selection of the reference clock signal.

[0105] This suppresses frequency fluctuations in the output clock signal caused by switching the reference clock signal. Temporarily reducing the division ratio temporarily shortens the period of the feedback clock signal. For example, if the first edge of the feedback clock signal from the frequency divider is slightly delayed relative to the first edge of the reference clock signal immediately after switching, it is possible to synchronize the edge timings of the next periods of both the reference clock signal and the feedback clock signal.

[0106] Here, the control circuit may reset the divider when switching the selection of the reference clock signal, and the period during which the division ratio is temporarily reduced may be one cycle or multiple cycles of the feedback clock signal immediately after the reset of the divider is released.

[0107] This makes it possible to match the edge timing of the next cycle (or several cycles later) immediately after resetting, for example, when the first edge timing of the feedback clock signal from the frequency divider is slightly delayed relative to the first edge timing of the reference clock signal immediately after switching.

[0108] Here, the control circuit may temporarily change the division ratio from N to (Nm) when switching the selection of the reference clock signal, where N is an integer indicating the division ratio in a locked state before switching the reference clock signal, and m is an integer corresponding to the time difference between the edge timing of the reference clock signal immediately after switching and the start timing of the divider immediately after reset is released.

[0109] This makes it possible to match the edge timing of the next cycle immediately after resetting with the first edge timing of the reference clock signal immediately after switching, thereby significantly suppressing frequency fluctuations.

[0110] Here, the control circuit may output a division ratio switching signal to the frequency divider, and the frequency divider may start dividing the frequency at a small division ratio while the division ratio switching signal is asserted.

[0111] This facilitates the control of temporarily reducing the frequency division ratio.

[0112] Here, the control circuit may temporarily mask the signal indicating the phase difference generated by the phase comparator when switching the selection of the reference clock signal.

[0113] According to this, if an extra pulse of one of the reference clock signal and the feedback clock signal is erroneously output when the selection of the reference clock signal is switched, the phase difference caused by the extra pulse can be masked. Also, if glitch noise occurs in the reference clock signal when the selection of the reference clock signal is switched, the phase difference caused by the glitch noise can be masked. As a result, frequency fluctuations can be suppressed when the selection of the reference clock signal is switched.

[0114] Here, the control circuit may release the mask when the phase difference between the reference clock signal and the feedback clock signal is smaller than a threshold value.

[0115] This allows the effective period of the mask to be optimized.

[0116] Here, the selection circuit may have a stop period in which it stops outputting the reference clock signal when switching the selection of the reference clock signal, and the control circuit may reset the frequency divider during the stop period and release the reset of the frequency divider at the edge timing of the reference clock signal after the stop period ends.

[0117] According to this, the stop period and reset release can prevent the output of an unnecessary reference clock signal when switching the selection of the reference clock signal, thereby reducing the causes of frequency fluctuations.

[0118] Here, the selection circuit may be configured not to output glitch noise when switching the selection of the reference clock signal.

[0119] This makes it possible to reduce glitch noise, which is a cause of frequency fluctuations, when switching the selection of the reference clock signal.

[0120] A transmission system according to an embodiment includes the above PLL circuit, a converter that converts parallel data into serial data in synchronization with the output clock signal, and a transmission driver that outputs the serial data to a communication line.

[0121] In each of the above embodiments, each component may be configured with dedicated hardware, or may be realized by executing a software program suitable for each component. Each component may also be realized by a program execution unit such as a CPU or processor reading and executing a software program recorded in a semiconductor memory or the like.

[0122] While the PLL circuit and transmission system according to one or more aspects of the present disclosure have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects of the present disclosure. [Industrial Applicability]

[0123] The present disclosure is applicable to a PLL circuit that is capable of switching reference clock signals. [Explanation of symbols]

[0124] 1 PLL circuit 2. Voltage Controlled Oscillator 3 frequency divider 4 PFD 5 CP 6 Low-pass filter 7 Switching circuit 11 Parallel-to-serial converter 12 Transmitting Driver 30 Synchronization circuit 31 Counter-type frequency divider circuit 32 counters 33 Comparator 34 Inverter circuit 35, 36, 41, 42, 77, 78 Flip-Flops 40 Phase comparator 43, 43a NAND circuit 44, 45, 52, 53, 55 switches 51, 54 current source 70 Selection circuit 71 Logic Circuits 72, 73 AND circuit 74 OR Circuit 75 Control circuit 76 XOR circuit 79 Inverter Circuit

Claims

1. 1. A PLL circuit for generating an output clock signal, comprising: a selection circuit that selects one of a plurality of clock signals as a reference clock signal for the PLL circuit; a control circuit that temporarily reduces a frequency division ratio of a frequency divider that generates a feedback clock signal to be compared with the reference clock signal when switching the selection of the reference clock signal; the control circuit resets the frequency divider when switching the selection of the reference clock signal; The period during which the division ratio is temporarily reduced is one cycle or multiple cycles of the feedback clock signal immediately after the reset of the frequency divider is released. PLL circuit.

2. The control circuit temporarily masks the detection result of the phase comparator in the PLL circuit when switching the selection of the reference clock signal.

2. The PLL circuit according to claim 1.

3. The PLL circuit further comprises: an oscillator for generating the output clock signal; a phase comparator that detects a phase difference between the reference clock signal and a feedback clock signal output from the frequency divider; a filter circuit that outputs a control signal to the oscillator according to the detected phase difference; Equipped with 2. The PLL circuit according to claim 1.

4. A PLL circuit for generating an output clock signal, comprising: a selection circuit that selects one of a plurality of clock signals as a reference clock signal for the PLL circuit; a control circuit that temporarily reduces a frequency division ratio of a frequency divider that generates a feedback clock signal to be compared with the reference clock signal when switching the selection of the reference clock signal; the control circuit temporarily changes the division ratio from N to (N-m) when switching the selection of the reference clock signal; N is an integer indicating a division ratio in a locked state before switching the reference clock signal, The m is an integer corresponding to the time difference between the edge timing of the reference clock signal immediately after switching and the start timing of the frequency divider immediately after reset is released. PLL circuit.

5. the control circuit outputs a division ratio switching signal to the frequency divider; The frequency divider starts frequency division at a small frequency division ratio while the frequency division ratio switching signal is asserted.

5. The PLL circuit according to claim 1.

6. The control circuit temporarily masks the signal indicating the phase difference generated by the phase comparator when switching the selection of the reference clock signal.

4. The PLL circuit according to claim 3.

7. The control circuit releases the mask when the phase difference between the reference clock signal and the feedback clock signal is smaller than a threshold value.

10. The PLL circuit according to claim 2 or 6.

8. A PLL circuit for generating an output clock signal, comprising: a selection circuit that selects one of a plurality of clock signals as a reference clock signal for the PLL circuit; a control circuit that temporarily reduces a frequency division ratio of a frequency divider that generates a feedback clock signal to be compared with the reference clock signal when switching the selection of the reference clock signal; the selection circuit has a stop period during which the reference clock signal is not output when switching the selection of the reference clock signal; The control circuit resets the frequency divider during the stop period and releases the reset state of the frequency divider at the edge timing of the reference clock signal that occurs at the end of the stop period. PLL circuit.

9. The selection circuit does not output glitch noise when switching the selection of the reference clock signal.

9. The PLL circuit according to claim 1, wherein the PLL circuit comprises: a first input terminal;

10. A PLL circuit according to any one of claims 1 to 4 and 8; a converter that converts parallel data into serial data in synchronization with the output clock signal; a transmission driver that outputs the serial data to a communication line. Transmission system.

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