Semiconductor Devices

Abstract

To provide a technology capable of enhancing performance of a semiconductor device and securing reliability of the semiconductor device.SOLUTION: A semiconductor device includes a plurality of unit cells UC. Each of the plurality of unit cells UC includes: a column region PC1; a column region PC2; a pair of trenches TR formed in an X direction between the column region PC1 and the column region PC2; and a pair of gate electrodes GE formed respectively in the pair of trenches TR via gate insulation films (GI). The pair of trenches TR and the pair of gate electrodes GE extend in a Y direction in a plan view. A width (L1) of the column region PC1 in the Y direction is larger than a width (L2) of the column region PC2 in the X direction. A plurality of column regions PC1 are formed while being apart from each other along the Y direction.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a column region below a body region and a method for manufacturing the same. [Background technology]

[0002] In semiconductor devices such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), a PN junction structure known as a superjunction structure (SJ structure) is used to improve breakdown voltage. In the case of n-type MOSFETs, by arranging p-type column regions two-dimensionally within the n-type drift region, the area around the column regions is depleted, improving breakdown voltage.

[0003] For example, Patent Document 1 proposes a multi-trench SJ structure in which one unit cell is provided with a pair of trench gates. Patent Document 1 aims to reduce the normalized on-resistance (Rsp) while suppressing increases in manufacturing variations by not providing a column region between the pair of trench gates. Patent Document 1 also discloses arranging multiple column regions formed around the pair of trench gates in a staggered pattern. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-7129 Summary of the Invention [Problem to be solved by the invention]

[0005] One possible method for further reducing the on-resistance and improving the performance of semiconductor devices is to increase the impurity concentration in the drift region to lower its resistance. However, in this case, if there is variation in the dimensions of the column region, the variation in breakdown voltage also increases. Therefore, it is easy to manufacture semiconductor devices with low reliability, so lowering the resistance of the drift region is not suitable for mass production.

[0006] The main object of the present application is to provide a technology that can improve the performance of a semiconductor device and ensure the reliability of the semiconductor device by reducing the on-resistance without lowering the resistance of the drift region. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0007] A brief summary of a representative embodiment of the present invention will be given below.

[0008] A semiconductor device according to one embodiment includes a plurality of unit cells. Each of the plurality of unit cells includes: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type formed on the surface of the drift region; a source region of the first conductivity type formed on the surface of the body region; a first column region of the second conductivity type and a second column region of the second conductivity type formed in the drift region below the body region and spaced apart from each other in a first direction in a plan view; a pair of trenches formed in the drift region between the first column region and the second column region in the first direction so that their bottoms reach positions deeper than the body region; and a pair of gate electrodes formed in the pair of trenches with gate insulating films interposed therebetween. Here, the pair of trenches and the pair of gate electrodes extend in a second direction perpendicular to the first direction in a plan view. The width of the first column region in the second direction is wider than the width of the first column region in the first direction. The first column regions are formed spaced apart from each other along the second direction.

[0009] A semiconductor device according to one embodiment includes a plurality of unit cells, each of which includes: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type formed on a surface of the drift region; a source region of the first conductivity type formed on a surface of the body region; a first column region of the second conductivity type and a second column region of the second conductivity type formed in the drift region so as to be located below the body region and spaced apart from each other in a first direction in a plan view; a pair of trenches formed in the drift region so that their bottoms reach positions deeper than the body region and formed between the first column region and the second column region in the first direction; and a pair of gate electrodes formed in the pair of trenches with gate insulating films interposed therebetween. Here, the pair of trenches and the pair of gate electrodes extend in a second direction perpendicular to the first direction in a planar view, the first column regions are formed at a distance from one another along the second direction, the second column regions are formed at a distance from one another along the second direction, the first column regions and the second column regions are arranged in a staggered pattern in a planar view, and a portion of one first column region and a portion of one second column region are adjacent to one another in the first direction. [Effects of the Invention]

[0010] According to one embodiment, the performance of the semiconductor device can be improved and the reliability of the semiconductor device can be ensured. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 3] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 4]1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 5] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 6] 1 is a plan view of a main part of a semiconductor device according to a first embodiment. [Figure 7] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] FIG. 10 is a plan view of a main part showing a semiconductor device according to a second embodiment. [Figure 13] 1 is a plan view of a main part of a semiconductor device according to a first study example. [Figure 14] FIG. 10 is a plan view of a main part showing a semiconductor device in Study Example 2. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0013] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0014] (Embodiment 1) A semiconductor device 100 according to the first embodiment will be described below with reference to Figures 1 to 4. Figure 1 is a plan view of a semiconductor chip which is the semiconductor device 100.

[0015] 1, most of the semiconductor device 100 is covered with a source wiring SW, and a gate wiring GW is formed around the source wiring SW. Although not shown here, the source wiring SW and gate wiring GW are covered with a protective film PIQ. Openings are provided in parts of the protective film PIQ, and the source wiring SW and gate wiring GW exposed in the openings become source pads and gate pads. External connection members such as wire bonding or clips (copper plates) are connected to the source pads and gate pads, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring substrate.

[0016] 1 is a region where main semiconductor elements such as power MOSFETs are formed. The termination region 2A shown in Fig. 1 is a region that surrounds the periphery of the cell region 1A and is located on the periphery of the semiconductor device 100.

[0017] <Structure of semiconductor device> Fig. 2 is an enlarged plan view of a main portion of a cell region 1A shown in Fig. 1. Fig. 3 is an enlarged plan view of a main portion of the periphery of a termination region 2A shown in Fig. 1. Fig. 4 is a cross-sectional view taken along line AA shown in Fig. 2.

[0018] 2, the semiconductor device 100 of the first embodiment includes a plurality of unit cells UC in a cell region 1A, and each unit cell UC has a multi-trench SJ structure. Two unit cells UC adjacent to each other in the X direction are arranged so as to be folded back while sharing one of the column regions PC1 and PC2.

[0019] 4 shows the cross-sectional structure of one unit cell UC of the semiconductor device 100. The semiconductor substrate SUB is made of, for example, n-type silicon and has a drift region NV made of an n-type semiconductor layer. In this example, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may also be a stacked structure of an n-type silicon substrate and a semiconductor layer grown on the silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked structure will also be described as the semiconductor substrate SUB.

[0020] A p-type body region is formed on the surface of the drift region NV. An n-type source region NS is formed on the surface of the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0021] In the drift region NV, p-type column regions PC1 and PC2 are formed to be located below the body region PB. The column regions PC1 and PC2 are physically separated from the body region PB in the Z direction. The column regions PC1 and PC2 have a higher impurity concentration than the body region PB.

[0022] A pair of trenches TR are formed in the drift region NV so that their bottoms reach a position deeper than the body region PB. A pair of gate electrodes GE are formed in the pair of trenches TR, with gate insulating films GI interposed therebetween. The gate insulating films GI are, for example, silicon oxide films, and the gate electrodes GE are, for example, polycrystalline silicon films doped with n-type impurities.

[0023] An interlayer insulating film IL is formed on the semiconductor substrate SUB so as to cover the pair of gate electrodes GE. A pair of holes CH1 and CH2 are formed in the interlayer insulating film IL. The pair of holes CH1 and CH2 penetrate the interlayer insulating film IL and the source region NS so that their bottoms are located in the body region PB. Although not shown here, a hole CH3 shown in FIG. 3 is formed in the interlayer insulating film IL in the termination region 2A. The hole CH3 is located above the gate electrode GE.

[0024] At the bottom of each of the pair of holes CH1 and CH2, a high-concentration region PR having an impurity concentration higher than that of the body region PB is formed in the body region PB.

[0025] A source wiring SW is formed on the interlayer insulating film IL to fill the pair of holes CH1 and CH2. The source wiring SW is electrically connected to the source region NS, the body region PB, and the heavily doped region PR and supplies a source potential to these. Although not shown here, a gate wiring GW is also formed on the interlayer insulating film IL to fill the hole CH3. The gate wiring GW is electrically connected to the gate electrode GE and supplies a gate potential to the gate electrode GE. The source wiring SW and the gate wiring GW are made of, for example, a barrier metal film such as a titanium nitride film and a main conductive film such as an aluminum film.

[0026] A protective film PIQ, such as a polyimide film, is formed on the source wiring SW and the gate wiring GW.

[0027] An n-type drain region ND and a drain electrode DE are formed on the back surface of the semiconductor substrate SUB. The n-type drain region ND has a higher impurity concentration than the drift region NV. The drain electrode DE is electrically connected to the drain region ND and supplies a drain potential to the drain region ND. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film made by appropriately stacking these metal films.

[0028] The semiconductor device 100 can be applied to, for example, a high-side MOSFET and a low-side MOSFET included in a DC / DC converter. When a DC / DC converter is used as a motor drive circuit, the gate electrode GE can be short-circuited to the source wiring SW to use the low-side MOSFET as a diode. Here, a voltage Vds is applied between the source and drain of the diode MOSFET due to the electromotive force generated by the motor (inductance), causing a change in output capacitance and a reverse recovery current. If the output capacitance is highly dependent on the voltage Vds, a sudden reverse recovery current occurs, which manifests as noise. While incorporating a snubber circuit (MIM capacitor) or the like to reduce this noise is considered, the provision of a snubber circuit presents a problem in that it limits the high-speed operation of the MOSFET.

[0029] Here, the column regions PC1 and PC2 in the first embodiment are physically separated from the body region PB. Therefore, a source potential is not applied to the column regions PC1 and PC2, and the column regions PC1 and PC2 have a floating structure. Although the column regions PC1 and PC2 may be physically in contact with the body region PB, it is more preferable that the column regions PC1 and PC2 have a floating structure.

[0030] In the case of a floating structure, the depletion layers generated from the column regions PC1 and PC2 and the body region PB are separated during thermal equilibrium (voltage Vds = 0V). Therefore, compared to when the column regions PC1 and PC2 are physically connected to the body region PB, it is possible to mitigate sudden changes in output capacitance during positive bias (voltage Vds > 0V). This makes it possible to reduce noise without incorporating a snubber circuit.

[0031] 2, in the cell region 1A, the column region PC1 and the column region PC2 are adjacent to each other and spaced apart in the X direction in a plan view. In the first embodiment, a plurality of column regions PC1 and a plurality of column regions PC2 are formed. The plurality of column regions PC1 are formed at intervals from each other along the Y direction. Similarly, the plurality of column regions PC2 are also formed at intervals from each other along the Y direction.

[0032] The pair of trenches TR and the pair of gate electrodes GE extend in the Y direction and are formed between the column region PC1 and the column region PC2 in the X direction. The pair of holes CH1 each extend in the Y direction. One hole CH1 is provided at a position overlapping the column region PC1 in a plan view, and the other hole CH1 is provided at a position overlapping the column region PC2 in a plan view. The hole CH2 extends in the Y direction and is formed between the pair of gate electrodes GE in the X direction. In the unit cell UC of the first embodiment, the pair of trenches TR are each arranged closer to the hole CH2 than to the hole CH1 in the X direction.

[0033] 3, in the termination region 2A, the column region PC1 and the column region PC2 are not divided into multiple pieces, but extend toward the periphery of the semiconductor device 100. In the termination region 2A, a pair of trenches TR are connected to each other, and a pair of gate electrodes GE are also connected to each other. A hole CH3 is arranged so as to overlap the connection point of the gate electrodes GE. A gate wiring GW is buried in the hole CH3.

[0034] Although a pair of trenches TR and a pair of gate electrodes GE of one unit cell UC are connected here, the trenches TR and gate electrodes GE of a plurality of unit cells UC adjacent to each other may be connected together.

[0035] Furthermore, a plurality of column regions PC3 are formed in the termination region 2A. The plurality of column regions PC3 are formed along the outer periphery of the semiconductor device 100 and surround the cell region 1A. That is, although FIG. 3 shows the case where the plurality of column regions PC3 extend in the X direction, the plurality of column regions PC3 also extend in the Y direction. The impurities and impurity concentrations constituting the column region PC3 are the same as those of the column regions PC1 and PC2.

[0036] <Study example and main features of the first embodiment> 13 and 14, the following describes Study Examples 1 and 2, which were studied by the present inventors. Then, the main features of the first embodiment are described using Fig. 13 and 14. Note that Fig. 13, Fig. 14, and Fig. 6 show a state in which the depletion layer 10 has sufficiently expanded from each column region.

[0037] As shown in FIG. 13, in Study Example 1, the column region PC4 has a striped shape (extending in the Y direction). To reduce the on-resistance and improve the performance of the semiconductor device 100, it is conceivable to increase the impurity concentration of the drift region NV and reduce the resistance of the drift region NV. However, in this case, if there is variation in the dimensions of the column region, the increase in the impurity concentration of the drift region NV will also increase the variation in the breakdown voltage. This poses a problem in that it becomes easier to manufacture semiconductor devices 100 with low reliability.

[0038] Furthermore, electrons flow (current path) between the two striped column regions PC4 from the source region NS through the drift region NV to the drain region ND. Here, because the column regions PC4 extend in the Y direction, the current path tends to concentrate at a specific location.

[0039] Study Example 2 was studied by the present inventors with reference to Patent Document 1, with the aim of reducing the on-resistance more than Study Example 1 without reducing the resistance of the drift region NV. As shown in Fig. 14, in Study Example 2, the column region PC5 is not striped, but is divided into multiple dots. Each of the multiple column regions PC5 is approximately square and arranged in a staggered pattern.

[0040] In addition, the impurities and impurity concentrations constituting the column regions PC4 and PC5 in the study examples 1 and 2 are the same as those of the column regions PC1 and PC2.

[0041] Dividing the column region PC5 into multiple regions alleviates current path concentration compared to Study Example 1. In other words, the current paths can be substantially increased, thereby reducing the on-resistance. However, simply dividing the column region PC5 into multiple regions and arranging multiple column regions PC5 results in some areas not being depleted, as shown in FIG. 14. This results in a problem of reduced breakdown voltage and reduced reliability of the semiconductor device 100.

[0042] One possible method for eliminating non-depleted areas is to expand the planar dimensions of each column region PC5 in the X and Y directions and move each column region PC5, for example, close to the vicinity of directly below the trench TR. In this case, however, although the breakdown voltage can be improved, it becomes difficult to improve the on-resistance.

[0043] The semiconductor device 100 of the first embodiment has been devised in consideration of the problems of the study examples 1 and 2. The main features of the first embodiment will be described below with reference to FIGS.

[0044] 5 and 6, in the first embodiment, a plurality of column regions PC1 and a plurality of column regions PC2 are formed spaced apart from each other along the Y direction. This is similar to the second study example, but in the first embodiment, some ingenuity has been put into the planar dimensions and arrangement intervals of the plurality of column regions PC1 and the plurality of column regions PC2.

[0045] The relationship between them will be explained below with reference to Fig. 5. Note that, although the width L1, width L2, and distance L3 will be explained below using the column region PC1 as a representative example, the same applies to the column region PC2.

[0046] In the first embodiment, the width L1 of the column region PC1 in the Y direction is wider than the width L2 of the column region PC1 in the X direction. Furthermore, the distance L3 between the column regions PC1 is shorter than the width L1. The width L1 is at least twice the width L2, and is, for example, 1.5 to 3 μm. The width L2 is, for example, 0.4 to 0.6 μm. The distance L3 is, for example, 1.0 to 1.4 μm.

[0047] Dividing the column region PC1 into multiple regions and setting an appropriate distance L3 between the multiple column regions PC1 alleviates the concentration of the current path. That is, the current path can be substantially increased, thereby reducing the on-resistance. Furthermore, widening the width L1 of the column region PC1 along the extension direction of the trench TR can suppress the risk of non-depleted areas occurring, as in Study Example 2.

[0048] The column regions PC1 and the column regions PC2 are arranged in a staggered pattern in plan view. Furthermore, a portion of one column region PC1 and a portion of one column region PC2 are adjacent to each other in the X direction. In FIG. 5, the distance between these adjacent regions is shown as distance L4 and distance L5. Distance L4 and distance L5 are, for example, 0.3 to 0.5 μm each. Distance L4 and distance L5 are preferably the same value, but may be different values.

[0049] The above-mentioned adjacency relationship between column region PC1 and column region PC2 can also be expressed as follows. For example, in cell region 1A, when an imaginary straight line VSL is drawn along the X direction, the imaginary straight line VSL always passes through column region PC1, column region PC2, or both. That is, there are cases where the imaginary straight line VSL passes through only one column region PC1, or where the imaginary straight line VSL passes through only one column region PC2, or where the imaginary straight line VSL passes through one column region PC1 and one column region PC2.

[0050] 6, dividing the column region PC1 into multiple parts results in the presence of a location where the depletion layer 10 does not sufficiently extend from between two column regions PC1 toward the trench TR. This is also the case in study example 2 of FIG. 14, but by not only adopting a staggered arrangement but also appropriately setting the distances L4 and L5, the depletion in that location can be compensated for by the depletion layer 10 from the column region PC2.

[0051] 5, the pitch of the unit cells UC is indicated as distance L6, the distance between the column region PC1 and the column region PC2 in the X direction is indicated as distance L7, and the width of each of the pair of trenches TR in the X direction is indicated as width L8. The distance L6 is, for example, 1.6 to 2.0 μm. The distance L7 is, for example, 1.1 to 1.5 μm. The width L8 is, for example, 0.2 to 0.4 μm. The relationship between these and the distance L3 by which the plurality of column regions PC1 are spaced apart from one another will be described.

[0052] When the trench TR is shallow, it is necessary to deplete the drift region NV located at the bottom of the trench TR as well. Therefore, it is preferable that the relationship "distance L3 < distance L7" is satisfied. Furthermore, when the trench TR is very deep, it is preferable that the distance L3 is longer than the value obtained by subtracting the width L8 of each of the pair of trenches TR from the distance L7. In other words, it is preferable that the relationship "distance L7-2 × width L8 < distance L3" is satisfied.

[0053] To summarize the above, in the first embodiment, the column regions PC1 and PC2 are divided into a plurality of regions, thereby alleviating the concentration of the current paths compared to the first study example. Therefore, the current paths can be substantially increased, and the on-resistance can be reduced without reducing the resistance of the drift region NV. On the other hand, the overall expansion of the depletion layer 10 can be made substantially the same as in the first study example, and therefore a sufficient breakdown voltage can be ensured. That is, according to the first embodiment, the performance of the semiconductor device 100 can be improved and the reliability of the semiconductor device 100 can be ensured.

[0054] <Method of manufacturing a semiconductor device> A method for manufacturing the semiconductor device 100 in the first embodiment will be described below with reference to Figures 7 to 11. Figures 7 to 11 are cross-sectional views taken along line AA in Figure 2, similar to Figure 4, and show steps for manufacturing one unit cell UC.

[0055] As shown in FIG. 7, first, a semiconductor substrate SUB is prepared, which has a drift region NV made of an n-type semiconductor layer. Next, a pair of trenches TR are formed in the drift region NV using photolithography and dry etching. Next, p-type impurities such as boron (B) are introduced using photolithography and ion implantation to form p-type column regions PC1 and PC2 in the drift region NV. Note that the column region PC3 shown in FIG. 3 is also formed in the termination region 2A using the same process as the process for forming the column regions PC1 and PC2.

[0056] Furthermore, in the first embodiment, in comparison with the first and second study examples, the column regions PC1 to PC3 can be formed by simply changing the mask pattern, and therefore, there is no need to add a new manufacturing process.

[0057] 8, a pair of gate electrodes GE are formed in the pair of trenches TR with a gate insulating film GI therebetween. First, a gate insulating film GI made of a silicon oxide film is formed on the semiconductor substrate SUB including the inside of the pair of trenches TR by, for example, thermal oxidation.

[0058] Next, a polycrystalline silicon film doped with, for example, n-type impurities is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method so as to fill the pair of trenches TR via the gate insulating film GI. Next, the polycrystalline silicon film located outside the pair of trenches TR is removed by, for example, a polishing process by a CMP (Chemical Mechanical Polishing) method or a dry etching process. Note that the gate insulating film GI located outside the pair of trenches TR may be removed by, for example, a wet etching process, or may be left.

[0059] As shown in Figure 9, a p-type body region PB is formed on the surface of the drift region NV, and an n-type source region NS is formed on the surface of the body region PB. First, a p-type impurity such as boron (B) is introduced by photolithography and ion implantation to form the p-type body region PB on the surface of the drift region NV. Next, an n-type impurity such as arsenic (As) is introduced by photolithography and ion implantation to form the n-type source region NS on the surface of the body region PB.

[0060] As shown in FIG. 10, an interlayer insulating film IL is formed on a semiconductor substrate SUB, a pair of holes CH1 and CH2 are formed in the interlayer insulating film IL, and a heavily doped region PR is formed in the body region PB.

[0061] First, an interlayer insulating film IL made of, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, CVD so as to cover the pair of gate electrodes GE. Next, a pair of holes CH1 and CH2 penetrating the interlayer insulating film IL and the source region NS is formed by photolithography and dry etching. The bottoms of the pair of holes CH1 and CH2 are located within the body region PB. Next, p-type impurities such as boron (B) are introduced into the bottoms of the pair of holes CH1 and CH2 by ion implantation, thereby forming p-type heavily doped regions PR within the body region PB.

[0062] 3 is also formed in the termination region 2A by the same process as the process for forming the pair of holes CH1 and CH2. The hole CH3 is located above the gate electrode GE.

[0063] 11, a source wiring SW is formed on the interlayer insulating film IL, and a protective film PIQ is formed on the source wiring SW. First, the source wiring SW is formed on the interlayer insulating film IL by sputtering or CVD so as to fill the pair of holes CH1 and CH2. Note that, by the same process as the process of forming the source wiring SW, a gate wiring GW is also formed on the interlayer insulating film IL so as to fill the hole CH3.

[0064] Next, a protective film PIQ made of, for example, a polyimide film is formed on the source wiring SW and the gate wiring GW by, for example, a coating method. Although not shown, thereafter, a part of the protective film PIQ is opened to expose regions that will become source pads and gate pads on the source wiring SW and the gate wiring GW.

[0065] After the manufacturing process of Figure 11, the semiconductor device 100 shown in Figure 4 is manufactured through the above steps. First, the back surface of the semiconductor substrate SUB is polished as necessary. Next, an n-type impurity such as arsenic (As) is introduced by ion implantation to form an n-type drain region ND on the back surface of the semiconductor substrate SUB. Next, a drain electrode DE is formed below the drain region ND by, for example, sputtering.

[0066] (Embodiment 2) The semiconductor device 100 according to the second embodiment will be described below with reference to Fig. 12. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0067] In the first embodiment, both the column region PC1 and the column region PC2 are divided into a plurality of pieces. In the second embodiment, one of the column region PC1 and the column region PC2 is divided into a plurality of pieces, but the other is not divided but has a stripe shape (a shape extending in the Y direction). That is, the width of the other column region in the Y direction is sufficiently wider than the width L1 of one column region in the Y direction.

[0068] 12 illustrates an example in which the column region PC1 is divided into multiple regions. In this case, the width of the column region PC2 in the Y direction is sufficiently wider than the width L1 of the column region PC1 in the Y direction. Therefore, the column region PC2 is adjacent to multiple column regions PC1 in the X direction.

[0069] In the second embodiment, the on-resistance can be reduced and a sufficient breakdown voltage can be ensured without reducing the resistance of the drift region NV. In terms of reducing the on-resistance, the first embodiment is superior to the second embodiment. In terms of ensuring the breakdown voltage, the second embodiment is superior to the first embodiment. In cases where priority is given to ensuring the breakdown voltage, but reduction of the on-resistance is also desired to some extent, it is preferable to apply the second embodiment.

[0070] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0071] 100 Semiconductor device 10 Depletion layer 1A cell area 2A Termination Area CH1~CH3 hole DE drain electrode GE gate electrode GI gate insulating film GW Gate wiring IL Interlayer insulating film ND drain region NS Source Region NV drift region PB body region PC1~PC5 column area PIQ protective film PR high concentration area SUB Semiconductor substrate SW source wiring TR Trench UC unit cell VSL Virtual Line

Claims

1. A semiconductor device including a plurality of unit cells, Each of the plurality of unit cells comprises: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type, the body region being formed on a surface of the drift region; a source region of the first conductivity type formed on a surface of the body region; a first column region of the second conductivity type and a second column region of the second conductivity type formed in the drift region so as to be located below the body region and adjacent to each other and spaced apart in a first direction in a plan view; a pair of trenches formed in the drift region such that their bottoms reach a position deeper than the body region, and formed between the first column region and the second column region in the first direction; a pair of gate electrodes formed in the pair of trenches with gate insulating films interposed therebetween; Equipped with the pair of trenches and the pair of gate electrodes extend in a second direction perpendicular to the first direction in a plan view; a width of the first column region in the second direction is wider than a width of the first column region in the first direction; a plurality of the first column regions are formed in the second direction and spaced apart from one another; a distance by which the plurality of first column regions are spaced apart from one another is shorter than a width of one of the first column regions in the second direction.

2. 2. The semiconductor device according to claim 1, the width of one of the first column regions in the second direction is at least twice the width of one of the first column regions in the first direction.

3. 3. The semiconductor device according to claim 2, a width of the second column region in the second direction is wider than a width of the second column region in the first direction; a plurality of the second column regions are formed in the second direction and spaced apart from one another; a distance by which the plurality of second column regions are spaced apart from one another is shorter than a width of one of the second column regions in the second direction.

4. 4. The semiconductor device according to claim 3, the width of one of the second column regions in the second direction is at least twice the width of one of the second column regions in the first direction.

5. 4. The semiconductor device according to claim 3, the plurality of first column regions and the plurality of second column regions are arranged in a staggered pattern in a plan view, a portion of one of the first column regions and a portion of one of the second column regions are adjacent to each other in the first direction.

6. 2. The semiconductor device according to claim 1, a distance by which the plurality of first column regions are spaced apart from one another is shorter than a distance between the first column region and the second column region in the first direction, and is longer than a value obtained by subtracting a width of each of the pair of trenches in the first direction from the distance between the first column region and the second column region in the first direction.

7. 2. The semiconductor device according to claim 1, the second column region extends in the second direction and is adjacent to the plurality of first column regions in the first direction.

8. 2. The semiconductor device according to claim 1, Each of the plurality of unit cells comprises: an interlayer insulating film formed on the semiconductor substrate so as to cover the pair of gate electrodes; a first hole penetrating the interlayer insulating film and the source region so that a bottom of the first hole is located within the body region; a source wiring formed on the interlayer insulating film so as to fill the first hole; Further provided with the first holes extend in the second direction so as to overlap the first column regions in a plan view.

9. A semiconductor device including a plurality of unit cells, Each of the plurality of unit cells comprises: a semiconductor substrate having a drift region made of a semiconductor layer of a first conductivity type; a body region of a second conductivity type opposite to the first conductivity type, the body region being formed on a surface of the drift region; a source region of the first conductivity type formed on a surface of the body region; a first column region of the second conductivity type and a second column region of the second conductivity type formed in the drift region so as to be located below the body region and spaced apart from each other in a first direction in a plan view; a pair of trenches formed in the drift region such that their bottoms reach a position deeper than the body region, and formed between the first column region and the second column region in the first direction; a pair of gate electrodes formed in the pair of trenches with gate insulating films interposed therebetween; Equipped with the pair of trenches and the pair of gate electrodes extend in a second direction perpendicular to the first direction in a plan view; a plurality of the first column regions are formed in the second direction and spaced apart from one another; a plurality of the second column regions are formed in the second direction and spaced apart from one another; the plurality of first column regions and the plurality of second column regions are arranged in a staggered pattern in a plan view, a portion of one of the first column regions and a portion of one of the second column regions are adjacent to each other in the first direction.

10. 10. The semiconductor device according to claim 9, a width of one of the first column regions in the second direction is wider than a width of one of the first column regions in the first direction; a width of one of the second column regions in the second direction being greater than a width of one of the second column regions in the first direction;

11. 11. The semiconductor device according to claim 10, the width of one of the first column regions in the second direction is at least twice the width of one of the first column regions in the first direction; the width of one of the second column regions in the second direction is at least twice the width of one of the second column regions in the first direction.

12. 11. The semiconductor device according to claim 10, a distance by which the plurality of first column regions are spaced apart from one another is shorter than a width of one of the first column regions in the second direction; a distance by which the plurality of second column regions are spaced apart from one another is shorter than a width of one of the second column regions in the second direction.

13. 10. The semiconductor device according to claim 9, a distance by which the plurality of first column regions are spaced apart from one another and a distance by which the plurality of second column regions are spaced apart from one another are shorter than a distance between the first column region and the second column region in the first direction, and are longer than a value obtained by subtracting a width of each of the pair of trenches in the first direction from the distance between the first column region and the second column region in the first direction.

14. 10. The semiconductor device according to claim 9, the second column region extends in the second direction and is adjacent to the plurality of first column regions in the first direction.

15. 10. The semiconductor device according to claim 9, Each of the plurality of unit cells comprises: an interlayer insulating film formed on the semiconductor substrate so as to cover the pair of gate electrodes; a first hole and a second hole penetrating the interlayer insulating film and the source region so that their bottoms are located within the body region; a source wiring formed on the interlayer insulating film so as to fill the first hole and the second hole; Further provided with the first hole extends in the second direction so as to overlap the plurality of first column regions in a plan view; the second hole extends in the second direction so as to overlap the second column regions in a plan view.

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