Memory device using voltage-controlled magnetic anisotropy effect, and its fabrication and writing methods

Abstract

An embedded eMRAM device for eFlash replacement includes MTJ pillars disposed between top and bottom electrodes to form an MRAM array. The bottom electrode is disposed above a substrate and surrounded by a first dielectric spacer, while the top electrode is disposed above the MTJ pillars and surrounded by a second dielectric spacer. The bottom metal plate is disposed between the first and second dielectric layers on either side of the bottom electrode and is electrically isolated from the bottom electrode by the first dielectric spacer. The top metal plate is disposed between the third and fourth dielectric layers on either side of the top electrode and is electrically isolated from the top electrode by the second dielectric spacer. A bias voltage applied to the top and bottom metal plates generates an external electric field in the MTJ pillars to produce the VCMA effect.

Description

[Technical Field]

[0001] The present invention relates generally to the field of magnetic storage devices, and more particularly to high-retention embedded magnetoresistive random access memory devices. [Background technology]

[0002] Currently, embedded spin-transfer torque (STT) MRAM (eMRAM) is considered a viable alternative to eFlash memory due to its range of applications and ease of use. Typical issues associated with eFlash, such as endurance and power consumption (at processes below 28 nm), can be avoided by seamless integration of STT-MRAM into CMOS and its voltage scheme. STT-MRAM can be integrated with only three additional masks, compared to the six to eight required for eFlash. eMRAM can also simultaneously simplify hardware and software design, improve energy efficiency, enhance form factors, and reduce costs for IoT devices. However, due to the data retention requirements of eMRAM, high Efficiency is required to ensure data reliability. b (i.e., an energy barrier between the P and AP stable states of the magnetic tunnel junction cell) is required, which can result in undesirably long write times that can be particularly impactful for high-speed applications. Summary of the Invention

[0003] and a top metal plate between a third dielectric layer and a fourth dielectric layer on either side of the top electrode, the top metal plate being electrically isolated from the top electrode by the second dielectric spacer. The top metal plate and the bottom metal plate generate an external electric field in each MTJ pillar to produce a voltage-controlled magnetic anisotropy effect. The present invention provides a memory device comprising: a plurality of MTJ pillars, each MTJ pillar disposed below a top electrode and above a bottom electrode to form an MRAM array, the bottom electrode being disposed above a substrate and surrounded by a first dielectric spacer, and the top electrode being disposed above each MTJ pillar and surrounded by a second dielectric spacer; a bottom metal plate disposed between a first dielectric layer and a second dielectric layer on either side of the bottom electrode, the bottom metal plate being electrically isolated from the bottom electrode by the first dielectric spacer; and a top metal plate between a third dielectric layer and a fourth dielectric layer on either side of the top electrode, the top metal plate being electrically isolated from the top electrode by the second dielectric spacer. The top metal plate and the bottom metal plate generate an external electric field in each MTJ pillar to produce a voltage-controlled magnetic anisotropy effect. The top and bottom metal plates are each electrically connected to a metal contact. An external electric field is generated, E b To reduce the σ, a bias voltage is applied to the top and bottom metal plates.

[0004] Another embodiment of the present disclosure is a first MRAM array, comprising: a first MTJ pillar disposed below a first top electrode and above a first bottom electrode, the first bottom electrode being disposed above a substrate and surrounded by a first dielectric spacer; the first MTJ pillar being disposed above the first MTJ pillar and surrounded by a second dielectric spacer; a bottom metal plate between a first dielectric layer and a second dielectric layer on either side of the first bottom electrode, the bottom metal plate being electrically isolated from the first bottom electrode by the first dielectric spacer; a top metal plate between a third dielectric layer and a fourth dielectric layer on either side of the top electrode, the second dielectric spacer being electrically isolated from the first bottom electrode by the first dielectric spacer; and a second MRAM array including a second MTJ pillar disposed below the second top electrode and above the second bottom electrode, the second bottom electrode being disposed above the substrate and surrounded by a first dielectric spacer, and the second top electrode being disposed above the second MTJ pillar and surrounded by a second dielectric spacer. The top and bottom metal plates are each electrically connected to a metal contact. The external electric field is generated to produce a voltage-controlled magnetic anisotropy effect in the first MTJ pillar. b To reduce the σ, a bias voltage is applied to the top and bottom metal plates.

[0005] Another embodiment of the present disclosure is to form a first MRAM array on a substrate, the first MRAM array including: a first MTJ pillar disposed below a first top electrode and above a first bottom electrode, the first bottom electrode disposed above the substrate and surrounded by a first dielectric spacer, the first top electrode disposed above the first MTJ pillar and surrounded by a second dielectric spacer, and a bottom metal plate between the first dielectric layer and a second dielectric layer on either side of the first bottom electrode. and a top metal plate between a third dielectric layer and a fourth dielectric layer on either side of the first top electrode, the top metal plate being electrically separated from the first top electrode by a second dielectric spacer, the top metal plate and the bottom metal plate forming a first MTJ pillar that generates an external electric field locally to produce a voltage-controlled magnetic anisotropy effect.

[0006] The method is b applying a bias voltage to the top and bottom metal plates to locally generate an external electric field to reduce E; transmitting a write current pulse through the first MRAM array using the top and bottom electrodes; and locally removing the external electric field to reduce E. b removing the bias voltage applied from the top metal plate and the bottom metal plate to increase

[0007] The method further includes forming a second MRAM array on the substrate, the second MRAM array including a second MTJ pillar disposed below a second top electrode and above a second bottom electrode, the second bottom electrode being disposed above the substrate and surrounded by a first dielectric spacer, and the second top electrode being disposed above the second MTJ pillar and surrounded by a second dielectric spacer.

[0008] The following detailed description, given by way of example and not intended to limit the invention thereto, will be best understood in conjunction with the accompanying drawings in which: [Brief explanation of the drawings]

[0009] [Figure 1] 1A-1C are cross-sectional views of a memory device at an intermediate step in a back-end (BEOL) integration process according to an embodiment of the present disclosure. [Figure 2A] FIG. 2 is a cross-sectional view of a memory device taken along line XX illustrating the formation of a bottom metal plate according to an embodiment of the present disclosure. [Figure 2B] A top view of the memory device. [Figure 3] 1A and 1B are cross-sectional views of memory devices after formation through openings according to embodiments of the present disclosure. [Figure 4A] FIG. 2 is a cross-sectional view of a memory device taken along line XX after formation of a first dielectric spacer according to an embodiment of the present disclosure. [Figure 4B] A top view of the memory device. [Figure 5A] FIG. 2 is a cross-sectional view of a memory device along line XX after formation of an MRAM stack according to an embodiment of the present disclosure. [Figure 5B] A top view of the memory device. [Figure 6A] FIG. 2 is a cross-sectional view of a memory device along line XX after patterning of the MRAM stack according to an embodiment of the present disclosure. [Figure 6B] A top view of the memory device. [Figure 7] FIG. 10 is a cross-sectional view of a memory device after formation of a second dielectric spacer and deposition of a third dielectric layer according to an embodiment of the present disclosure. [Figure 8A] FIG. 2 is a cross-sectional view of a memory device taken along line XX after deposition and patterning of a top metal plate according to an embodiment of the present disclosure. [Figure 8B]A top view of the memory device. [Figure 9] FIG. 10 is a cross-sectional view of a memory device after deposition of a fourth dielectric layer and patterning of contacts according to an embodiment of the present disclosure. [Figure 10A] FIG. 2 is a cross-sectional view of a memory device taken along line XX after formation of a third dielectric spacer according to an embodiment of the present disclosure. [Figure 10B] A top view of the memory device. [Figure 11A] FIG. 2 is a cross-sectional view of a memory device taken along line XX after contact metallization according to an embodiment of the present disclosure. [Figure 11B] A top view of the memory device. DETAILED DESCRIPTION OF THE INVENTION

[0010] The drawings are not necessarily to scale. The drawings are merely schematic representations and are not intended to portray specific parameters of the invention. The drawings are intended to depict merely exemplary embodiments of the invention. Like numbering in the drawings represents like elements.

[0011] Although detailed embodiments of the claimed structures and methods are disclosed herein, it will be understood that the disclosed embodiments are merely exemplary of the claimed structures and methods, which may be embodied in various forms. However, the present invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. The description may omit details of well-known features and techniques so as not to unnecessarily obscure the presented embodiments.

[0012] For purposes of the following description, terms such as "upper," "lower," "right," "left," "vertical," "horizontal," "top," "bottom," and derivatives thereof, refer to the disclosed structures and methods and their orientation in the drawing figures. Terms such as "above," "overlying," "atop," "on top," "positioned on," or "positioned atop" refer to a first element, e.g., a first structure, being on a second element, e.g., a second structure, where an intervening element, such as an interface structure, may be present between the first and second elements. The term "direct contact" refers to a connection between a first element, e.g., a first structure, and a second element, e.g., a second structure, without any intermediate conductive, insulating, or semiconducting layer at the interface between the two elements.

[0013] Although terms such as "first," "second," and the like may be used herein to describe various elements, it will be understood that these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below could be referred to as a second element without departing from the scope of the present concepts.

[0014] In order to avoid obscuring the presentation of embodiments of the present invention, in the following detailed description, some process steps or operations known in the art may be combined together for purposes of presentation and illustration, and in some cases may not be described in detail. In other cases, some process steps or operations known in the art may not be described at all. It should be understood that the following description instead focuses on the distinctive features or elements of various embodiments of the present invention.

[0015] STT-MRAM devices are two-terminal devices similar to conventional MRAM devices, except that the write current path passes through the magnetic layers of each memory element. The free layer is set by spin transfer torque from a spin-polarized current passing through the reference magnetic layer. In STT-MRAM devices, the spin of electrons is flipped using a spin-polarized current. This effect can be achieved in a magnetic tunnel junction (MTJ) or a spin valve. The spin-polarized current is generated by passing a current through a thin magnetic layer, which is then directed into an even thinner magnetic layer, thereby transferring angular momentum to this thin layer and changing its spin. Generally, the magnetization direction of the reference magnetic layer is invariant, while the magnetization direction of the free layer can be changed. Therefore, a magnetic field determines the electrical properties of the MTJ. In applications, the conductance difference resulting from a change in the magnetic field in the ferromagnetic layers is utilized. The magnetization orientation (m z ) is the level of MTJ resistance, i.e., the low resistance in the parallel state (R P ) and high resistance in the antiparallel state (R AP ) These two stable states of the MTJ can be used to represent a logic 0 or a logic 1.

[0016] In STT-MRAM, the STT effect causes the current to exceed the critical current I c0 When I is larger than I, it is possible to switch the MTJ state by a bidirectional current I. This improves the scalability of circuits with MTJs, allowing for denser layouts and simpler designs, due to the use of the same line for writing and reading the MTJ state. However, the drawback of scaling down using STTs is that the thermal stability factor (D) scales linearly with area, resulting in increased retention failure due to thermal instability, resulting in unreliable operation. Therefore, a high E is required to maintain data reliability. b (E bis the energy barrier between the P and AP stable states of the MTJ cell. This results in undesirably long write times that can be particularly problematic for high-speed write applications, because the switching current of the STT is inversely proportional to the write pulse width.

[0017] Therefore, embodiments of the present disclosure provide an embedded STT-MRAM (eMRAM) memory device and method for fabricating the same, in which an external electric field is induced in the MTJ cell, for use as an eFlash replacement. The external electric field utilizes the voltage-controlled magnetic anisotropy (VCMA) effect to reduce the energy barrier (E) between the AP and P states in the MTJ cell. b ), resulting in an improvement in overall MTJ speed. In the present embodiment, efficient energy consumption and area reduction can be achieved by using a voltage-controlled MTJ using an electric field (or voltage). In the VCMA effect, an electric field is used to switch the state of the MTJ, which occurs when the field-induced accumulation of electronic charge changes the occupation of atomic orbitals at the interface. This, together with spin-orbit interactions, can result in a change in magnetic anisotropy. In this way, the embodiments of the present disclosure can achieve a critical current I c0 Lower E, which reduces the b to provide.

[0018] More specifically, embodiments of the present disclosure use top and bottom metal plates electrically isolated from the top and bottom electrodes of the MTJ by a dielectric material to introduce an external electric field, thereby producing a VCMA effect in the memory device.

[0019] An embodiment in which top and bottom metal plates can be used to create the VCMA effect and introduce an external electric field into an MTJ cell of a memory device is described in detail below with reference to the accompanying drawings of FIGS. 1-11B.

[0020] 1, there is shown a cross-sectional view of a memory device 100 at an intermediate step during a back-end (BEOL) integration process, according to an embodiment of the present disclosure. At this step in the manufacturing process, the memory device 100 includes a simplified substrate 102 containing one or more metal-oxide-semiconductor field-effect transistors (not shown). In this embodiment, the memory device 100 may be an embedded STT-MRAM (eMRAM) device.

[0021] 2A, a cross-sectional view of memory device 100 along line XX is shown after formation of bottom metal plate 206, in accordance with an embodiment of the present disclosure. In this embodiment, FIG. 2B is a top view of memory device 100.

[0022] In this embodiment, a first dielectric layer 204 is deposited on the memory device 100 above the substrate 102 prior to forming the bottom metal plate 206. The first dielectric layer 204 may, for example, comprise a low-k dielectric material having a dielectric constant k in the range of about 2.0 to about 2.7 and may be deposited directly above the substrate 102 by any suitable deposition process, such as, for example, chemical vapor deposition (CVD). The thickness of the first dielectric layer 204 may vary from about 20 nm to about 80 nm and ranges therebetween. In an exemplary embodiment, the first dielectric layer 204 may have a thickness that varies between 10 nm and 40 nm.

[0023] After deposition of the first dielectric layer 204, a bottom metal plate 206 is formed in the memory device 100. The bottom metal plate 206 is made of a first conductive material. According to an embodiment, the first conductive material forming the bottom metal plate 206 may include a metal such as tungsten, tungsten carbide, copper, titanium, titanium nitride, etc. In some embodiments, the bottom metal plate 206 may be comprised of a multi-layer stack including one or more layers of metal.

[0024] In an exemplary embodiment, the bottom metal plate 206 may have a (vertical) thickness that varies from about 5 nm to about 30 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0025] 2A-2B, a patterning process is performed on the bottom metal plate 206, as shown in FIG. 2B. The process of patterning the bottom metal plate 206 consists of steps well known in the art and generally includes forming a pattern on a photoresist layer (not shown) that is transferred to a hard mask and used to pattern the underlying bottom metal plate 206 by any suitable etching technique. In an exemplary embodiment, the bottom metal plate 206 may be patterned using ion beam etching (IBE) or reactive ion etching (RIE) techniques. As depicted in FIG. 2B, after the patterning process is completed, a first plurality of trenches 208 are formed in the bottom metal plate 206.

[0026] After patterning the bottom metal plate 206, a second dielectric layer 210 is formed on the memory device 100 above the bottom metal plate 206, as depicted in FIG. 2A. The second dielectric layer 210 may comprise similar materials and may be formed in a manner similar to the first dielectric layer 210 (FIG. 2A) previously described. The thickness of the second dielectric layer 210 may vary from about 20 nm to about 80 nm and ranges therebetween, although other thicknesses above or below this range may be used as desired for a particular application.

[0027] 3, there is shown a cross-sectional view of memory device 100 after the formation of a first via opening 302, in accordance with an embodiment of the present disclosure. First via opening 302 is formed to electrically connect memory device 100 to a subsequently formed conductive structure.

[0028] As known to those skilled in the art, the process of forming first via opening 302 in memory device 100 includes depositing a photoresist layer (not shown) above second dielectric layer 210, exposing a pattern on the photoresist layer, and transferring the exposed pattern to the underlying first dielectric layer 204, bottom metal plate 206, and second dielectric layer 210 to form first via opening 302, as depicted in the figures. After transferring the pattern and forming first via opening 302, the photoresist layer can be removed using any photoresist stripping method known in the art, including, for example, plasma ashing.

[0029] 4A, there is shown a cross-sectional view of memory device 100 along line XX after formation of first dielectric spacers 430 and bottom electrode 420, in accordance with an embodiment of the present disclosure. In this embodiment, FIG. 4B is a top view of memory device 100.

[0030] A first dielectric spacer 430 is formed in the first via opening 302 (FIG. 3). The first dielectric spacer 430 may be made of an insulator material such as an oxide, nitride, oxynitride, silicon carbon oxynitride, silicon boron oxynitride, a low-k dielectric, or any combination thereof. Standard deposition and etching techniques may be used to form the first dielectric spacer 430. As known to those skilled in the art, the deposited insulator material is removed from all horizontal surfaces of the memory device 100 using, for example, an anisotropic etch. According to one embodiment, the (horizontal) thickness of the first dielectric spacer 430 may vary between about 5 nm and about 15 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0031] 4A-4B , after the formation of the first dielectric spacers 430, the bottom electrode 420 can be deposited on the memory device 100 using standard deposition methods. A conductive material forming the bottom electrode 420 is deposited in the remaining space within the first dielectric spacers 430. Exemplary deposition processes that can be used to form the bottom electrode 420 include chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. The bottom electrode 420 is formed above conductive structures (not shown) in the substrate 102 and substantially fills the space between the first dielectric spacers 430 as depicted in the figures. In an exemplary embodiment, the bottom electrode 420 can be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof.

[0032] After formation of bottom electrode 420, a planarization process, such as chemical mechanical polishing (CMP), may be performed to remove excess (overflow) portions of the conductive material forming bottom electrode 420 from memory device 100. After the planarization process, the top surfaces of bottom electrode 420 and second dielectric layer 210 are substantially coplanar.

[0033] As depicted in the figure, first dielectric spacers 430 surround bottom electrode 420. As a result, first dielectric spacers 430 electrically isolate bottom electrode 420 from bottom metal plate 206. Similarly, first dielectric layer 204 electrically isolates bottom metal plate 206 from substrate 102, while second dielectric layer 210 electrically isolates bottom metal plate 206 from subsequently formed conductive structures.

[0034] 5A, there is shown a cross-sectional view of memory device 100 along line XX after deposition of MRAM stack 500, in accordance with an embodiment of the present disclosure. In this embodiment, FIG. 5B is a top view of memory device 100.

[0035] According to one embodiment, an MRAM stack 500 is formed above the bottom electrode 420. The MRAM stack 500 may include an MTJ pillar composed of at least a magnetic reference layer 520, a tunnel barrier layer 530, and a magnetic free layer 540. The MRAM stack 500 may further include a conductive hard mask layer 550 disposed above the MTJ pillar and a patterned hard mask layer 560 disposed above the conductive hard mask layer 550, as depicted in FIG. 5A. It should be noted that other MTJ configurations are possible for the MTJ pillars of the MRAM stack 500, such as having the magnetic free layer 540 disposed at the bottom of the MTJ pillar and the magnetic reference layer 520 disposed at the top of the MTJ pillar. The various material layers of the MRAM stack 500 may be formed using one or more deposition processes, such as, for example, plating, sputtering, plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

[0036] The magnetic reference layer 520 has a fixed magnetization. The magnetic reference layer 520 can be composed of a metal or a metal alloy (or stack thereof) including one or more metals that exhibit high spin polarization. In an alternative embodiment, exemplary metals for forming the magnetic reference layer 520 can include iron, nickel, cobalt, chromium, boron, or manganese. Exemplary metal alloys can include the metals exemplified above. In another embodiment, the magnetic reference layer 520 can be a multilayer configuration having (1) highly spin-polarized regions formed from metals and / or metal alloys using the metals described above, and (2) regions constructed from one or more materials that exhibit strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, and ruthenium, which can be arranged in alternating layers. The regions of strong PMA may also include alloys that exhibit strong PMA, with exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-platinum, cobalt-palladium, iron-platinum, or iron-palladium, or combinations thereof. These alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be employed.

[0037] The tunnel barrier layer 530 is made of an insulating material and is formed to a thickness to provide adequate tunneling resistance. Exemplary materials for the tunnel barrier layer 530 include magnesium oxide, aluminum oxide, and titanium oxide, or materials with higher electrical tunneling conductance, such as semiconductors or low bandgap insulators.

[0038] The magnetic free layer 540 may be composed of a magnetic material (or stack of magnetic materials) having a magnetization that can be changed in orientation relative to the magnetization orientation of the magnetic reference layer 520. Exemplary magnetic materials for the magnetic free layer 540 include alloys and / or multilayers of cobalt, iron, cobalt-iron alloys, nickel, nickel-iron alloys, and cobalt-iron-boron alloys.

[0039] It should be noted that while some elements and / or features of memory device 100 are illustrated, they have not been described in detail to avoid unnecessarily obscuring the presented embodiments.

[0040] 5A-5B, conductive hardmask layer 550 comprises a metallic hardmask typically required to protect MRAM stack 500 during subsequent etching steps. In exemplary embodiments, conductive hardmask layer 550 may be composed of metals such as TaN, TaAlN, WN, and TiN.

[0041] According to one embodiment, the patterning hardmask layer 560 disposed above the conductive hardmask layer 550 can be fabricated from a dielectric material (e.g., silicon dioxide, silicon nitride, silicon carbide, etc.), multiple layers of dielectric material, or an organic planarization layer (OPL), or a combination thereof. The conductive hardmask layer 550 and the patterning hardmask layer 560 can be formed by any suitable deposition method known in the art. Note that the conductive hardmask layer 550 is not a sacrificial layer, whereas the patterning hardmask layer 560 is a sacrificial layer in that the patterning hardmask layer 560 will be removed after the patterning process is completed.

[0042] 6A, a cross-sectional view of memory device 100 along line XX is shown after patterning of MRAM stack 500, according to an embodiment of the present disclosure. In this embodiment, FIG. 6B is a top view of memory device 100. As can be seen, patterned MRAM stack 500 is disposed above bottom electrode 420 such that the top surface of bottom electrode 420 contacts a central portion of the bottom surface of MRAM stack 500.

[0043] The process of patterning the MRAM stack 500 consists of steps well known in the art and generally includes forming a pattern on a photoresist layer (not shown) that is transferred to the patterning hard mask layer 560 and used to pattern the underlying MTJ pillars and conductive hard mask layer 550 by any suitable etching technique. In an exemplary embodiment, the MRAM stack 500 may be patterned using an ion beam etching (IBE) technique. After patterning the MRAM stack 500, a recess 610 is formed in the memory device 100. The recess 610 extends through a first (top) portion of the second dielectric layer 210. As depicted in FIG. 6A , a second portion of the second dielectric layer 210 remains above the bottom metal plate 206 between the patterned MRAM structures. In this embodiment, the patterning hard mask layer 560 is removed after patterning the MRAM stack 500 using any suitable etching technique.

[0044] Referring now to FIG. 7, there is shown a cross-sectional view of the memory device 100 after the formation of second dielectric spacers 730 and the deposition of a third dielectric layer 720, according to an embodiment of the present disclosure.

[0045] According to one embodiment, second dielectric spacers 730 are formed in recess 610 (FIG. 6A), followed by deposition of third dielectric layer 720. Third dielectric layer 720 substantially fills the remaining space in recess 610 (FIG. 6A) and extends over the top surface of conductive hard mask layer 550, as shown. Third dielectric layer 720 electrically isolates conductive hard mask layer 550 and the underlying MTJ layer from subsequently formed conductive structures.

[0046] In an exemplary embodiment, the second dielectric spacers 730 are made of the same or similar materials and formed in a similar manner as the first dielectric spacers 430 described above with reference to Figures 4A-4B. Similarly, the third dielectric layer 720 is made of the same materials and formed in a similar manner as the first dielectric layer 204 and the second dielectric layer 210 described above with reference to Figures 2A-2B. In some embodiments, a planarization process may be performed on the memory device 100 after the formation of the third dielectric layer 720.

[0047] Referring now to FIG. 8A, a cross-sectional view of memory device 100 along line XX is shown after deposition and patterning of top metal plate 840, according to an embodiment of the present disclosure. In this embodiment, FIG. 8B is a top view of memory device 100. As depicted in FIG. 8A, top metal plate 840 is formed above third dielectric layer 720. Top metal plate 840 is fabricated from a second conductive material similar to the first conductive material forming bottom metal plate 206 described above with reference to FIGS. 2A-2B.

[0048] In an exemplary embodiment, the top metal plate 840 may have a (vertical) thickness that varies from 5 nm to about 30 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0049] According to one embodiment, a patterning process is performed on the top metal plate 840, as shown in FIG. 8B. The process of patterning the top metal plate 840 consists of steps well known in the art and generally includes forming a pattern on a photoresist layer (not shown) that is transferred to a hard mask (not shown) and used to pattern the underlying top metal plate 840 by any suitable etching technique. In an exemplary embodiment, the top metal plate 840 may be patterned using ion beam etching (IBE) or reactive ion etching (RIE) techniques. After the patterning process is completed, a second plurality of trenches 808 are formed in the top metal plate 840, as depicted in FIG. 8B.

[0050] Referring now to FIG. 9, a cross-sectional view of the memory device 100 is shown after deposition of a fourth dielectric layer 920 and formation of a second via opening 902, according to an embodiment of the present disclosure.

[0051] After patterning the top metal plate 840, a fourth dielectric layer 920 is formed on the memory device 100 above the top metal plate 840. In one embodiment, the fourth dielectric layer 920 substantially fills the second plurality of trenches 808 shown in FIG. 8B . The fourth dielectric layer 920 may include materials similar to the first dielectric layer 204, the second dielectric layer 210, and the third dielectric layer 720 described above and may be formed in a similar manner. As known to those skilled in the art, the process of forming the second via opening 902 in the memory device 100 includes depositing a photoresist layer (not shown) above the second dielectric layer 210, exposing a pattern on the photoresist layer, and transferring the exposed pattern to the underlying fourth dielectric layer 920, the top metal plate 840, and the third dielectric layer 720 to form the second via opening 902, as depicted in the figures. After transferring the pattern and forming the second via opening 902, the photoresist layer can be removed using any photoresist stripping method known in the art, including, for example, plasma ashing. As shown in FIG. 9, the second via opening 902 exposes the top surface of the conductive hard mask layer 550.

[0052] 10A, there is shown a cross-sectional view of memory device 100 along line XX after formation of third dielectric spacers 1030 and top electrode 1020, in accordance with an embodiment of the present disclosure. In this embodiment, FIG. 10B is a top view of memory device 100.

[0053] Similar to the first dielectric spacer 430 (FIGS. 4A-4B), the third dielectric spacer 1030 is formed within the second via opening 902 (FIG. 9) using methods well known in the art. After the formation of the third dielectric spacer 1030, the top electrode 1020 is formed in the remaining space within the second via opening 902 (FIG. 9). The third dielectric spacer 1030 may be formed using techniques and materials similar to those used for the first dielectric spacer 430 (FIGS. 4A-4B). As known to those skilled in the art, the deposited insulator material forming the third dielectric spacer 1030 may be removed from all horizontal surfaces of the memory device 100 using, for example, an anisotropic etch.

[0054] According to one embodiment, the (horizontal) thickness of the third dielectric spacer 1030 may vary between about 5 nm and about 15 nm, although other thicknesses above or below this range may be used as desired for a particular application.

[0055] Similar to the bottom electrode 420 (FIGS. 4A-4B), the top electrode 1020 can be deposited on the memory device 100 using standard deposition methods. For example, a chemical vapor deposition (CVD) process can be used to form the top electrode 1020. In some embodiments, the top electrode 1020 can be composed of a conductive material such as, for example, Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof.

[0056] 10A-10B, the third dielectric spacer 1030 surrounds the top electrode 1020. As a result, the third dielectric spacer 1030 electrically isolates the top electrode 1020 from the top metal plate 840.

[0057] At this step in the manufacturing process, a planarization process, such as chemical mechanical polishing (CMP), may be performed to remove excess (overflow) portions of the conductive material that forms the top electrode 1020 from the memory device 100 .

[0058] Thus, by forming the top metal plate 840 and the bottom metal plate 206 separate from the top electrode 1020 and the bottom electrode 420 of the MRAM array, an external electric field is introduced to the MTJ cells of the MRAM, thereby creating an energy barrier (E b ) and improve overall MTJ speed.

[0059] Note that the top metal plate 840 and the bottom metal plate 206 are each electrically connected to a (separate) metal contact (not shown). In some embodiments, the metal contact may include an external metal contact located outside the MRAM array. In other embodiments, the metal contact may be located within the MRAM array region. As may be known to those skilled in the art, if the top metal plate 840 and the bottom metal plate 206 are not connected to a metal contact (not shown), they will not function and an electric field cannot be generated between the top metal plate 840 and the bottom metal plate 206.

[0060] Accordingly, embodiments of the present disclosure provide an operation sequence for a write function that includes: 1) E b 1) applying a bias voltage to the top metal plate 840 and the bottom metal plate 206 to locally generate an external electric field to reduce Eb; 2) sending a write current pulse through the MRAM junction using the top electrode 1020 and the bottom electrode 420; and 3) removing the applied bias voltage from the top metal plate 840 and the bottom metal plate 206 to locally remove the external electric field and increase Eb again to improve the stability of the magnetic state and increase the retention time.

[0061] 11A, a cross-sectional view of memory device 100 along line XX is shown after contact metallization in accordance with an embodiment of the present disclosure. In this embodiment, FIG. 11B is a top view of memory device 100.

[0062] 11A-11B depict regions of memory device 100 in which top metal plate 840 and bottom metal plate 206 are not incorporated into the MRAM array. In this case, memory device 100 may additionally or alternatively have one or more MRAM arrays that include top metal plate 840 and bottom metal plate 206, e.g., for eFLASH replacement (as described above), where other MRAM arrays on the same chip may not include top metal plate 840 and bottom metal plate 206.

[0063] Finally, embodiments of the present disclosure provide a memory device having top and bottom metal plates locally integrated into each MTJ for introducing an external electric field. The top and bottom metal plates are electrically isolated from the MTJ cell and from the top and bottom electrodes by multiple dielectric layers. In this arrangement, E b Reduction of the write current and desired E via the local electric field generated by the top and bottom metal plates, which causes the VCMA effect that regulates b It may be possible to adjust.

[0064] While the descriptions of various embodiments of the present invention have been presented for illustrative purposes, they are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technology found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a memory device, a plurality of MTJ pillars, each MTJ pillar disposed below a top electrode and above a bottom electrode to form an MRAM array, the bottom electrodes being disposed above a substrate and surrounded by a first dielectric spacer, and the top electrodes being disposed above each MTJ pillar and surrounded by a second dielectric spacer; a bottom metal plate between a first dielectric layer and a second dielectric layer on either side of the bottom electrode, the bottom metal plate being electrically isolated from the bottom electrode by the first dielectric spacer; and top metal plates between third and fourth dielectric layers on either side of the top electrode, the top metal plates being electrically isolated from the top electrode by the second dielectric spacers, wherein the top and bottom metal plates generate an external electric field in each MTJ pillar to produce a voltage-controlled magnetic anisotropy effect.

2. 2. The memory device of claim 1, wherein the top metal plate and the bottom metal plate are each electrically connected to a metal contact.

3. The external electric field is generated E ｂ 3. The memory device of claim 1, wherein a bias voltage is applied to the top metal plate and the bottom metal plate to reduce an energy barrier between the P and AP stable states of the MTJ cell.

4. a region disposed between each of the MRAM arrays for electrically isolating the MRAM arrays, the region being filled with a portion of the third dielectric layer and surrounded by a third dielectric spacer; The memory device of claim 1 further comprising:

5. 2. The memory device of claim 1, wherein each of the plurality of MTJ pillars comprises a magnetic reference layer above the bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a magnetic free layer above the tunnel barrier layer.

6. 2. The memory device of claim 1, wherein each of the plurality of MTJ pillars comprises a magnetic free layer above the bottom electrode, a tunnel barrier layer above the magnetic free layer, and a magnetic reference layer above the tunnel barrier layer.

7. The MRAM array comprises: The memory device of claim 5 , further comprising a conductive hard mask layer over the MTJ pillars.

8. 10. The memory device of claim 1, wherein the top metal plate and the bottom metal plate are made of a conductive material including at least one of tungsten, tungsten carbide, copper, titanium, and titanium nitride.

9. a memory device, a first MRAM array, a first MTJ pillar disposed below a first top electrode and above a first bottom electrode, the first bottom electrode being disposed above a substrate and surrounded by a first dielectric spacer, and the first top electrode being disposed above the first MTJ pillar and surrounded by a second dielectric spacer; a bottom metal plate between the first and second dielectric layers on either side of the first bottom electrode, the bottom metal plate being electrically isolated from the first bottom electrode by the first dielectric spacers; the first MRAM array comprising: top metal plates between third and fourth dielectric layers on either side of the first top electrode, the top metal plates being electrically separated from the first top electrode by the second dielectric spacers, wherein the top and bottom metal plates locally generate an external electric field in the first MTJ pillar to produce a voltage-controlled magnetic anisotropy effect; a second MRAM array, the second MRAM array comprising: a second MTJ pillar disposed below a second top electrode and above a second bottom electrode, the second bottom electrode being disposed above the substrate and surrounded by the first dielectric spacer, and the second top electrode being disposed above the second MTJ pillar and surrounded by the second dielectric spacer; and A memory device comprising:

10. 10. The memory device of claim 9, wherein the top metal plate and the bottom metal plate are each electrically connected to a metal contact.

11. 11. The memory device of claim 9, wherein a bias voltage is applied to the top metal plate and the bottom metal plate to generate the external electric field.

12. a region disposed between the first and second MRAM arrays to electrically isolate the first MRAM array from the second MRAM array, the region being filled with a portion of the third dielectric layer and surrounded by a third dielectric spacer; The memory device of claim 9 further comprising:

13. 10. The memory device of claim 9, wherein the first MTJ pillar comprises a magnetic reference layer above the first bottom electrode, a tunnel barrier layer above the magnetic reference layer, and a magnetic free layer above the tunnel barrier layer, and the second MTJ pillar comprises the magnetic reference layer above the second bottom electrode, the tunnel barrier layer above the magnetic reference layer, and the magnetic free layer above the tunnel barrier layer.

14. 10. The memory device of claim 9, wherein the first MTJ pillar comprises a magnetic free layer above the first bottom electrode, a tunnel barrier layer above the magnetic free layer, and a magnetic reference layer above the tunnel barrier layer, and the second MTJ pillar comprises a magnetic free layer above the second bottom electrode, a tunnel barrier layer above the magnetic free layer, and a magnetic reference layer above the tunnel barrier layer.

15. 10. The memory device of claim 9, wherein the top metal plate and the bottom metal plate are made of a conductive material including at least one of tungsten, tungsten carbide, copper, titanium, and titanium nitride.

16. 1. A method of forming a memory device, comprising: forming a first MRAM array on a substrate, the first MRAM array comprising: a first MTJ pillar disposed below a first top electrode and above a first bottom electrode, the first bottom electrode being disposed above the substrate and surrounded by a first dielectric spacer, and the first top electrode being disposed above the first MTJ pillar and surrounded by a second dielectric spacer; a bottom metal plate between the first and second dielectric layers on either side of the first bottom electrode, the bottom metal plate being electrically isolated from the first bottom electrode by the first dielectric spacers; and top metal plates between third and fourth dielectric layers on either side of the first top electrode, the top metal plates being electrically isolated from the first top electrode by the second dielectric spacers, wherein the top and bottom metal plates locally generate an external electric field in the first MTJ pillars to produce a voltage-controlled magnetic anisotropy effect.

10. A method of forming a memory device, comprising:

17. forming a second MRAM array on the substrate, the second MRAM array comprising: forming the second MRAM array on the substrate, the second MTJ pillar being disposed below a second top electrode and above a second bottom electrode, the second bottom electrode being disposed above the substrate and surrounded by the first dielectric spacer, and the second top electrode being disposed above the second MTJ pillar and surrounded by the second dielectric spacer.

17. The method of claim 16, further comprising:

18. 18. The method of claim 16 or 17, wherein the top metal plate and the bottom metal plate are each electrically connected to a metal contact.

19. A method for operating a write function of the memory device of claim 3, comprising: The above E ｂ applying a bias voltage to the top metal plate and the bottom metal plate to locally generate the external electric field to reduce transmitting a write current pulse through the MRAM junction using the top and bottom electrodes; The external electric field is locally removed, and the E ｂ removing the applied bias voltage from the top metal plate and the bottom metal plate to increase A method comprising:

20. a region disposed between the first and second MRAM arrays to electrically isolate the first MRAM array from the second MRAM array, the region being filled with a portion of the third dielectric layer and surrounded by a third dielectric spacer; 20. The method of claim 17, further comprising:

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