Semiconductor package manufacturing method and semiconductor package

Abstract

To provide a method for manufacturing a semiconductor package which can improve heat dissipation properties of a plurality of semiconductor elements having different functions while compactly arranging the semiconductor elements, in a semiconductor package called FOWLP.SOLUTION: A first external terminal 3 and a second external terminal 4 as electrodes for heat dissipation are arranged on an upper surface of a support, and a first semiconductor element 5 is mounted on the first external terminal 3. Then, a first outer body 18 for holding the first external terminal 3, the second external terminal 4 and the first semiconductor element 5 is formed by molding the upper surface of the support with a resin. Then, a re-wiring layer 7 is formed on an upper surface of the first outer body 18, and a second semiconductor element 8 is mounted on the re-wiring layer 7 and the second semiconductor element 8 is connected to the second external terminal 4 through the re-wiring layer 7. Then, a second outer body 25 is formed by molding the upper surface of the first outer body 18, and then the support 50 is removed from a lower surface 2a of the first outer body 18.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor package and a semiconductor package. Ji Regarding. [Background technology]

[0002] As electronic devices become smaller and more powerful, the semiconductor packages they use are becoming smaller and denser. To address this issue, a new semiconductor package called FOWLP (Fan Out Wafer Level Package) has been proposed. Unlike BGA (Ball Grid Array), FOWLP does not have a package substrate, resulting in a thinner package and shorter wiring, enabling faster transmission speeds. This has attracted attention in recent years.

[0003] As an example of FOWLP, a semiconductor chip package incorporating a semiconductor element (first semiconductor chip) surrounded by a resin layer is partially sealed with a sealing material, a rewiring layer is formed above the semiconductor chip package, and semiconductor chip packages incorporating a second semiconductor chip and a third semiconductor chip are mounted on the rewiring layer (see, for example, Patent Document 1). Below the semiconductor chip package incorporating the first semiconductor chip, connection terminals for external connection are provided via the rewiring layer. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6455998 Summary of the Invention [Problem to be solved by the invention]

[0005] However, conventional semiconductor packages, including the above-mentioned FOWLP, do not have a structure that efficiently dissipates heat generated by semiconductor elements to the outside, making it difficult to apply them to semiconductor elements that generate high heat, such as power elements and processor chips.

[0006] Therefore, the present invention provides a semiconductor package manufacturing method and a semiconductor package that can improve the heat dissipation of semiconductor elements while compactly arranging multiple semiconductor elements in a semiconductor package called FOWLP. Ji The purpose is to provide. [Means for solving the problem]

[0007] The method for manufacturing a semiconductor package of the present invention includes an external terminal installation step of installing a first external terminal and a second external terminal as heat dissipation electrodes on the upper surface of a support; a first semiconductor element mounting step of mounting a first semiconductor element on the first external terminal; a first molding step of forming a first outer body that holds the first external terminal, the second external terminal, and the first semiconductor element by molding the upper surface of the support with resin; and a reinforcing layer including an insulating layer that is connected to the second external terminal and the first semiconductor element, respectively, on the upper surface of the first outer body. a rewiring layer forming step of forming a wiring layer; a second semiconductor element connecting step of mounting a second semiconductor element on the rewiring layer and connecting the second semiconductor element to the second external terminal via the rewiring layer; a second molding step of forming a second outer body that covers the entire rewiring layer including the insulating layer and the second semiconductor element by applying molding to the upper surface of the first outer body; and a support removing step of removing the support from the lower surface of the first outer body to expose each of the first external terminal and the second external terminal on the lower surface of the first outer body. the rewiring layer includes a rewiring portion connected to the first semiconductor element, the second semiconductor element, and the second external terminal; the insulating layer includes a first insulating layer and a second insulating layer laminated on the first insulating layer; and in the rewiring layer forming step, the rewiring portion is formed covered with the first insulating layer and the second insulating layer. .

[0008] The semiconductor package of the present invention comprises a first external terminal as a heat dissipation electrode, a second external terminal, a first semiconductor element mounted on the first external terminal, a rewiring layer including an insulating layer connected to the second external terminal and the first semiconductor element, a second semiconductor element mounted on the rewiring layer and connected to the second external terminal via the rewiring layer, and an outer casing made of resin and holding the first external terminal, the second external terminal, the first semiconductor element, the rewiring layer, and the second semiconductor element, wherein the outer casing encapsulates the entire rewiring layer including the insulating layer. The rewiring layer includes a rewiring portion connected to the first semiconductor element, the second semiconductor element, and the second external terminal, the insulating layer includes a first insulating layer and a second insulating layer stacked on the first insulating layer, and the rewiring portion is formed by being covered with the first insulating layer and the second insulating layer. . [Effects of the Invention]

[0010] According to the present invention, in a semiconductor package called FOWLP, it is possible to compactly arrange a plurality of semiconductor elements while improving the heat dissipation of the semiconductor elements. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a side cross-sectional view of a semiconductor package according to a first embodiment of the present invention; [Figure 2] (a) (b) (c) (d) are explanatory diagrams of a method for manufacturing a semiconductor package according to the first embodiment of the present invention. [Figure 3] (a) (b) (c) (d) are explanatory diagrams of a method for manufacturing a semiconductor package according to the first embodiment of the present invention. [Figure 4] 1 is an explanatory diagram of a method for manufacturing a semiconductor package according to the first embodiment of the present invention; [Figure 5] 1A is a side cross-sectional view of a semiconductor package manufacturing method according to a first embodiment of the present invention, showing a copper sputtering process at the end of the process; FIG. 1B is a side cross-sectional view of a resist coating process at the end of the process; and FIG. 1C is a side cross-sectional view of a resist removal process at the end of the process. [Figure 6] 1A is a side cross-sectional view of a semiconductor package manufacturing method according to a first embodiment of the present invention, showing a state where an etching step is completed; FIG. 1B is a side cross-sectional view of a semiconductor package manufacturing method according to a first embodiment of the present invention, showing a state where a resist cleaning step is completed; [Figure 7] FIG. 1 is a diagram showing a state in which the semiconductor package according to the first embodiment of the present invention is mounted on a product. [Figure 8] 1A and 1B are diagrams showing an example in which a substrate for mounting electronic components constituting a semiconductor package according to the first embodiment of the present invention is used as a double-sided mounting substrate; [Figure 9] 10 is a side cross-sectional view of a semiconductor package according to a second embodiment of the present invention. [Figure 10] (a) (b) (c) (d) (e) are explanatory diagrams of a method for manufacturing a semiconductor package according to a second embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0012] (Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings. Fig. 1 shows a semiconductor package 1 manufactured by a method for manufacturing a semiconductor package according to the first embodiment.

[0013] The semiconductor package 1 includes the following elements inside and outside an outer casing 2 made of resin. Specifically, the outer casing 2 holds a first external terminal 3 and a plurality of second external terminals 4 exposed on the lower surface 2a, which is the first surface, and a first semiconductor element 5 inside. In the first embodiment, a thermosetting resin is used as the resin for the outer casing 2, but a thermoplastic resin may also be used. The first semiconductor element 5 is a high-heat-generating element such as a power element, and is mounted on the first external terminal 3. In the first embodiment, a flip-chip type element is used as the first semiconductor element 5, but the first semiconductor element 5 is not limited to this and may be a surface-mount type electronic component, including a wire-bonded type.

[0014] The first external terminal 3 is in contact with a surface 5a of the first semiconductor element 5 opposite to the functional surface via a bonding paste (not shown). The first external terminal 3 is used as a heat dissipation electrode for dissipating heat from the first semiconductor element 5 to the outside. The second external terminal 4 is an electrode that is electrically connected via a solder bump 6 to another semiconductor package that is separately mounted on a motherboard (substrate board) on which the semiconductor package 1 is mounted. The number of the first external terminal 3, the second external terminal 4, and the first semiconductor element 5 may be one or more.

[0015] One end (bottom surface) of each of the first external terminal 3 and the second external terminal 4 is exposed from the bottom surface 2a of the outer casing 2. Solder bumps 6 serving as external output terminals are formed on one end of each of the first external terminal 3 and the second external terminal 4. The semiconductor package 1 is connected to a motherboard by the solder bumps 6.

[0016] The outer casing 2 further holds therein a rewiring layer 7 electrically connected to each of the second external terminals 4 and the first semiconductor element 5, and a plurality of second semiconductor elements 8 mounted above the rewiring layer 7 and electrically connected to the rewiring layer 7. In the first embodiment, a flip-chip type second semiconductor element 8 is exemplified, but this is not limiting and may be a surface-mount type electronic component, including a wire-bonding type. The plurality of second semiconductor elements 8 may be of different types. As described above, the outer casing 2 is formed from resin and holds the first external terminals 3, the second external terminals 4, the first semiconductor element 5, the rewiring layer 7, and the second semiconductor element 8. The first semiconductor element 5 is connected to the second semiconductor element 8 and / or the second external terminal 4 via the rewiring layer 7.

[0017] The redistribution layer 7 includes an insulating layer 9 consisting of a first insulating layer 9a and a second insulating layer 9b laminated on the first insulating layer 9a. The insulating layer 9 is formed by curing a polyimide resin that has been applied by, for example, a conventional spin coating method. The second insulating layer 9b (the upper surface 7a, which is the first surface of the redistribution layer 7) is provided with a plurality of electrode portions (electrode pads) 10. Solder bumps 11 provided on electrode pads 12 of the second semiconductor element 8 are bonded to the electrode portions 10. In other words, the second semiconductor element 8 is mounted on the redistribution layer 7 with its functional surface facing the redistribution layer 7.

[0018] The rewiring layer 7 has a rewiring portion 14 electrically connected to the electrode pads 12 and the second external terminals 4 of the second semiconductor element 8, and to the electrode pads 13 of the first semiconductor element 5. The rewiring portion 14 is formed by, for example, copper plating.

[0019] Next, a method for manufacturing the semiconductor package 1 will be described. First, as shown in FIG. 2(a), first external terminals 3 and second external terminals 4 are disposed as heat dissipation electrodes on the upper surface of a support 50 made of a metal material (ST (step) 1: external terminal disposing step). The second external terminals 4 are disposed on the support 50 in a matrix, with multiple terminals arranged vertically and horizontally, corresponding to the arrangement of the solder bumps 6 of the semiconductor package 1 to be manufactured. The number and arrangement of the solder bumps 6 are not particularly limited. The support 50 in the first embodiment is made of, for example, stainless steel (e.g., SUS430). The support 50 is preferably a plate-shaped member.

[0020] As shown in FIG. 2(a), a gold plating film (gold film) 15 is formed on the lower surface of each of the first external terminal 3 and the second external terminal 4, which are mounted on the upper surface of the support 50. The material of the film to be formed may be silver, tin, or palladium, in addition to gold. The formation of the gold plating film (gold film) 15 is optional and not essential. The first external terminal 3 has a flange 16a at its upper end. The second external terminal 4 also has a flange 16b at its upper end. The flanges 16a and 16b are on the lower surfaces of the first external terminal 3 and the second external terminal 4, respectively, and have an inner diameter larger than the surface that contacts the support 50. The formation of these flanges 16a and 16b is optional and not essential.

[0021] A method for installing the first external terminals 3 and the second external terminals 4 on the upper surface of the support 50 will be described. First, a resist is applied to the upper surface of the support 50, and holes (openings) are formed at the locations where the first external terminals 3 and the second external terminals 4 will be installed by exposure and development. Then, gold plating is applied to the bottom of the holes, and nickel is grown within the holes by plating. The nickel is grown by plating beyond the thickness of the resist, spreading over the upper surface of the resist, thereby forming flanges 16a and 16b. The resist is then removed, leaving the first external terminals 3 and the second external terminals 4 installed on the support 50, with a gold plating film (gold film) 15 applied to the underside and flanges 16a and 16b with inner diameters larger than the surface in contact with the support 50. Copper may be used instead of nickel.

[0022] 2(b), a suction nozzle 17 provided in a semiconductor element mounting device (not shown) is used to mount the first semiconductor element 5 on the first external terminals 3 (ST2: first semiconductor element mounting step). That is, the first semiconductor element 5 is sucked from the functional surface side by the suction nozzle 17, and the first semiconductor element 5 is aligned above the first external terminals 3 to which bonding paste has been previously supplied, and then the suction nozzle 17 is lowered (arrow a). Once the first semiconductor element 5 has been placed on the first external terminals 3, suction by the suction nozzle 17 is released and the suction nozzle 17 is raised.

[0023] 2(c), a first molding device (not shown) is used to apply a resin (thermosetting resin) molding to the upper surface of the support 50, thereby forming a first outer body 18 that holds (in other words, seals) the first external terminals 3, the second external terminals 4, and the first semiconductor element 5 therein (ST3: first molding step). The first outer body 18 constitutes the lower portion of the outer body 2.

[0024] When the first outer casing 18 is formed on the upper surface of the support 50, the thermosetting resin is heated and put into a fluid state, flows under the flanges 16a, 16b of the first external terminal 3 and the second external terminal 4, and is thermally cured in that state. Therefore, after the thermosetting resin is thermally cured, the flanges 16a, 16b of the first external terminal 3 and the second external terminal 4 are sandwiched above and below by the first outer casing 18.

[0025] 2(d), a laser via processing device (not shown) is used to perform laser via processing on the first outer shell 18 to form via holes 19 (ST4: via hole forming step). As a result, the electrode pads 13 formed on the respective upper surfaces of the first external terminal 3 and the second external terminal 4 and on the upper surface (functional surface) of the first semiconductor element 5 are exposed upward.

[0026] 5(a), a copper sputtering device (not shown) is used to perform copper sputtering on the upper surface of the first outer casing 18 (ST5: copper sputtering step). As a result, a copper sputtered film (copper film) 20 is formed on the upper surface of the first outer casing 18, including the upper surfaces of the electrode pads 13 of the first semiconductor element 5 and the upper surfaces of the second external terminals 4.

[0027] 5(b), a plating device (not shown) is used to perform copper plating on the upper surface of the copper sputtered film 20 (ST6: copper plating step). As a result, a copper-plated film (copper film) 21 is formed on the upper surface of the copper sputtered film 20. Next, as shown in FIG. 5(c), a resist 22 is applied by a resist application device (not shown), exposed by a resist exposure device (not shown), and developed, thereby forming a resist 22 in an area including the inside of the via hole 19 and the periphery of the via hole 19 (ST7: resist formation step).

[0028] Next, as shown in FIG. 6(a), for example, an etching apparatus (not shown) is used to etch the copper sputtered film 20 and the copper plated film 21 using the resist 22 as a mask (ST8: etching step). As a result, the copper sputtered film 20 and the copper plated film 21 are removed except for the area including the inside of the via hole 19 and the periphery of the via hole 19 (resist formation area). Next, as shown in FIG. 6(b), the resist 22 is removed by cleaning using a resist cleaning apparatus (not shown) (ST9: resist removal step). As a result, a copper thin film layer is formed on the inner wall of the via hole 19 and the periphery of the via hole 19, with the copper plated film 21 laminated on the upper surface of the copper sputtered film 20.

[0029] Next, as shown in Figure 3(a), a redistribution layer 7 electrically connected to the second external terminal 4 and the first semiconductor element 5 is formed on the upper surface of the first outer body 18 by a conventionally known process (e.g., spin coating) (ST10: redistribution layer formation step). On the upper surface of the redistribution layer 7, a mounting region 23 for mounting the second semiconductor element 8 and a plurality of electrodes 10 electrically connected to the second semiconductor element 8 mounted on the mounting region 23 are formed. For convenience, the redistribution layer 7 is illustrated simply in Figures 3 and 4. The redistribution layer is also illustrated simply in Figures 7 and 8.

[0030] In the rewiring layer formation process, plating (not shown) is applied to the upper surface of the electrode portion 10. This plating consists of a nickel plating film applied to the surface of the electrode portion 10 and a gold plating film applied to the surface of the nickel plating film.

[0031] The portion of the semiconductor package 1 manufactured by the end of this rewiring layer forming process forms the base portion of the semiconductor package 1 and includes a support 50, a first external terminal 3 and a second external terminal 4 mounted on the support 50, a first semiconductor element 5 mounted on the first external terminal 3, a first outer casing 18 formed from resin (thermosetting resin) and holding the first external terminal 3, the second external terminal 4, and the first semiconductor element 5, and a rewiring layer 7 on the upper surface of the first outer casing 18 and electrically connected to the second external terminal 4 and the first semiconductor element 5. The base substrate 1A, which is the portion forming the base of this semiconductor package 1, corresponds to the substrate in the manufacturing process of a conventionally known semiconductor package with a substrate.

[0032] 3(b), a bonding tool 24 included in a bonding apparatus (not shown) is used to mount (bond) a second semiconductor element 8 on the rewiring layer 7, and electrically connect the second semiconductor element 8 to the second external terminals 4 via the rewiring layer 7 (ST11: second semiconductor element connection step). That is, after the second semiconductor element 8, with its functional surface facing downward, is picked up by the bonding tool 24, the bonding solder bumps 11 provided on the lower surface of the second semiconductor element 8 are aligned above the electrode portions 10 provided on the upper surface of the rewiring layer 7, and the bonding tool 24 is then lowered (arrow b). This bonds the solder bumps 11 and the electrode portions 10 together.

[0033] Once the second semiconductor elements 8 are mounted on the rewiring layer 7, the bonding tool 24 is raised. That is, in this step (ST11), the second semiconductor elements 8 are mounted on the rewiring layer 7 and electrically connected to each other at the same time. The multiple second semiconductor elements 8 are picked up individually by the bonding tool 24 and mounted in predetermined mounting areas 23.

[0034] Next, as shown in FIG. 3(c), a second molding device (not shown) is used to mold the upper surface of the first outer casing 18 with resin (thermosetting resin) to form a second outer casing 25. As a result, an outer casing 2 consisting of the first outer casing 18 and the second outer casing 25 is formed, and the rewiring layer 7 and the second semiconductor element 8 are sealed by the second outer casing 25 (ST12: second molding step). That is, in this step, the upper surface of the first outer casing 18 is molded to form the second outer casing 25 that holds the rewiring layer 7 and the second semiconductor element 8. The thermosetting resin used in this second molding step is the same (same type) as the thermosetting resin used when forming the first outer casing 18 in the first molding step (ST3). As a result, the entire outer casing 2 is made of the same material. In this step (ST12), it is not necessary to cover the entire redistribution layer 7 with the second outer body 25, and molding may be applied only to the area necessary for resin-sealing the second semiconductor element 8. That is, in this step (ST12), molding is applied to the upper surface of the first outer body 18, thereby covering at least a portion of the redistribution layer 7 and the second semiconductor element 8.

[0035] 3(d), the support 50 is peeled off and removed from the underside of the first outer body 18 (underside 2a of the outer body 2) (ST13: support removal step). This exposes the lower ends (undersides) of the first external terminal 3 and the second external terminal 4 on the underside of the first outer body 18. That is, in this step, the support 50 is removed from the underside of the first outer body 18, exposing the first external terminal 3 and the second external terminal 4 (gold plating film (gold film) 15) on the underside of the first outer body 18.

[0036] As described above, when the first outer casing 18 is formed on the upper surface of the support body 50 in the first molding step (ST3), the thermosetting resin flows under the flanges 16a, 16b of the first external terminal 3 and the second external terminal 4 placed on the upper surface of the support body 50 and hardens, so that the flanges 16a, 16b are sandwiched above and below by the first outer casing 18. Therefore, when the support body 50 is peeled off from the outer casing 2, the flanges 16a, 16b act as stoppers, preventing the first external terminal 3 and the second external terminal 4 from slipping out of the outer casing 2 (first outer casing 18).

[0037] 4, a bump forming device (not shown) is used to form solder bumps 6 on each of the first external terminals 3 and the second external terminals 4 exposed on the lower surface 2a of the outer casing 2 (ST14: bump forming step). This completes the semiconductor package 1, which has solder bumps 6 on the lower surface 2a of the outer casing 2 that holds (seals) the first external terminals 3, the second external terminals 4, the rewiring layer 7, the first semiconductor element 5, and the second semiconductor element 8 therein (also see FIG. 1).

[0038] 7, an example of a semiconductor package 1 mounted on a product such as a portable communication terminal such as a smartphone or a notebook personal computer will be described. A motherboard (substrate board) 26 provided in the product has a first surface 26a on which a plurality of electrodes 27 for external input / output and an electrode 28 for heat dissipation are provided. An electrode 29 is provided on a second surface 26b opposite to the first surface 26a of the motherboard 26, at a position facing the electrode 28 for heat dissipation. A via 30 electrically connected to the electrode 28, 29 is provided in the motherboard 26 so as to penetrate the motherboard 26 in the thickness direction (arrow c).

[0039] Electrode section 29 provided on motherboard 26 is joined to product housing 32 made of a metal material such as aluminum via grease 31. This allows heat to be dissipated to housing 32 via motherboard 26.

[0040] The semiconductor package 1 is mounted on a first surface 26a of a motherboard 26. More specifically, the solder bumps 6 formed on the first external terminals 3 are bonded to electrode portions 28 for heat dissipation formed on the first surface 26a of the motherboard 26. Furthermore, the solder bumps 6 formed on the second external terminals 4 are bonded to electrode portions 27 for external input / output formed on the first surface 26a of the motherboard 26. Therefore, heat generated from the first semiconductor element 5 is dissipated to the housing 32 through the first external terminals 3, the electrodes 28 and 29, and the vias 30. This makes it possible to efficiently dissipate heat from the first semiconductor element 5 in a compact configuration.

[0041] As described above, the manufacturing method of the semiconductor package 1 according to the first embodiment enables a semiconductor package 1 called a FOWLP to compactly arrange multiple semiconductor elements at different heights while improving the heat dissipation of the first semiconductor element 5. Furthermore, in the semiconductor package 1 in which the entire outer casing 2 encapsulating the redistribution layer 7, the first semiconductor element 5, and the second semiconductor element 8 is formed from the same (same type) thermosetting resin, there is no difference in the thermal expansion coefficient between the top and bottom surfaces of the outer casing 2, making it less susceptible to warping due to heat. Therefore, even if the outer casing 2 is subjected to thermal changes after being mounted on the motherboard 26, defects such as the solder bumps 6 peeling off from the motherboard 26 are less likely to occur. Furthermore, because the outer casing 2 is supported by a hard support 50 made of a metal material until just before the solder bumps 6 are formed on the bottom surface 2a, processing is easy, and the final size of the semiconductor package 1 can be made extremely thin.

[0042] Furthermore, in the semiconductor package 1 manufactured by the manufacturing method for the semiconductor package 1 according to the first embodiment, as described above, the flanges 16a, 16b act as retainers for the first external terminals 3 and the second external terminals 4, preventing the first external terminals 3 and the second external terminals 4 from slipping out of the outer casing 2 (first outer casing 18). As a result, even after the solder bumps 6 are formed, the first external terminals 3 and the second external terminals 4 do not slip out downward from the outer casing 2. For this reason, the solder bumps 6 are less likely to fall out of the outer casing 2, and a semiconductor package 1 with high structural reliability can be obtained.

[0043] Next, application examples of the semiconductor package 1 will be described with reference to Figures 8(a) and (b). Figures 8(a) and (b) show a substrate 1Aa (electronic circuit board) for mounting electronic components, in which the support 50 has been removed from the base substrate 1A shown in Figure 3(a). In Figure 8(a), the lower ends of the first external terminal 3 and the second external terminals 4a, 4b sealed in the first outer casing 18 (outer casing 2) are exposed from the lower surface 18a, which is the first surface of the first outer casing 18.

[0044] A first electronic component 40, which is a passive element such as a capacitor, is connected to a second external terminal 4a exposed from a bottom surface 18a, which is the first surface of the first outer casing 18. Similarly, a lead 41a of a second electronic component 41, which is a semiconductor package component, is connected to a second external terminal 4b exposed from the bottom surface 18a.

[0045] The upper surface 7a of the rewiring layer 7, which is arranged on the upper surface 18b (the second surface opposite to the first surface) of the first outer body 18, is provided with an electrode portion 10a that is wire-bonded to a third electronic component 42 such as a bare chip, and an electrode portion 10b that is connected to a fourth electronic component 43 that is a passive element such as a capacitor.

[0046] The third electronic component 42 is mounted by COB (Chip On Board). That is, after the third electronic component 42 is mounted on the rewiring layer 7, the third electronic component 42 and the electrode portion 10a are connected with wires 44 by a wire bonding device (not shown). Thereafter, the third electronic component 42 and the wires 44 are sealed with resin 45.

[0047] The first electronic component 40, the second electronic component 41, and the fourth electronic component 43 are mounted by SMT (Surface Mount Technology). That is, after solder 47 is supplied to the second external terminals 4a, 4b and the electrode portions 10b by screen printing or the like, each electronic component is mounted by a mounting head (not shown). In addition, the first outer casing 18 (outer casing 2) and the rewiring layer 7 each have a mounting region 48 where the electronic components (first to fourth electronic components 40, 41, 42, 43) are mounted.

[0048] In this way, the substrate 1Aa can be used as an electronic component mounting substrate, allowing electronic components to be mounted on both the lower surface 18a of the first outer casing 18 and the first surface 7a of the rewiring layer 7. That is, the substrate 1Aa incorporating the first semiconductor element 5 can be used as an electronic circuit board for double-sided mounting, and high-density mounting can be achieved in a limited space. Note that, as shown in FIG. 8(b), the multiple electronic components mounted on the substrate 1Aa may be limited to electronic components mounted by SMT (first and second electronic components 40, 41, fourth and fifth electronic components 43, 49).

[0049] (Embodiment 2) Next, a second embodiment of the present invention will be described with reference to FIGS. 9 and 10. The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor package 100 in the second embodiment differs from the first embodiment in that a metal pillar 33 is provided on one second external terminal 4 (on the left side of the drawing). That is, a metal pillar 33 formed in a pillar shape is provided on the upper surface of one second external terminal 4. Copper, which has good conductivity, is preferable as the metal used for the pillar 33, but gold, nickel, silver, etc. may also be used. The pillar 33 may be any element having electrodes on both sides. That is, the second external terminal 4 is connected to the rewiring layer 7 via an element (pillar 33) having electrodes on both a first surface 33a and a second surface 33b opposite the first surface 33a.

[0050] In the method for manufacturing the semiconductor package 100, first, as shown in FIG. 10(a), the first external terminal 3 and the second external terminal 4, each having a flange 16a, 16b formed thereon, are placed on the upper surface of the support 50. Next, as shown in FIG. 10(b), a pillar 33 is formed on one of the second external terminals 4. The pillar 33 can be formed, for example, by a plating method. That is, in the second embodiment, after the external terminal placement step (ST1), the pillar 33 is formed on the second external terminal 4 (pillar formation step). Here, the pillar 33 is formed so that the height of the upper surface of the pillar 33 is approximately the same as the height of the upper surface of the first semiconductor element 5. The pillar 33 may be formed on all of the second external terminals 4.

[0051] 10(c), a suction nozzle (not shown) is used to mount the first semiconductor element 5 on the first external terminal 3. Then, as shown in Fig. 10(d), a thermosetting resin is molded onto the upper surface of the support 50 to form a first outer body 18 that holds the first external terminal 3, the second external terminal 4, the first semiconductor element 5, and the pillars 33. That is, the first molding step (ST3) is performed with the element (pillars 33) placed on the second external terminal 4.

[0052] 10(e), laser via processing is performed on the first outer body 18 to form via holes 19, so that the electrode pads 13 formed on the upper surfaces of the second external terminals 4, the upper surfaces of the pillar portions 33, and the upper surface of the first semiconductor element 5 are exposed upward. Thereafter, the same processes as those after the copper sputtering process (ST5) described in the first embodiment are carried out.

[0053] The present invention is not limited to the above-described first and second embodiments, and various modifications are possible without departing from the spirit of the invention. For example, in the external terminal installation step (ST1), a plurality of first external terminals 3 may be installed according to the number of first semiconductor elements 5 to be sealed in the first outer casing 18. In such a case, in the first semiconductor element mounting step (ST2), two or more first semiconductor elements 5 are mounted on the first external terminals 3. Furthermore, the support body 50 may be made of a metal material other than stainless steel (e.g., copper). Furthermore, the first semiconductor element 5 and the second semiconductor element 8 in the first and second embodiments are conceptually intended to broadly include electronic circuit components (electronic components). [Industrial Applicability]

[0054] The present invention provides a semiconductor package manufacturing method and a semiconductor package that can improve the heat dissipation of semiconductor elements while compactly arranging multiple semiconductor elements in a semiconductor package called FOWLP. [Explanation of symbols]

[0055] 1,100 semiconductor packages 1Aa substrate 2. Outer body 3 First external terminal 4 Second external terminal 5. First semiconductor element 7 Redistribution layer 8 Second semiconductor element 18 First outer shell 25 Second outer shell 33 Pillar section 40 First Electronic Component 41 Secondary Electronic Components 42 Third Electronic Component 43 The fourth electronic component 49 The fifth electronic component 50 Support

Claims

1. an external terminal installation step of installing a first external terminal and a second external terminal as heat dissipation electrodes on the upper surface of the support; a first semiconductor element mounting step of mounting a first semiconductor element on the first external terminal; a first molding step of forming a first outer body that holds the first external terminals, the second external terminals, and the first semiconductor element by molding an upper surface of the support with resin; a rewiring layer forming step of forming a rewiring layer including an insulating layer on an upper surface of the first outer body, the rewiring layer being connected to the second external terminals and the first semiconductor element; a second semiconductor element connecting step of mounting a second semiconductor element on the rewiring layer and connecting the second semiconductor element to the second external terminal via the rewiring layer; a second molding process of forming a second outer body that covers the entire redistribution layer including the insulating layer and the second semiconductor element by applying molding to an upper surface of the first outer body; a support removing step of removing the support from the lower surface of the first outer body to expose each of the first external terminal and the second external terminal on the lower surface of the first outer body, the rewiring layer includes a rewiring portion connected to the first semiconductor element, the second semiconductor element, and the second external terminal; the insulating layer includes a first insulating layer and a second insulating layer stacked on the first insulating layer; In the rewiring layer forming step, the rewiring portion is formed to be covered with the first insulating layer and the second insulating layer.

2. the second external terminal is connected to the rewiring layer via an element having electrodes on a first surface and a second surface opposite to the first surface, 2. The method for manufacturing a semiconductor package according to claim 1, wherein the first molding step is performed with the element attached to the second external terminal.

3. 3. The method for manufacturing a semiconductor package according to claim 1, wherein the first semiconductor element is connected to the second semiconductor element and / or the second external terminal via the rewiring layer.

4. In the external terminal installation step, a plurality of the first external terminals are installed, 4. The method for manufacturing a semiconductor package according to claim 1, wherein in the first semiconductor element mounting step, two or more first semiconductor elements are mounted on a plurality of first external terminals.

5. a first external terminal as a heat dissipation electrode; a second external terminal; a first semiconductor element mounted on the first external terminal; a rewiring layer including an insulating layer connected to each of the second external terminals and the first semiconductor element; a second semiconductor element mounted on the rewiring layer and connected to the second external terminal via the rewiring layer; an outer shell formed from a resin and holding the first external terminal, the second external terminal, the first semiconductor element, the rewiring layer, and the second semiconductor element; the outer shell encapsulates the entire redistribution layer including the insulating layer; the rewiring layer includes a rewiring portion connected to the first semiconductor element, the second semiconductor element, and the second external terminal; the insulating layer includes a first insulating layer and a second insulating layer stacked on the first insulating layer; The rewiring portion is formed by being covered with the first insulating layer and the second insulating layer.

6. The semiconductor package of claim 5 , wherein the first external terminal and the second external terminal are exposed from a first surface of the outer casing.

Images