Semiconductor device manufacturing method

Abstract

To improve the reliability of a semiconductor device.SOLUTION: A method for manufacturing a semiconductor device includes forming a trench TR1 on a semiconductor substrate SUB, forming a first insulation film IF1 inside the trench TR1 and on an upper surface (TS) of the semiconductor substrate SUB, implanting ions into the insulation film IF1, thinning the thickness of the insulation film IF1 by etching the insulation film, and forming a conductive film (CF1) inside the trench TR1 via the insulation film IF1. In a plan view, the trench TR1 extends in a Y direction. Ions are implanted in a direction inclined at a prescribed angle from an extension direction of a normal line 10 with respect to the upper surface (TS) of the semiconductor substrate SUB.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a gate electrode and a field plate electrode inside a trench and a manufacturing method thereof. [Background technology]

[0002] Semiconductor devices equipped with semiconductor elements such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) employ a trench gate structure in which a gate electrode is embedded inside a trench. One type of trench gate structure is a split gate structure in which a field plate electrode is formed at the bottom of the trench and a gate electrode is formed at the top of the trench. The field plate electrode is electrically connected to the source electrode. This field plate electrode extends the depletion layer in the drift region, thereby enabling the drift region to be highly concentrated and the resistance of the drift region to be reduced.

[0003] For example, Patent Document 1 discloses a semiconductor device that employs a split gate structure having a gate electrode and a field plate electrode. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-199109 Summary of the Invention [Problem to be solved by the invention]

[0005] According to the research of the present inventors, it has been found that when a conductive film that forms the base of a field plate electrode is deposited, voids called seams are likely to occur in the conductive film, and that these voids can cause various problems. Figures 25 to 27 show a semiconductor device that is an example of research conducted by the present inventors, showing the manufacturing process before and after the formation of the field plate electrode. The problems that arise in the example of research will be explained below using Figures 25 to 27. The example of research and its problems are not previously known knowledge, but are new findings discovered by the present inventors.

[0006] 25, in the split gate structure, first, a trench TR1 is formed in a semiconductor substrate SUB. Next, an insulating film IF1 for insulating the semiconductor substrate SUB from the field plate electrode is formed inside the trench TR1. The insulating film IF1 is a silicon oxide film formed by a CVD (Chemical Vapor Deposition) method.

[0007] When the insulating film IF1 is formed by the CVD method, the thickness of the insulating film IF1 tends to be thick at the top (opening) of the trench TR1, and the insulating film IF1 is likely to overhang. For example, the thickness T4 of the insulating film IF1 at the position of the upper surface of the semiconductor substrate SUB is thicker than the thickness T3 of the insulating film IF1 at a position halfway between the upper surface of the semiconductor substrate SUB and the deepest part of the trench TR1. Note that the "thickness" referred to here is the thickness based on the side surface (inner wall surface) of the trench TR1, not the bottom surface of the trench TR1.

[0008] As shown in FIG. 26, a conductive film CF1 for a field plate electrode is deposited inside trench TR1 by CVD. The conductive film CF1 is, for example, an n-type polycrystalline silicon film. If the insulating film IF1 has an overhanging shape, the conductive film CF1 is likely to be poorly filled. In other words, voids 20 are likely to occur in the conductive film CF1.

[0009] 27 shows how the conductive film CF1 is processed to form the field plate electrode FP while the void 20 is still present. First, the conductive film CF1 formed outside the trench TR1 is removed, and then the conductive film CF1 is set back by etching, thereby forming the field plate electrode FP. Next, the insulating film IF1 formed outside the trench TR1 is removed by wet etching, and the insulating film IF1 inside the trench TR1 is set back. Next, a gate insulating film GI is formed inside the trench TR1 on the insulating film IF1 by thermal oxidation, and an insulating film IF2 is formed on the surface of the field plate electrode FP exposed from the insulating film IF1.

[0010] Here, since the conductive film CF1 is etched while voids 20 are present, the upper part of the field plate electrode FP is likely to have an abnormal shape. Furthermore, the insulating film IF2 is formed along the voids 20. This causes volume expansion inside the field plate electrode FP, and stress acts from the insulating film IF2 to the outside of the trench TR1. This stress is particularly likely to act near the corners of the trench TR1. Therefore, crystal defects 30 are likely to occur in the semiconductor substrate SUB located near the corners of the trench TR1. If a large number of these crystal defects 30 occur, they will become leak paths, causing a decrease in the breakdown voltage of the MOSFET.

[0011] 27, a gate electrode is formed on the field plate electrode FP via the insulating film IF2. If a void 20 is formed, the upper part of the field plate electrode FP is likely to be processed into a protrusion, and since an electric field tends to concentrate in such a protrusion, the insulation resistance between the field plate electrode FP and the gate electrode is likely to deteriorate.

[0012] The main object of the present application is to solve the problems of the study example and improve the reliability of the semiconductor device by suppressing the occurrence of voids 20. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0013] A brief summary of a representative embodiment of the present invention will be given below.

[0014] A method for manufacturing a semiconductor device according to one embodiment includes the steps of: (a) preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) forming a first trench in the upper surface of the semiconductor substrate; (c) forming a first insulating film inside the first trench and on the upper surface of the semiconductor substrate; (d) performing a first ion implantation into the first insulating film; (e) after step (d), thinning the first insulating film by etching the first insulating film; and (f) after step (e), forming a first conductive film inside the first trench through the first insulating film. Here, the first trench extends in a first direction in a plan view, and in step (d), the first ion implantation is performed in a direction tilted at a first angle from a direction normal to the upper surface of the semiconductor substrate in a cross-sectional view.

[0015] According to one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, a first trench formed in the upper surface of the semiconductor substrate so as to extend in a first direction in a plan view, a field plate electrode formed in the first trench at a lower portion of the first trench, and a gate electrode formed in the first trench at an upper portion of the first trench and electrically insulated from the field plate electrode, wherein a portion of the field plate electrode is formed not only in the lower portion of the first trench but also in the upper portion of the first trench and forms a contact portion for the field plate electrode, and in a cross-sectional view, a width of the contact portion at the upper surface of the semiconductor substrate is wider than a width of the contact portion at a position halfway between the upper surface of the semiconductor substrate and the deepest portion of the first trench. [Effects of the Invention]

[0016] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] 1 is an enlarged plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 3] 1 is an enlarged plan view showing a main part of a semiconductor device according to a first embodiment. [Figure 4] 1 is a cross-sectional view showing a semiconductor device in a first embodiment. [Figure 5] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device in the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view showing a manufacturing process following FIG. 5. [Figure 7] 7A to 7C are cross-sectional views showing a manufacturing process following FIG. 6. [Figure 8] 8 is a cross-sectional view showing a manufacturing process following FIG. 7. [Figure 9] 9 is a cross-sectional view showing a manufacturing process following FIG. 8. [Figure 10] 10 is a cross-sectional view showing a manufacturing process following FIG. 9. [Figure 11] 11 is a cross-sectional view showing a manufacturing process following FIG. 10. [Figure 12] 12 is a cross-sectional view showing a manufacturing process following FIG. 11. [Figure 13] 13 is a cross-sectional view showing a manufacturing process following FIG. 12. [Figure 14] 14 is a cross-sectional view showing a manufacturing process following FIG. 13. [Figure 15] 15 is a cross-sectional view showing a manufacturing process following FIG. 14. [Figure 16] 16 is a cross-sectional view showing a manufacturing process following FIG. 15. [Figure 17] FIG. 17 is a cross-sectional view showing a manufacturing process following FIG. [Figure 18] 18 is a cross-sectional view showing a manufacturing process following FIG. 17. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing process following FIG. [Figure 20] 19A to 19C are cross-sectional views showing the manufacturing process following FIG. [Figure 21] 10 is an enlarged plan view showing a manufacturing process of a semiconductor device in accordance with a second embodiment. FIG. [Figure 22] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a third embodiment. [Figure 23] 10A to 10C are cross-sectional views showing a manufacturing process of a semiconductor device according to a modified example. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing process following FIG. 23. [Figure 25] 1A to 1C are cross-sectional views showing a manufacturing process of a semiconductor device in a study example. [Figure 26] FIG. 26 is a cross-sectional view showing a manufacturing process following FIG. 25. [Figure 27] FIG. 27 is a cross-sectional view showing a manufacturing process following FIG. 26. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0019] The X, Y, and Z directions described herein intersect and are perpendicular to one another. In this application, the Z direction is described as the vertical, height, or thickness direction of a structure. In addition, expressions such as "plan view" and "planar view" used in this application mean that the surface formed by the X and Y directions is a "plane," and that this "plane" is viewed from the Z direction.

[0020] (Embodiment 1) <Structure of semiconductor device> 1 to 4, a semiconductor device 100 according to a first embodiment will be described below. The semiconductor device 100 includes a MOSFET with a trench gate structure as a semiconductor element. The MOSFET according to the first embodiment has a split gate structure including a gate electrode GE and a field plate electrode (fixed potential electrode) FP.

[0021] Fig. 1 is a plan view of a semiconductor chip that is a semiconductor device 100. Fig. 1 mainly shows a wiring pattern formed above a semiconductor substrate SUB. Fig. 2 is an enlarged plan view of a main portion of a region 1A shown in Fig. 1. Fig. 3 shows the structure below Fig. 2, illustrating the structure of a trench gate formed in the semiconductor substrate SUB.

[0022] As shown in FIG. 1, most of the semiconductor device 100 is covered with a source electrode (fixed potential supply wiring) SE. A gate wiring GW is provided along the periphery of the semiconductor device 100 and surrounds the source electrode SE in a plan view. Although not shown here, the source electrode SE and gate wiring GW are covered with a protective film such as a polyimide film. An opening is provided in a part of the protective film, and the source electrode SE and gate wiring GW exposed in the opening become a source pad SP and a gate pad GP. External connection members such as wires or clips (copper plates) are connected to the source pad SP and the gate pad GP, thereby electrically connecting the semiconductor device 100 to another semiconductor chip or a wiring board.

[0023] The semiconductor device 100 also includes a cell region CR and an outer periphery region OR that surrounds the cell region CR in a plan view. Major semiconductor elements such as multiple MOSFETs are formed in the cell region CR. The outer periphery region OR is used to connect the gate electrode GE to the gate wiring GW and to form a trench TR2 that functions as a termination region.

[0024] The positions of the holes CH1 to CH4 shown in Fig. 3 correspond to the positions of the holes CH1 to CH4 shown in Fig. 2. As shown in Fig. 3, in the cell region CR, the trenches TR1 extend in the Y direction and are adjacent to each other in the X direction. The width of each trench TR1 in the X direction is, for example, not less than 1.5 μm and not more than 1.8 μm. Furthermore, the trenches TR1 are spaced apart from each other in the X direction at intervals of not less than 0.7 μm and not more than 1.0 μm.

[0025] Inside the trench TR1, a field plate electrode FP is formed below (at the bottom) the trench TR1, and a gate electrode GE is formed above (at the top) the trench TR1. The field plate electrode FP and the gate electrode GE extend in the Y direction along the trench TR1.

[0026] A part of the field plate electrode FP forms a contact portion FPa. The field plate electrode FP constituting the contact portion FPa is formed inside the trench TR1 of the cell region CR not only below the trench TR1 but also above the trench TR1.

[0027] A trench (termination trench) TR2 is formed in the outer peripheral region OR. The trench TR2 extends in the Y and X directions so as to surround the cell region CR. The width of the trench TR2 is the same as that of the trench TR1. A field plate electrode FP is formed inside the trench TR2.

[0028] 3, the gate electrode GE, contact portion FPa, and field plate electrode FP inside trench TR2 are exposed. In the peripheral region OR, a hole CH2 is formed on the gate electrode GE, and the gate electrode GE is electrically connected to the gate wiring GW via the hole CH2. In the cell region CR, a hole CH3 is formed on the contact portion FPa, and the contact portion FPa is electrically connected to the source electrode SE via the hole CH3. In the peripheral region OR, a hole CH4 is formed on a part of the field plate electrode FP, and the field plate electrode FP is electrically connected to the source electrode SE via the hole CH4.

[0029] The cross-sectional structure of the semiconductor device 100 will be described below with reference to Fig. 4. Fig. 4 is a cross-sectional view taken along the lines AA and BB shown in Figs.

[0030] First, the basic structure of a MOSFET will be described using the cross section AA in Figure 4. The semiconductor device 100 includes a semiconductor substrate SUB having an upper surface TS and a lower surface BS. The semiconductor substrate SUB has a low-concentration n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. Note that the drift region NV may be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P). In the present application, such a stacked body consisting of an n-type silicon substrate and an n-type semiconductor layer will also be described as the semiconductor substrate SUB.

[0031] A plurality of trenches TR1 are formed in the upper surface TS of the semiconductor substrate SUB, each reaching a predetermined depth from the upper surface TS of the semiconductor substrate SUB. The depth of each trench TR1 is, for example, 5 μm or more and 7 μm or less. The depth of trench TR2 shown in FIG. 3 is also the same as that of trench TR1. Inside trench TR1, a field plate electrode FP is formed below trench TR1 with an insulating film IF1 interposed therebetween, and a gate electrode GE is formed above trench TR1 with a gate insulating film GI interposed therebetween.

[0032] The position of the upper surface of the insulating film IF1 is lower than the position of the upper surface of the field plate electrode FP. The gate insulating film GI is formed inside the trench TR1 on the insulating film IF1. An insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1. In addition, the gate electrode GE is also formed between the field plate electrode FP exposed from the insulating film IF1 and the semiconductor substrate SUB, with the gate insulating film GI and insulating film IF2 interposed therebetween.

[0033] The insulating film IF1 is formed between the semiconductor substrate SUB and the field plate electrode FP. The insulating film IF2 is formed between the gate electrode GE and the field plate electrode FP. The gate insulating film GI is formed between the semiconductor substrate SUB and the gate electrode GE. These insulating films electrically insulate the semiconductor substrate SUB, the gate electrode GE, and the field plate electrode FP from one another.

[0034] The upper surface of the gate electrode GE is slightly recessed from the upper surface TS of the semiconductor substrate SUB. An insulating film IF3 is formed on part of the upper surface of the gate electrode GE so as to be in contact with the gate insulating film GI.

[0035] The gate electrode GE and the field plate electrode FP are made of, for example, a polycrystalline silicon film doped with n-type impurities. The insulating films IF1, IF2, IF3 and gate insulating film GI are made of, for example, a silicon oxide film.

[0036] The thickness of the insulating film IF1 is greater than the thicknesses of the insulating films IF2, IF3, and gate insulating film GI. The thickness of the insulating film IF1 is, for example, 400 nm or more and 600 nm or less. The thickness of each of the insulating film IF2 and the gate insulating film is, for example, 50 nm or more and 80 nm or less. The thickness of the insulating film IF3 is, for example, 30 nm or more and 80 nm or less.

[0037] A p-type body region PB is formed in the semiconductor substrate SUB (specifically, in a position closer to the upper surface than the lower surface BS of the semiconductor substrate SUB) so as to be shallower than the trench TR1. An n-type source region NS is formed in the body region PB. The source region NS has a higher impurity concentration than the drift region NV.

[0038] An n-type drain region ND is formed in the semiconductor substrate SUB on the lower surface BS side of the semiconductor substrate SUB. The drain region ND has a higher impurity concentration than the drift region NV. A drain electrode DE is formed below the lower surface BS of the semiconductor substrate SUB. The drain electrode DE is made of a single-layer metal film such as an aluminum film, a titanium film, a nickel film, a gold film, or a silver film, or a laminated film made by appropriately stacking these metal films.

[0039] An interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB so as to cover the trench TR1. The interlayer insulating film IL is made of, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 700 nm or more and 900 nm or less. The interlayer insulating film IL may be a stacked film of a thin silicon oxide film and a thick silicon oxide film containing phosphorus (PSG: Phospho Silicate Glass film).

[0040] A hole CH1 is formed in the interlayer insulating film IL, reaching the source region NS and the body region PB. A high-concentration diffusion region PR is formed in the body region PB at the bottom of the hole CH1. The high-concentration diffusion region PR has a higher impurity concentration than the body region PB.

[0041] A source electrode SE is formed on the interlayer insulating film IL. The source electrode SE is embedded in the hole CH1. The source electrode SE is electrically connected to the source region NS, the body region PB, and the heavily doped diffusion region PR, and supplies a source potential (fixed potential) to these regions.

[0042] 2 and 3, a hole CH2 is formed in the interlayer insulating film IL, and a gate wiring GW is formed on the interlayer insulating film IL. The hole CH2 reaches the gate electrode GE, and the gate wiring GW is embedded in the hole CH2. The gate wiring GW is electrically connected to the gate electrode GE and supplies a gate potential to the gate electrode GE.

[0043] As shown in the BB cross section in Figure 4, a part of the field plate electrode FP forms a contact portion FPa of the field plate electrode FP. The position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. That is, the position of the upper surface of the insulating film IF1 in the AA cross section is located at a depth of 1.2 μm or more and 1.5 μm or less from the upper surface TS of the semiconductor substrate SUB. The position of the upper surface of the insulating film IF1 in the BB cross section is located at a depth of 50 nm or more and 500 nm or less from the upper surface TS of the semiconductor substrate SUB.

[0044] The position of the upper surface of the contact portion FPa is higher than the position of the upper surface TS of the semiconductor substrate SUB, and is located at a height of 200 nm or more and 400 nm or less from the upper surface TS of the semiconductor substrate SUB.

[0045] A hole CH3 is formed in the interlayer insulating film IL, reaching the contact portion FPa. A source electrode SE is buried in the hole CH3. The source electrode SE is electrically connected to the field plate electrode FP and supplies a source potential to the field plate electrode FP.

[0046] Although not shown here, a field plate electrode FP is also formed inside trench TR2 shown in FIG. 3 with insulating film IF1 interposed therebetween. A hole CH4 is formed in interlayer insulating film IL, reaching a part of field plate electrode FP inside trench TR2. A source electrode SE is buried inside hole CH4. The source electrode SE is electrically connected to field plate electrode FP inside trench TR2 and supplies a source potential to field plate electrode FP inside trench TR2. That is, the cross-sectional view of the location where hole CH4 is located in FIG. 3 is the same as the structure of cross section BB in FIG. 4.

[0047] The source electrode SE and the gate wiring GW are each made of, for example, a barrier metal film and a conductive film formed on the barrier metal film, where the barrier metal film is, for example, a titanium nitride film, and the conductive film is, for example, an aluminum film.

[0048] The source electrode SE and the gate wiring GW may be composed of a plug layer filling the holes CH1 to CH4 and a wiring layer formed on the interlayer insulating film IL. In this case, the wiring layer is composed of the barrier metal film and the conductive film. The plug layer is composed of a stacked film of a barrier metal film such as a titanium nitride film and a conductive film such as a tungsten film.

[0049] <Method of manufacturing a semiconductor device> 5 to 20, the manufacturing steps included in the manufacturing method of the semiconductor device 100 will be described below. In the following description, the cross sections AA and BB in FIG. 4 will be used. As described above, the cross-sectional structures of the trench TR2, the hole CH4, and their surroundings in the outer peripheral region OR are almost the same as the structure of the BB cross section in FIG. 4. The description of the manufacturing steps for these cross-sectional structures is also almost the same as the description of the manufacturing steps for the BB cross section, and therefore detailed description thereof will be omitted.

[0050] The main feature of the manufacturing method of the semiconductor device 100 according to the first embodiment is the manufacturing process for forming the insulating film IF1 and the field plate electrode FP. Such a feature will be explained as appropriate in comparison with the above-mentioned study example.

[0051] First, an n-type semiconductor substrate SUB having an upper surface TS and a lower surface BS is prepared, as shown in Fig. 5. As described above, the n-type semiconductor substrate SUB itself constitutes the drift region NV, but the drift region NV may also be an n-type semiconductor layer grown on an n-type silicon substrate by epitaxial growth while introducing phosphorus (P).

[0052] Next, a trench TR1 is formed in the upper surface TS of the semiconductor substrate SUB. To form the trench TR1, first, for example, a silicon oxide film is formed on the semiconductor substrate SUB by, for example, a CVD method. Next, a resist pattern having an opening is formed on the silicon oxide film by photolithography. Next, the silicon oxide film is patterned by performing an etching process (for example, a dry etching process) using the resist pattern as a mask to form a hard mask HM. Next, the resist pattern is removed by an ashing process. Next, an etching process (for example, a dry etching process) is performed using the hard mask HM as a mask to form the trench TR1 in the semiconductor substrate SUB. Thereafter, the hard mask HM is removed by an etching process (for example, a wet etching process) using a solution containing, for example, hydrofluoric acid.

[0053] In the outer circumferential region OR, the trench TR2 is formed by the same process as that for forming the trench TR1.

[0054] Next, as shown in FIG. 6, an insulating film IF1 made of, for example, a silicon oxide film is formed inside the trench TR1 and on the semiconductor substrate SUB. First, a first silicon oxide film IF1a is formed inside the trench TR1 and on the semiconductor substrate SUB by thermal oxidation. Next, a second silicon oxide film IF1b is formed on the first silicon oxide film IF1a by CVD. The insulating film IF1 includes the first silicon oxide film IF1a and the second silicon oxide film IF1b. The thickness of the first silicon oxide film IF1a is, for example, 100 nm or more and 200 nm or less. The thickness of the second silicon oxide film IF1b is, for example, 300 nm or more and 400 nm or less.

[0055] Although it is possible to form the entire insulating film IF1 by thermal oxidation, in that case, the semiconductor substrate SUB in a wafer state is likely to warp due to stress from the insulating film IF1, which may cause problems in the subsequent manufacturing process. On the other hand, in consideration of improving the interface state between the insulating film IF1 and the semiconductor substrate SUB, it is preferable that the silicon oxide film in contact with the semiconductor substrate SUB be formed by thermal oxidation. Therefore, in the first embodiment, the insulating film IF1 is configured by a stacked film of a first silicon oxide film IF1a that is formed by thermal oxidation and is relatively thin, and a second silicon oxide film IF1b that is formed by CVD and is relatively thick.

[0056] Here, when the CVD method is applied to the formation of the insulating film IF1, the thickness of the insulating film IF1 tends to be large at the top (opening) of the trench TR1, and the insulating film IF1 is likely to have an overhanging shape, as explained in the study example of Fig. 25. In this case, as explained in the study example of Fig. 26, voids 20 are likely to be generated in the conductive film CF1 during the formation of the conductive film CF1.

[0057] <<Step of implanting ions into insulating film IF1>> Therefore, in order to solve the above problem, the inventors of the present application have devised a method of implanting ions into the insulating film IF1 above the trench TR1, partially changing the etching rate of the etching process, and suppressing the overhang.

[0058] Specifically, first, as shown in FIG. 6, ions are implanted into the insulating film IF1. This ion implantation is performed from a direction tilted at a predetermined angle from the direction of extension of a normal 10 to the upper surface TS of the semiconductor substrate SUB (hereinafter referred to as the "normal direction"). Here, a case where two ion implantations are performed is illustrated. The first ion implantation is performed from a direction tilted at an angle θ1 from the normal direction, and the second ion implantation is performed from a direction tilted at an angle θ2 from the normal direction. The angles θ1 and θ2 are different from each other.

[0059] The larger the implantation angle, the easier it is to implant ions into the insulating film IF1 closer to the top (opening) of the trench TR1. By making the implantation angle smaller, ions can be implanted not only near the top of the trench TR1 but also into the insulating film IF1 at a position distant from the top of the trench TR1.

[0060] As the ion species for ion implantation, for example, arsenic (As), phosphorus (P), or boron difluoride (BF2) can be applied. The total implantation dose of ion implantation is 1×10 13 / cm 2 It is preferable that the implantation angles (angle θ1 and angle θ2) of the ion implantation be set within a range of 20 degrees or more and 60 degrees or less.

[0061] Although the example shown here is one in which ion implantation is performed twice, ion implantation may be performed three or more times from different angles. Also, ion implantation does not necessarily have to be performed multiple times, as long as it is performed at least once.

[0062] The etching rate of the etching process differs between the ion-implanted area and the non-ion-implanted area. The ion-implanted area has a higher etching rate than the non-ion-implanted area. The more ions are implanted in the area, the higher the etching rate.

[0063] After the above-described ion implantation into the insulating film IF1, the insulating film IF1 is etched to reduce its thickness. Note that the etching performed on the insulating film IF1 after the ion implantation is an etching process with a higher isotropic component than an anisotropic component. Specifically, for example, a wet etching process using a solution containing hydrofluoric acid is used. As a result, the insulating film IF is etched not only in the thickness direction of the semiconductor substrate SUB (the Z direction shown in FIG. 7 ) but also in the direction along the upper surface TS (or lower surface BS) of the semiconductor substrate SUB (the X direction, horizontal direction shown in FIG. 7 ).

[0064] 7 shows the state of the insulating film IF1 after the etching process. The insulating film IF1 is thin overall, but the thickness of the insulating film IF1 is thinner near the top (opening) TOP of the trench TR1 into which ions have been implanted. For example, in the X direction shown in FIG. 7, the thickness T2 of the insulating film IF1 at the position of the upper surface TS of the semiconductor substrate SUB is thinner than the thickness T1 of the insulating film IF1 at a position halfway between the upper surface TS of the semiconductor substrate SUB and the deepest part of the trench TR1. Therefore, the overhang of the insulating film IF1 is eliminated and the aspect ratio is improved, making it less likely that voids 20 will occur in the conductive film CF1 when the conductive film CF1 is formed in the next step.

[0065] The characteristics of the thickness T1 and the thickness T2 of the insulating film IF1 can be restated as follows, for example. In a cross-sectional view, the trench TR has a bottom surface TR1b and a side surface (inner wall surface) TR1s. Note that the deepest part of the trench TR1 is located in a part of the bottom surface TR1b. That is, the bottom surface TR1b and the side surface TR1s do not intersect with each other at a right angle, but strictly speaking, are rounded as shown in FIG. 7. In a cross-sectional view, the insulating film IF1 has a first portion formed on the side surface TR1s and located at the top (opening) TOP of the trench TR1, and a second portion formed on the side surface TR1s and located closer to the bottom surface TR1b than the top TOP of the trench TR1. The thickness of the first portion is thinner than the thickness of the second portion. Note that the "thickness" referred to here is the thickness based on the side surface TR1s (thickness in the X direction shown in FIG. 7), not the bottom surface TR1b (deepest part).

[0066] For example, the thickness of the first portion corresponds to the thickness T2 of the insulating film IF1, and the thickness of the second portion includes the thickness T1 of the insulating film IF1.

[0067] <<Field plate electrode FP formation process>> After the ion implantation, the insulating film IF1 is etched, and then, as shown in FIGS. 8 to 11, a field plate electrode FP is formed so as to fill the trench TR1 with the insulating film IF1 interposed therebetween.

[0068] First, as shown in FIG. 8, a conductive film CF1 is formed on the insulating film IF1 by, for example, a CVD method. The conductive film CF1 is, for example, an n-type polycrystalline silicon film. At this time, the inside of the trench TR1 is not completely filled with the conductive film CF1. The thickness of the conductive film CF1 is, for example, 200 nm or more and 300 nm or less.

[0069] Next, as shown in FIG. 9, an etching process is performed on the conductive film CF1 to reduce the thickness of the conductive film CF1. Note that, for the etching process performed on the conductive film CF1, an etching process having a larger anisotropic component than isotropic component is used. Since the conductive film CF1 is processed into a sidewall shape inside the trench TR1, the thickness of the conductive film CF1 becomes thinner as it approaches the top of the trench TR1.

[0070] Next, as shown in FIG. 10, a conductive film CF2 is formed, for example, by a CVD method so as to fill the inside of the trench TR1 through the insulating film IF1 and the conductive film CF1. The conductive film CF2 is also formed on the insulating film IF1 outside the trench TR1. The conductive film CF2 is, for example, an n-type polycrystalline silicon film. The thickness of the conductive film CF2 is, for example, 800 nm or more and 1200 nm or less. In the manufacturing process of FIG. 9, since the thickness of the conductive film CF1 becomes thinner as it approaches the top of the trench TR1, voids 20 are less likely to occur in the conductive film CF2 when the conductive film CF2 is formed.

[0071] Next, as shown in FIG. 11, the conductive film CF2 formed outside the trench TR1 is removed by performing, for example, a polishing process using a CMP (Chemical Mechanical Polishing) method or an etching process. In this way, a field plate electrode FP including the conductive film CF1 and the conductive film CF2 formed inside the trench TR1 is formed. At this point, the position of the upper surface of the field plate electrode FP is higher than the position of the upper surface TS of the semiconductor substrate SUB.

[0072] In this way, a field plate electrode FP with suppressed generation of voids 20 can be formed. Note that, even if the ion implantation and the etching process in FIG. 6 are not performed and the thickness of the insulating film IF1 does not satisfy the relationship in FIG. 7 (“T2 < T1”), the method for forming the field plate electrode FP described in FIGS. 8 to 11 is effective as a technique for suppressing the generation of voids 20.

[0073] Next, as shown in FIG. 12, portions of the field plate electrode FP are selectively recessed (cross section AA) so that a portion of the field plate electrode FP remains as the contact portion FPa (cross section BB). First, a resist pattern RP1 is formed to selectively cover the region that will become the contact portion FPa. Next, an etching process (e.g., dry etching process) is performed using the resist pattern RP1 as a mask. This selectively recesses the field plate electrode FP other than the contact portion FPa. After that, the resist pattern RP1 is removed by ashing.

[0074] 13, part of the insulating film IF1 is removed by etching (for example, wet etching). As a result, the insulating film IF1 on the semiconductor substrate SUB is removed, and further, inside the trench TR1, the position of the upper surface of the insulating film IF1 becomes lower than the position of the upper surface of the field plate electrode FP. That is, the insulating film IF1 is recessed. Furthermore, in the region (AA cross section) where the field plate electrode FP is recessed, part of the insulating film IF1 is exposed inside the trench TR1, and therefore, etching of this insulating film IF1 progresses quickly.

[0075] At this point, the position of the upper surface of the insulating film IF1 in contact with the field plate electrode FP other than the contact portion FPa is lower than the position of the upper surface of the insulating film IF1 in contact with the contact portion FPa. Moreover, by removing the insulating film IF1 on the semiconductor substrate SUB, the position of the upper surface of the contact portion FPa is higher than the position of the upper surface TS of the semiconductor substrate SUB.

[0076] Furthermore, since the field plate electrode FP is formed along the shape of the insulating film IF1, the width W2 of the upper part of the contact portion FPa is wider than the width W1 of the lower part of the contact portion FPa, as shown in the BB cross section. For example, in the X direction, the width W2 of the contact portion FPa at the position of the upper surface TS of the semiconductor substrate SUB is wider than the width W1 of the contact portion FPa at a position halfway between the upper surface TS of the semiconductor substrate SUB and the deepest part of the trench TR1.

[0077] 14, a gate insulating film GI made of, for example, a silicon oxide film is formed by thermal oxidation inside the trench TR1 on the insulating film IF1 and on the semiconductor substrate SUB. At the same time, an insulating film IF2 is formed on the upper surface and side surfaces of the field plate electrode FP exposed from the insulating film IF1.

[0078] Next, on the field plate electrode FP that was recessed in the manufacturing process of Figure 12, a conductive film CF3 is formed inside the trench TR1 and on the semiconductor substrate SUB by, for example, a CVD method so as to fill the inside of the trench TR1 (AA cross section). Here, the conductive film CF3 is also formed inside the trench TR1 in which the contact portion FPa is formed (BB cross section). The conductive film CF3 is, for example, an n-type polycrystalline silicon film. The thickness of the conductive film CF3 is, for example, not less than 800 nm and not more than 1200 nm.

[0079] 15, the conductive film CF3 is subjected to an etching process (e.g., dry etching process) to remove the conductive film CF2 formed outside the trench TR1 and form the gate electrode GE inside the trench TR1 (cross section AA). By this etching process, the conductive film CF3 is removed inside the trench TR1 where the contact portion FPa is formed (cross section BB).

[0080] In order to completely remove the conductive film CF3 inside the trench TR1 in which the contact portion FPa is formed and the conductive film CF3 outside the trench TR1, over-etching is performed on the conductive film CF3 in this etching process. As a result, the position of the upper surface of the gate electrode GE becomes slightly lower than the position of the upper surface TS of the semiconductor substrate SUB, as shown in the AA cross section in FIG.

[0081] 16, an insulating film IF3 is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR1. The insulating film IF3 is made of, for example, a silicon oxide film or a silicon nitride film.

[0082] 17, first, an etching process (e.g., a dry etching process) is performed on the insulating film IF3. As a result, the insulating film IF3 is left on the upper surface of part of the gate electrode GE so as to be in contact with the gate insulating film GI (AA cross section). Also, the insulating film IF3 is left on the side surface of the contact portion FPa via the insulating film IF2 (BB cross section).

[0083] 17, a p-type body region PB is formed in the semiconductor substrate SUB by introducing, for example, boron (B) by ion implantation at a position closer to the upper surface TS of the semiconductor substrate SUB than the lower surface BS of the semiconductor substrate SUB. The body region PB is formed to be shallower than the trench TR1. Next, after covering the periphery of the contact portion FPa with a resist pattern, an n-type source region NS is formed in the body region PB by introducing, for example, arsenic (As) by ion implantation. Next, the resist pattern is removed by ashing. Thereafter, the semiconductor substrate SUB is subjected to a heat treatment to diffuse the impurities contained in the source region NS and the body region PB.

[0084] Before the ion implantation of the source region NS and the body region PB, a thin silicon oxide film may be formed as a through film on the semiconductor substrate SUB. This through film may be removed after the ion implantation, or may be left as a part of the interlayer insulating film IL.

[0085] 18, an interlayer insulating film IL is formed on the upper surface TS of the semiconductor substrate SUB by, for example, a CVD method so as to cover the trench TR1. The interlayer insulating film IL is made of, for example, a silicon oxide film. The interlayer insulating film IL may be a stacked film of a thin silicon oxide film formed by a CVD method and a PSG film formed by a coating method.

[0086] Next, holes CH1 to CH4 are formed in the interlayer insulating film IL as shown in Fig. 19. Although the holes CH2 and CH4 are not shown here, they are formed in the same step as the step of forming the hole CH3.

[0087] First, a resist pattern having a pattern that opens the semiconductor substrate SUB in which the source region NS is formed is formed on the interlayer insulating film IL. Next, an etching process (e.g., dry etching process) is performed using the resist pattern as a mask to form a hole CH1 in the interlayer insulating film IL, reaching the source region NS and the body region PB. The bottom of the hole CH1 is located within the body region PB. Next, boron (B), for example, is introduced into the body region PB at the bottom of the hole CH1 by ion implantation, thereby forming a p-type high-concentration diffusion region PR. Thereafter, the resist pattern is removed by ashing.

[0088] Next, a resist pattern is formed on the interlayer insulating film IL, the resist pattern having openings on the gate electrode GE in the peripheral region OR, on the contact portion FPa in the cell region CR, and on the field plate electrode FP in the peripheral region OR. Next, an etching process (e.g., dry etching process) is performed using the resist pattern as a mask to form a hole CH2 in the interlayer insulating film IL that reaches the gate electrode GE, a hole CH3 that reaches the contact portion FPa, and a hole CH4 that reaches the field plate electrode FP in the peripheral region OR. The resist pattern is then removed by ashing.

[0089] It is noted that the step of forming the hole CH1 and the step of forming the holes CH2 to CH4 may be performed in any order.

[0090] 20, a source electrode SE and a gate wiring GW surrounding the source electrode SE in a plan view are formed on the interlayer insulating film IL. First, a laminated film including a barrier metal film made of, for example, a titanium nitride film and a conductive film made of, for example, an aluminum film is formed on the interlayer insulating film IL by sputtering or CVD. Next, the laminated film is patterned to form the source electrode SE and the gate wiring GW.

[0091] The gate wiring GW is buried in the hole CH2 and electrically connected to the gate electrode GE. The source electrode SE is buried in the hole CH1, the hole CH3, and the hole CH4 and electrically connected to the source region NS, the body region PB, the heavily doped diffusion region PR, and the field plate electrode FP.

[0092] Next, although not shown here, a protective film made of, for example, a polyimide film is formed on the source electrode SE and the gate wiring GW by, for example, a coating method. Parts of the protective film are opened to expose the regions of the source electrode SE and the gate wiring GW that will become the source pad SP and the gate pad GP.

[0093] Thereafter, the semiconductor device 100 shown in FIG. 4 is manufactured through the following manufacturing steps. First, the lower surface BS of the semiconductor substrate SUB is polished as necessary. Next, an n-type drain region ND is formed by introducing, for example, arsenic (As) into the lower surface BS of the semiconductor substrate SUB by ion implantation. Next, a drain electrode DE is formed below the lower surface BS of the semiconductor substrate SUB by sputtering.

[0094] <Structural features of semiconductor devices> 8 to 11, in the first embodiment, no void 20 is formed in the field plate electrode FP. Therefore, even if the insulating film IF2 is formed, the problem of crystal defects 30 occurring in the semiconductor substrate SUB located near the corners of the trench TR1 due to volume expansion occurring inside the field plate electrode FP, as in the studied example, is unlikely to occur.

[0095] Furthermore, when voids 20 are formed, the upper portion of field plate electrode FP is likely to be processed into a protruding portion, which causes electric field concentration at such a protruding portion, and this can lead to a problem of deterioration in the dielectric strength between field plate electrode FP and gate electrode GE. In the first embodiment, this problem is also suppressed. Therefore, according to the first embodiment, the problem of a decrease in the breakdown voltage of the MOSFET can be suppressed, and the reliability of semiconductor device 100 can be improved.

[0096] 13, the width W2 of the upper part of the contact part FPa is wider than the width W1 of the lower part of the contact part FPa. This relationship also applies to the final structure shown in FIG.

[0097] 7, the thickness T2 of the insulating film IF1 at the position of the upper surface TS of the semiconductor substrate SUB was thinner than the thickness T1 of the insulating film IF1 at a position halfway between the upper surface TS of the semiconductor substrate SUB and the deepest part of the trench TR1. In FIG. 4, the insulating film IF1 has receded, but a portion of the insulating film IF1 remains, inheriting this relationship. For example, as shown in the B-B cross section of FIG. 4, the thickness of the insulating film IF1 in contact with the contact portion FPa is thinnest at a portion of the insulating film IF1 closest to the upper surface of the contact portion FPa.

[0098] In the first embodiment, the width W2 of the upper portion of the contact portion FPa is increased, which increases the margin for misalignment when forming the hole CH3, making it easier to position the hole CH3 above the contact portion FPa.

[0099] (Embodiment 2) The semiconductor device according to the second embodiment will be described below with reference to Fig. 21. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0100] In the second embodiment, similarly to the first embodiment, in the ion implantation step of Fig. 6, ions are implanted into the insulating film IF1 from directions tilted at a predetermined angle from the normal direction. Furthermore, in the second embodiment, as shown in Fig. 21, in plan view, multiple ion implantations are performed from directions tilted at different angles from the extension direction of the trench TR1 (Y direction). Fig. 21 shows a case where 12 ion implantations IMP1 to IMP12 are performed from directions tilted at different angles from each other in plan view.

[0101] In plan view, if ion implantation is performed in the same direction as the extension direction (Y direction) of the trench TR1, ions will also be implanted into the insulating film IF1 located at the bottom of the trench TR1. As a result, the etching rate of the insulating film IF1 located at the bottom of the trench TR1 will be increased by the etching process (e.g., wet etching process) in the next process, and the thickness of the insulating film IF1 will be locally thin. This may cause problems such as a deterioration in the dielectric strength voltage.

[0102] Furthermore, if the semiconductor device 100 includes a trench TR2 as a termination region in the outer peripheral region OR, such a problem may also occur in the trench TR2. As shown in Fig. 3, the trench TR2 is formed to surround the cell region CR in a plan view, and includes a portion extending in the Y direction and a portion extending in the X direction.

[0103] 21 need to be performed from directions other than the Y direction and the X direction, respectively. In other words, the multiple ion implantations IMP1 to IMP12 are performed from directions other than the extension direction of the trench TR1 and directions other than directions inclined at angles that are multiples of 90 degrees from the extension direction of the trench TR1, respectively.

[0104] As shown in FIG. 3 , the trench TR2 may have a corner TR2a connecting a portion extending in the Y direction with a portion extending in the X direction. The corner TR2a extends in a direction inclined at a 45-degree angle from the Y direction or the X direction in a plan view. While providing the corner TR2a is not essential, if such a corner TR2a is not provided, the portion extending in the Y direction and the portion extending in the X direction will be connected at a right angle. This can easily cause variations in the thickness of the insulating film IF1 or poor embedding of the conductive film CF1 at the right angle. Therefore, to prevent such problems, it is preferable for the trench TR2 to have a corner TR2a.

[0105] When the trench TR2 has a corner portion TR2a, it is necessary to prevent ions from being implanted into the insulating film IF1 located at the bottom of the corner portion TR2a. Therefore, the multiple ion implantations IMP1 to IMP12 in Fig. 21 must be performed in a direction other than the Y direction, a direction other than the X direction, and a direction other than a direction tilted at an angle of 45 degrees from the Y direction or the X direction. In other words, the multiple ion implantations IMP1 to IMP12 are performed in a direction other than the extension direction of the trench TR1 and a direction other than a direction tilted at an angle that is a multiple of 45 degrees from the extension direction of the trench TR1.

[0106] The depths of the ion implantations IMP1 to IMP12 will be described when the multiple ion implantations IMP1 to IMP12 according to the second embodiment are viewed in cross section. For example, assume that the implantation angles of the ion implantations IMP1 to IMP12 in cross section are the same, such as the implantation angle θ1 in FIG. 6. In this case, the ions implanted into the insulating film IF1 at angles inclined by 180 degrees, such as the ion implantations IMP2 and IMP8, will have the same depth.

[0107] Furthermore, for example, the ion implantations IMP1, IMP2, and IMP3 are at different angles in a plan view, and therefore the depths of these ion implantations are different from one another. In the ion implantation IMP1, which has a small inclination angle from the extension direction of the trench TR1, the depth of ions implanted into the insulating film IF1 is the deepest. In the ion implantation IMP3, which has a inclination angle from the extension direction of the trench TR1 close to 90 degrees, the depth of ions implanted into the insulating film IF1 is the shallowest. In the ion implantation IMP2, the depth of ions implanted into the insulating film IF1 is between the depths of the ion implantations IMP1 and IMP3.

[0108] In this way, even if the implantation angle θ1 is the same in cross section, by varying the implantation angle in plan view, the depth distribution of ions implanted into the insulating film IF1 can be controlled. Note that, in addition to performing multiple ion implantations IMP1 to IMP12 at the implantation angle θ1 in Figure 6, multiple ion implantations IMP1 to IMP12 may also be performed at various other implantation angles, such as the implantation angle θ2 in Figure 6. This allows for more detailed control of the depth distribution of ions.

[0109] In the second embodiment, the case where 12 ion implantations IMP1 to IMP12 are performed is exemplified, but the number of ion implantations in the second embodiment is not limited to 12, and can be set to any number as needed.

[0110] (Embodiment 3) The semiconductor device according to the third embodiment will be described below with reference to Fig. 22. In the following description, differences from the first embodiment will be mainly described, and descriptions of points that overlap with the first embodiment will be omitted.

[0111] In the first embodiment, ions are implanted into the insulating film IF1, but in the third embodiment, ions are implanted into the conductive film CF1.

[0112] Fig. 22 shows ion implantation into the conductive film CF1 after the formation of the conductive film CF1 of Fig. 8 and before the etching process of Fig. 9 is performed. The ion species for this ion implantation is preferably an impurity exhibiting n-type conductivity, such as arsenic (As) or phosphorus (P). In other words, the ion species for this ion implantation is preferably an impurity of the same conductivity type as the conductivity type of the field plate electrode FP (conductive film CF1, conductive film CF2).

[0113] Ion implantation into the conductive film CF1 is performed using the same method as ion implantation into the insulating film IF1. That is, as shown in FIG. 22, ion implantation into the conductive film CF1 is performed from a direction tilted at a predetermined angle (angle θ1, angle θ2, etc.) from the normal direction to the upper surface TS of the semiconductor substrate SUB, similar to ion implantation into the insulating film IF1. The larger the implantation angle, the easier it is to implant ions into the conductive film CF1 near the top of the trench TR1. By reducing the implantation angle, ions can be implanted not only near the top of the trench TR1 but also into the conductive film CF1 at a position distant from the top of the trench TR1.

[0114] The etching rate of the etching process shown in FIG. 9 differs between the ion-implanted area and the non-ion-implanted area. The ion-implanted area has a higher etching rate than the non-ion-implanted area. The more ions are implanted in an area, the higher the etching rate.

[0115] 9, the conductive film CF1 located at the top of the trench TR1 becomes thinner than in Embodiment 1. By forming the conductive film CF2 in FIG. 10 in this state, the conductive film CF2 can be easily embedded in the trench TR1 well, and the generation of the void 20 can be further suppressed.

[0116] Furthermore, in the third embodiment, using the same technical concept as in the second embodiment, multiple ion implantations can be performed from directions inclined at different angles from the extension direction (Y direction) of the trench TR1 in a plan view.

[0117] 6 to 11 is effective as a technique for suppressing the generation of voids 20. This also applies to the third embodiment.

[0118] (Variation) A semiconductor device according to a modification of the third embodiment will be described below with reference to Figures 23 and 24. Figures 23 and 24 show how an oxide film is formed on the surface of the conductive film CF1 and then removed after the ion implantation of Figure 22 and before the etching process of Figure 9 is performed.

[0119] As shown in FIG. 23, a thermal oxidation process is performed on the conductive film CF1. This thermal oxidation process forms an oxide film OX1 on the surface of the conductive film CF1. At this time, the ion implantation shown in FIG. 22 is performed on the upper part of the conductive film CF1. That is, the upper part of the conductive film CF1 contains more n-type impurities than the lower part of the conductive film CF1. When a thermal oxidation process is performed in this state, due to the effect of accelerated oxidation, the oxidation progresses faster in areas containing more impurities. Therefore, the oxide film OX1 is formed thicker on the upper part of the conductive film CF1 than on the lower part of the conductive film CF1.

[0120] 24, the oxide film OX1 is removed by etching. The thickness of the remaining conductive film CF1 is thinner above the trench TR1 than below the trench TR1. This etching is performed by wet etching using a solution containing hydrofluoric acid, for example.

[0121] By performing an etching process (e.g., a dry etching process) on the conductive film CF1 in this state, the thickness of the conductive film CF1 located near the upper part of the trench TR1 can be made even thinner than in Fig. 9. Therefore, the conductive film CF2 can be more easily embedded inside the trench TR1, and the occurrence of the void 20 can be further suppressed.

[0122] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention. [Explanation of symbols]

[0123] 100 Semiconductor device 10 Normal 20 void 30 Crystal defects 1A area BS bottom side CF1~CF3 Conductive film CH1~CH4 hole CR Cell Area DE drain electrode FP field plate electrode FPa contact part GE gate electrode GI gate insulating film GP Gate Pad GW Gate wiring HM Hard Mask IF1~IF3 insulating film IF1a First silicon oxide film IF1b Second silicon oxide film IL Interlayer insulating film ND drain region NS Source Region NV drift region OR outer area OX1 oxide film PB body region PR high concentration diffusion region SP sauce pad SUB Semiconductor substrate SE source electrode TOP Top (opening) TR1 trench (trench in the cell area) TR2 Trench (Termination Trench) TR2a corner section TS top surface

Claims

1. (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) forming a first trench in the top surface of the semiconductor substrate; (c) forming a first insulating film inside the first trench and on the top surface of the semiconductor substrate; (d) performing a first ion implantation into the first insulating film; (e) after the step (d), performing an etching process on the first insulating film to reduce the thickness of the first insulating film; (f) after the step (e), forming a first conductive film in the first trench with the first insulating film interposed therebetween; Equipped with the first trench extends in a first direction in a plan view, In the step (d), the first ion implantation is performed in a direction tilted at a first angle from a direction normal to the top surface of the semiconductor substrate in a cross-sectional view; In the step (d), a second ion implantation is performed after the first ion implantation; the first ion implantation is performed in a direction tilted at the first angle from the first direction in a plan view; the second ion implantation is performed in a direction tilted from the first direction to a second angle different from the first angle in a plan view; The semiconductor device has a cell region in which a plurality of MOSFETs are formed, and a peripheral region surrounding the cell region in a plan view, Each of the plurality of MOSFETs the first trench; the first insulating film; a field plate electrode made of the first conductive film; Including, In the step (b), a second trench is formed in the upper surface of the semiconductor substrate located in the peripheral region; the second trench extends in the first direction and in a second direction perpendicular to the first direction in a plan view so as to surround the cell region in a plan view; a first ion implantation step of implanting ions into a semiconductor substrate, the first ion implantation step being performed in a direction other than the first direction and a direction other than a direction inclined at an angle that is a multiple of 90 degrees from the first direction when viewed in a plan view;

2. 2. The method for manufacturing a semiconductor device according to claim 1, The first trench has, in a cross-sectional view, The bottom and The sides and and The first insulating film has, in a cross-sectional view, a first portion formed on the side surface of the first trench and positioned at an opening of the first trench; a second portion formed on the side surface of the first trench and located closer to the bottom surface of the first trench than the opening of the first trench; and After the step (e), the thickness of the first portion is smaller than the thickness of the second portion; A method for manufacturing a semiconductor device, wherein the thickness of each of the first portion and the second portion is a thickness based on the side surface of the first trench, not the bottom surface of the first trench.

3. 2. The method for manufacturing a semiconductor device according to claim 1, the second trench has a corner portion connecting a portion extending in the first direction and a portion extending in the second direction, the corner portion extends in a direction inclined at an angle of 45 degrees from the first direction or the second direction in a plan view, a first ion implantation step of implanting ions into a semiconductor substrate, the first ion implantation step being performed in a direction other than the first direction and a direction other than a direction inclined at an angle that is a multiple of 45 degrees from the first direction when viewed in a plan view;

4. (a) providing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) forming a first trench in the top surface of the semiconductor substrate; (c) forming a first insulating film inside the first trench and on the top surface of the semiconductor substrate; (d) performing a first ion implantation into the first insulating film; (e) after the step (d), performing an etching process on the first insulating film to reduce the thickness of the first insulating film; (f) after the step (e), forming a first conductive film in the first trench with the first insulating film interposed therebetween; Equipped with the first trench extends in a first direction in a plan view, In the step (d), the first ion implantation is performed in a direction tilted at a first angle from a direction normal to the top surface of the semiconductor substrate in a cross-sectional view; The step (f) is (f1) after the step (e), forming the first conductive film on the first insulating film; (f2) after the step (f1), performing an etching process on the first conductive film to reduce the thickness of the first conductive film; (f3) after the step (f2), forming a second conductive film in the interior of the first trench via the first insulating film and the first conductive film so as to fill the interior of the first trench; and The step (f) is (f4) between the step (f1) and the step (f2), implanting ions into the first conductive film from a direction inclined at a fifth angle from a normal direction to the top surface of the semiconductor substrate; The method for manufacturing a semiconductor device further comprises:

5. 5. The method for manufacturing a semiconductor device according to claim 4, The step (f) is (f5) forming an oxide film on the surface of the first conductive film by thermal oxidation treatment between the (f4) step and the (f2) step; (f6) a step of removing the oxide film by etching between the step (f5) and the step (f2); The method for manufacturing a semiconductor device further comprises:

6. 5. The method for manufacturing a semiconductor device according to claim 4, (g) after the step (f), selectively retracting another portion of the field plate electrode so that a portion of the field plate electrode made of the first conductive film and the second conductive film formed inside the first trench after the step (f3) remains as a contact portion; (h) after the step (g), recessing the first insulating film so that the position of the upper surface of the first insulating film is lower than the position of the upper surface of the field plate electrode inside the first trench; (i) after the step (h), forming a gate insulating film on the first insulating film inside the first trench and forming a second insulating film on the top surface and side surfaces of the field plate electrode exposed from the first insulating film; (j) after the step (i), forming a gate electrode on the field plate electrode recessed in the step (g) so as to fill the inside of the first trench; The method for manufacturing a semiconductor device further comprises:

7. 7. The method for manufacturing a semiconductor device according to claim 6, a first trench formed on the first surface of the semiconductor substrate and a second trench formed on the second surface of the semiconductor substrate; a second trench formed on the first trench and a third trench formed on the second surface of the semiconductor substrate;

8. 7. The method for manufacturing a semiconductor device according to claim 6, (k) after the step (j), forming a body region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate so as to be shallower than the first trench in a cross-sectional view; (l) after the step (k), forming a source region of the first conductivity type in the body region; (m) after the step (l), forming an interlayer insulating film on the top surface of the semiconductor substrate so as to cover the first trench; (n) after the step (m), forming a first hole in the interlayer insulating film that reaches the source region and the body region, a second hole that reaches the gate electrode, and a third hole that reaches the contact portion; (o) after the step (n), forming a source electrode and a gate wiring surrounding the source electrode in a plan view on the interlayer insulating film; (p) after step (o), forming a drain electrode below the lower surface of the semiconductor substrate; Further provided with the gate wiring is embedded in the second hole and is electrically connected to the gate electrode; the source electrode is embedded in the first hole and the third hole, and is electrically connected to the body region and the field plate electrode in the source region.

9. 2. The method for manufacturing a semiconductor device according to claim 1, The step (c) (c1) forming a first silicon oxide film in the first trench and on the top surface of the semiconductor substrate by a thermal oxidation method; (c2) forming a second silicon oxide film on the first silicon oxide film by a CVD method; and The method for manufacturing a semiconductor device, wherein the first insulating film includes the first silicon oxide film and the second silicon oxide film.

10. 10. The method for manufacturing a semiconductor device according to claim 9, In the step (c1), the first silicon oxide film is formed so that the thickness of the first silicon oxide film is thinner than the thickness of the second silicon oxide film.

Images