ESD protection circuit and semiconductor device

Abstract

To provide an ESD protection circuit that can reduce the layout area, reduce a leakage current, and prevent malfunctions.SOLUTION: An ESD protection circuit 100 connected between a VDD terminal and a VSS terminal in parallel with an internal circuit C that operates at a specified operating voltage includes an NMOS transistor 110 in which an N-type high concentration drain region 114a is connected to the VDD terminal, and a gate 116 is in a floating state, and a high concentration source region 114b is connected to the VSS terminal, and a threshold voltage and a trigger voltage Vtrig of a parasitic bipolar transistor of the NMOS transistor 110 are higher than the operating voltage and lower than the breakdown voltage of the internal circuit C.SELECTED DRAWING: Figure 2A

Description

[Technical Field]

[0001] The present invention relates to an ESD protection circuit and a semiconductor device. [Background technology]

[0002] Semiconductor integrated circuits are vulnerable to electrostatic discharge (ESD) and can easily be destroyed. For this reason, semiconductor integrated circuits often include an ESD protection circuit to protect the internal circuitry from ESD.

[0003] This ESD protection circuit is designed to operate only when a surge voltage caused by electrostatic discharge is applied to a power supply line or the like, and protects the internal circuitry by quickly directing the surge current to a ground line or the like without destroying itself before the surge current flows into the internal circuitry. Specifically, when the source of electrostatic discharge is the human body, the ESD protection circuit operates by directing a surge current of several amperes to ground potential or the like before the surge voltage of several thousand volts caused by the electrostatic discharge reaches the breakdown voltage of the internal circuitry.

[0004] Examples of such ESD protection circuits include a diode-type ESD protection circuit that uses a breakdown phenomenon, a GG (Gate Grounded)-MOS (Metal-Oxide-Semiconductor) ESD protection circuit that uses the snapback action of a parasitic bipolar transistor, and a capacitively coupled MOS-type ESD protection circuit in which a MOS transistor turns on when a voltage with a short rise time is applied.

[0005] As an example of a capacitively coupled MOS type ESD protection circuit, the drain and source terminals of a MOS transistor are connected to V SS Each terminal (excluding the V DD terminal, input terminal or output terminal) and V SS In a GG-MOS type ESD protection circuit connected between the gate terminal and V SSIt has been proposed to connect each terminal except the terminal via a capacitor (see, for example, Patent Document 1). This capacitively coupled MOS type ESD protection circuit uses V SS The capacitors between each pad and the gate terminal, except for the V SS When static electricity is discharged to each pad except the terminal, the high-frequency component of the surge voltage with a short rise time passes through the capacitor and reaches the gate terminal. This causes the gate potential to fluctuate, turning the MOS transistor on and causing V SS The internal circuitry is protected from electrostatic discharge by passing surge current to the terminal side. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-269437 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of one aspect of the present invention is to provide an ESD protection circuit that can reduce the layout area, reduce leakage current, and prevent malfunction. [Means for solving the problem]

[0008] The ESD protection circuit in one embodiment of the present invention comprises: An ESD protection circuit connected in parallel with a protected circuit that operates at a predetermined operating voltage between a first terminal and a second terminal, an NMOS transistor having a drain connected to the first terminal, a gate in a floating state, and a source connected to the second terminal; In the NMOS transistor, the avalanche breakdown voltage of the parasitic diode and the trigger voltage of the parasitic bipolar transistor are higher than the operating voltage and lower than the breakdown voltage of the circuit to be protected. [Effects of the Invention]

[0009] According to one aspect of the present invention, it is possible to provide an ESD protection circuit that can reduce the layout area, reduce leakage current, and prevent malfunction. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to one embodiment of the present invention. [Figure 2A] FIG. 2A is a schematic cross-sectional view showing an example of the structure of an NMOS transistor according to this embodiment. [Figure 2B] FIG. 2B is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. [Figure 2C] FIG. 2C is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. [Figure 2D] FIG. 2D is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. [Figure 2E] FIG. 2E is an explanatory diagram showing an example of the operation of the NMOS transistor in this embodiment. [Figure 2F] FIG. 2F is a graph showing an example of the current-voltage characteristics of the ESD protection circuit according to this embodiment. [Figure 3A] FIG. 3A is a schematic cross-sectional view showing another example of the structure of the NMOS transistor according to this embodiment. [Figure 3B] FIG. 3B is a schematic cross-sectional view showing yet another example of the NMOS transistor according to this embodiment. [Figure 3C] FIG. 3C is a schematic cross-sectional view showing yet another example of the NMOS transistor according to this embodiment. [Figure 3D] FIG. 3D is a schematic cross-sectional view showing yet another example of the NMOS transistor according to this embodiment. [Figure 3E]FIG. 3E is a schematic cross-sectional view showing yet another example of the NMOS transistor according to this embodiment. [Figure 3F] FIG. 3F is a schematic cross-sectional view showing yet another example of an NMOS transistor according to this embodiment. [Figure 3G] FIG. 3G is a schematic cross-sectional view showing yet another example of an NMOS transistor according to this embodiment. [Figure 3H] FIG. 3H is a schematic cross-sectional view showing yet another example of an NMOS transistor according to this embodiment. [Figure 4A] FIG. 4A is a circuit diagram showing an example of a conventional diode-type ESD protection circuit. [Figure 4B] FIG. 4B is a graph showing an example of current-voltage characteristics (by diode junction area) of a conventional diode-type ESD protection circuit. [Figure 5A] FIG. 5A is a circuit diagram showing an example of a conventional GG-MOS type ESD protection circuit. [Figure 5B] FIG. 5B is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit. [Figure 5C] FIG. 5C is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit when taking into consideration the reduction of leakage current. [Figure 5D] FIG. 5D is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit when the reduction of leakage current is not taken into consideration. [Figure 6A] FIG. 6A is a circuit diagram showing an example of a conventional capacitively coupled MOS type ESD protection circuit. [Figure 6B] FIG. 6B is a graph showing an example of the current-voltage characteristics (by rise time of surge voltage) of a conventional capacitively coupled MOS type ESD protection circuit. DETAILED DESCRIPTION OF THE INVENTION

[0011] The present invention is based on the finding that the internal circuit can be protected even if the gate is connected to a high-potential terminal from which static electricity is discharged, rather than connecting the gate to a low-potential terminal such as ground potential as in conventional GG-MOS type ESD protection circuits. As a result, in one embodiment of the present invention, the layout area can be made smaller than that of a conventional diode-type ESD protection circuit, the leakage current can be reduced more than that of a GG-MOS-type ESD protection circuit, and malfunctions that occur in capacitively coupled MOS-type ESD protection circuits can be prevented.

[0012] First, as conventional techniques, a diode-type ESD protection circuit, a GG-MOS-type ESD protection circuit, and a capacitively coupled MOS-type ESD protection circuit will be described with reference to FIGS. 4A to 6B. Hereinafter, the voltage and current caused by electrostatic discharge may be simply referred to as "surge voltage" and "surge current."

[0013] FIG. 4A is a circuit diagram showing an example of a conventional diode-type ESD protection circuit. As shown in FIG. 4A, this diode-based ESD protection circuit 500 includes a V DD terminal and V SS The diode-type ESD protection circuit 500 is a circuit in which a diode 510 is connected between the V DD When a surge voltage is applied to the terminal, the surge current flows through the diode 510 by utilizing the breakdown phenomenon, thereby protecting the internal circuit C from electrostatic discharge. The breakdown voltage of diode 510 can be adjusted by adjusting the impurity concentration of the PN junction, making it easy to accommodate the operating voltages of various semiconductor integrated circuits. Furthermore, its simple structure reduces variations in characteristics, and since it does not use an insulating film, the insulating film will not be destroyed.

[0014] FIG. 4B is a graph showing an example of the current-voltage characteristics (by diode junction area) of a conventional diode-type ESD protection circuit. In this graph, the horizontal axis is V DDThe vertical axis is the terminal voltage, and the vertical axis is the surge current flowing through the diode-type ESD protection circuit. The solid line shows the current-voltage characteristics of a diode with a large junction area, and the dotted line shows the current-voltage characteristics of a diode with a small junction area. In addition to the graph in Figure 4B, the graphs in Figures 5B, 5C, 5D, and 6B assume a 2,000V HBM (Human Body Model) when 2,000V of static electricity charged to a human body is applied to the VDD terminal. In order to prevent the internal circuit from being destroyed by 2,000V HBM, the ESD protection circuit connected in parallel with the internal circuit must be able to withstand a surge current of approximately 1 ampere before the surge current flows into the internal circuit. SS It needs to be routed to the terminals.

[0015] In the current-voltage characteristic shown by the dotted line in Figure 4B, the diode junction area is small and the resistance value of the parasitic resistance is high, so a surge current of 1 ampere is SS On the other hand, in the current-voltage characteristics shown by the solid line in Figure 5A, the diode junction area is large and the resistance value of the parasitic resistance is low, so a surge current of 1 ampere is passed through V before the surge voltage reaches the breakdown voltage of the internal circuit. SS It can be passed to the terminals. Therefore, in order for a diode-type ESD protection circuit to protect the internal circuit from 2,000V HBM, the junction area of ​​the diode must be made large, which increases the layout area of ​​the semiconductor integrated circuit.

[0016] In terms of reducing the layout area of ​​a semiconductor integrated circuit, a GG-MOS type ESD protection circuit that utilizes snapback action is more advantageous than a diode type ESD protection circuit.

[0017] Next, a conventional GG-MOS type ESD protection circuit will be described.

[0018] FIG. 5A is a circuit diagram showing an example of a conventional GG-MOS type ESD protection circuit. As shown in FIG. 5A, the GG-MOS type ESD protection circuit 600 has a MOS transistor 610 whose drain and source terminals are connected to V DD terminal and V SS terminals, and the gate terminal is connected to V SS A circuit connected to a terminal.

[0019] FIG. 5B is a graph comparing the current-voltage characteristics of a conventional diode-type ESD protection circuit and a conventional GG-MOS-type ESD protection circuit. In this graph, the horizontal axis is V DD The vertical axis represents the voltage at the terminal, and the vertical axis represents the surge current flowing through each ESD protection circuit. The solid line represents the current-voltage characteristics of a GG-MOS-type ESD protection circuit with a small layout area, and the dotted line represents the current-voltage characteristics of a diode-type ESD protection circuit with a small layout area similar to the dotted line in Figure 4B. In other words, in Figure 5B, the layout area of ​​the conventional GG-MOS-type ESD protection circuit is the same as that of the conventional diode-type ESD protection circuit.

[0020] In the current-voltage characteristics of the GG-MOS type ESD protection circuit shown by the solid line in FIG. 5B, when a surge voltage is applied, avalanche breakdown occurs in the parasitic diode of the MOS transistor 610, and then V DD The terminal voltage reaches the trigger voltage. Here, the trigger voltage refers to the trigger voltage of the parasitic bipolar transistor, the voltage at which the parasitic bipolar transistor switches from off to on. When the parasitic bipolar transistor turns on, the number of current paths flowing from the drain to the source increases compared to when it is off, so the same current can flow with a lower drain voltage, and a phenomenon (snapback operation) occurs in which the voltage drops after the trigger voltage is reached, as shown in Figure 5B. This snapback operation allows conventional GG-MOS type ESD protection circuits to withstand a surge current of 1 ampere before the surge voltage reaches the breakdown voltage of the internal circuitry. SS It can be passed to the terminals.

[0021] The leakage current and breakdown voltage of this GG-MOS type ESD protection circuit are affected by multiple parameters, such as the gate length of the MOS transistor, the gate insulating film thickness, the channel impurity concentration, and the impurity concentration in the low-concentration region near the drain, making it more complex than the diode type, but it is possible to fine-tune the desired characteristics by adjusting the concentration of the impurities implanted near the drain region.

[0022] However, if the operating voltage of the internal circuit is around 2V, adjustment becomes difficult with diode type and GG-MOS type. Generally, for internal circuits with an operating voltage of around 2V, it is necessary to lower the minimum operating voltage, and in order to improve the on / off ratio of the MOS transistors used in the internal circuit, the gate insulating film thickness of the MOS transistors in the internal circuit is set to 4nm to 5nm. When the gate insulating film is a thin silicon oxide film like the one mentioned above, the intrinsic breakdown voltage slightly exceeds 10MV / cm, so the intrinsic breakdown voltage of the gate insulating film of the MOS transistors in the internal circuit is often around 5.5V. For this reason, ESD protection circuits are required to have a V DD Protection must be performed when the terminal voltage is within the range of 2V to 5.5V. In diode-type ESD protection circuits and GG-MOS-type ESD protection circuits, if you try to keep the protection operation within the above range, the leakage current will increase at an operating voltage of 2 V, as shown in Figure 5D. Conversely, if you try to suppress the leakage current, the protection operation will not be complete within the above range, as shown in Figure 5C, and the voltage will exceed 5.5 V before a surge current of 1 ampere flows, destroying the internal circuitry.

[0023] In this way, when the operating voltage of the internal circuit in a diode-type ESD protection circuit or a GG-MOS-type ESD protection circuit approaches 2 V, the trade-off between leakage current and protection operating voltage (i.e., off-current and on-voltage) means that the ESD protection function can no longer be fulfilled. The capacitively coupled MOS type ESD protection circuit, which will be explained next, resolves this trade-off.

[0024] Fig. 6A is a circuit diagram showing an example of a conventional capacitively coupled MOS type ESD protection circuit, and Fig. 6B is a graph showing an example of the current-voltage characteristics (by surge voltage rise time) of the conventional capacitively coupled MOS type ESD protection circuit.

[0025] As shown in FIG. 6A, the capacitively coupled MOS ESD protection circuit 700 has a drain and a source terminal of a MOS transistor 710 connected to V DD terminal and V SS The GG-MOS type is similar to the GG-MOS type in that it is connected to the V DD The gate is connected to the terminal, and V SS The difference is that the MOS transistor 710 is also connected to a terminal. The threshold voltage of the MOS transistor 710 is set to 2V or less.

[0026] When the rise time of the surge voltage is long, the potential of the capacitively coupled gate of the capacitively coupled MOS type ESD protection circuit 700 is less likely to fluctuate, and the ESD protection circuit does not pass a current. In other words, in this case, the capacitively coupled MOS type ESD protection circuit 700 does not perform protection operation in the range of 2V to 5.5V, and exhibits the current-voltage characteristics shown by the solid line in Figure 6B, thereby reducing leakage current. On the other hand, when the rise time of the surge voltage is short, the potential of the capacitively coupled gate fluctuates, and the MOS transistor 710, whose threshold voltage is set to 2V or less, performs protection operation by passing a current through the channel, thereby discharging the surge current.

[0027] In this way, the capacitively coupled MOS type ESD protection circuit 700 eliminates the trade-off between the diode type ESD protection circuit and the GG-MOS type ESD protection circuit by switching the ON / OFF characteristics by capacitive coupling.

[0028] However, capacitively coupled MOS-type ESD protection circuits can only be used on limited terminals because they malfunction when used with terminals that input or output signals with short rise times similar to those of electrostatic discharges. Furthermore, because a high voltage is applied to the gate of a capacitively coupled MOS type ESD protection circuit during operation, avalanche breakdown, which causes the activation of a parasitic bipolar transistor, is unlikely to occur. As a result, the current-voltage characteristics of a capacitively coupled MOS type ESD protection circuit, as shown by the solid line in Figure 6B, are similar to those of a diode-type ESD protection circuit, as shown by the dotted line in Figure 4B. Therefore, if a large current is to be passed, the layout area must be increased, as shown by the solid line in Figure 4B.

[0029] Therefore, the present invention is designed to solve the above problems as follows. An ESD protection circuit according to one embodiment of the present invention includes an NMOS transistor connected between a first terminal and a second terminal in parallel with a protected circuit operating at a predetermined operating voltage, the NMOS transistor having a drain connected to the first terminal, a floating gate, and a source connected to the second terminal, with the avalanche breakdown voltage of the parasitic diode and the trigger voltage of the parasitic bipolar transistor being higher than the operating voltage of the protected circuit and lower than the breakdown voltage of the protected circuit. As a result, this ESD protection circuit can have a smaller layout area than conventional diode-type or capacitively coupled MOS-type ESD protection circuits, can reduce leakage current more than diode-type or GG-MOS-type ESD protection circuits, and does not malfunction like capacitively coupled MOS-type ESD protection circuits, and can also be used for terminals that input and output voltages with short rise times. The predetermined operating voltage is a predetermined voltage at which the protected circuit can operate, and is in the range from the minimum operating voltage to the maximum operating voltage of the protected circuit.

[0030] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted. In the drawings, the X, Y, and Z directions are perpendicular to one another. The direction including the X direction and the opposite direction of the X direction (-X direction) is referred to as the "X-axis direction," the direction including the Y direction and the opposite direction of the Y direction (-Y direction) is referred to as the "Y-axis direction," and the direction including the Z direction and the opposite direction of the Z direction (-Z direction) is referred to as the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the surface of each film facing the Z direction may be referred to as the "surface." The drawings are schematic, and the ratios of width, length, depth, etc. are not as shown in the drawings.

[0031] (Example of embodiment) FIG. 1 is a circuit diagram showing an ESD protection circuit and a semiconductor device according to one embodiment of the present invention. As shown in FIG. 1, in a semiconductor device 10, an internal circuit C is connected between a VDD terminal serving as a first terminal and a VSS terminal serving as a second terminal. The internal circuit C operates on the operating voltage applied between the VDD terminal and the VSS terminal at the ground potential. The ESD protection circuit 100 is connected in parallel with an internal circuit C, which is a circuit to be protected from damage due to electrostatic discharge. The ESD protection circuit 100 is an NMOS (N-channel MOS) transistor 110 having a drain 110D electrically connected to a VDD terminal, a gate 110G in a floating state, and a source 110S electrically connected to a VSS terminal. The operating voltage of the internal circuit C varies depending on the purpose, but in this embodiment, this operating voltage is set to 2V, and 2V is applied to the VDD terminal. Generally, when the operating voltage of an internal circuit is 2 V, the intrinsic breakdown voltage of the gate insulating film of a MOS transistor included in the internal circuit is about 5.5 V. For this reason, if there is no ESD protection circuit, when static electricity is discharged to the VDD terminal, a voltage of 5.5 V or more will be applied to the gate insulating film of the MOS transistor included in the internal circuit, causing it to break down. In other words, the ESD protection circuit 100 should perform protection operation before the voltage of the VDD terminal becomes 5.5V or higher, and should not perform protection operation when the VDD terminal is applied with 2V, which is the operating voltage of the internal circuit C. Also, the intrinsic breakdown voltage of the gate insulating film of the NMOS transistor 110 should be set to 5.5V. gate The thickness of the insulating film may be set.

[0032] FIG. 2A is a schematic cross-sectional view showing an example of the structure of an NMOS transistor according to this embodiment. As shown in FIG. 2A, the structure of the NMOS transistor 110 includes a P-type well region 112, which is a P-type low concentration region, formed in a semiconductor substrate 111, and a P-type medium concentration region 113a formed on this P-type well region 112. In this embodiment, the P-type medium concentration region 113a is formed on the P-type well region 112, but this is not limited to this, and instead of forming the P-type medium concentration region 113a, the low concentration P-type well region 112 may be made medium concentration.

[0033] A gate insulating film 115 is laminated on the upper surface of this P-type medium concentration region 113a, and a gate electrode 116 is further laminated on the gate insulating film 115. An N-type heavily doped drain region 114a and an N-type heavily doped source region 114b are formed above the P-type moderately doped region 113a so as to sandwich the gate electrode 116 in plan view. In this manner, the P-type moderately doped region 113a is also provided in the channel region between the N-type heavily doped drain region 114a and the N-type heavily doped source region 114b. Furthermore, a well electrode 114c is formed as a P-type heavily doped region above the P-type moderately doped region 113a at a position spaced apart from the N-type heavily doped source region 114b. In this embodiment, the N-type high concentration source region 114b and the well electrode 114c are spaced apart, but this is not limiting, and the N-type high concentration source region 114b and the well electrode 114c may be in contact with each other like a butting contact. The N-type heavily doped drain region 114a is V DDThe gate electrode 116 is in a floating state, and the N-type high concentration source region 114b and the well electrode 114c are connected to the V SS is connected to the terminal.

[0034] Generally, the well region of the ESD protection circuit is often formed simultaneously with the well region of the internal circuit in the same process, so it is not necessarily common to form the P-type medium concentration region 113a in addition to the P-type well region 112 as in this embodiment.

[0035] By adjusting the impurity concentration of the P-type medium concentration region 113a, the threshold voltage of the NMOS transistor 110, the avalanche breakdown voltage of the parasitic diode, and the parasitic bipolar transistor The trigger voltage can be adjusted a do. As described above, the ESD protection circuit 100 must perform a protection operation before the voltage of the VDD terminal becomes 5.5 V or higher, and must not perform a protection operation when the operating voltage of the internal circuit C, 2 V, is applied to the VDD terminal. Therefore, the threshold voltage of the NMOS transistor 110, the avalanche breakdown voltage of the parasitic diode, and the parasitic bipolar transistor The trigger voltage is adjusted to 2 V or more and 5.5 V or less by adjusting the impurity concentration of the P-type medium concentration region 113a.

[0036] Here, the operating voltage of the internal circuit C is 2V. DD The operating principle when positive static electricity flows into the terminal is described below.

[0037] The gate electrode of this NMOS transistor 110 is in a floating state, and V DD terminal and V SS If there is a voltage difference between the terminals, leakage current is likely to flow due to the punch-through phenomenon, so voltages exceeding the operating voltage of 2V are V DD It is necessary to prevent punch-through from occurring when a voltage is applied to the terminal. It is also preferable to adjust this punch-through so that it does not exceed 5.5V, which is the breakdown voltage of the internal circuit C. This adjustment is performed by adjusting the impurity concentration of the P-type medium concentration region 113a, that is, by adjusting the threshold value of the NMOS transistor 110. The punch-through current can also be adjusted by extending the gate length of the NMOS transistor 110. By adjusting the above, V DD It suppresses leakage current when an operating voltage of 2V is applied to the terminal, and V DD When a surge voltage of 2V or more is applied to the terminal, a punch-through phenomenon causes a surge current to flow from the N-type heavily doped drain region 114a to the N-type heavily doped source region 114b via the channel region of the NMOS transistor 110 (protection operation 1).

[0038] However, with only this protection operation 1, the current-voltage characteristics will be similar to "in the case of an input voltage with a short rise time" shown by the solid line in Fig. 6B, and a small area will not be able to protect the internal circuit C. In order to protect the internal circuit C, the gate width of the gate electrode 116 must be widened to allow a larger surge current to flow, but this results in a larger layout area and a larger leakage current. In the case of a conventional GG-MOS type ESD protection circuit, the gate electrode is connected to the VSS terminal, so the electric field near the semiconductor surface between the gate and drain becomes strong, causing a surface breakdown, and the carriers generated by this become parasitic bipolar transistors. Transistor On the other hand, in this embodiment, since the gate electrode is in a floating state, the operation of a parasitic bipolar transistor due to surface breakdown as in a GG-MOS type ESD protection circuit cannot be expected, but the presence of the P-type medium concentration region 113a causes avalanche breakdown in the parasitic diode formed by the junction between the P-type medium concentration region 113a and the N-type heavily doped drain region 114a, and therefore the operation of a parasitic bipolar transistor can be induced.

[0039] The avalanche breakdown voltage of this parasitic diode and the trigger voltage of the parasitic bipolar transistor whose operation is induced by this breakdown voltage are also adjusted by the impurity concentration of the P-type intermediate concentration region 113a, similar to the threshold voltage. Similarly to the threshold voltage, the avalanche breakdown voltage of the parasitic diode is adjusted to 2V or more so that the leakage current is below the desired level when the operating voltage of the internal circuit C, 2V, is applied to the VDD terminal. This naturally causes the trigger voltage of the parasitic bipolar transistor, which is induced to operate, to also be 2V or more. In addition, in order to protect the internal circuit C from ESD surges applied from the VDD terminal, the parasitic bipolar transistor The trigger voltage of the parasitic diode is adjusted to 5.5 V or less. At this time, when the avalanche breakdown voltage of the parasitic diode is set to 2 V or more, the parasitic bipolar transistor If the trigger voltage exceeds 5.5V, the gate length of the NMOS transistor 110 is shortened to reduce the parasitic bipolar transistor. transistor In addition, since the gate electrode is not connected to the VSS terminal like in the GG-MOS type ESD protection circuit, the parasitic bipolar transistor is less susceptible to damage than the GG-MOS type ESD protection circuit. Transistor Another advantage is that it is easier to lower the trigger voltage for operation and to protect the internal circuitry.

[0040] This parasitic bipolar Transistor By this operation, in addition to the surge current that flows in the channel region from the N-type heavily doped drain region 114a to the N-type heavily doped source region 114b as the protection operation 1, a parasitic bipolar transistor in a portion deeper than the channel region (in the -Z direction) is generated. transistor More surge current in the area to flush (protective operation 2).

[0041] In other words, the surge current flows through two paths: the current path through the channel region (protection operation 1) and the parasitic bipolar transistor deeper than the channel region (-Z direction). transistor Because there are two paths for current flowing through the region (protection operation 2), it is possible to further reduce the area compared to the GG-MOS type ESD protection circuit, which has an area advantage among conventional technologies.

[0042] In the structure of the NMOS transistor 110, the channel region is the P-type medium concentration region 113a, and therefore, the threshold voltage and the breakdown voltage of the parasitic diode can be adjusted to desired values ​​simultaneously by adjusting the impurity concentration of the P-type medium concentration region 113a.

[0043] Next, the negative static charge V DD This section describes the case where a discharge occurs at a terminal.

[0044] As shown in FIG. 2E, the negative charges flow in the forward direction in the parasitic diode between the N-type heavily doped drain region 114a and the P-type well region 112, and then flow from the P-type well region 112 through the well electrode 114c, which is a P-type heavily doped region, to V SS The current flows to the terminal. Since there is no point in the above path where a high electric field is applied, it does not lead to breakdown. Therefore, the ESD protection circuit 100 uses the structure of the NMOS transistor 110 to transfer negative charges to V SS By passing current through the terminal, the internal circuit C can be protected.

[0045] In a method for forming the NMOS transistor 110, for example, a P-type well region 112 is first formed in a semiconductor substrate 111, and a gate insulating film 115 and a gate electrode 116 are then formed thereon. P-type impurities are then implanted into the entire surface of the semiconductor substrate 111 so as to penetrate through the gate insulating film 115 and the gate electrode 116 to form a P-type medium concentration region 113a, and then N-type impurities are implanted at a high concentration to form an N-type high concentration drain region 114a and an N-type high concentration source region 114b. The P-type medium concentration region 113a may be formed before the gate insulating film 115 and the gate electrode 116 are formed.

[0046] As described above, the ESD protection circuit 100 is connected in parallel with the internal circuit C, which operates at a predetermined operating voltage, between the VDD terminal and the VSS terminal, and includes an NMOS transistor 110. The NMOS transistor 110 has an N-type heavily doped drain region 114a and a gate electrode 116 connected to the VDD terminal, and an N-type heavily doped source region 114b connected to the VSS terminal. As shown in FIG. 2F, the threshold voltage, the Zener breakdown voltage of the parasitic diode, and the trigger voltage of the parasitic bipolar transistor of this NMOS transistor 110 are higher than the operating voltage of the internal circuit C and lower than the breakdown voltage of the internal circuit C. As a result, the ESD protection circuit 100 can reduce the layout area and the leakage current, and can also ESD protection circuit This can prevent malfunctions that may occur due to the

[0047] Next, other examples of the structure of NMOS transistors other than the NMOS transistor 110 shown in FIG. 2A will be described with reference to FIGS. 3A to 3H. 3A to 3H are schematic cross-sectional views showing the vicinity of the N-type heavily doped drain region 114a, the N-type heavily doped source region 114b, and the gate electrode 116. FIG. Furthermore, any of the NMOS transistors shown in FIG. 2A and FIGS. 3A to 3H may be used as the NMOS transistors of the ESD protection circuits shown in FIGS. 1, 2A, and 2B.

[0048] FIG. 3A shows a structure similar to that of the NMOS transistor 110 shown in FIG. 2A, except that a P-type medium concentration channel region 117 is further formed in the NMOS transistor 110 shown in FIG. 2A. By forming this P-type medium concentration channel region 117, the impurity concentration of the P-type medium concentration channel region 117 can be adjusted separately from the P-type medium concentration region 113a. For example, the operating voltage of the internal circuit C can be adjusted by V DDSuppose the impurity concentration of the P-type medium concentration region 113a is adjusted to a lower concentration to increase the avalanche breakdown voltage of the parasitic diode in order to suppress leakage current when voltage is applied to the terminal. This, in turn, lowers the threshold voltage, making punch-through more likely to occur, and ultimately may make it impossible to suppress leakage current in the NMOS transistor 110. Even in such a case, the presence of the P-type medium concentration channel region 117 makes it possible to independently adjust the impurity concentration of this region, thereby raising the threshold without changing the avalanche breakdown voltage of the parasitic diode of the NMOS transistor 110 and suppressing leakage.

[0049] FIG. 3B shows a structure similar to that of the NMOS transistor 110 shown in FIG. 3A, except that a P-type medium concentration region 113b is formed directly below the N-type heavily doped drain region 114a instead of the P-type medium concentration region 113a in the NMOS transistor 110 shown in FIG. 3A. By using the structure of FIG. 3B, not only can the same effect as that of FIG. 3A be obtained, but also the parasitic bipolar transistor directly below the P-type medium concentration channel region 117 can be prevented. transistor 3A, the trigger voltage of the parasitic bipolar transistor is lowered, and the internal circuit C is more easily protected than in FIG. 3A.

[0050] FIG. 3C shows a structure similar to that of the NMOS transistor 110 shown in FIG. 3B, except that an N-type low concentration region 118a is formed in the NMOS transistor 110 shown in FIG. 3B. The N-type low-concentration region 118a has a so-called DDD (Double Diffused Drain) structure. This DDD structure is generally used to improve the drain breakdown voltage of MOS transistors, and this structure can also be applied to the present invention. The formation of this N-type low-concentration region 118a effectively expands the N-type high-concentration drain region 114a, facilitating heat dispersion and improving electrostatic breakdown voltage.

[0051] Figures 3D to 3G show structures similar to those of the NMOS transistors shown in Figures 2A and 3A to 3C, respectively, except that sidewall spacers 119 are provided on the side walls of the gate insulating film 115 and the gate electrode 116. Figure 3H shows a structure similar to that of the NMOS transistor shown in Figure 3G, except that the N-type low concentration region 118a is replaced with a shallowly formed N-type low concentration region 118b. The sidewall spacers 119 are a technique used in general semiconductor manufacturing processes, and are formed by removing the insulating film formed on the entire surface by etching back after forming the gate insulating film 115 and the gate electrode 116. By utilizing Figures 3D to 3H, the present invention can be applied to manufacturing processes that use sidewall spacers without any additional steps.

[0052] 3G to 3H, an N-type region exists directly below the sidewall spacer 119. These N-type low concentration regions 118a and 118b are what are known as a DDD (Double Diffused Drain) structure and an LDD (Lightly Doped Drain) structure. The DDD and LDD structures are generally used to improve the drain breakdown voltage of transistors, and these structures can also be applied to the present invention. The formation of this N-type low concentration region 118b effectively expands the N-type high concentration drain region 114a, facilitating heat dispersion and improving electrostatic breakdown voltage.

[0053] As described above, the ESD protection circuit according to one embodiment of the present invention has an NMOS transistor connected between a first terminal and a second terminal in parallel with a protected circuit that operates at a predetermined operating voltage. The NMOS transistor has a drain connected to the first terminal, a gate in a floating state, and a source connected to the second terminal, and has a threshold voltage and a parasitic bipolar transistor. transistor The trigger voltage is higher than the operating voltage and lower than the breakdown voltage of the protected circuit. As a result, this ESD protection circuit can reduce the layout area, reduce the leakage current, and prevent malfunctions that occur in capacitively coupled MOS type ESD protection circuits.

[0054] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to this embodiment, and includes designs within the scope of the invention that do not deviate from the gist of the invention. Specifically, in this embodiment, the first terminal is V DD Although the terminals are described as such, they are not limited to this and may be, for example, input terminals, output terminals, etc. Furthermore, even if an LDD structure is adopted for the NMOS transistor, the sidewall spacer may not be formed. [Explanation of symbols]

[0055] 10 Semiconductor devices 100 ESD protection circuit 110 NMOS transistor 110D Drain 110S Sauce 110G Gate 111 Semiconductor substrate 112 P-type well region 113a,113b P-type medium concentration region 114a N-type heavily doped drain region 114b N-type high concentration source region 115 Gate insulating film 116 Gate electrode 117 P-type medium concentration channel region (P-type medium concentration region) 118a,118b N-type low concentration region 119 Sidewall spacer C Internal circuit (protected circuit)

Claims

1. An ESD protection circuit connected in parallel with a protected circuit that operates at a predetermined operating voltage between a first terminal and a second terminal, an NMOS transistor having a drain connected to the first terminal, a gate not connected to anything, and a source connected to the second terminal; The NMOS transistor has a threshold voltage and a trigger voltage of a parasitic bipolar transistor that are higher than the operating voltage and lower than a breakdown voltage of the circuit to be protected.

2. The NMOS transistor is a semiconductor substrate; a P-type well region formed on the front surface side of the semiconductor substrate; an N-type heavily doped drain region and an N-type heavily doped source region, which are spaced apart from each other above the P-type well region and have impurity concentrations higher than the impurity concentration of the P-type well region; a P-type intermediate concentration region provided in at least a region in contact with the N-type heavily doped drain region, the P-type intermediate concentration region having a P-type impurity concentration higher than that of the P-type well region; a gate insulating film provided on a semiconductor surface between the N-type heavily doped drain region and the N-type heavily doped source region; a gate electrode provided on the gate insulating film; 10. The ESD protection circuit of claim 1, comprising:

3. 3. The ESD protection circuit of claim 2, wherein the medium concentration P-type region also contacts the P-type well region.

4. 4. The ESD protection circuit according to claim 2, wherein the P-type medium concentration region is further provided in a channel region between the N-type high concentration drain region and the N-type high concentration source region.

5. 5. The ESD protection circuit according to claim 2, wherein a P-type medium concentration channel region is provided on the surface of the semiconductor substrate between the N-type high concentration drain region and the N-type high concentration source region.

6. 6. The ESD protection circuit according to claim 2, wherein the NMOS transistor further comprises a DDD structure.

7. 6. The ESD protection circuit according to claim 4, wherein the NMOS transistor further comprises an LDD structure.

8. 8. The ESD protection circuit according to claim 2, wherein the NMOS transistor further comprises sidewall spacers on the sidewalls of the gate insulating film and the gate electrode.

9. 9. A semiconductor device comprising: an ESD protection circuit according to claim 1; and a circuit to be protected from electrostatic discharge by said ESD protection circuit, said circuit being connected in parallel.

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