Manufacturing method of power semiconductor element and power semiconductor element

Abstract

The present disclosure relates to a method for manufacturing a power semiconductor device (1, 40), comprising forming a plurality of growth templates on a carrier substrate (2), including at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+ / p- / n- / n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+ / n- / p- / n+ structures. The present disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), and a plurality of first semiconductor structures (5) of a first type and a plurality of second semiconductor structures (6) of a second type formed in the at least one dielectric layer (4, 27, 31).

Description

[Technical Field]

[0001] The present disclosure relates generally to semiconductor devices and methods for fabricating the same, and more particularly to a novel approach for integrating at least two groups of different types of wide bandgap semiconductor structures into a single power semiconductor device. [Background technology]

[0002] Wide-bandgap (WBG) semiconductor materials, such as silicon carbide (SiC), have advantageous properties, including high critical electric fields and electron mobility, or high-frequency switching. Therefore, they offer a much larger Baliga figure of merit (BFOM) compared to commonly used semiconductor materials, such as silicon, making them a good choice for power semiconductor devices, such as power MISFETs. These advantages enable several applications for energy efficiency and electrical transport. However, the relatively high cost and processing complexity associated with fabricating power semiconductor devices containing WBG materials limit their application in many fields. Summary of the Invention [Means for solving the problem]

[0003] Embodiments of the present disclosure relate to a method for manufacturing a power semiconductor device that includes forming a plurality of hollow growth templates on a carrier substrate and selectively growing first and second sequences of differentially doped WBG semiconductor materials in the plurality of hollow growth templates, as well as a power semiconductor device that includes a carrier substrate, a dielectric layer, and a plurality of first and second semiconductor structures formed therein.

[0004] According to a first aspect of the present disclosure, there is provided a method for manufacturing a power semiconductor device, the method including: forming a plurality of growth templates on a carrier substrate, the plurality of growth templates including at least a first plurality of hollow growth templates and a second plurality of hollow growth templates; - selectively growing a first sequence of differently doped WBG semiconductor materials into each of the first hollow growth templates, thereby forming a corresponding plurality of first semiconductor structures of a first type, in particular n+ / p- / n- / n+ structures; - selectively growing a second sequence of differently doped WBG semiconductor materials into each of the second hollow growth templates, thereby forming a corresponding plurality of second semiconductor structures of a second type, in particular n+ / n- / p- / n+ structures.

[0005] The above processing steps allow multiple groups of different types of WBG semiconductor structures to be grown on a common carrier structure. This allows for the efficient production of multiple WBG semiconductor structures of the same type, for example, to carry high currents and / or high voltages within one branch of a circuit, and for the implementation of different structures within a single integrated power device, for example, for different branches of a circuit. For example, when individual first and second semiconductor structures are connected in parallel, they can carry relatively high currents. Furthermore, when multiple first semiconductor structures of a first type and multiple second semiconductor structures of a second type are connected in series, they can form commonly occurring circuit components such as the lower and upper halves of a half-bridge. Furthermore, by using WBG semiconductor materials selectively grown in the growth template, high critical fields and electron mobilities can be achieved, for example, improving energy efficiency and enabling high-frequency switching.

[0006] In at least one implementation, regions of vertically oriented growth templates are formed, each extending in a direction perpendicular to a major surface of a carrier substrate, thereby enabling the fabrication of vertical power components, such as vertical MISFETs.

[0007] In at least one implementation, forming the plurality of hollow growth templates may include depositing and structuring a sacrificial material, particularly amorphous silicon, on a carrier substrate, covering the structured sacrificial material with a layer of dielectric material, and selectively removing the sacrificial material surrounded by the dielectric material to form the first and second plurality of growth templates, which enables the creation of a plurality of very narrow vertical growth templates using conventional semiconductor processing steps.

[0008] In at least one implementation, the top ends of the plurality of growth templates are initially sealed, and the method further includes opening only the top ends of a first subset of the plurality of growth templates before growing the first sequence of differently doped WBG semiconductor materials, resealing the top ends of the first subset after growing the first sequence of differently doped WBG semiconductor materials, and opening only the top ends of a second subset of the plurality of growth templates before growing the second sequence of differently doped WBG semiconductor materials. In this manner, at least some of the growth templates can be formed together while different types of semiconductor structures can be grown at a later stage using conventional semiconductor processing equipment.

[0009] In at least one implementation, the first and second sequences of different WBG semiconductor materials are selectively grown by chemical vapor deposition (CVD) using different dopant profiles, which allows for the use of conventional processing chambers and mitigates subsequent implantation of dopants into previously grown epilayers.

[0010] In at least one implementation, the method further includes forming a plurality of first gate structures surrounding at least a portion of each of the plurality of first semiconductor structures and / or forming a plurality of second gate structures surrounding at least a portion of each of the plurality of second semiconductor structures. In this manner, the first and / or second semiconductor structures can be switched, for example, to implement a half-bridge of an inverter circuit. Furthermore, by completely surrounding the respective semiconductor structures, a particularly fast switching response can be achieved.

[0011] In at least one implementation, the method further includes forming at least one dielectric layer, wherein the first gate contact is embedded in the at least one dielectric layer and the second gate contact is formed on or near a top surface of the at least one dielectric layer, which, among other things, enables the respective gate contacts to be positioned proximate to respective drift layers of the first and second semiconductor structures and vertically offset relative to one another.

[0012] In at least one implementation, the method further includes forming a first top contact electrically connected to at least a subgroup of the plurality of first semiconductor structures, particularly a positive DC terminal of the half-bridge structure, a second top contact electrically connected to at least a subgroup of the plurality of second semiconductor structures, particularly a negative DC terminal of the half-bridge structure, and / or a bottom contact electrically connected to at least a subgroup of the plurality of first semiconductor structures and a subgroup of the plurality of second semiconductor structures, particularly an AC terminal of the half-bridge structure. Such connection arrangements enable parallel connection of some or all of the first and second semiconductor structures, respectively.

[0013] According to a second aspect of the present disclosure, there is provided a power semiconductor device, the device comprising: a carrier substrate with at least one bottom contact, in particular an AC terminal of a half-bridge construction; at least one dielectric layer formed on a carrier substrate, a plurality of first semiconductor structures of a first type, in particular n+ / p- / n- / n+ structures, formed in at least one dielectric layer, each of the first semiconductor structures being electrically connected to a bottom contact and comprising a first sequence of differently doped sub-layers of a WBG semiconductor material; a plurality of second semiconductor structures of a second type, in particular n+ / n- / p- / n+ structures, formed in the at least one dielectric layer, each of the second semiconductor structures being electrically connected to a bottom contact and comprising a second sequence of differently doped sub-layers of WBG semiconductor material; a first upper contact arranged on the upper surface of the at least one dielectric layer, in particular a positive DC terminal of the half-bridge structure, electrically connecting at least a subgroup of the first semiconductor structures; and - a second upper contact arranged on the upper surface of the at least one dielectric layer, in particular a negative DC terminal of the half-bridge structure, the second upper contact electrically connecting at least a subgroup of the plurality of second semiconductor structures.

[0014] The power semiconductor device according to the second embodiment is useful for monolithic integration of power semiconductor devices comprising a plurality of series and / or parallel connected semiconductor structures made from WBG semiconductor material, which may be manufactured using the manufacturing method according to the first aspect, and provides similar advantages and features as described above.

[0015] In at least one implementation, the first and second semiconductor structures are selectively grown nanowire structures having diameters of 10 nm to 10 μm and / or lengths of 1 μm to 100 μm. At least one dielectric layer may have a thickness of 1 μm to 100 μm. Such semiconductor structures enable high power density and therefore space-efficient integration of power semiconductor devices. They are suitable for voltages and currents generated in typical power applications such as electric vehicle inverters and / or solar power generation.

[0016] In at least one implementation, the carrier substrate comprises a layer made of silicon or polycrystalline silicon carbide, the at least one dielectric layer comprises an oxide, particularly silicon dioxide or aluminum oxide, and / or the WBG semiconductor material comprises silicon carbide, particularly one of 4H-SiC, 6H-SiC, or 3C-SiC. Notably, the above-described device structure and corresponding processing steps enable the combination of active semiconductor structures made of WBG semiconductor materials on a carrier substrate made of a relatively inexpensive semiconductor material, such as silicon or polycrystalline silicon carbide.

[0017] In at least one implementation, the device comprises a half-bridge or full-bridge circuit, which are often used in various power applications such as inverters, rectifiers, and converters.

[0018] While the present disclosure provides multiple embodiments, all features described with respect to a first embodiment are also disclosed herein with respect to a second embodiment, and vice versa, even if the respective feature is not explicitly mentioned in the context of the particular embodiment.

[0019] The accompanying drawings are included to provide a further understanding. In the drawings, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0020] [Figure 1] 1 is a schematic cross-sectional view of a power semiconductor device comprising two different types of semiconductor structures; [Figure 2] 1 shows schematically the process steps of a method for manufacturing a power semiconductor component; [Figure 3a] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3b] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3c] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3d] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3e] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3f] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3g] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3h] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3i] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3j] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3k] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3l] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3m] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3n] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3o] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3p] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3q] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 3r] 1 shows stages in the manufacture of a power semiconductor device comprising a half-bridge circuit. [Figure 4a] FIG. 1 is a perspective view of a power semiconductor element. [Figure 4b] FIG. 2 shows a perspective view of the upper contact of the power semiconductor element. DETAILED DESCRIPTION OF THE INVENTION

[0021] FIG. 1 shows a schematic cross-sectional view of a power semiconductor device 1 according to the present disclosure. The power semiconductor device 1 shown in Figure 1 includes a carrier substrate 2. The carrier substrate 2 may include, for example, a portion of a silicon wafer and / or one or more epitaxially grown layers (epilayers or epitaxial layers) or amorphous silicon carbide (SiC). As shown in Figure 2, a bottom contact 3 is formed on a lower major surface of the carrier substrate 2. The bottom contact 3 may form a common terminal for all semiconductor structures formed on the carrier substrate 2.

[0022] On the opposite upper surface of the carrier substrate 2, a dielectric layer 4 is formed. The dielectric layer 4 may be formed from an electrically insulating material such as a dioxide, for example, silicon dioxide (SiO2) or aluminum oxide (Al2O3). A plurality of vertical semiconductor structures 5, 6 are formed within the dielectric layer 4. In particular, in the embodiment shown in Figure 1, a regular pattern of alternating first semiconductor structures 5 and second semiconductor structures 6 is formed.

[0023] The first semiconductor structure 5 and the second semiconductor structure 6 differ in their dopant profiles and / or functions. For example, as described in further detail below, the first semiconductor structure 5 may form a switching component of a lower leg of a half-bridge circuit, and the second semiconductor structure 6 may form a switching component of an upper leg of the same half-bridge circuit.

[0024] In the embodiment shown in FIG. 1 , a plurality of different top contacts 7 and 8 are formed on the top surface of the dielectric layer 4 to connect the first semiconductor structure 5 and the second semiconductor structure 6. In particular, several first top contacts 7 for connecting the first semiconductor structures 5 and several second top contacts 8 for connecting the second semiconductor structures 6 are formed. Note the fact that in the cross section shown in FIG. 1 , only a single semiconductor structure 5 or 6 is shown connected to each top contact 7 and 8. However, in reality, additional semiconductor structures of the same type may be present behind or in front of the row of semiconductor structures shown in the cross section of FIG. 1 . In this case, each top contact 7 and 8 connects several or all of the first semiconductor structures 5 or second semiconductor structures 6 of the same type. Specifically, the two different top contacts 7 and 8 may form the positive and negative DC contacts of a half-bridge circuit, and the bottom contact 3 may form the AC contact.

[0025] FIG. 2 shows schematically a method for manufacturing a power semiconductor device such as the power semiconductor device 1 of FIG.

[0026] In a first step S1, multiple hollow growth templates are formed. This can be achieved, for example, by selective etching of a dielectric layer and / or deposition of a sacrificial material that is then covered with a dielectric material, as described below. As further shown in FIG. 2, step S1 includes the formation of a first growth template in step S1a and the formation of a second growth template in step S1b. In practice, these two steps may be performed partially or completely simultaneously. However, in other implementations, the first and second growth templates may be formed separately from each other.

[0027] In the second step S2, a first semiconductor structure is formed in the first hollow growth template formed in step S1a. For example, a first type of semiconductor structure, such as an n+ / p- / n- / n+ structure, may be formed by selective area epitaxy. This can be achieved, among other things, by selectively growing, i.e., depositing, differentially doped WBG semiconductor materials only within the first hollow growth template, while growth is inhibited in other areas covered by the growth template material. The above designation of layers repeats each sublayer and the WBG semiconductor materials grown in the order in which they were grown, i.e., from substrate 2 upwards. That is, the n+ material is deposited first, followed by the p- material, the n- material, and finally the n+ material.

[0028] In a third step S3, second semiconductor structures 6 are formed in the second hollow growth template formed in step S1b. The second semiconductor structures 6 differ from the first semiconductor structures 5 grown in step S2 in their physical composition, dopant profile, and / or function. For example, they may have an inverted dopant profile or sublayer sequence. For example, an n+ / n- / p- / n+ WBG semiconductor structure may be grown in the second hollow growth template.

[0029] While the above describes the formation of two groups of growth templates and two types of semiconductor structures, it should be noted that more than two types of hollow growth templates and more than two types of semiconductor structures may be similarly formed.

[0030] The schematic diagram of Figure 2 focuses on the formation of distinct first and second semiconductor structures 5 and 6, respectively. The formation of the actual power semiconductor device may include multiple additional processing steps, such as the formation of top and bottom contacts and gate electrodes. Such steps are described in more detail below with respect to the fabrication of a half-bridge structure comprising multiple vertical MISFETs.

[0031] 3a to 3r show various stages in the manufacture of a power semiconductor device comprising a half-bridge circuit.

[0032] 3a shows a cross section of a carrier substrate 9 coated with an epitaxial layer 10. The growth substrate 9 and the epitaxial layer 10 formed on top of it together form the carrier substrate 2.

[0033] In the described embodiment, epitaxial layer 10 may function as a growth seed for semiconductor structures that are selectively grown at a later stage. In this case, epitaxial layer 10 removes growth defects. In other embodiments, epitaxial layer 10 itself may form part of the completed semiconductor device. For example, epitaxial layer 10 may act as a drift layer. In yet other embodiments, epitaxial layer 10 may be omitted entirely.

[0034] On top of the carrier substrate 2 a sacrificial material, for example polycrystalline silicon, is deposited so as to form a sacrificial layer 11 .

[0035] 3b shows the situation after structuring of the sacrificial layer 11. For example, a corresponding photoresist pattern and conventional etching may be used to remove portions of the sacrificial layer 11 to form a plurality of sacrificial vertically oriented nanowires 12. The sacrificial nanowires 12 form a positive template for the subsequently formed semiconductor structure.

[0036] Figure 3c shows the situation after the sacrificial nanowires 12 have been covered with a first dielectric layer 13. For example, SiO2 or Al2O3 may be deposited on all exposed surfaces of the carrier substrate 2 and the sacrificial nanowires 12 to coat the remaining sacrificial material on all sides.

[0037] Figure 3d shows the situation after a photoresist layer 14 has been applied for planarization. Initially, the photoresist layer 14 covers all of the first dielectric layer 13 so that the sacrificial nanowires 12 are embedded in the photoresist material.

[0038] 3e shows the situation after the top of the photoresist layer 14 has been removed to partially expose the top ends 17 of all of the sacrificial nanowires 12. This may be achieved, for example, by dry etching, plasma etching, or other known semiconductor processing methods. Note the fact that the sacrificial nanowires 12 are still covered and encapsulated by the first dielectric layer 13.

[0039] FIG. 3F shows the situation after applying and structuring the second dielectric layer 15 so as to cover the top ends of a subset of the nanowires 12. In particular, in the example shown in FIG. 3F, every third row of nanowires 12 is covered by the remaining material of the second dielectric layer 15, such as SiO or AlO. On the other hand, the second dielectric layer 15 has openings 16 formed therein, exposing the top ends 17 of every other nanowire 12. In the described embodiment, the materials of the first and second dielectric layers 13 and 15 are different and can therefore be selectively etched using an appropriate agent. Alternatively, the second dielectric layer 15 may be selectively deposited only in the areas corresponding to the covered subset of nanowires 12.

[0040] 3g shows the situation after the top of the first dielectric layer 13 has been removed, for example by etching, to expose the sacrificial material at the top ends 17 of the first subgroup of sacrificial nanowires 12. In this step, a different etchant may be used to selectively etch the material of the first dielectric layer 13. However, partial removal of the second dielectric layer 15, which is typically much thicker, is also acceptable.

[0041] 3h shows the situation after the sacrificial material of the first subgroup of nanowires 17 has been removed, for example by etching, to form a plurality of first hollow growth templates 18. For example, potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) may be used in a wet etching step to remove the exposed Si material forming the nanowires 17. Alternatively, XeF2 vapor-phase etching may be used for the Si material. Nanowires 17 formed from carbon (C) may be removed, for example, by O2 plasma etching.

[0042] Figure 3i shows the situation after removal of the second dielectric layer 15 and the remaining parts of the photoresist layer 14. It can be seen that the first open hollow growth templates 18 alternate with the remaining sacrificial nanowires 12, the upper ends 17 of which are still covered, i.e., closed, by the first dielectric layer 13. Thus, when the WBG semiconductor material is applied in the processing chamber, selective growth occurs only in the first hollow growth templates 18.

[0043] FIG. 3j shows the situation after selectively growing a first sequence of differently doped WBG semiconductor material in each of the first plurality of growth templates 18 to form the first semiconductor structure 5.

[0044] For example, 4H-SiC may be used to form SiC AccuFETs or power MOSFETs due to its advantages in 4H-SiC growth techniques and its attractive electronic properties, such as a larger bandgap and higher carrier mobility than other available wafer-scale SiC polytypes, such as 6H-SiC or 3C-SiC. However, such materials may also be used for selective growth of semiconductor structures. Note that the crystalline material of the epitaxial layer 10 can act as a growth seed for selectively grown WBG materials, and the diameter of the hollow growth template 18 can be chosen small enough to implement defect filters.

[0045] In the example provided, the entire semiconductor structure 5 may have a diameter in the range of 10 nm to 10 μm and a length in the longitudinal or normal direction relative to the top surface of the carrier substrate 2 of 1 μm to 100 μm. Due to their small size, the semiconductor structure 5 is also referred to in part as a nanowire structure in this disclosure. The doping concentration and diameter determine the resistance and current carrying capacity of each nanowire, while its length determines its blocking voltage.

[0046] In the particular example shown, chemical vapor deposition (CVD) is used to sequentially deposit first the n+ doped WBG sublayer 19 of the power MOSFET, followed by the p-doped WBG sublayer 20, followed by the n-doped WBG sublayer 21, followed by the n+ doped WBG sublayer 22. However, other types of semiconductor devices, such as AccuFETs, may be formed as well. In the completed device, the p-WBG sublayer 20 acts as the channel or depletion region, and the n-WBG sublayer 21 acts as the drift layer of the power MOSFET structure. Note also the fact that essentially the same type of semiconductor structure 5 is grown in parallel in all open first hollow growth templates 18, while WBG material is not deposited in the closed, yet-filled, sacrificial nanowires 12.

[0047] 3k shows the situation after the entire top surface of the device under fabrication has been coated with a thin metal layer 23. This may be done, for example, by atomic layer deposition (ALD) or other suitable processing methods. Material from metal layer 23 is then used to form gate lines and gate spacers for the previously grown first semiconductor structure 5.

[0048] Figure 3l shows the situation after removing part of the metal layer 23 in the area of ​​the remaining sacrificial nanowires 12. For example, a suitable photoresist mask in combination with selective etching can be used for this purpose. This results in a first gate line 24 being formed only in the area of ​​the first growth template 18. The gate line 24 then connects all the gate spacers of the first semiconductor structure 5, but is electrically isolated from the second semiconductor structure that will be formed subsequently.

[0049] FIG. 3m shows the situation after performing a gate metal etch to form first gate structures in the form of bottom gate spacers 26. The gate spacers 26 cylindrically surround each of the first semiconductor structures 5. During this processing step, the metal material of the metal layer 23 remains vertically only adjacent to the p-WBG sublayer 20, so that the gate spacers 26 can be used as control gates symmetrically surrounding the channel region of the completed MISFET structure on all sides.

[0050] 3n shows the situation after deposition of a third dielectric layer 27 on top of the fabricated device, which covers both the first semiconductor structure 5 and the remaining sacrificial nanowires 12.

[0051] FIG. 3o shows the situation after planarization of the device, exposing and opening the previously closed top ends 17, and removing the remaining sacrificial material of the second subset of initially grown sacrificial nanowires 12. This may be performed in a manner similar to that described above with respect to FIGS. 3e-3h for the first subset of sacrificial nanowires 12. For example, a further photoresist mask may be applied and planarized in a subsequent lithography step. Alternatively, a spin-on glass (SOG) layer may be formed. A plurality of second openings 29 are formed in the third dielectric layer 27 to expose the top ends 17 of the sacrificial nanowires 17, after which the top ends 17 are opened and the remaining sacrificial material is removed to form a second hollow growth template 28. At the same time, the previously fabricated first semiconductor structure 5 and associated bottom gate spacer 26 remain covered by the remaining portion of the third dielectric layer 27.

[0052] Figure 3p shows the situation after selective growth of second semiconductor structures 6 of a second type in second hollow growth template 28, as described above with respect to Figure 3j. However, as shown in Figure 3p, the sequence of the differentially doped WBG semiconductor materials for second semiconductor structures 6 is different. In the example provided, the sequence of WBG sublayers 19-22 is reversed: n+ WBG sublayer 22 is deposited first, followed by n- WBG sublayer 21, p- WBG sublayer 20, and finally n+ WBG sublayer 19.

[0053] Furthermore, as also shown in Figure 3p, after growing the second semiconductor structure 6, a further metal layer is deposited in the opening 16 surrounding the second hollow growth template 28. The deposited metal material is etched to form a second gate line (not visible in Figure 3p) and a corresponding second gate structure in the form of an upper gate spacer 30 surrounding the p-WBG sublayer 20 that forms the depletion layer of the resulting MISFET structure.

[0054] 3q shows the situation after further dielectric material has been deposited and planarized to form fourth dielectric layer 31. The thickness of the completed dielectric layer 31 corresponds approximately to the length of first and second semiconductor structures 5 and 6. Thus, at this stage, the top edges of first semiconductor structure 4 and second semiconductor structure 6 are exposed at the surface of fourth dielectric layer 31.

[0055] 3r shows the situation after forming metal contacts that electrically contact the respective edges of the grown semiconductor structures 5 and 6. In particular, alternating first and second top contacts 7 and 8 are formed to contact the top n+ WBG sublayer 22 of the first semiconductor structure 5 and the top n+ WBG sublayer 19 of the second semiconductor structure 6, respectively. Additionally, a metal layer is deposited on the bottom surface of the substrate 9 to form a common bottom contact 3 for all semiconductor structures 5 and 6.

[0056] Figure 4a shows a perspective view of a completed power semiconductor device 40 implementing a half-bridge circuit, which may be manufactured using the method described above with respect to Figures 3a-3r. Portions of the semiconductor device 40 have been removed from the view of Figure 4a to show the internal structure of the completed device.

[0057] As can be seen in Figure 4a, the semiconductor device 40 comprises a two-dimensional array of nanostructures or nanowires formed from a WBG material. As can be seen in the partial cross-sectional view of the first row shown in Figure 4a, the internal structure of the nanostructures embedded in the dielectric layer 4 differs with respect to their respective dopant profiles, as explained above. Thus, a first group of first semiconductor structures 5 of a first type and a second group of second semiconductor structures 6 of a second type are formed in the dielectric layer 4.

[0058] All first semiconductor structures 5 of a first type are connected in parallel using a positive DC (DC+) terminal 32 and an AC terminal 34. Correspondingly, all second semiconductor structures 6 of a second type are connected in parallel using a negative DC (DC-) terminal 33 and an AC terminal 34. It can be seen that each bottom gate spacer 26 and top gate spacer 30 completely surrounds each semiconductor structure 5 and 6, respectively. Furthermore, it can be seen that the individual bottom gate spacers 26 are connected in parallel by the metal material forming the first gate line 24, and the top gate spacers 30 are connected in parallel by the second gate line 25. Externally, the gate lines 24 and / or 25 are connected to one or more gate runners 35 or gate contacts disposed on the top surface of the dielectric layer 4.

[0059] 4b shows the top contact structure formed on the top surface of the dielectric layer 4. High-side gate contact 36 and low-side gate contact 37 are connected to the embedded first gate line 24 of the bottom gate spacer 26 and the second gate line 25 of the top gate spacer 30, respectively. In addition, a positive bus bar 38 is connected to all DC+ terminals 32 formed in every third column of the completed array. Correspondingly, a negative bus bar 39 is connected to all DC− terminals 33 in the remaining columns of the array.

[0060] The semiconductor devices 1 and 40 and the corresponding fabrication methods described above have several advantages over existing power semiconductor structures and fabrication methods. Among other things, the advantageous properties of WBG semiconductor materials, such as high critical electric fields and electron mobility and / or the potential for very high frequency switching, result in a much larger Baliga figure of merit (BFOM) compared to commonly used silicon. This makes such materials a suitable choice for power switching applications and enables several applications for energy transmission and electrical transport.

[0061] The specific fabrication method detailed above allows for cost-effective fabrication of highly integrated SiC power semiconductor devices. Notably, no implantation or activation is required during fabrication of semiconductor devices 1 and 40. Furthermore, it allows for the use of relatively inexpensive substrates, such as Si or polycrystalline SiC. The fabrication method has a low thermal budget and allows for advanced high-K gate dielectric integration. Furthermore, selective formation of two distinct groups of hollow growth masks 18 and 28 allows for the integrated formation of half or full bridges in a single design.

[0062] Together, such an integrated SiC half-bridge device concept allows SiC technology to enter lower voltage classes, for example, below 1.2 kV.

[0063] The embodiments illustrated in Figures 1-4B above represent exemplary embodiments of the improved power semiconductor devices 1 and 40 and methods of fabrication thereof. As such, they do not constitute an exhaustive list of all embodiments of the improved devices and methods of fabrication. Actual devices and methods of fabrication may differ from the illustrated embodiments, for example, with respect to materials used, specific processing steps, and circuit configurations. [Explanation of symbols]

[0064] Reference sign 1. Power semiconductor element 2 Carrier Board 3 bottom contacts 4 Dielectric Layer 5 (first) semiconductor structure 6 (second) semiconductor structure 7 (first) upper contact 8 (second) upper contact 9 Substrate 10 Epitaxial layer 11 Sacrificial Layer 12 Sacrificial nanowires 13 (first) dielectric layer 14 Photoresist layer 15 (second) dielectric layer 16 Opening 17 Upper end 18 (first) hollow growth template 19 n+WBG sublayer 20 p-WBG sublayer 21 n-WBG sublayer 22 n+WBG sublayers 23 Metal layer 24 (first) gate line 25 (second) gate line 26 (bottom) gate spacer 27 (third) dielectric layer 28 (second) hollow growth template 29 (second) opening 30 (top) gate spacer 31 (fourth) dielectric layer 32 DC+ terminal 33 DC-Terminal 34 AC terminal 35 Gate Runner 36 (high side) gate contact 37 (low side) gate contact 38 Positive bus bar 39 Negative bus bar 40 Power semiconductor element (having a half-bridge circuit)

Claims

1. - forming (S1) a plurality of growth templates on a carrier substrate (2), the plurality of growth templates including at least a plurality of first hollow growth templates (18) and a plurality of second hollow growth templates (28); - selectively growing (S2) a first sequence of differently doped wide bandgap semiconductor materials (WBG semiconductor materials) in each of said first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type; - forming a plurality of first gate structures, each of said first gate structures surrounding at least a channel region of a corresponding first semiconductor structure (5) of said plurality of first semiconductor structures (5); - forming at least one dielectric layer (4, 27, 31), said first gate structure being embedded in said at least one dielectric layer (4, 27, 31); - selectively growing (S3) in each of said second hollow growth templates (28) a second sequence of differently doped WBG semiconductor material, different from said first sequence, thereby forming a corresponding plurality of second semiconductor structures (6) of different second types; forming a plurality of second gate structures, each of which surrounds a channel region of a corresponding second semiconductor structure (6) of at least the plurality of second semiconductor structures (6), and which are formed at or near a top surface of the at least one dielectric layer (4, 27, 31) such that the first gate structure and the second gate structure are vertically offset with respect to each other; A method for manufacturing a power semiconductor element (1, 40), comprising:

2. 2. The method of claim 1, wherein in forming (S1) the plurality of growth templates (18, 28), an array of vertically oriented growth templates is formed, each of the vertically oriented growth templates extending in a direction perpendicular to a major surface of the carrier substrate (2).

3. forming (S1) a plurality of growth templates (18, 28); - depositing and structuring a sacrificial material on said carrier substrate (2), - covering said structured sacrificial material with a layer (13) of dielectric material; - selectively removing said sacrificial material surrounded by said dielectric material to form a plurality of said first hollow growth templates (18) and a plurality of said second hollow growth templates (28); 3. The method of claim 1 or 2, comprising:

4. First, the top ends (17) of the plurality of growth templates are sealed, and the method comprises: - opening only the top ends (17) of a first subset of the plurality of growth templates before growing the first sequence of differently doped WBG semiconductor materials; - resealing the top ends (17) of the first subset after growing the first sequence of differently doped WBG semiconductor materials; - opening only the top ends (17) of a second subset of the plurality of growth templates before growing the second sequence of differently doped WBG semiconductor materials; 3. The method of claim 1 or 2, further comprising:

5. 3. The method of claim 1, wherein the first and second sequences of differently doped WBG semiconductor materials are selectively grown by chemical vapor deposition (CVD) using different dopant profiles.

6. 3. The method according to claim 1, wherein the first hollow growth template (18) and / or the second hollow growth template (28) extend to a crystalline material of the carrier substrate (2), and in selectively growing (S2, S3), the crystalline material acts as a seed region for the WBG semiconductor material.

7. - selectively growing (S2) the first sequence of differently doped WBG semiconductor materials in each of the first hollow growth templates (18) to form a corresponding plurality of n+ / p- / n- / n+ semiconductor structures; and - selectively growing (S3) the second sequence of differently doped WBG semiconductor materials into each of the second hollow growth templates (28), forming a corresponding plurality of n+ / n- / p- / n+ semiconductor structures (6); 3. The method according to claim 1 or 2.

8. - forming first upper contacts (7) electrically connected to at least a subgroup of said plurality of first semiconductor structures (5); forming second upper contacts (8) electrically connected to at least a subgroup of said plurality of second semiconductor structures (6); and / or - forming bottom contacts (3) electrically connected to at least a subgroup of said plurality of first semiconductor structures (5) and a subgroup of said plurality of second semiconductor structures (6); 3. The method of claim 1 or 2, further comprising:

9. a carrier substrate (2) provided with at least one bottom contact (3), - at least one dielectric layer (4, 27, 31) formed on said carrier substrate (2), a plurality of first semiconductor structures (5) of a first type formed in said at least one dielectric layer (4, 27, 31), each of said plurality of first semiconductor structures (5) being electrically connected to said bottom contact (3) and comprising a first sequence of differently doped sublayers (19, 20, 21, 22) of a wide bandgap semiconductor material (WBG semiconductor material); a plurality of buried first gate structures arranged in said at least one dielectric layer (4, 27, 31), each of said first gate structures surrounding a channel region of a corresponding one of said plurality of first semiconductor structures (5); a plurality of second semiconductor structures (6) of different second types formed in said at least one dielectric layer (4, 27, 31), each of said second semiconductor structures (6) being electrically connected to said bottom contact (3) and comprising a second sequence of differently doped sublayers (22, 21, 20, 19) of said WBG semiconductor material, said second sequence being different from said first sequence; a plurality of second gate structures arranged on or near a top surface of said at least one dielectric layer (4, 27, 31), each of said second gate structures surrounding a channel region of a corresponding one of said second semiconductor structures (6), said first gate structure and said second gate structure being vertically offset with respect to each other; - first upper contacts (7) arranged on the upper surface of said at least one dielectric layer (4, 27, 31), said first upper contacts (7) electrically connecting at least a subgroup of said plurality of first semiconductor structures (5); - second upper contacts (8) arranged on the upper surface of said at least one dielectric layer (4, 27, 31), said second upper contacts (8) electrically connecting at least a subgroup of said plurality of second semiconductor structures (6); A power semiconductor element (1, 40).

10. - said plurality of first semiconductor structures (5) of said first type are n+ / p- / n- / n+ semiconductor structures, and - said second semiconductor structure (6) of said second type is an n+ / n- / p- / n+ semiconductor structure, Element (1, 40) according to claim 9.

11. - said at least one dielectric layer (4, 27, 31) comprises an array of vertically oriented growth templates extending in a direction perpendicular to the main surface of said carrier substrate (2); - the plurality of first semiconductor structures (5) are nanowire structures selectively grown in a first subset of the array of vertically oriented growth templates; and - said second semiconductor structure (6) is a nanowire structure selectively grown in a second subset of said array of vertically oriented growth templates; Element (1, 40) according to claim 9 or 10.

12. - the nanowire structure has a diameter between 10 nm and 10 μm, - the nanowire structure has a length between 1 μm and 100 μm, and / or - said at least one dielectric layer (4, 31) has a thickness between 1 μm and 100 μm, Element (1, 40) according to claim 11.

13. - said carrier substrate (2) comprises a layer made of silicon (Si) and / or polycrystalline silicon carbide (poly-SiC), - said at least one dielectric layer (4, 27, 31) comprises a dioxide, and / or the WBG semiconductor material comprises silicon carbide (SiC); Element (1, 40) according to claim 9 or 10.

14. The method of claim 13, wherein a plurality of the embedded first gate structures are configured to form a first metal insulator semiconductor field effect transistor (MISFET); and / or a plurality of said second gate structures are configured to form a second MISFET; Element (1, 40) according to claim 9 or 10.

15. a half-bridge circuit, wherein at least one of the bottom contacts (3) corresponds to an AC terminal (34) of the half-bridge circuit, the first upper contact (7) corresponds to a positive DC terminal (32) of the half-bridge circuit, and the second upper contact (8) corresponds to a negative DC terminal (33) of the half-bridge circuit, the embedded first gate structure being connected in parallel to the first gate contact (36) for selectively switching a first branch of the half-bridge circuit, and the second gate structure being connected in parallel to the second gate contact (37) for selectively switching a second branch of the half-bridge circuit, or a full bridge circuit, wherein the embedded first gate structures corresponding to a first subset of the plurality of first semiconductor structures (5) are connected in parallel to a first gate contact for selectively switching a first branch of the full bridge circuit, the embedded first gate structures corresponding to a second subset of the plurality of first semiconductor structures (5) are connected in parallel to a second gate contact for selectively switching a second branch of the full bridge circuit, the second gate structures corresponding to a first subset of the second semiconductor structures (6) are connected in parallel to a third gate contact for selectively switching a third branch of the full bridge circuit, and the second gate structures corresponding to a second subset of the second semiconductor structures (6) are connected in parallel to a fourth gate contact for selectively switching a fourth branch of the full bridge circuit. Element (1, 40) according to claim 14, comprising:

Images