Radio frequency crossover with high isolation in microelectronic H-frame devices.

Abstract

A microelectronic H-frame device including an RF crossover includes a stack of two or more substrates, where a bottom surface of a top substrate includes a top substrate bottom metallization and a top surface of the bottom substrate includes a bottom substrate top metallization, where the top substrate bottom metallization and the bottom substrate top metallization form a ground plane that provides isolation to allow a first signal line to traverse one or more of the top substrate and the bottom substrate without being impeded by a second signal line that traverses one or more of the top substrate and the bottom substrate at a non-zero angle to the first signal line, and where at least one of the first signal line and the second signal line proceeds to a second horizontal plane with the protection of the ground plane, thereby providing isolation from the other signal line.

Description

[Technical Field]

[0001] The present invention relates to a radio frequency crossover with high isolation in a microelectronic H-frame device.

[0002] Government Rights Statement The United States Government has rights in this invention pursuant to Government Contract No. 17-C-3186.

[0003] CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation-in-part of U.S. Patent Application No. 17 / 198,700, filed March 11, 2021, entitled "MICROELECTRONICS H-FRAME DEVICE," the entire contents of which are incorporated herein by reference.

[0004] This application also includes subject matter related to the subject matter of the following commonly assigned applications: The applications listed below are incorporated herein by reference in their entireties:

[0005] "FILTER WITH AN ENCLOSURE HAVING A MICROMACHINED INTERIOR USING SEMICONDUCTOR FABRICATION," Kunkee et al., filed April 28, 2020, Serial No. 16 / 860,642.

[0006] "CHANNELIZED FILTER USING SEMICONDUCTOR FABRICATION," Duan et al., filed June 30, 2020, Serial No. 16 / 916,644. Summary of the Invention

[0007] A microelectronic H-frame device, including a radio frequency (RF) crossover, includes a stack of two or more substrates, with a micromachined top cover attached to the top side of the device and a micromachined bottom cover attached to the bottom side of the device, forming an entirely microelectronic "H-frame" package. "H-frame" refers to a double-sided metal housing in which electronics are packaged to form a "module." Specifically, the letter "H" refers to the vertical cross-sectional shape of the housing. The horizontal bar of the "H" refers to a "central web," or common shared floor for component mounting. Substrate transmission lines, printed circuit boards, and other electronic components are attached to both the top and bottom sides of the central web. The vertical bar of the "H" refers to the perimeter vertical walls of the housing. The H-frame device is described in more detail in an application by Duan et al., entitled "MICROELECTRONICS H-FRAME DEVICE," filed March 11, 2021, and serial number 17 / 198,700.

[0008] The top chip's geometry can be different from the bottom chip's geometry. The top and bottom chips, even if different, can be fabricated on the same wafer. The top surface of the top chip and the bottom surface of the bottom chip are fabricated together on the front side of the wafer. Once the wafer is diced into chips, the top and bottom chips can be bonded together. When the number of desired chips is large, e.g., when the number of desired chips is greater than about 10, it is also possible to use a first dedicated wafer for the top chips and a second dedicated wafer for the bottom chips.

[0009] Embodiments of the present invention provide a compact vertical feedthrough transition that allows the spiral inductor to "escape" from the sealed cavity.

[0010] The metallization on the top and bottom covers and the through-substrate vias included in the substrates together form a continuous metal shield, or "wall," for the package. An intermediate substrate metallization ("intermediate" metal layer), including one or more of the top-substrate bottom metallization and the bottom-substrate top metallization, is sandwiched between the two substrates in the new H-frame to create a ground plane. The ground plane can provide isolation for first and second signal lines that cross within a microelectronic H-frame device, including radio frequency (RF) crossovers. The device's ground structure includes a substrate ground structure. The substrate ground structure includes at least one of the top-substrate top metallization, the bottom-substrate bottom metallization, the top-substrate bottom metallization, the bottom-substrate top metallization, and a through-substrate via that provides electrical connection from the top-substrate top metallization to the bottom-substrate bottom metallization. Bumps couple these two metallizations together through a bonding process. Passive circuits, such as filters, power splitters, and couplers, can be patterned directly on the top side of the substrate. Similarly, pads can be patterned directly on the top side of the substrate. The pads can be used to attach discrete circuits such as monolithic microwave integrated circuits (MMICs), capacitors, etc. Radio frequency (RF) transmission lines can include one or more of microstrip, coplanar waveguide (CPW), and stripline. RF transmission lines can run on the top side of the substrate, or even a thin "center web" or "intermediate" metal layer. RF transmission lines can switch layers. RF transmission lines can transition to different line types with fully integrated transitions including one or more of through-substrate vias, patterned metallization on the substrate, and vertical walls included in the cover.

[0011] Alcoves created in one of the covers, located at the electrical input and output of the H-frame, have metallized walls and help gradually transform the direction of the electric field from vertical (in the microstrip line) to horizontal (in the so-called "vertical coaxial cable" formed by the signal via and its surrounding ground vias). This helps achieve good return loss and suppresses radiation leakage, resulting in a transition design with good RF integrity.

[0012] The alcove is a portion of the outer wall of the cover that is used to create an escape transition. The alcove is contoured to facilitate a good RF transition. The alcove does not destroy the wall or introduce holes in the outer wall, thus maintaining the environmental seal provided by the outer wall of the cover.

[0013] The alcove with metallized walls helps to gradually transform the electric field direction from vertical (in the microstrip line) to horizontal (in the so-called "vertical coaxial cable" formed by the signal via and its surrounding ground vias), which helps to achieve good return loss as well as reduce radiation leakage, resulting in a transition design with good RF integrity.

[0014] The alcove in the escape transition is part of the outer wall of the cover. The alcove is contoured to facilitate a good RF transition. The alcove does not destroy the wall or introduce holes in the outer wall, thus maintaining the environmental seal provided by the outer wall of the cover.

[0015] A microelectronic high-isolation H-frame device including a radio frequency (RF) crossover is a stack of two or more substrates, the stack of substrates including a top substrate and a bottom substrate, at least one of the top substrate and the bottom substrate including at least one of a transmission line, a circuit board, a filter, a power splitter, a coupler, and another electronic component, bonding of the top substrate to the bottom substrate creates an electrical connection between the top substrate and the bottom substrate, a bottom surface of the top substrate includes a top-substrate bottom metallization, and a top surface of the bottom substrate includes a bottom-substrate top metallization. , a stack of two or more substrates, wherein the top substrate bottom metallization and the bottom substrate top metallization form a ground plane configured to provide isolation to allow a first signal line to traverse one or more of the top and bottom substrates without being impeded by a second signal line traversing one or more of the top and bottom substrates at a non-zero angle relative to the first signal line, and at least one of the first and second signal lines travels in a second horizontal plane with the protection of the ground plane, thereby providing isolation from the other signal line.

[0016] A microelectronic high-isolation H-frame device including a radio frequency (RF) crossover includes a stack of two or more substrates, the stack of substrates including a top substrate and a bottom substrate, at least one of the top substrate and the bottom substrate including at least one of a transmission line, a circuit board, a filter, a power splitter, a coupler, and another electronic component, bonding of the top substrate to the bottom substrate creates an electrical connection between the top substrate and the bottom substrate, a bottom surface of the top substrate includes a top-substrate bottom metallization, and a top surface of the bottom substrate includes a bottom-substrate top metallization, the top-substrate bottom metallization and the bottom-substrate top metallization allowing a first signal line to traverse one or more of the top substrate and the bottom substrate without being obstructed by a second signal line traversing one or more of the top substrate and the bottom substrate at a non-zero angle relative to the first signal line. the device further includes a ground structure configured to ground the device, the ground structure including a substrate ground structure including at least one of a top substrate top metallization, a bottom substrate bottom metallization, a top substrate bottom metallization, a bottom substrate top metallization, and a through-substrate via providing an electrical connection from the top substrate top metallization to the bottom substrate bottom metallization.

[0017] The accompanying drawings are used to more fully describe various exemplary embodiments and provide visual representations that can be used by those skilled in the art to better understand the exemplary embodiments disclosed herein and their inherent advantages, in which like reference numerals identify corresponding elements. [Brief explanation of the drawings]

[0018] [Figure 1A] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1B] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1C] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1D] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1E] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1F] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1G] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 1H] FIG. 1 is a diagram of a microelectronic H-frame device. [Figure 2] FIG. 11 shows details of signals entering a vertical feedthrough subcircuit in an H-frame device. [Figure 3A] FIG. 1 illustrates a diagram of radio frequency (RF) crossovers within an H-frame device. [Figure 3B] FIG. 1 illustrates a diagram of radio frequency (RF) crossovers within an H-frame device. DETAILED DESCRIPTION OF THE INVENTION

[0019] 1A-1H are a set of eight drawings of microelectronic H-frame devices.

[0020] FIG. 1A shows an exploded view of a microelectronic H-frame device 100.

[0021] The microelectronic H-frame device 100 includes a top cover 102. For example, the top cover 102 includes a semiconductor.

[0022] For example, as shown, the top cover 102 includes three top cover cavities 104A-104C: a first top cover cavity 104A, a second top cover cavity 104B, and a third top cover cavity 104C. The first top cover cavity 104A includes a partial first top cover cavity 104A. The second top cover cavity 104B includes a fully formed second top cover cavity 104B. The third top cover cavity 104C includes a partial third top cover cavity 104C.

[0023] For example, as described in more detail below, the top cover 102 may be micro-machined to form one or more of the top cover cavities 104A-104C. For example, as described in more detail below, the top cover 102 may be plated to form one or more of the top cover cavities 104A-104C. For example, the top cover 102 may be plated using gold to form one or more of the top cover cavities 104A-104C.

[0024] The microelectronic H-frame device 100 further includes a bottom cover 106. For example, the bottom cover 106 includes a semiconductor. The bottom cover 106 includes one or more bottom cover cavities 108. For example, as shown, the bottom cover 106 includes one bottom cover cavity 108. For example, as described in more detail below, the bottom cover 106 is micro-machined to form the bottom cover cavities 108. For example, as described in more detail below, the bottom cover 106 is plated to form the bottom cover cavities 108. For example, as described in more detail below, the bottom cover 106 is plated using gold to form the bottom cover cavities 108.

[0025] Microelectronic H-frame device 100 further includes substrate 110. Preferably, but not necessarily, substrate 110 includes a substantially planar substrate 110. Preferably, but not necessarily, substrate 110 is configured to be encapsulated between bottom cover 106 and top cover 102. For example, substrate 110 has a thickness of about 200 microns to about 800 microns.

[0026] Substrate 110 includes a top substrate 112. Preferably, but not necessarily, top substrate 112 includes silicon carbide (SiC).

[0027] The top substrate 112 is operably connected to the top cover 102. Preferably, the top substrate 112 is bonded to the top cover 102. The top substrate 112 includes a top substrate top surface 114. Preferably, but not necessarily, the top substrate top surface 114 includes the circuit components of the H-frame device 100, such as, for example, one or more of transistors, resistors, capacitors, and transmission lines.

[0028] Preferably, but not necessarily, the upper substrate upper surface 114 includes a first bonding interface 114 at which the upper substrate 112 is physically bonded to the upper cover 102. Preferably, but not necessarily, the upper substrate 112 is physically bonded to the upper cover 102. For example, the upper substrate 112 is physically bonded to the upper cover 102 at the upper substrate upper surface 114. For example, gold-gold compression bonding is used to physically attach the upper substrate 112 to the upper cover 102 at the upper substrate upper surface 114. For example, a first adhesive (not shown in FIG. 1A ) physically attaches the upper substrate 112 to the upper cover 102 at the upper substrate upper surface 114. For example, the first adhesive includes epoxy. For example, the first adhesive includes conductive epoxy. For example, the first adhesive includes gold that can be compression bonded to gold on the upper cover 102.

[0029] Preferably, but not necessarily, the top substrate top surface 114 is configured to support a top substrate top metallization 116. For example, the top substrate top metallization 116 has a thickness of about 1 micron to about 13 microns. For example, the top substrate top metallization 116 has a thickness of about 3.5 microns. For example, the top substrate top metallization 116 has a thickness of about 5.5 microns. The top substrate top metallization 116 includes a top substrate top ground plane 116A that is used as one or more of a reference conductor and a "ground conductor" in the H-frame device 100. The top substrate top metallization 116B includes a first input / output port 116B, which will be described in more detail below in FIG. 1C. The top substrate top metallization 116C includes a second input / output port 116C, which will also be described in more detail below in FIG. 1C. The top substrate top metallization 116D includes a first top substrate top signal line 116D configured to conduct a signal.

[0030] The top substrate top metallization 116 includes one or more top substrate top metallization openings 118A-118C. For example, as shown, the top substrate top metallization 116 includes three top substrate top metallization openings 118A-118C: a first top substrate top metallization opening 118A, a second top substrate top metallization opening 118B, and a third top substrate top metallization opening 118C. The first top substrate top metallization opening 118A includes a partial first top substrate top metallization opening 118A. The second top substrate top metallization opening 118B includes a fully formed second top substrate top metallization opening 118B. The third top substrate top metallization opening 118C includes a partial third top substrate top metallization opening 118C.

[0031] As will be described in more detail below, the first top substrate top metallization opening 118A is designed to generally align with the first top cover cavity 104A. Similarly, as will be described in more detail below, the second top substrate top metallization opening 118B is designed to generally align with the second top cover cavity 104B. As will be described in more detail below, the third top substrate metallization opening 118C is designed to generally align with the third top cover cavity 104C.

[0032] The top substrate 112 further includes a top substrate bottom surface 120. The top substrate bottom surface 120 includes a top substrate bottom ground plane 122A that is used as one or more of the reference and ground conductors in the H-frame device 100.

[0033] Preferably, but not necessarily, the top-substrate bottom surface 120 is configured to support a top-substrate bottom metallization 122. For example, the top-substrate bottom metallization 122 has a thickness of about 1 micron to about 13 microns. For example, the top-substrate bottom metallization 122 has a thickness of about 3.5 microns. For example, the top-substrate bottom metallization 122 has a thickness of about 5.5 microns. The top-substrate bottom metallization 122 includes a top-substrate bottom ground plane 122A, a first top-substrate bottom signal line 122B, a circular top-substrate bottom metallization via pad 122C, and a second top-substrate bottom signal line 122D. These three top-substrate bottom metallizations 122B, 122C, and 122D are described in more detail in FIGS. 2A and 2B.

[0034] The top-substrate bottom metallization 122 includes one or more top-substrate bottom metallization openings 123A-123C. For example, as shown, the top-substrate bottom metallization 122 includes three top-substrate bottom metallization openings 123A-123C: a first top-substrate bottom metallization opening 123A, a second top-substrate bottom metallization opening 123B, and a third top-substrate bottom metallization opening 123C.

[0035] The top substrate 112 further includes a plurality of metallized top substrate through-substrate signal vias 124A-124D, which are configured to provide a vertical electrical connection between the top substrate top metallization 116 and the top substrate bottom metallization 122. Bonding of the top cover 102 to the top substrate 112 creates a vertical electrical connection between the top substrate 112 and the top cover 102.

[0036] As described in more detail below, the top substrate through-substrate signal vias 124A-124D are preferably hermetically sealed electrical feed-through vias. The top substrate through-substrate signal vias 124A-124D are preferably formed by etching through the top substrate 112 and plating the inner walls of the voids created by the etching, as described in more detail below. Preferably, the top surface of at least one of the top substrate through-substrate signal vias 124A-124D is sealed. For example, preferably, the top surfaces of all of the top substrate through-substrate signal vias 124A-124D are sealed using gold. For example, preferably, the top surfaces of all of the top substrate through-substrate signal vias 124A-124D are sealed using gold. The top substrate signal vias 124A-124D are configured to provide high isolation while conducting electronic signals from the top substrate bottom metallization 122 to the top substrate top metallization 116.

[0037] For example, the top surface of at least one of the upper substrate through-substrate signal vias 124A-124D is preferably sealed using a solid cap comprising gold. The upper substrate through-substrate signal vias 124A-124D include a first upper substrate through-substrate signal via 124A, a second upper substrate through-substrate signal via 124B, a third upper substrate through-substrate signal via 124C, and a fourth upper substrate through-substrate signal via 124D. As described in more detail below, the upper substrate through-substrate signal vias 124A-124D are preferably hermetically sealed electrical feed-through vias. The upper substrate through-substrate signal vias 124A-124D are preferably formed by etching through the upper substrate 112 and plating the inner walls of the voids created by the etching, as described in more detail below. The top surface of at least one of the upper substrate through-substrate signal vias 124A-124D is preferably sealed. For example, preferably, the top surface of at least one of the upper substrate through substrate signal vias 124A-124D is sealed using gold. The functions of the second upper substrate through substrate signal via 124B and the third upper substrate through substrate signal via 124E are explained in more detail in Figures 2A and 2B.

[0038] The upper substrate 112 further includes a plurality of upper substrate ground vias 125A-125O, which are configured to provide electrical grounding. The upper substrate ground vias 125A-125O include a first upper substrate ground via 125A, a second upper substrate ground via 125F, and a third upper substrate ground via 125K. The functions of the first upper substrate ground via 125A, the second upper substrate ground via 125F, the third upper substrate ground via 125K, and the fourth upper substrate ground via 125M are described in more detail in Figures 1C, 1D, 1E, and 2.

[0039] Substrate 110 further includes a bottom substrate 126. Thus, substrate 110 includes a stack of top substrate 112 and bottom substrate 126. More generally, substrate 110 includes a stack of two or more substrates. Device 100 further includes metallization located between top substrate 112 and bottom substrate 126.

[0040] Preferably, but not necessarily, the bottom substrate 126 comprises silicon carbide (SiC).

[0041] The bottom substrate 126 is operably connected to the bottom cover 106. Preferably, the bottom substrate 126 is bonded to the bottom cover 106. The bottom substrate 126 includes a bottom substrate bottom surface 128. Preferably, but not necessarily, the bottom substrate bottom surface 128 includes the circuit components of the H-frame device 100, such as, for example, one or more of transistors, capacitors, and transmission lines. Preferably, but not necessarily, the bottom substrate bottom surface 128 includes a second bonding interface 128 where the bottom substrate 126 is physically bonded to the bottom cover 106. Preferably, but not necessarily, the bottom substrate 126 is physically bonded to the bottom cover 106. For example, the bottom substrate 126 is physically bonded to the bottom cover 106 at the bottom substrate bottom surface 128. For example, gold-gold pressure bonding is used to physically attach the top substrate 112 to the bottom cover 106 at the bottom substrate bottom surface 128. For example, a second adhesive (not shown in FIG. 1A) physically attaches bottom substrate 126 to bottom cover 106 at bottom substrate bottom surface 128. For example, the second adhesive comprises an epoxy.

[0042] Preferably, but not necessarily, bottom substrate bottom surface 128 is configured to support bottom substrate bottom metallization 130. For example, bottom substrate bottom metallization 130 has a thickness of about 1 micron to about 13 microns. For example, bottom substrate bottom metallization 130 has a thickness of about 3.5 microns. For example, bottom substrate bottom metallization 130 has a thickness of about 5.5 microns.

[0043] The bottom substrate 126 further includes a bottom substrate top surface 132. The bottom substrate top surface 132 is bonded to the top substrate bottom surface 120. As will be described in more detail below, the bottom substrate top surface 132 is bonded to the top substrate bottom surface 120 using a plurality of bonding bumps included on both the bottom substrate top surface 132 and the top substrate bottom surface 120.

[0044] The bottom substrate top surface 132 and the top substrate bottom surface 120 meet at a third bonding interface 134. Preferably, but not necessarily, the bottom substrate top surface 132 is configured to support a bottom substrate top metallization 135.

[0045] The bottom substrate top metallization 135 includes a bottom substrate top ground plane 135A, a first bottom substrate top signal line 135B, a circular bottom substrate top metallization via pad 135C, and a second bottom substrate top signal line 135D. The first top substrate bottom signal line 122B and the first bottom substrate top signal line 135B together form a first intermediate substrate signal line 122B-135B.

[0046] The bottom substrate top metallization 135 includes one or more bottom substrate top metallization openings 136A-136C. For example, as shown, the bottom substrate top metallization 135 includes three bottom substrate top metallization openings 136A-136C: a first bottom substrate top metallization opening 136A, a second bottom substrate top metallization opening 136B, and a third bottom substrate top metallization opening 136C.

[0047] As will be described in more detail below, the first bottom substrate top metallization opening 136A is configured to substantially align with the first top substrate bottom cavity 123A. Similarly, the second bottom substrate top metallization opening 136B is configured to substantially align with the second top substrate bottom cavity 123B. Similarly, the third bottom substrate top metallization opening 136C is configured to substantially align with the third top substrate bottom cavity 123C. When designing the H-frame device 100, the first top substrate bottom cavity 123A substantially matches the shape of the first bottom substrate top metallization opening 136A. Similarly, when designing the H-frame device 100, the second top substrate bottom cavity 123B substantially matches the shape of the second bottom substrate top metallization opening 136B. Also, in designing the H-frame device 100, the third top substrate bottom cavity 123C closely matches the shape of the third bottom substrate top metallization opening 136C.

[0048] For example, the bottom substrate top metallization 135 has a thickness of about 1 micron to about 13 microns. For example, the bottom substrate top metallization 135 has a thickness of about 3.5 microns. For example, the bottom substrate top metallization 135 has a thickness of about 5.5 microns. The bottom substrate top metallization 135 is preferably in electrical contact with the top substrate bottom metallization 122, thereby creating a vertical electrical connection between the top substrate bottom metallization 122 and the bottom substrate top metallization 135. Bonding the bottom cover 106 to the bottom substrate 126 creates a first vertical electrical connection between the bottom substrate 126 and the bottom cover 106.

[0049] Using a first vertical electrical connection, the top substrate top metallization 116 is electrically connected to the top substrate bottom metallization 122 on the outside of the top cover 102. The shape of the top substrate bottom metallization 122 connects the first vertical electrical connection on the outside of the top cover 102 to the first vertical electrical connection on the inside of the top cover 102. Using the first vertical electrical connection, the top substrate bottom metallization 122 is electrically connected to the top substrate top metallization 116 on the inside of the top cover 102.

[0050] Using a second vertical electrical connection, the bottom substrate bottom metallization 130 is electrically connected to the bottom substrate top metallization 135 inside the bottom cover 106 .

[0051] The bottom substrate bottom metallization 130 further includes a bottom substrate bottom signal line 137 configured to conduct a signal.

[0052] The bottom substrate bottom metallization 130 includes one or more bottom substrate bottom metallization openings 138. As shown, the bottom substrate metallization 130 includes one bottom substrate bottom metallization opening 138. The bottom substrate bottom metallization opening 138 includes a fully formed bottom substrate bottom metallization opening 138.

[0053] As will be explained in more detail below, the bottom substrate bottom metallization opening 138 is designed to generally align with the bottom cover cavity 108 .

[0054] The bottom substrate 126 further includes a plurality of bottom substrate through-substrate signal vias 140A-140B, which are configured to provide a second vertical electrical connection between the bottom substrate top metallization 135 and the bottom substrate bottom metallization 130. Bonding the bottom cover 106 to the bottom substrate 126 creates the second vertical electrical connection between the bottom substrate 126 and the bottom cover 106.

[0055] As described in more detail below, the bottom substrate through-substrate vias 140A-140B are preferably hermetically sealed electrical feed-through vias. The bottom substrate through-substrate vias 140A-140B are preferably formed by etching through the top substrate 112 and plating the inner walls of the voids created by the etching, as described in more detail below. Preferably, the top surface of at least one of the bottom substrate through-substrate vias 140A-140B is sealed. For example, preferably, the top surface of at least one of the bottom substrate through-substrate vias 140A-140B is sealed using gold. For example, preferably, the top surface of at least one of the bottom substrate through-substrate vias 140A-140B is sealed using a solid cap comprising gold. For example, preferably, the top surface of at least one of the bottom substrate through-substrate vias 140A-140B is sealed using a solid cap made of gold. The bottom substrate through-substrate signal vias 140A-140B are configured to provide high isolation while conducting electronic signals from the bottom substrate top metallization 135 to the bottom substrate bottom metallization 130.

[0056] The bottom substrate through-substrate signal vias 140A-140B include a first bottom substrate signal via 140A and a second bottom substrate signal via 140B. These two bottom substrate signal vias 140A and 140B are described in more detail in Figures 1H, 2A, and 2G.

[0057] The bottom substrate 126 further includes a plurality of bottom substrate through-substrate ground vias 141A-141N, which are configured to provide electrical grounding. The bottom substrate ground vias 141A-141N include a first bottom substrate ground via 141A, a second bottom substrate ground via 141F, and a third bottom substrate ground via 141H. The functions of the first bottom substrate ground via 141A, the second bottom substrate ground via 141F, and the third bottom substrate ground via 141H are described in more detail in FIG. 1H.

[0058] FIG. 1B shows a detailed view of the top cover 102 and bottom cover 106.

[0059] Similarly, the top cover 102 includes a first top cover cavity 104A, a second top cover cavity 104B, and a third top cover cavity 104C.

[0060] Similarly, the first top cover cavity 104A includes a partial first top cover cavity 104A. The partial first top cover cavity 104A includes an upper first cavity wall 143A. The upper first cavity wall 143A becomes visible after the top cover 102 is bonded to the substrate 110, as described in more detail below.

[0061] Similarly, the second top cover cavity 104B includes a fully formed second top cover cavity 104B. The second top cover cavity 104B includes a second top cavity wall 143B.

[0062] Similarly, the third top cover cavity 104C includes a partial third top cover cavity 104C. The partial third top cover cavity 104C includes an upper third cavity wall 143C. The upper third cavity wall 143C becomes visible after the top cover 102 is bonded to the substrate 110, as described in more detail below.

[0063] Top cover 102 further includes top cover metallization 145. Top cover metallization 145 grounds top cover 102, thereby providing an integral part of the overall grounding structure of microelectronic H-frame device 100. For example, top cover metallization 145 includes singly connected top cover metallization 145. For example, as described in more detail below, top cover metallization 145 is produced by performing gold plating on a micro-machined silicon wafer.

[0064] The top cover metallization 145 includes a metallized upper cavity floor 146. The second top cover cavity 104B includes a metallized upper cavity floor 146. When the top cover 102 is bonded to the top substrate 120, the metallized upper cavity floor 146 becomes the top cover ceiling 146 of the top cover 102.

[0065] Top cover metallization 145 further includes metallized top cover top surface 147. As described in more detail below, during fabrication of the device (item 100 in FIG. 1A), metallized top cover top surface 147 is bonded to bumps on top substrate top surface 114 to complete the bond.

[0066] The top cover metallization 145 further includes a metallized second upper cavity wall 143B. The second top cover cavity 104B includes a metallized second upper cavity wall 143B.

[0067] Bottom cover 106 further includes bottom cover metallization 149. Bottom cover metallization 149 grounds top cover 102. Thus, bottom cover metallization 149 provides an integral part of the overall grounding structure of the microelectronic H-frame device (item 100 in FIG. 1A). For example, bottom cover metallization 149 includes a singly connected bottom cover metallization 149. For example, as described in more detail below, bottom cover metallization 149 is produced by performing gold plating on a micro-machined silicon wafer.

[0068] Bottom cover metallization 149 includes a metallized bottom cavity floor 150. Bottom cover cavity 108 includes a metallized bottom cavity floor 150. When bottom cover 106 is bonded to bottom substrate 126, metallized bottom cavity floor 150 becomes the floor 150 of bottom cover 106.

[0069] Bottom cover metallization 149 further includes a metallized bottom cover top surface 151. As described in more detail below, during fabrication of the device (item 100 in FIG. 1A), metallized bottom cover top surface 151 is bonded to bumps on the bottom substrate bottom surface (item 128 in FIG. 1A) to complete the bond.

[0070] The bottom cover metallization 149 further includes a metallized bottom cavity wall 152. The bottom cover cavity 108 includes a metallized bottom cavity wall 152.

[0071] 1C shows a detailed view of the top substrate 112. Similarly, the top substrate 112 includes a top substrate top surface 114, a top substrate top metallization 116, a top substrate bottom surface 120, top substrate through-substrate vias 124A-124D, and top substrate ground vias 125A, 125K, and 125M. Similarly, the top substrate bottom surface 120 includes a top substrate bottom metallization 122.

[0072] Similarly, the top substrate top metallization 116 includes a top substrate top ground plane 116A, a first input / output port 116B, a second input / output port 116C, and a first top substrate top signal line 116D.

[0073] Similarly, the top substrate 112 further includes a first input / output port 116B. Preferably, but not necessarily, the top substrate top surface 114 includes the first input / output port 116B. The first input / output port 116B is configured to receive one or more of an input signal and transmit an output signal. The first input / output port 116B includes a first port first ground metal pad 154A, a first port signal metal pad 154B, and a first port second ground metal pad 154C.

[0074] A first ground metal pad 154A of the first port is operably connected to the top substrate bottom surface 120 by one or more of the top substrate through-substrate vias 124A-124D. A second ground metal pad 154C of the first port is operably connected to the top substrate ground plane 120 by one or more of the top substrate through-substrate vias 124A-124D.

[0075] The top substrate 112 further includes a second input / output port 116C. Preferably, but not necessarily, the top substrate top surface 114 includes the second input / output port 116C. The second input / output port 116C is configured to receive one or more of an input signal and a output signal. The second input / output port 116C includes a second port first ground metal pad 156A, a second port signal metal pad 156B, and a second port second ground metal pad 156C. The second port signal metal pad includes a third signal line 156B.

[0076] A first ground metal pad 156A of the second port is operably connected to the top substrate bottom surface 120 by one or more of the top substrate through-substrate vias 124A-124D. A second ground metal pad 156C of the second port is operably connected to the top substrate bottom surface 120 by one or more of the top substrate through-substrate vias 124A-124D.

[0077] The top substrate top metallization 116 further includes one or more top substrate top metallization continuous bumps 158A-158B. As shown, the top substrate top metallization 116 includes two top substrate top metallization concentric continuous bumps 158A, 158B that can be used to bond the top substrate 112 to the top cover 102. Preferably, the concentric top substrate top metallization continuous bumps 158A, 158B are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0078] The top substrate top metallization 116 further includes one or more top substrate top metallization individual bumps 160A-160P, which can be used to bond the top substrate 112 to the top cover 102. Preferably, the top substrate top metallization individual bumps 160A-160P are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0079] Preferably, the top substrate top metallization continuous bumps 158A, 158B are configured to provide an environmental seal configured to prevent foreign matter from entering the top cover 102 after the formation of the bond on the top substrate top surface 114, thereby protecting the H-frame device 100.

[0080] Preferably, the top substrate top metallization individual bumps 160A-160P are configured to provide an environmental seal configured to prevent foreign matter from entering the top cover 102 after the formation of bonds on the top substrate top surface 114, thereby protecting the H-frame device 100.

[0081] The dotted line 161 in FIG. 1C bounds a detailed view of the device, which is provided and explained in more detail in FIG. 1E.

[0082] 1D shows an exploded view of the top substrate 112. The top substrate 112 includes a top substrate top metallization 116, a top substrate bottom metallization 122, and a top dielectric 162. The top dielectric 162 includes an electrical insulator 162. Similarly, the top substrate top metallization 116 includes top substrate through-substrate vias 124A-124D, top substrate ground vias 125F, 125K, and 125M, top substrate top metallization continuous bumps 158A-158B, and top substrate top metallization discrete bumps 160A-160P.

[0083] Also shown are upper substrate top surface 114, upper substrate bottom surface 120, and upper substrate through-substrate vias 124A-124D.

[0084] The top substrate top metallization 116 further includes a first input / output port 116 B. The top substrate top metallization 116 further includes a second input / output port 116 C.

[0085] The upper dielectric 162 includes an upper substrate top surface 114, an upper substrate bottom surface 120, and upper substrate through-substrate vias 124A-124D.

[0086] Similarly, the first input / output port 116B includes a first port first ground metal pad 154A, a first port signal metal pad 154B, and a first port second ground metal pad 154C. Similarly, the first port first ground metal pad 154A is operably connected to the top substrate bottom ground plane 122A by one or more of the top substrate through-substrate vias 124A-124D. The first port second ground metal pad 154C is operably connected to the top substrate ground plane 122A by one or more of the top substrate through-substrate vias 124A-124D.

[0087] Similarly, the second input / output port 116C includes a second port first ground metal pad 156A, a second port signal metal pad 156B, and a second port second ground metal pad 156C. Similarly, the second port first ground metal pad 156A is operably connected to the top substrate bottom ground plane 122A by one or more of the top substrate through-substrate vias 124A-124D. Similarly, the second port second ground metal pad 156C is operably connected to the top substrate ground plane 122A by one or more of the top substrate through-substrate vias 124A-124D.

[0088] The top-substrate bottom metallization 122 includes a grounded top-substrate bottom ground plane 122A, a first top-substrate bottom signal line 122B configured to conduct a signal, and a first top-substrate bottom metallization opening 123A, a second top-substrate bottom metallization opening 123B, and a third top-substrate bottom metallization opening 123C.

[0089] In designing the H-frame device 100, the first top substrate bottom signal line 122B generally conforms to the bottom substrate top signal line (item 135B shown in FIG. 1A, not shown in FIG. 1D). The first top substrate bottom signal line 122B is bonded to the bottom substrate top signal line (item 135B shown in FIG. 1A, not shown in FIG. 1D) at a third bonding interface 134 using a plurality of bonding bumps (not shown in FIG. 1D). The first top substrate bottom signal line 122B and the first bottom substrate top signal line (item 135B shown in FIG. 1A, not shown in FIG. 1D) together form the first middle substrate signal line 122B-135B.

[0090] In designing the H-frame device 100, the circular top substrate bottom metallization via pad 122C generally matches the shape of the circular bottom substrate top metallization via pad (item 135C shown in FIG. 1A, not shown in FIG. 1D). The circular top substrate bottom metallization via pad 122C is bonded to the circular bottom substrate top metallization via pad (item 135C shown in FIG. 1A, not shown in FIG. 1D) at a third bonding interface 134 using a plurality of bonding bumps (not shown in FIG. 1D). The circular top substrate bottom metallization via pad 122C and the circular bottom substrate top metallization via pad (item 135C shown in FIG. 1A, not shown in FIG. 1D) together form via pads 122C-135C, which help provide one or more of electrical connection and electrical fencing.

[0091] Similarly, the top-substrate bottom metallization 122 further includes a circular top-substrate bottom metallization 122C and a second top-substrate bottom signal line 122D.

[0092] The top-substrate bottom metallization 122 further includes one or more top-substrate bottom metallization continuous bumps 163A-163B. As shown, the top-substrate bottom metallization 122 includes two concentric top-substrate bottom metallization continuous bumps 163A, 163B that can be used to bond the top substrate 112 to the bottom substrate 126. Preferably, the concentric top-substrate bottom metallization continuous bumps 163A, 163B are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0093] The top substrate bottom metallization 122 further includes one or more top substrate bottom metallization individual bumps 164A-164P that can be used to bond the top substrate 112 to the bottom substrate 126. Preferably, the top substrate bottom metallization individual bumps 164A-164P are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0094] Preferably, the top substrate bottom metallization continuous bumps 163A, 163B are configured to provide an environmental seal configured to prevent foreign matter from entering the substrate 110 after the formation of the bond at the top substrate bottom surface 120, thereby protecting the H-frame device 100.

[0095] Preferably, the top substrate bottom metallization individual bumps 164A-164P are configured to provide an environmental seal configured to prevent foreign matter from entering the substrate 110 after the formation of the bond at the top substrate bottom surface 120, thereby protecting the H-frame device 100.

[0096] Figure IE shows a detailed view of portion 161 of Figure 1C, showing a portion of top substrate 112. Dotted line 161 in Figure 1C bounds the detailed view of the device shown in Figure IE.

[0097] Similarly, the top substrate 112 includes a top substrate top surface 114, top substrate top metallizations 116A and 116C, a top substrate bottom surface 120, top substrate through-substrate vias 124A-124D, and top substrate ground vias 125F, 125K, and 125M.

[0098] Similarly, the upper substrate 112 further includes a second input / output port 116C. Preferably, but not necessarily, the upper substrate top surface 114 includes the second input / output port 116C. Similarly, the second input / output port 116C includes a second port first ground metal pad 156A, a second port signal metal pad 156B, and a second port second ground metal pad 156C.

[0099] The first ground metal pad 156A of the second port is operably connected to the top substrate bottom ground plane 122A by a second top substrate ground via 125F. The second port's second signal metal pad 156B is operably connected to the second top substrate bottom signal line 122D by a fourth top substrate through-substrate via 124D. The fourth top substrate through-substrate via 124D includes a high-temperature top substrate ground via 124D that can be used in transitions. The second port's third top metal pad 156C is operably connected to the top substrate bottom ground plane 122A by a third top substrate ground via 125K. The third top substrate ground via 125K is configured to provide a common ground for one or more of the top substrate 112 and the H-frame device 100. The fourth top substrate ground via 125M is configured to provide a common ground for one or more of the top substrate 112 and the H-frame device 100.

[0100] Similarly, the top substrate top metallization 116 further includes one or more top substrate top metallization continuous bumps 158A-158B. As shown, the top substrate top metallization 116 includes two concentric top substrate top metallization continuous bumps 158A, 158B that can be used to bond the top substrate 112 to the top cover 102. Preferably, the top substrate top metallization concentric continuous bumps 158A, 158B are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0101] Similarly, the top substrate top metallization 116 further includes one or more top substrate top metallization individual bumps 160A-160P that can be used to bond the top substrate 112 to the top cover 102. Preferably, the individual bumps 160A-160P are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0102] Preferably, the top substrate top metallization continuous bumps 158A, 158B are also configured to provide an environmental seal configured to prevent foreign matter from entering the top cover 102 after the formation of the bond on the top substrate top surface 114, thereby protecting the H-frame device 100.

[0103] 1F shows a detailed view of bottom substrate 126. Similarly, bottom substrate 126 includes bottom substrate bottom surface 128, bottom substrate top surface 132, bottom substrate top metallization 135 (shown in more detail here, and therefore four bottom substrate top metallization regions shown here), bottom substrate bottom metallization opening 138, bottom substrate through-substrate vias 140A and 140B, and bottom substrate ground vias 141F and 141H. Similarly, bottom substrate top surface 132 includes bottom substrate top metallization 135. Similarly, bottom substrate top metallization 135 includes first bottom substrate first metallization opening 136A, second bottom substrate top metallization opening 136B, and third bottom substrate top metallization opening 136C.

[0104] The bottom substrate top metallization 135A further includes one or more bottom substrate top metallization continuous bumps 165A-165B. As shown, the bottom substrate top metallization 135A includes two concentric bottom substrate top metallization continuous bumps 165A, 165B that can be used to bond the bottom substrate 126 to the top substrate 112. Preferably, the concentric bottom substrate top metallization continuous bumps 165A, 165B are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0105] The bottom substrate top metallization 135A further includes one or more bottom substrate top metallization individual bumps 166A-166P that can be used to bond the bottom substrate 126 to the top substrate 112. Preferably, the bottom substrate top metallization individual bumps 166A-166P are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0106] Preferably, the bottom substrate top metallization continuous bumps 165A, 165B are configured to provide an environmental seal configured to prevent foreign matter from entering between the top substrate 112 and the bottom substrate 126 after the formation of the bond at the surface 134, thereby protecting the H-frame device 100.

[0107] Preferably, the bottom substrate top metallization individual bumps 166A-166P are configured to provide one or more environmental seals configured to prevent one or more of moisture and foreign matter from entering between the top substrate 112 and the bottom substrate 126 after the formation of the bond on the bottom substrate top surface 132, thereby protecting the H-frame device 100.

[0108] The dotted line 175 in FIG. 1F demarcates a detailed view of the device, which is provided and described in more detail in FIG. 1H.

[0109] 1G shows an exploded view of bottom substrate 126. Similarly, bottom substrate 126 includes bottom substrate bottom metallization 130, bottom substrate top metallization 135, and bottom substrate bottom metallization opening 138. Bottom substrate bottom metallization 130 includes bottom substrate bottom signal line 137 configured to conduct a signal.

[0110] Bottom substrate 126 further includes bottom dielectric 179. Bottom dielectric 179 includes an electrical insulator. Similarly, bottom substrate top metallization 135 includes bottom substrate top metallization continuous bumps 165A-165B and bottom substrate top metallization discrete bumps 166A-166P.

[0111] Also shown are bottom substrate bottom surface 128, bottom substrate top surface 132, bottom substrate through-substrate vias 140A and 140B, and bottom substrate ground vias 141F and 141H.

[0112] Bottom dielectric 179 includes bottom substrate bottom surface 128, bottom substrate top surface 132, and bottom substrate through-substrate vias 140A and 140B.

[0113] The bottom substrate bottom metallization 130 includes a grounded bottom substrate bottom ground plane 180. The bottom substrate bottom metallization 130 includes a bottom substrate bottom signal line 137 configured to conduct a signal.

[0114] The bottom substrate bottom metallization 130 further includes one or more bottom substrate bottom metallization continuous bumps 183A-183B. As shown, the bottom substrate bottom metallization 130 includes two concentric bottom substrate bottom metallization continuous bumps 183A, 183B, which can be used to bond the bottom substrate 126 to the bottom cover 106. Preferably, the bottom substrate bottom metallization concentric continuous bumps 183A, 183B are spaced apart such that they are separated by less than about 0.1 wavelengths of the highest frequency of interest. Preferably, the bottom substrate bottom metallization discrete bumps 185A-185P are spaced apart such that they are separated by less than about 0.1 wavelengths of the highest frequency of interest.

[0115] Preferably, the bottom substrate bottom metallization continuous bumps 183A, 183B are configured to provide an environmental seal configured to prevent foreign matter from entering the substrate 110 after the formation of the bond at the bottom substrate bottom surface 128, thereby protecting the H-frame device 100.

[0116] Preferably, the bottom substrate bottom metallization individual bumps 185A-185P are configured to provide one or more environmental seals configured to prevent one or more of moisture and foreign matter from entering the bottom cover 106 after the formation of bonds on the bottom substrate bottom surface 128, thereby protecting the H-frame device 100.

[0117] Figure 1H shows a detailed view of portion 175 of Figure 1F, showing a portion of bottom substrate 126. Dotted line 175 in Figure 1F marks the boundary of the detailed view of the device shown in Figure 1H.

[0118] Similarly, bottom substrate 126 includes bottom substrate bottom surface 128, bottom substrate top surface 132, bottom substrate top metallization 135A and 135C-135D, bottom substrate through-substrate vias 140A and 140B, bottom substrate top metallization concentric continuous bumps 165A-165B, bottom substrate top metallization discrete bumps 164A-164P, and bottom substrate bottom ground plane 180. Preferably, concentric bottom substrate bottom metallization continuous bumps 165A, 165B are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0119] The bottom substrate 126 includes second bottom substrate through-substrate vias 140B, including second high-temperature bottom substrate through-substrate via 140B usable in the transition. The bottom substrate 126 further includes second bottom substrate ground via 141F and third bottom substrate ground via 141H. The second bottom substrate ground via 141F is configured to provide a common ground for one or more of the bottom substrate 126 and the H-frame device 100. Similarly, the third bottom substrate ground via 141H is configured to provide a common ground for one or more of the bottom substrate 126 and the H-frame device 100.

[0120] Bottom substrate bottom metallization 130 further includes one or more individual bumps 185A-185P that can be used to bond bottom substrate 126 to bottom cover 106. Preferably, individual bumps 185A-185P are spaced apart such that they are separated by less than about 0.1 wavelength of the highest frequency of interest.

[0121] Preferably, the bottom substrate bottom metallization continuous bumps 183A, 183B are configured to provide an environmental seal configured to prevent foreign matter from entering the bottom cavity (not shown in this view, item 108 in FIG. 1A) after the formation of a bond to the bottom cover 106 at the bottom substrate bottom surface 128, thereby protecting the H-frame device 100.

[0122] FIG. 2 shows details of the signals entering the vertical feedthrough subcircuit 220 in the H-frame device 100.

[0123] FIG. 2 shows details of subcircuit 220 (which is the same subcircuit 220 as the second subcircuit 220 described in FIG. 2E of the "Microelectronics H-Frame Device" application) and illustrates vertical feedthrough circuit 220 for signals entering subcircuit 220 of H-frame device 100. Similarly, H-frame device 100 includes top cover 102, bottom cover 106, and substrate 110. Similarly, top cover 102 includes second top cavity 104B. Similarly, second top cavity 104B includes second top cavity wall 143B. Similarly, bottom cover 106 includes bottom cavity 108. Similarly, bottom cavity 108 includes bottom cavity wall 152. Bottom cavity 108 has a representative bottom cavity diameter 260 equal to approximately 800 microns.

[0124] Similarly, substrate 110 includes a top substrate 112 and a bottom substrate 126. Similarly, top substrate 112 includes a top substrate top surface 114 and a top substrate bottom surface 120. Similarly, top substrate top surface 114 includes a first top substrate top signal line 116D. Similarly, bottom substrate 126 includes a bottom substrate top surface 132, which is bonded to top substrate bottom surface 120 at a third bonding interface 134 after assembly. Similarly, top substrate bottom surface 120 includes a first signal bottom substrate signal via 140A and a bottom substrate bottom signal line 137. Bottom substrate top surface 132 and top substrate bottom surface 120 include top and bottom metallization openings 262 where substrate material has been removed, which allow signals to pass through bottom substrate top surface 132 and top substrate bottom surface 120. The top and bottom metallization openings 262 have a typical cutout diameter 265 equal to approximately 600 microns.

[0125] Similarly, the bottom surface further includes a bottom substrate bottom surface 128 .

[0126] An electronic signal preferably enters sub-circuit 220 on top substrate top surface 114 from first sub-circuit 210 via first top substrate top signal line 116D. Before striking second top cavity wall 143B, the electronic signal travels from first top substrate top signal line 116D to third top substrate signal via 124C. Third top substrate signal via 124C electrically connects first top substrate top signal line 116D to via pads 122C-135C, described above with respect to FIG. 1D .

[0127] As described above with respect to FIG. 1D , in designing the H-frame device 100, the circular top substrate bottom metallization via pad 122C generally conforms in shape to the circular bottom substrate top metallization via pad (item 135C shown in FIG. 1A, not shown in FIG. 2 ). The circular top substrate bottom metallization via pad 122C is bonded to the circular bottom substrate top metallization via pad (item 135C shown in FIG. 1A, not shown in FIG. 2 ) at a third bonding interface 134 using a plurality of bonding bumps (not shown in FIG. 2 ). The circular top substrate bottom metallization via pad 122C and the circular bottom substrate top metallization via pad (item 135C shown in FIG. 1A, not shown in FIG. 2 ) together form via pads 122C-135C, which help provide one or more of electrical connection and electrical fencing. The via pads 122C-135C have a typical via pad diameter 270 equal to approximately 200 microns.

[0128] The third top substrate signal via 124C is coupled to the bottom substrate top surface 132 at a third bonding interface 134. The third top substrate signal via 124C includes a one-layer vertical feedthrough 124E. The electronic signal then travels from the circular top substrate bottom metallization via pad 122C through the top and bottom metallization openings 262 to the first bottom substrate signal via 140A. The first bottom substrate signal via 140A electrically connects the signal to the bottom substrate bottom signal line 137. Once the signal reaches the bottom substrate bottom signal line 137, the signal continues as an inverted microstrip traveling away from the bottom cavity wall 152 toward the third sub-circuit 230, which is shown in more detail in FIG. 2G of the co-filed "Microelectronics H-Frame Device" application.

[0129] The second top cavity wall 143B and the bottom cavity wall 152 comprise integral components of the vertical feedthrough transition circuit 220. The second top cavity wall 143B and the bottom cavity wall 152 help gradually change the direction of the electric field within the vertical feedthrough transition circuit 220. The second top cavity wall 143B and the bottom cavity wall 152 essentially form a vertical channel connecting the first top substrate top signal line 116D and the first bottom substrate signal via 140A. The first top substrate top signal line 116D and the first bottom substrate signal via 140A become horizontal channels 116D and 137, respectively, connected to each other via the first-layer vertical feedthrough 124E, the circular top substrate bottom metallization via pad 122C, and the first bottom substrate signal via 140A. Together, these elements form a Z-shaped three-dimensional channelization 272 that prevents signals from leaking into areas outside the channelization 272. The Z-shape of the channelization 272 is an example, and other configurations are possible within the scope of embodiments of the present invention. The channelization 272 allows the electronic signal to undergo one or more of a change in direction and a change in height. As shown, the signal is initially horizontal while passing through the first top substrate top signal line 116D, then becomes vertical while passing through the first-layer vertical feedthrough 124E, the circular top substrate bottom metallization via pad 122C, and the first bottom substrate signal via 140A. The signal then becomes horizontal again while passing through the bottom substrate bottom signal line 137.

[0130] 2 via a bottom substrate bottom signal line 137 located on the bottom substrate bottom surface 128. The subcircuit 220 therefore functions as a vertical feedthrough transition 220, receiving a signal on the top substrate top surface 114 via the first top substrate top signal line 116D and generating an output signal on the bottom substrate bottom surface 128.

[0131] 3A-3B are a set of two drawings showing diagrams of radio frequency (RF) crossovers within an H-frame device.

[0132] 3A shows a top view of a microelectronic H-frame device 100 including a radio frequency (RF) crossover 300. Also shown are a top cover 102, a second top cover cavity 104B, a bottom cover 106, a bottom cover cavity 108, a substrate 110, a top substrate 112, a first bonding interface 114, a first input / output port 116B, a second input / output port 116C, a first top substrate top signal line 116D, a top substrate bottom surface 120, a first top substrate bottom signal line 122B, a circular top substrate bottom metallization via pad 122C, a second top substrate bottom signal line 122D, a second top substrate signal via 124B, a third top substrate signal via 124C, a fourth top substrate signal via 124D, and a first top substrate ground via 124C. 5A, second top substrate ground via 125F, third top substrate ground via 125K, fourth top substrate ground via 125M, bottom substrate 126, second bonding interface 128, third bonding interface 134, bottom substrate bottom signal line 137, first bottom substrate signal via 140A, second bottom substrate signal via 140B, first port first ground metal pad 154A, first port signal metal pad 154B, first port second ground metal pad 154C, second port first ground metal pad 156A, second port signal metal pad 156B, and second port second ground metal pad 156C. In this example, a typical thickness of SiC substrate 110 is about 200 microns, and the relative dielectric value of SiC substrate 110 is about 9.7.

[0133] The sub-circuit 220 includes a vertical feedthrough circuit 220 or a microstrip 220. The vertical feedthrough circuit 220 includes a first top substrate upper signal line 116D extending on the top substrate upper surface 114. The second microstrip 220 further includes a top substrate bottom surface 120 disposed between the top substrate 112 and the bottom substrate 126.

[0134] The second sub-circuit 220 includes a portion of the first top substrate signal line 116D, a third top substrate signal via 124C, a circular top substrate bottom metallization via pad 122C, a first bottom substrate signal via 140A, and a portion of the bottom substrate bottom signal line 137. The first top substrate signal line 116D is operably connected to the third top substrate signal via 124C. Preferably, as shown, the first top substrate signal line 116D is electrically connected to the third top substrate signal via 124C. The third top substrate signal via 124C is operably connected to the circular top substrate bottom metallization via pad 122C. Preferably, as shown, the first top substrate signal via 124C is electrically connected to the circular top substrate bottom metallization via pad 122C.

[0135] As can be seen more clearly in circuit 205 of FIG. 2B of the "Microelectronics H-Frame Device" application, but also now in item 310 of FIG. 3, the first signal line 310 is, from left to right, First port signal metal pad 154B, Top through-substrate signal vias 124A, first top substrate bottom signal line 122B, second top substrate signal via 124B, first top substrate top signal line 116D, third top substrate signal via 124C, circular top substrate bottom metallization via pad 122C, first bottom substrate signal via 140A, bottom substrate bottom signal line 137, second bottom substrate bottom signal via 140B, second top substrate bottom signal line 122D, fourth top substrate signal via 124D, and finally second port signal metal pad 156B.

[0136] RF intersection 300 includes a first signal line 310. First signal line 310 is the same item as circuit 205 in FIG. 2B of the "Microelectronics H-Frame Device" application. RF intersection 300 further includes a second signal line 320. Second signal line 320 crosses one or more of top substrate 112 and bottom substrate 126 at a non-zero angle 330 relative to first signal line 310. As shown in FIG. 3, angle 330 is equal to 90 degrees, although any non-zero angle 330 is possible and within the scope of embodiments of the present invention. The top substrate bottom metallization (item 122 in Figures 1A, 1C, and 1D) and the bottom substrate top metallization (item 135 in Figures 1A, 1D, and 1F-1H) together form ground planes 122-135 configured to provide insulation to allow the first signal line 310 to cross one or more of the top substrate 112 and the bottom substrate 126 without being obstructed by the second signal line 320.

[0137] The first top substrate top signal line 116D is located on the first signal line first horizontal plane 340. (It is also easy to decide to describe the RF intersection 300, including the first signal line 310, from right to left, in which case the description of the RF intersection 300 would begin with the second top substrate bottom signal line 122D and proceed right to left to the second bottom substrate bottom signal via 140B, then the bottom substrate bottom signal line 137, and then the first top substrate top signal line 116D.) The first signal line first horizontal plane 340 includes one or more of the top substrate top surface 114, the bottom substrate bottom surface 128, and the ground planes 122-135. As shown, the first signal line first horizontal plane 340 includes the top substrate top surface 114.

[0138] The first signal line 310 passes successively through the third top substrate signal via 124C, the circular top substrate bottom metallization via pad 122C, the first bottom substrate signal via 140A, and then the bottom substrate bottom signal line 137 located on the bottom substrate bottom surface 128. The second horizontal plane 350 of the first signal line includes one or more of the top substrate top surface 114, the bottom substrate bottom surface 128, and the ground planes 122-135. As shown, the second horizontal plane 350 of the first signal line includes the bottom substrate bottom surface 128.

[0139] At least one of the first signal conductor 310 and the second signal conductor 320 travels from the first signal conductor first horizontal plane 340 to the first signal conductor second horizontal plane 350 with the protection of the ground planes 122-135, thereby providing isolation from one or more of the second signal conductor 320 and the first signal conductor 310, respectively. As shown, with the protection of the ground planes 122-135, the first signal conductor 310 travels from the first signal conductor first horizontal plane 340 to the first signal conductor second horizontal plane 350 with the protection of the ground planes 122-135, thereby providing isolation from the second signal conductor 320. For example, the first signal conductor 310 travels from the first signal conductor first horizontal plane 340 to the first signal conductor second horizontal plane 350 through one or more of an escape transition, a crossover transition, and a feedthrough transition. For example, the feedthrough transition includes a vertical feedthrough transition.

[0140] Optionally, as shown, the second top substrate bottom signal line 122D is located on the first signal line's third horizontal plane 360. The first signal line's third horizontal plane 360 ​​includes one or more of the top substrate top surface 114, the bottom substrate bottom surface 128, and the ground planes 122-135. As shown, the first signal line's third horizontal plane 360 ​​includes the ground planes 122-135.

[0141] At least one of the first signal conductor 310 and the second signal conductor 320 travels from the first signal conductor second horizontal plane 350 to the first signal conductor third horizontal plane 360 ​​with the protection of the ground planes 122-135, thereby providing isolation from one or more of the second signal conductor 320 and the first signal conductor 310, respectively. As shown, with the protection of the ground planes 122-135, the first signal conductor 310 travels from the first signal conductor second horizontal plane 350 to the first signal conductor third horizontal plane 360 ​​with the protection of the ground planes 122-135, thereby providing isolation from the second signal conductor 320. For example, the first signal conductor 310 travels from the first signal conductor second horizontal plane 350 to the first signal conductor third horizontal plane 360 ​​through one or more of an escape transition, a crossover transition, and a feedthrough transition. For example, the feedthrough transition includes a vertical feedthrough transition.

[0142] 3B shows a direct side view of the microelectronic H-frame device 100 including the radio frequency (RF) crossover 300. Also shown are the top cover 102, the bottom cover 106, the bottom cover cavity 108, the substrate 110, the top substrate 112, the first bonding interface 114, the first input / output port 116B, the second input / output port 116C, the first top substrate top signal line 116D, the top substrate bottom surface 120, the first top substrate bottom signal line 122B, the circular top substrate bottom metallization via pad 122C, the second top substrate bottom signal line 122D, the second top substrate signal via 124B, the third top substrate signal via 124C, the fourth top substrate signal via 124D, the first top substrate ground via 125A, and the second top substrate signal via 126B. Shown are substrate ground via 125F, third top substrate ground via 125K, fourth top substrate ground via 125M, bottom substrate 126, second bonding interface 128, third bonding interface 134, bottom substrate bottom signal line 137, first bottom substrate signal via 140A, second bottom substrate signal via 140B, first port first ground metal pad 154A, first port signal metal pad 154B, first port second ground metal pad 154C, second port first ground metal pad 156A, second port signal metal pad 156B, and second port second ground metal pad 156C. In FIG. 3B, the bottom substrate cavity (item 108 in FIG. 3A) and the angle between the first signal line 310 and the second signal line 320 (item 330 in FIG. 3A) are not visible.

[0143] Similarly, the sub-circuit 220 includes a first top substrate upper signal line 116D extending on the top substrate upper surface 114. Similarly, the second microstrip 220 further includes a top substrate bottom surface 120 disposed between the top substrate 112 and the bottom substrate 126.

[0144] Similarly, the second sub-circuit 220 includes a portion of the first top substrate signal line 116D, a third top substrate signal via 124C, a circular top substrate bottom metallization via pad 122C, a first bottom substrate signal via 140A, and a portion of the bottom substrate bottom signal line 137. Similarly, the first top substrate signal line 116D is electrically connected to the third top substrate signal via 124C. Similarly, the third top substrate signal via 124C is electrically connected to the circular top substrate bottom metallization via pad 122C.

[0145] Similarly, the first signal line 310 is, from left to right, First port signal metal pad 154B, Top through-substrate signal vias 124A, first top substrate bottom signal line 122B, second top substrate signal via 124B, first top substrate top signal line 116D, third top substrate signal via 124C, circular top substrate bottom metallization via pad 122C, first bottom substrate signal via 140A, bottom substrate bottom signal line 137, second bottom substrate bottom signal via 140B, second top substrate bottom signal line 122D, fourth top substrate signal via 124D, and finally second port signal metal pad 156B.

[0146] Similarly, RF intersection 300 includes a first signal line 310. Similarly, RF intersection 300 further includes a second signal line 320. Similarly, top substrate bottom metallization (item 122 in FIGS. 1A, 1C, and 1D) and bottom substrate top metallization (item 135 in FIGS. 1A, 1D, and 1F-1H) together form ground planes 122-135 configured to provide isolation to allow first signal line 310 to cross one or more of top substrate 112 and bottom substrate 126 without being obstructed by second signal line 320.

[0147] Similarly, the first signal line 310 includes, in relevant portions for the description of this figure, a first top substrate top signal line 116D extending along the top substrate top surface 114, a third top substrate signal via 124C, a circular top substrate bottom metallization via pad 122C, a first bottom substrate signal via 140A, a bottom substrate bottom signal line 137, a second bottom substrate bottom signal via 140B, and finally a second top substrate bottom signal line 122D.

[0148] Similarly, the first top substrate top signal line 116D is located on the first signal line first horizontal surface 340. Similarly, the first signal line first horizontal surface 340 includes the top substrate top surface 114.

[0149] Similarly, the first signal line 310 passes successively through the third top substrate signal via 124C, the circular top substrate bottom metallization via pad 122C, the first bottom substrate signal via 140A, and then the bottom substrate bottom signal line 137 located on the bottom substrate bottom surface 128. The second horizontal plane 350 of the first signal line includes one or more of the top substrate top surface 114, the bottom substrate bottom surface 128, and the ground planes 122-135. As shown, the second horizontal plane 350 of the first signal line includes the bottom substrate bottom surface 128.

[0150] Similarly, with the protection of the ground planes 122-135, the first signal conductor 310 travels from the first signal conductor first horizontal plane 340 to the first signal conductor second horizontal plane 350 with the protection of the ground planes 122-135, thereby providing isolation from the second signal conductor 320.

[0151] Optionally, as shown, the second top-substrate bottom signal line 122D also lies on the first signal line's third horizontal plane 360. The first signal line's third horizontal plane 360 ​​also includes the ground planes 122-135.

[0152] Similarly, with the protection of the ground planes 122-135, the first signal conductor 310 travels from the first signal conductor second horizontal plane 350 to the first signal conductor third horizontal plane 360 ​​with the protection of the ground planes 122-135, thereby providing isolation from the second signal conductor 320.

[0153] For signal vias, 50-micron diameter metallized through-wafer vias are used to connect ground metallization on opposing surfaces of the substrate to form a highly insulating electromagnetic via fence. Simulations show that these vias can be used to provide high isolation of up to 40 decibels (dB) at 20 GHz when spaced at a minimum pitch of 400 microns (μm). The via fences and gold-plated silicon enclosure walls allow individual elements of the two isolated circuits to be effectively enclosed in their own electromagnetically shielded cavities, minimizing cross-coupling. The through-wafer vias facilitate substantially continuous ground continuity for RF return currents between the top and bottom covers, enabling probe testing of the filter after fabrication. A further advantage of embodiments of the present invention is that the "walls" formed by the gold-plated silicon enclosure walls and via fences can be used not only to isolate channels, but also to isolate individual elements. According to embodiments of the present invention, electrical isolation between individual elements eliminates the undesirable cross-coupling found in prior art open-face printed designs, thus enabling rapid development and compact layouts.

[0154] Another advantage provided by embodiments of the present invention is that additional compaction is provided by replacing the metal central web in a conventional H-frame with a conceptual three-layer printed circuit board (PCB). Higher compaction is provided by embodiments of the present invention due to one or more of condensed routing and higher component counts.

[0155] Yet a further advantage of embodiments of the present invention is that they eliminate prior art feedthrough transitions, which require many intricate components and complex assembly procedures, while introducing the risk of large manufacturing variations and / or electric field leakage. In sharp contrast, embodiments of the present invention enable the fabrication of both chips in a single manufacturing process.

[0156] Still further advantages of embodiments of the present invention include that they allow the design of RF transitions with intricate features at no additional cost for optimum performance in terms of return loss and insertion loss, particularly where near perfect isolation from other areas under the same cover is provided.

[0157] A further advantage provided by embodiments of the present invention is that transitions at multiple locations may be formed simultaneously within a substrate.

[0158] The disclosed microelectronic H-frame device has several distinct advantages. It provides a rigid substrate with a much better defined geometry than the softer prior art printed circuit board layers and prior art low temperature co-fired ceramic (LTCC) layers that are prone to shrinkage. A better defined geometry implies better controlled RF characteristics, such as line impedance and loss, and therefore more predictable RF performance.

[0159] Yet a further advantage of embodiments of the present invention is that the size of the feedthrough transition, including end walls and cutouts in the ground plane, is approximately 30 mils for a stack of two 8 mil thick substrates, compared to approximately 102 mils, which is a typical dimension for a conventional machined H-frame housing of the prior art. A further advantage of embodiments of the present invention is that they provide a savings of over 10 times in the transition area. Yet another advantage provided by embodiments of the present invention is that they provide a feedthrough transition without the need to create additional components or add additional manufacturing steps required to create them. The primary difference between embodiments of the present invention and conventional prior art machined H-frame devices is that embodiments of the present invention provide a compact, cost-effective vertical feedthrough.

[0160] An additional advantage of embodiments of the present invention is that they provide three-dimensional field channelization and isolation. Embodiments of the present invention allow circuit elements to be placed closely together but with walls between them, which eliminates potential coupling and therefore results in a more compact layout. Thus, another advantage of embodiments of the present invention is compaction of the circuit layout.

[0161] Embodiments of the present invention provide high precision in patterning metallization, with typical linewidth errors of approximately 1 micron compared to prior art techniques which typically have typical linewidth errors at least 10 times higher.

[0162] The disclosed new methods and new electronic devices for building electronics modules facilitate an order of magnitude reduction in size, weight, and power (SWAP). The disclosed new methods and new devices also provide the RF integrity inherent in high quality RF products.

[0163] A dramatically different electronic device system is described that possesses deep compaction, microelectronic precision, and unprecedented RF routing flexibility and manufacturing repeatability.

[0164] Another advantage of embodiments of the present invention is the versatility of transmission line styles that are available. The disclosed microelectronic H-frame devices allow RF transmission lines to be constructed using one or more of microstrip, coplanar waveguide (CPW), and stripline. This flexibility allows designers to select the appropriate line type in different regions for optimal RF performance.

[0165] In embodiments of H-frame devices that include three or more substrates, H-frame functionality is maintained, and one or more of routing flexibility, routing density, and the ability to incorporate three-dimensional components increases rapidly as the number of substrates used by the device increases.

[0166] Yet a further advantage of embodiments of the present invention is that bonding two wafers in a stack essentially collapses the central web, which in conventional machined H-frames has a typical thickness in the range of 40-160 mils, into a thin metal layer that can be only a few microns thick. The change from a finite thickness to a "zero" thickness central web eliminates the need for conventional feedthroughs. More importantly, collapsing the central web changes the design paradigm to the use of planar technologies, where intricate features realized in patterned metallization for optimal RF performance are now possible at no additional cost.

[0167] Another advantage provided by embodiments of the present invention is the versatility of vertical walls. The cover not only completely seals the package for foreign object debris (FOD) protection, but also provides vertical walls when needed. For example, vertical walls provide RF path channelization, cavity demodulation for stability, and good isolation in vertical transition designs.

[0168] Vertical feedthroughs in microelectronic H-frames (Figure 2, bottom) include one or more of patterned metallization on the substrate, through-substrate vias, and vertical metal walls provided by a micromachined cover. The transition is designed with intricate features at no additional cost for optimal performance for return loss and insertion loss, especially near-perfect isolation from other areas under the same cover.

[0169] A further advantage of embodiments of the present invention is that the distance between the escape line and the spiral turn is increased from approximately 3 microns for a typical prior art air bridge to approximately 200 microns of wafer thickness. The increased spacing reduces capacitive coupling, thereby helping to reduce performance sensitivity to manufacturing variations. While the above exemplary embodiments have been described using some components in exemplary configurations, those skilled in the art will understand that other exemplary embodiments may be implemented using different configurations and / or different components. For example, those skilled in the art will understand that the order of some steps and some components may be changed without substantially impairing the functionality of the present invention. Those skilled in the art will further understand that the number of variations on embodiments of the present invention is nearly limitless. For example, a first RF trace may extend at any non-zero angle relative to a second RF trace. For example, the designation of the first and second signals at an RF intersection is arbitrary and may be reversed without substantially affecting embodiments of the present invention. For example, it may be a second signal trace that traverses one or more of the top and bottom substrates without being obstructed by a first signal trace that traverses one or more of the top and bottom substrates at a non-zero angle relative to the second signal trace, and at least one of the first and second signal traces travels to a second horizontal plane with the protection of a ground plane, thereby providing isolation from the other signal trace.

[0170] For example, a stack containing three or more wafers may be used. For example, if three wafers are used, there will be four metal layers and four different RF transitions. For example, the respective designations of "top" and "bottom" are arbitrary. Such designations may be reversed or otherwise modified without substantially altering the invention. For example, instead of being plated on the substrate, the bond bumps may be plated on one or more of the top cover and bottom cover.

[0171] The representative embodiments and disclosed subject matter described in detail herein have been presented by way of example and illustration, not limitation. Those skilled in the art will understand that various changes in form and detail of the described embodiments may be made, resulting in equivalent embodiments that remain within the scope of the invention. Accordingly, it is intended that the subject matter in the above description be interpreted as illustrative and not in a limiting sense.

Claims

1. 1. A stack including two or more substrates, the stack including a top substrate and a bottom substrate, at least one of the top substrate and the bottom substrate including at least one of a transmission line, a circuit board, a filter, a power splitter, a coupler, and another electronic component, bonding the top substrate to the bottom substrate creates an electrical connection between the top substrate and the bottom substrate, a bottom surface of the top substrate including a top substrate bottom metallization, a top surface of the bottom substrate including a bottom substrate top metallization, and a top substrate bottom metallization and a bottom substrate top metallization. a stack including two or more substrates, wherein a rise includes a ground plane configured to provide isolation to allow a first signal line to cross one or more of the top and bottom substrates without being obstructed by a second signal line, the second signal line crossing one or more of the top and bottom substrates at a non-zero angle relative to the first signal line, and at least one of the first and second signal lines transitioning to a second horizontal plane while protected by the ground plane, thereby providing isolation from the other signal line; a top cover including vertical walls and a top cover metallization; and A bottom cover including vertical walls and bottom cover metallization A microelectronic high isolation H-frame device including a radio frequency (RF) crossover, comprising:

2. 2. The microelectronic high isolation H-frame device of claim 1, wherein the at least one of the first signal line and the second signal line transitions from the second horizontal plane to a third horizontal plane while protected by the ground plane, whereby the ground plane provides isolation from the other signal line.

3. 10. The microelectronic high isolation H-frame device of claim 1, wherein a first horizontal surface comprises one of a top surface of said top substrate, a bottom surface of said bottom substrate, and said ground plane.

4. 2. The microelectronic high isolation H-frame device of claim 1, wherein said second horizontal surface comprises one of a top surface of said top substrate, a bottom surface of said bottom substrate, and said ground plane.

5. 3. The microelectronic high isolation H-frame device of claim 2, wherein said third horizontal surface comprises one of a top surface of said top substrate, a bottom surface of said bottom substrate, and said ground plane.

6. The microelectronic high-isolation H-frame device of claim 1 further comprising a grounding structure configured to ground the microelectronic high-isolation H-frame device.

7. 7. The microelectronic high-isolation H-frame device of claim 6, wherein the grounding structure comprises a substrate grounding structure, the substrate grounding structure comprising a top substrate top metallization, a bottom substrate bottom metallization, the top substrate bottom metallization, the bottom substrate top metallization, and through-substrate vias providing electrical connection from the top substrate top metallization to the bottom substrate bottom metallization.

8. 10. The microelectronic high isolation H-frame device of claim 1, wherein said first signal line transitions to said second horizontal plane through a feedthrough transition.

9. The microelectronic high isolation H-frame device of claim 8 , wherein said feedthrough transition comprises a vertical feedthrough transition.

10. 3. The microelectronic high isolation H-frame device of claim 2, wherein said first signal line transitions to said third horizontal plane through a vertical feedthrough transition.

11. the bottom substrate further comprising a plurality of bottom substrate signal vias; 8. The microelectronic high isolation H-frame device of claim 7, wherein the bottom substrate signal via is configured to provide high isolation while conducting an electronic signal from the first signal line included in the bottom substrate top metallization to the first signal line included in the bottom substrate bottom metallization.

12. the top substrate further comprises a plurality of top substrate signal vias; 8. The microelectronic high isolation H-frame device of claim 7, wherein the top substrate signal via is configured to provide high isolation while conducting an electronic signal from the first signal line included in the top substrate bottom metallization to the first signal line included in the top substrate top metallization.

13. a stack including two or more substrates, the stack including a top substrate and a bottom substrate, at least one of the top substrate and the bottom substrate including at least one of a transmission line, a circuit board, a filter, a power splitter, a coupler, and another electronic component, bonding of the top substrate to the bottom substrate creates an electrical connection between the top substrate and the bottom substrate, a bottom surface of the top substrate including a top substrate bottom metallization and a top surface of the bottom substrate including a bottom substrate top metallization, the top substrate bottom metallization and the bottom substrate top metallization including a ground plane, the ground plane configured to provide isolation to allow a first signal line to cross one or more of the top substrate and the bottom substrate without being obstructed by a second signal line, the second signal line crossing one or more of the top substrate and the bottom substrate at a non-zero angle relative to the first signal line; a top cover including vertical walls and a top cover metallization; and A bottom cover including vertical walls and bottom cover metallization 1. A microelectronic high isolation H-frame device including a radio frequency (RF) crossover, comprising: at least one of the first signal line and the second signal line transitions to a second horizontal plane while protected by the ground plane, whereby the ground plane provides isolation from the other signal line; the at least one of the first signal line and the second signal line travels from the second horizontal plane to a third horizontal plane while protected by the ground plane, thereby providing isolation from the other signal line; 1. A microelectronic high-isolation H-frame device, further comprising a grounding structure configured to ground the microelectronic high-isolation H-frame device, the grounding structure comprising a substrate grounding structure, the substrate grounding structure comprising a top substrate top metallization, a bottom substrate bottom metallization, the top substrate bottom metallization, the bottom substrate top metallization, and a through-substrate via providing an electrical connection from the top substrate top metallization to the bottom substrate bottom metallization.

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