Silicon carbide semiconductor device

Abstract

To provide a semiconductor device whose channel width density per unit area can be improved and on resistance can be reduced.SOLUTION: A semiconductor device includes a semiconductor substrate with a first conductivity type, a first semiconductor layer with the first conductivity type, a second semiconductor layer 3 with a second conductivity type, a first semiconductor region 7 with the first conductivity type, a second semiconductor region 8 with the second conductivity type, a gate insulating film, a gate electrode 10, an interlayer insulating film, a first electrode, a second electrode, and a trench. The first semiconductor region 7 and the second semiconductor region 8 are disposed periodically apart from each other in a first direction (y direction) where the trench extends in a stripe shape.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Silicon carbide (SiC) is expected to be a next-generation semiconductor material that will replace silicon (Si). Compared to conventional semiconductor devices that use silicon carbide as the semiconductor material, semiconductor devices that use silicon carbide as the semiconductor material (hereinafter referred to as silicon carbide semiconductor devices) have various advantages, such as the ability to reduce the resistance of the device in the on-state to one-hundredth of that of conventional semiconductor devices that use silicon as the semiconductor material, and the ability to be used in higher temperature environments (over 200°C). This is due to the characteristics of the material itself, namely, that the band gap of silicon is about three times larger than that of silicon, and that the dielectric breakdown field strength is nearly one order of magnitude greater than that of silicon.

[0003] To date, commercially available silicon carbide semiconductor devices include Schottky barrier diodes (SBDs) and vertical MOSFETs (metal oxide semiconductor field effect transistors) with planar gate structures or trench gate structures.

[0004] The trench gate structure is a MOS gate structure in which a MOS gate is embedded in a trench formed on the front surface of a semiconductor substrate (semiconductor chip), and a channel (inversion layer) is formed along the sidewall of the trench in a direction perpendicular to the front surface of the semiconductor substrate. This allows for a higher unit cell (element constituent unit) density per unit area compared to a planar gate structure in which the channel is formed along the front surface of the semiconductor substrate, thereby increasing the current density per unit area, and is therefore advantageous in terms of cost. The planar gate structure is a MOS gate structure in which a MOS gate is provided as a flat plate on the front surface of the semiconductor substrate.

[0005] The structure of a conventional silicon carbide semiconductor device will be described by taking a trench MOSFET as an example (see, for example, Patent Documents 1 and 2 listed below). FIG. 17 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 17, a trench MOSFET 150 has an n + An n-type silicon carbide epitaxial layer 102 is deposited on the front surface of the n-type silicon carbide substrate 101. + On the surface side opposite to the silicon carbide substrate 101 side, an n-type high concentration region 106 is provided. + The surface layer on the side opposite to the silicon carbide substrate 101 side is provided with a first p + The n-type base region 104 is selectively provided in the n-type high concentration region 106. A second p + A mold base region 105 is optionally provided.

[0006] The trench MOSFET 150 further includes a p-type silicon carbide epitaxial layer 103, an n-type silicon carbide epitaxial layer 104, and a + Type source region 107, p ++ The semiconductor device is provided with a contact region 108, a gate insulating film 109, a gate electrode 110, an interlayer insulating film 111, a source electrode 113, a backside electrode 114, a trench 118, a source electrode pad (not shown), and a drain electrode pad (not shown). + Type source region 107, p ++ A source electrode pad is provided on the mold contact region 108 and on the source electrode 113 . [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2018-019045 [Patent Document 2] Japanese Patent Application Publication No. 2018-019046 Summary of the Invention [Problem to be solved by the invention]

[0008] 18 is a plan view taken along the line AA' of FIG. 17, showing the structure of a conventional silicon carbide semiconductor device. As shown in FIG. 18, trenches 118 are provided in a stripe pattern, and n + Type source region 107, p ++ type contact region 108, n + The source regions 107 are provided in this order in a stripe pattern.

[0009] p ++ The p-type contact region 108 is necessary to keep the p-type silicon carbide epitaxial layer 103 at the same potential as the source electrode 113. In a conventional silicon carbide semiconductor device, the striped n + p type source region 107 ++ The p-type contact region 108 maintained the p-type silicon carbide epitaxial layer 103 and the source electrode 113 at the same potential.

[0010] However, between the trenches 118 + Type source region 107, p ++ type contact region 108, n + In the structure in which the type source region 107 is provided, there is a limit to how narrow the cell pitch can be, and there is also a limit to how much the channel width density can be improved.

[0011] SUMMARY OF THE INVENTION In order to solve the above-mentioned problems associated with the prior art, an object of the present invention is to provide a silicon carbide semiconductor device that enables a narrower cell pitch (distance between trenches). [Means for solving the problem]

[0012] In order to solve the above-mentioned problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features: The silicon carbide semiconductor device includes: a trench provided in a first main surface of a semiconductor substrate including a first conductivity type semiconductor substrate, the trench having a plurality of longitudinal portions extending in a first direction; a first semiconductor region of the first conductivity type selectively provided in the first main surface of the semiconductor substrate so as to contact sidewalls of at least some of the plurality of longitudinal portions; a bottom region of a second conductivity type selectively provided in the first main surface of the semiconductor substrate so as to contact bottoms of at least some of the plurality of longitudinal portions; and a second semiconductor region of the second conductivity type selectively provided in the first main surface of the semiconductor substrate, extending from the first main surface along sidewalls of the longitudinal portions to the bottom region. The second semiconductor region has a semiconductor layer of a second conductivity type, a high-concentration semiconductor region of the second conductivity type that has a higher impurity concentration than the semiconductor layer and is selectively provided on the first main surface of the semiconductor substrate, and a connection region of the second conductivity type that connects the semiconductor layer and the bottom region, the first semiconductor region and the high-concentration semiconductor region are periodically arranged apart from each other in the first direction, and in a planar view, the distance between adjacent high-concentration semiconductor regions in the first direction is 2.514 μm or more.

[0013] In order to solve the above-mentioned problems and achieve the object of the present invention, another silicon carbide semiconductor device according to the present invention has the following features: The other silicon carbide semiconductor device includes a trench provided on a first main surface of a semiconductor base including a semiconductor substrate of a first conductivity type, the trench having a plurality of longitudinal portions extending in a first direction, and a trench provided between adjacent ones of the longitudinal portions. the semiconductor substrate includes a plurality of mesa regions and a bottom region of a second conductivity type provided in contact with the bottoms of at least some of the longitudinal portions, the mesa region having a semiconductor layer of the second conductivity type, a first semiconductor region of the first conductivity type selectively provided on the first main surface of the semiconductor substrate and provided in contact with the side walls of at least some of the longitudinal portions, and a high-concentration semiconductor region of the second conductivity type having a higher impurity concentration than the semiconductor layer, selectively provided on the first main surface of the semiconductor substrate, and second-conductivity type connection regions connecting the semiconductor layer and the bottom region are provided periodically in the first direction, the first semiconductor regions and the high-concentration semiconductor regions are periodically arranged apart from each other in the first direction, and the distance between adjacent high-concentration semiconductor regions in the first direction in a planar view is 2.514 μm or more.

[0014] In order to solve the above-mentioned problems and achieve the object of the present invention, another silicon carbide semiconductor device according to the present invention has the following features: The other silicon carbide semiconductor device comprises: a trench provided in a first main surface of a semiconductor base including a semiconductor substrate of a first conductivity type, the trench having a plurality of longitudinal portions extending in a first direction, a plurality of first mesa regions provided between adjacent ones of the longitudinal portions, a plurality of second mesa regions provided between adjacent ones of the longitudinal portions, and a gate electrode embedded in one or more of the longitudinal portions with a gate insulating film interposed therebetween, the first mesa region being selectively provided on the first main surface of the semiconductor base, the first semiconductor region of the first conductivity type provided so as to be in contact with the gate insulating film, and a semiconductor layer of a second conductivity type below the first semiconductor region and in contact with the gate insulating film; a second conductivity type high concentration semiconductor region selectively provided on the first main surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor layer; The second mesa region has a second semiconductor region of a second conductivity type provided from the bottom of one of the adjacent long portions to the bottom of the other of the long portions. The first semiconductor regions and the high-concentration semiconductor regions are periodically arranged apart from each other in the first direction, and the interval between adjacent high-concentration semiconductor regions in the first direction is 2.514 μm or more in plan view. [Effects of the Invention]

[0015] The silicon carbide semiconductor device according to the present invention has the effect of enabling the cell pitch (distance between trenches) to be narrowed. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a plan view showing a structure of a silicon carbide semiconductor device according to a first embodiment. [Figure 2] 2 is a cross-sectional view taken along line AA' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. [Figure 3] 2 is a cross-sectional view taken along line BB' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. [Figure 4] 2 is a cross-sectional view taken along CC' in FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 5] FIG. 4 is a plan view showing another structure of the silicon carbide semiconductor device in accordance with the first embodiment. [Figure 6] 3 is a graph showing channel width density of the silicon carbide semiconductor device according to the first embodiment. [Figure 7] 1 is a cross-sectional view (part 1) showing a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. [Figure 8] 10 is a cross-sectional view (part 2) illustrating a state during manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 9] 10 is a cross-sectional view (part 3) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 10] 10 is a cross-sectional view (part 4) illustrating a state during the manufacture of the silicon carbide semiconductor device according to the first embodiment. FIG. [Figure 11] 5 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 5). FIG. [Figure 12] FIG. 6 is a cross-sectional view showing a state during manufacture of the silicon carbide semiconductor device according to the first embodiment (part 6). [Figure 13] FIG. 10 is a plan view showing a structure of a silicon carbide semiconductor device according to a second embodiment. [Figure 14] 13 is a cross-sectional view taken along line AA' of FIG. 12 showing the structure of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 15] 13 is a cross-sectional view taken along line BB' of FIG. 12 showing the structure of a silicon carbide semiconductor device according to a second embodiment. FIG. [Figure 16] 10 is a graph showing channel width density of the silicon carbide semiconductor device according to the second embodiment. [Figure 17] FIG. 1 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 18] FIG. 18 is a plan view taken along the line AA' of FIG. 17 showing the structure of a conventional silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0017] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. The same symbols for n or p, including + and -, indicate similar concentrations, but do not necessarily mean that the concentrations are the same. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. In this specification, in the Miller index notation, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0018] (Embodiment 1) The semiconductor device according to the first embodiment is configured using a semiconductor (referred to as a wide bandgap semiconductor) having a bandgap wider than that of silicon (Si). The structure of the semiconductor device according to the first embodiment will be described taking as an example a case where silicon carbide (SiC) is used as the wide bandgap semiconductor. FIG. 1 is a plan view showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 3 is a cross-sectional view taken along line B-B' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment. FIG. 4 is a cross-sectional view taken along line C-C' of FIG. 1 showing the structure of the silicon carbide semiconductor device according to the first embodiment.

[0019] 2 to 4, the trench MOSFET 50 has a MOS gate with a trench gate structure on the front surface of the semiconductor substrate (the surface on the side of the p-type silicon carbide epitaxial layer 3 described later). + The semiconductor device is formed by epitaxially growing an n-type silicon carbide epitaxial layer (first semiconductor layer of first conductivity type) 2 and a p-type silicon carbide epitaxial layer (second semiconductor layer of second conductivity type) 3 in this order on a silicon carbide substrate (semiconductor substrate of first conductivity type) 1. An n-type heavily doped region 6 may also be epitaxially grown on the n-type silicon carbide epitaxial layer 2.

[0020] The MOS gate of the trench gate structure is formed by a p-type silicon carbide epitaxial layer 3, an n + p-type source region (first semiconductor region of first conductivity type) 7, ++ The semiconductor device is composed of a contact region (second semiconductor region of a second conductivity type) 8, a trench 18, a gate insulating film 9 and a gate electrode 10.

[0021] Specifically, trenches 18 penetrate p-type silicon carbide epitaxial layer 3 from the front surface of the semiconductor substrate in depth direction z to reach n-type heavily doped region 6 (if n-type heavily doped region 6 is not provided, n-type silicon carbide epitaxial layer 2, hereinafter referred to as (2)). Depth direction z is the direction from the front surface to the back surface of the semiconductor substrate. Trenches 18 are arranged in a stripe pattern.

[0022] Inside the trench 18, a gate insulating film 9 is provided along the inner wall of the trench 18, and a gate electrode 10 is provided on the gate insulating film 9 so as to be embedded inside the trench 18. One unit cell of the main semiconductor element is composed of the gate electrode 10 in one trench 18 and adjacent mesa regions (regions between adjacent trenches 18) sandwiching the gate electrode 10. Although only one trench MOS structure is shown in Figures 2 and 3, more trench-structured MOS gate (insulated gate made of metal-oxide film-semiconductor) structures may be arranged in parallel.

[0023] An n-type region (hereinafter referred to as a high-concentration n-type region) 6 may be provided in the surface layer on the source side (the side of the source electrode 13 described later) of the n-type silicon carbide epitaxial layer 2 so as to be in contact with the p-type silicon carbide epitaxial layer 3. The high-concentration n-type region 6 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. This high-concentration n-type region 6 is provided uniformly in a direction parallel to the front surface of the substrate (the front surface of the semiconductor substrate) so as to cover, for example, the inner wall of the trench 18.

[0024] The n-type high concentration region 6 extends from the interface with the p-type silicon carbide epitaxial layer 3 to a position deeper on the drain side (the side of the back electrode 14 described later) than the bottom surface of the trench 18. + The mold base regions 4 and 5 may be selectively provided. + The base region 4 has a second p-type region between adjacent trenches 18 (mesa region). + The second p-type silicon carbide epitaxial layer 3 is provided in contact with the p-type base region 5 and the trench 18. + The mold base region 5 covers at least the bottom surface of the trench 18. The bottom corners of the trench 18 are the boundaries between the bottom surface and the sidewalls of the trench 18.

[0025] 1st, 2p +The pn junction between the n-type base regions 4, 5 and the n-type silicon carbide epitaxial layer 2 is formed at a position deeper on the drain side than the bottom of the trench 18. + The first and second base regions 4 and 5 may be provided inside the n-type silicon carbide epitaxial layer 2. + The depth positions of the drain side ends of the base regions 4 and 5 are 1st and 2nd p + It is sufficient that the pn junction between the n-type base regions 4, 5 and the n-type silicon carbide epitaxial layer 2 is located deeper on the drain side than the bottom of the trench 18, and various changes can be made according to design conditions. + The mold base regions 4 and 5 can prevent a high electric field from being applied to the gate insulating film 9 along the bottom surface of the trench 18.

[0026] The p-type silicon carbide epitaxial layer 3 contains n + A source region 7 is selectively provided. + The p ++ A contact region 8 is optionally provided. + The source region 7 is in contact with the gate insulating film 9 on the sidewall of the trench 18 and faces the gate electrode 10 via the gate insulating film 9 on the sidewall of the trench 18 .

[0027] The interlayer insulating film 11 is provided on the entire front surface of the semiconductor substrate so as to cover the gate electrode 10. The interlayer insulating film 11 has a contact hole that penetrates the interlayer insulating film 11 in the depth direction z and reaches the front surface of the substrate.

[0028] The source electrode (first electrode) 13 is formed on the semiconductor substrate (n + The source electrode 13 is in ohmic contact with the source region 7 and is electrically insulated from the gate electrode 10 by an interlayer insulating film 11. A source electrode pad (not shown) is provided on the source electrode 13. ++ When the contact region 8 is provided, the source electrode 13 is ++ The metal layer 10 makes ohmic contact with the metal contact region 8 .

[0029] A back surface electrode (second electrode) 14 that serves as a drain electrode is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the back surface electrode 14.

[0030] In the first embodiment, as shown in FIG. 1, the trenches 18 extend in a stripe shape in the y direction (first direction), and + A plurality of n-type silicon carbide substrates are arranged in the x-direction (second direction) perpendicular to the y-direction within the front surface of the silicon carbide substrate 1. + Type source region 7 and p ++ The mold contact regions 8 are provided between the trenches 18 so as to be in contact with the trenches 18 in the x direction, and are periodically arranged spaced apart from one another in the y direction.

[0031] n + Type source region 7 and p ++ By arranging the contact region 8 in this way, + Type source region 7 and ++ This allows the width of the contact region 8 to be narrowed, thereby enabling the cell pitch (the distance between trenches 18) to be narrowed. As a result, the silicon carbide semiconductor device according to the first embodiment can improve the channel width density per unit area and reduce the on-resistance.

[0032] Also, n + Type source region 7 and p ++ A space is provided between the p-type contact region 8 and the p-type silicon carbide epitaxial layer 3, and the p-type silicon carbide epitaxial layer 3 is exposed therein. + Since the ion implantation mask is misaligned in the off-axis direction of the silicon carbide substrate 1, the position of the ion implantation mask is easily misaligned. + Type source region 7 and p ++ If the contact region 8 overlaps with the gate electrode 1, point defects occur, resulting in a decrease in gate reliability.

[0033] In the first embodiment, n + Type source region 7 and p ++ By providing a gap between the n-type contact region 8 and the n-type contact region 9, + Type source region 7 or p ++Even if the position of the ion implantation mask is shifted when forming the n-type contact region 8, + Type source region 7 and p ++ Therefore, the n-type contact region 8 can be prevented from overlapping with the n-type contact region 8. + Type source region 7 and p ++ By overlapping with the mold contact region 8, the occurrence of point defects can be prevented, and gate reliability can be improved.

[0034] Also, n + Type source region 7 and p ++ The positions of the ion implantation masks for the type contact region 8 may be shifted by about 0.2 μm. Furthermore, the diffusion of ions during ion implantation may cause the n + Type source region 7 and p ++ The area of ​​the n-type contact region 8 may expand by about 0.3 μm. + Type source region 7 and p ++ The distance between the mold contact region 8 is preferably (0.3+0.2)×2=1.0 μm or more.

[0035] 2 and 4, the n + In the region facing the region where the source region 7 is provided in the depth direction z, the p-type silicon carbide epitaxial layer 3 and the n-type high concentration region 6(2) are arranged. As shown in FIGS. 3 and 4, the p-type silicon carbide epitaxial layer 3 and the n-type high concentration region 6(2) are arranged between the trenches 18. ++ In a region facing the region where the contact region 8 is provided in the depth direction z, a p-type silicon carbide epitaxial layer 3 and a first p-type silicon carbide epitaxial layer 4 are formed. + The base region 4 and the second p + As shown in FIG. 4, the p-type base regions 5 are arranged adjacent to each other between the trenches 18. ++ type contact region 8 and n + In a region opposite to the region where the source region 7 is not provided in the depth direction z, the p-type silicon carbide epitaxial layer 3 and the first p + The base region 4 and the second p + The mold base regions 5 are arranged adjacent to each other.

[0036] 5 is a plan view showing another structure of the silicon carbide semiconductor device according to the first embodiment. ++ The contact region 8 is bordered on both sides by the trench 18. However, as shown in FIG. ++ The mold contact region 8 may be in contact with the trench 18 on only one side, or may not be in contact with the trench 18 on either side.

[0037] Conditions for improving the channel width density of the silicon carbide semiconductor device according to the first embodiment will be described in detail below. First, the channel width density Dch' of the conventional silicon carbide semiconductor device is determined. The width of the gate electrode 110 in the conventional silicon carbide semiconductor device is defined as Lg' (μm), n + The length of the source region 107 in the x direction is Ln' (μm), and ++ The length of the mold contact region 108 in the x direction is defined as Lp' (μm) (see FIG. 18). For example, the respective values ​​are Lg'=0.7 μm, Ln'=0.85 μm, and Lp'=1 μm.

[0038] Here, if the cell pitch Py' in the y direction is a fixed value, for example, 1 μm, then the cell pitch Px' (μm) in the x direction, the cell pitch Py' (μm) in the y direction, the channel width Wch' (μm) in the y direction, and the channel width density Dch' (μm / μm 2 ) becomes: Px'=Lg'+2Ln'+Lp' Py'=1 Wch'=2Py' Dch'=Wch' / (Px'×Py')=2 / (Lg'+2Ln'+Lp')

[0039] Similarly in the first embodiment, the width of the gate electrode 10 is Lg, n + The length of the source region 7 in the x direction is Ln. + The length of the source region 7 in the y direction is Wn, p ++ The length of the contact region 8 in the y direction is Wpc, n + Type source region 7 and p ++ The length of the gap between the contact region 8 and the substrate 1 in the y direction is defined as Wp (see FIG. 1).

[0040] In this case, the cell pitch in the x direction is Px (μm), the cell pitch in the y direction is Py (μm), the channel width in the y direction is Wch (μm), and the channel width density is Dch (μm / μm 2 ) becomes: Px=Lg+Ln Py=2Wp+Wpc+Wn Wch=2Wn (channel is n + (because they are formed on both sides of the source region 7) Dch=Wch / (Px×Py)=2Wn / {(Lg+Ln)×(2Wp+Wpc+Wn)}

[0041] From these, the condition for improving the channel width density in the silicon carbide semiconductor device according to the first embodiment is Dch≧Dch′. Wn≧(2Wp+Wpc)×Px / (Px'-Px)=(2Wp+Wpc)×(Lg+Ln) / (Lg'+2Ln'+Lp'-Lg-Ln) Since the above holds true, the silicon carbide semiconductor device according to the first embodiment can have a higher channel width density than conventional silicon carbide semiconductor devices.

[0042] 6 is a graph showing the channel width density of the silicon carbide semiconductor device according to the first embodiment. In FIG. 6, the horizontal axis represents Wn(n + The vertical axis represents the channel width density Dch in units of μm / μm. 2 In the conventional silicon carbide semiconductor device, the channel width density is shown when Lg'=0.7 μm, Ln'=0.85 μm, and Lp'=1 μm.

[0043] The silicon carbide semiconductor device according to the first embodiment shows a case where Lg=0.7 μm, Ln=1.1 μm, Wp=1 μm, and Wpc=1 μm in Example 1, and a case where Lg=0.7 μm, Ln=0.85 μm, Wp=1 μm, and Wpc=1 μm in Example 2.

[0044] From FIG. 6, it can be seen that in Example 1, when Wn≧3.375 μm or more, the channel width density Dch is higher than that of the conventional silicon carbide semiconductor device, and in Example 2, when Wn≧2.514 μm or more, the channel width density Dch is higher than that of the conventional silicon carbide semiconductor device.

[0045] (Method for Manufacturing Silicon Carbide Semiconductor Device According to First Embodiment) Next, a description will be given of a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. Figures 7 to 12 are cross-sectional views showing states during the manufacturing process of the silicon carbide semiconductor device according to the first embodiment.

[0046] First, n-type silicon carbide + A silicon carbide substrate 1 is prepared. + A first n-type silicon carbide epitaxial layer 2a is epitaxially grown to a thickness of, for example, about 30 μm on the first main surface of the silicon carbide substrate 1 while doping it with n-type impurities, for example, nitrogen atoms (N). The state up to this point is shown in FIG.

[0047] Next, an ion implantation mask having predetermined openings is formed on the surface of the first n-type silicon carbide epitaxial layer 2a by photolithography, for example, using an oxide film. Then, p-type impurities such as aluminum are implanted into the openings in the oxide film to form first p-type impurities having a depth of about 0.5 μm. + A mold base region 4 is formed.

[0048] Also, the adjacent 1st page + The first p is formed so that the distance from the first p to the base region 4 is about 1.5 μm. + The impurity concentration of the base region 4 is set to, for example, 5×10 18 / cm 3 Set it to a certain extent.

[0049] Next, a portion of the ion implantation mask may be removed, and n-type impurities such as nitrogen may be ion-implanted into the opening to form a lower n-type heavily doped region 6a having a depth of, for example, about 0.5 μm in a portion of the surface region of the first n-type silicon carbide epitaxial layer 2a. The impurity concentration of the lower n-type heavily doped region 6a may be set to, for example, 1×1017 / cm 3 The state up to this point is shown in Figure 8.

[0050] Next, a second n-type silicon carbide epitaxial layer 2b doped with n-type impurities such as nitrogen is formed on the surface of the first n-type silicon carbide epitaxial layer 2a to a thickness of about 0.5 μm. The impurity concentration of the second n-type silicon carbide epitaxial layer 2b is 3×10 15 / cm 3 Hereinafter, first n-type silicon carbide epitaxial layer 2a and second n-type silicon carbide epitaxial layer 2b are combined to form n-type silicon carbide epitaxial layer 2.

[0051] Next, n + An ion implantation mask having a predetermined opening is formed by photolithography on the surface of the second n-type silicon carbide epitaxial layer 2b in a region opposite in the depth direction z to the region where the source region 7 is not provided. Then, p-type impurities such as aluminum are implanted into the opening in the oxide film to form a second p-type impurity having a depth of about 0.5 μm. + The mold base region 5 (not shown) is + The second p + The impurity concentration of the base region 5 is set to, for example, 5×10 18 / cm 3 Set it to about this extent.

[0052] Next, a portion of the ion implantation mask may be removed, and n-type impurities such as nitrogen may be ion-implanted into the opening to form an upper n-type heavily doped region 6b having a depth of, for example, about 0.5 μm in a portion of the surface region of the second n-type silicon carbide epitaxial layer 2b. The impurity concentration of the upper n-type heavily doped region 6b may be set to, for example, 1×10 17 / cm 3 The upper n-type heavily doped region 6b and the lower n-type heavily doped region 6a are formed so that at least a portion of them are in contact with each other, forming the n-type heavily doped region 6. However, the n-type heavily doped region 6 may or may not be formed over the entire surface of the substrate. The state up to this point is shown in FIG.

[0053] Next, a p-type silicon carbide epitaxial layer 3 is formed by epitaxial growth on the surface of the n-type silicon carbide epitaxial layer 2 to a thickness of about 1.1 μm. The impurity concentration of the p-type silicon carbide epitaxial layer 3 is 4×10 17 / cm 3 After forming p-type silicon carbide epitaxial layer 3 by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the channel region of p-type silicon carbide epitaxial layer 3.

[0054] Next, an ion implantation mask having predetermined openings is formed by photolithography on the surface of the p-type silicon carbide epitaxial layer 3. N-type impurities such as nitrogen (N) and phosphorus (P) are ion-implanted into the openings to form n-type impurities in a portion of the surface of the p-type silicon carbide epitaxial layer 3. + Next, the n-type source region 7 is formed. + The ion implantation mask used for forming the p-type source region 7 is removed, and a new ion implantation mask having a predetermined opening is formed in the same manner. P-type impurities such as phosphorus are ion-implanted into a portion of the surface of the p-type silicon carbide epitaxial layer 3, forming p ++ A contact region 8 (not shown) is formed. ++ The impurity concentration of the n-type contact region 8 is set to be higher than the impurity concentration of the p-type silicon carbide epitaxial layer 3. + Type source region 7 and p ++ The mold contact region 8 is formed in the shape of the plan view of Fig. 1. The state up to this point is shown in Fig. 10. Fig. 10 shows the A-A' cross section of Fig. 1.

[0055] Next, heat treatment (annealing) is carried out in an inert gas atmosphere at about 1700°C to form the first p + Mold base region 4, second p + Type base region 5, n + Type source region 7 and p ++An activation process is performed on the mold contact region 8. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be performed by performing a heat treatment each time an ion implantation is performed.

[0056] Next, a trench forming mask having a predetermined opening is formed by photolithography on the surface of the p-type silicon carbide epitaxial layer 3, using, for example, an oxide film. Next, trenches 18 are formed by dry etching, penetrating the p-type silicon carbide epitaxial layer 3 and reaching the n-type high concentration region 6(2). The bottom of trench 18 is located at the first p-type region formed in the n-type high concentration region 6(2). + This may extend to the mold base region 4. The trench mask is then removed, as shown in FIG.

[0057] Next, n + A gate insulating film 9 is formed on the surface of the source region 7 and along the bottom and sidewalls of the trench 18. This gate insulating film 9 may be formed by thermal oxidation at a temperature of about 1000°C in an oxygen atmosphere. Alternatively, this gate insulating film 9 may be formed by a deposition method using a chemical reaction such as high temperature oxidation (HTO).

[0058] Next, a polycrystalline silicon film doped with, for example, phosphorus atoms is provided on the gate insulating film 9. This polycrystalline silicon film may be formed so as to fill the trench 18. This polycrystalline silicon film is patterned by photolithography and left inside the trench 18 to form the gate electrode 10.

[0059] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 9 and the gate electrode 10, forming an interlayer insulating film 11. The interlayer insulating film 11 and the gate insulating film 9 are patterned by photolithography. + Type source region 7 and p ++A contact hole is formed that exposes the contact region 8. Then, a heat treatment (reflow) is performed to flatten the interlayer insulating film 11. The state up to this point is shown in FIG. 12. After the contact hole is formed in the interlayer insulating film 11, a barrier metal made of titanium (Ti), titanium nitride (TiN), or a laminate of titanium and titanium nitride may be formed. In this case, the barrier metal may also have an n-type impurity. + Type source region 7 and p ++ A contact hole is provided exposing the mold contact region 8 .

[0060] Next, a conductive film that will become the source electrode 13 is formed in the contact hole provided in the interlayer insulating film 11 and on the interlayer insulating film 11. The conductive film is, for example, a nickel (Ni) film. + A nickel (Ni) film is similarly formed on the second main surface of the silicon carbide substrate 1. Thereafter, a heat treatment is performed at a temperature of, for example, about 970° C. to silicide the nickel film inside the contact hole to form the source electrode 13. At the same time, the nickel film formed on the second main surface is silicided to form the n + This forms a back surface electrode 14 that forms an ohmic junction with the silicon carbide substrate 1. Thereafter, the unreacted nickel film is selectively removed to leave the source electrode 13 only in the contact hole, for example.

[0061] Next, a source electrode pad (not shown) is formed so as to fill the contact hole. A part of the metal layer deposited to form the source electrode pad may be used as a gate pad. + On the back surface of the silicon carbide substrate 1, a metal film such as a nickel (Ni) film or a titanium (Ti) film is formed by sputter deposition or the like in the contact portion of the back surface electrode 14. This metal film may be a laminate of a plurality of Ni films and Ti films. Then, annealing such as rapid thermal annealing (RTA) is performed so that the metal film is silicided to form an ohmic contact. Then, a thick film such as a laminate film in which a Ti film, a Ni film, and a gold (Au) are sequentially laminated is formed by electron beam (EB) deposition or the like to form the back surface electrode 14.

[0062] In the above-described epitaxial growth and ion implantation, n-type impurities (n-type dopants) may be, for example, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb), which impart n-type conductivity to silicon carbide. P-type impurities (p-type dopants) may be, for example, boron (B), aluminum (Al), gallium (Ga), indium (In), or thallium (Tl), which impart p-type conductivity to silicon carbide. In this manner, the trench MOSFET 50 shown in FIGS. 1 to 4 is completed.

[0063] As described above, according to the silicon carbide semiconductor device of the first embodiment, n + Type source region and p ++ The contact regions are provided between the trenches in the x direction so as to contact the trenches, and are periodically arranged spaced apart from each other in the y direction. + Type source area and ++ The width of the die contact region can be narrowed, which allows the cell pitch to be narrowed, improving the channel width density per unit area and reducing the on-resistance.

[0064] Also, n + Type source region and p ++ A space is provided between the p-type contact region and the p-type silicon carbide epitaxial layer, thereby exposing the p-type silicon carbide epitaxial layer. + Type source region and p ++ Therefore, the n-type contact region can be prevented from overlapping with the n-type contact region. + Type source region and p ++ This can prevent point defects from occurring due to overlap with the mold contact region, thereby improving gate reliability.

[0065] (Embodiment 2) Fig. 13 is a plan view showing a structure of a silicon carbide semiconductor device according to embodiment 2. Fig. 14 is a cross-sectional view taken along line A-A' of Fig. 12 showing a structure of a silicon carbide semiconductor device according to embodiment 2. Fig. 15 is a cross-sectional view taken along line B-B' of Fig. 12 showing a structure of a silicon carbide semiconductor device according to embodiment 2.

[0066] The silicon carbide semiconductor device 51 according to the second embodiment differs from the silicon carbide semiconductor device 50 according to the first embodiment in that the entire region sandwiched between the trenches 18 is p ++ The point is that the silicon carbide semiconductor device 51 has a diode cell region 20 provided with a contact region 8. By providing the diode cell region 20, it is not necessary to connect an external diode when the silicon carbide semiconductor device 51 is used in an inverter or the like.

[0067] As shown in FIGS. 14 and 15, in the diode cell region 20, p ++ In a region facing the region where the contact region 8 is provided in the depth direction z, a p-type silicon carbide epitaxial layer 3 and a first p-type silicon carbide epitaxial layer 4 are formed. + The base region 4 and the second p + The second conductive type base regions (third semiconductor regions) 5 are arranged in contact with each other.

[0068] Between the diode cell regions 20, n + Type source region and p ++ A MOS cell region 21 is provided in which one or more MOS stripes having a contact region are arranged. Fig. 13 shows an example in which three MOS stripes are arranged in the MOS cell region 21. In the MOS cell region 21, as in the first embodiment, n + Type source region 7 and p ++ The mold contact regions 8 are provided between the trenches 18 so as to be in contact with the trenches 18 in the x direction, and are periodically arranged spaced apart from one another in the y direction.

[0069] As shown in FIG. 14, the n-type MOS cell region 21 is formed between the trenches 18. +In the region facing the region where the source region 7 is provided in the depth direction z, a p-type silicon carbide epitaxial layer 3 and an n-type high concentration region 6(2) are arranged, as in the first embodiment. Although not shown, the p-type silicon carbide epitaxial layer 3 and the n-type high concentration region 6(2) are arranged between the trenches 18 of the MOS cell region 21. ++ In a region facing the region where the contact region 8 is provided in the depth direction z, a p-type silicon carbide epitaxial layer 3 and a first p-type silicon carbide epitaxial layer 4 are formed. + The base region 4 and the second p + The p-type base regions 5 are arranged in contact with each other. That is, they have the same structure as the diode cell region 20. Although not shown, p-type base regions 5 are arranged between the trenches 18 of the MOS cell region 21. ++ type contact region 8 and n + In a region opposite to the region where the source region 7 is not provided in the depth direction z, the p-type silicon carbide epitaxial layer 3 and the first p + The base region 4 and the second p + The base regions 5 are arranged in contact with each other. That is, they have the same structure as the diode cell region 20.

[0070] Also, the first p + n of type base region 4 + The surface of the silicon carbide substrate 1 is a first p-type silicon carbide layer in the MOS cell region 21. + n of type base region 4 + The p-type region may be shallower than the surface on the silicon carbide substrate 1 side, that is, on the source electrode 13 side. In this case, when the diode cell region 20 operates and avalanche breakdown occurs, the provision of a continuous p-type region makes it easier for current to flow, thereby reducing the potential difference.

[0071] In the second embodiment, as in the first embodiment, p ++ The mold contact region 8 may be in contact with the trench 18 on only one side, or may not be in contact with the trench 18 on either side.

[0072] Hereinafter, a condition for improving the channel width density of the silicon carbide semiconductor device according to the second embodiment will be described in detail. When the number of MOS cell regions 21 arranged between diode cell regions 20 is n, p++ The length of the mold contact region 8 in the x direction is defined as Lp.

[0073] In this case, the cell pitch in the x direction is Px (μm), the cell pitch in the y direction is Py (μm), the channel width in the y direction is Wch (μm), and the channel width density is Dch (μm / μm 2 ) becomes: Px = n × (Lg + Ln) + Lg + Lp Py=2Wp+Wpc+Wn Wch=2nWn Dch=Wch / (Px×Py)=2nWn / [{n(Lg+Ln)+Lg+Lp}×(2Wp+Wpc+Wn)]

[0074] From these, the condition for improving the channel width density in the silicon carbide semiconductor device according to the second embodiment is Dch≧Dch′. Wn≧(2Wp+Wpc)×Px / (nPx'-Px)=(2Wp+Wpc)×{n(Lg+Ln)+Lg+Lp} / {n(Lg'+2Ln'+Lp')-n(Lg+Ln)-Lg-Lp} Since the above holds true, the silicon carbide semiconductor device according to the second embodiment can have a higher channel width density than conventional silicon carbide semiconductor devices.

[0075] 16 is a graph showing channel width density of the silicon carbide semiconductor device according to the second embodiment. In FIG. 16, the horizontal axis represents Wn(n + The vertical axis represents the channel width density Dch in units of μm / μm. 2 In the conventional silicon carbide semiconductor device, the channel width density is shown when Lg'=0.7 μm, Ln'=0.85 μm, and Lp'=1 μm.

[0076] The silicon carbide semiconductor device according to the second embodiment shows a case where Lg=0.7 μm, Ln=1.1 μm, Wp=1 μm, and Wpc=1 μm in Example 1, and Lg=0.7 μm, Ln=0.85 μm, Wp=1 μm, and Wpc=1 μm in Example 2. In Examples 1 and 2, n (n between the trenches included in MOS cell region 21) + Type source region 7 and p ++ 10 shows the cases where the number of MOS stripes having the contact region 8 is 1 to 4.

[0077] 16 shows that in Example 1, when n≧2 or more, the channel width density Dch can be made higher than that of the conventional silicon carbide semiconductor device. Specifically, when n=2, Wn≧11.572 μm or more, when n=3, Wn≧7.2 μm or more, and when n=4, Wn≧5.87 μm or more, the channel width density Dch is higher than that of the conventional silicon carbide semiconductor device. Furthermore, in Example 2, when n≧1 or more, the channel width density Dch can be made higher than that of the conventional silicon carbide semiconductor device. Specifically, when n=1, Wn≧31 μm or more, when n=2, Wn≧6.489 μm or more, when n=3, Wn≧4.65 μm or more, and when n=4, Wn≧3.975 μm or more, the channel width density Dch is higher than that of the conventional silicon carbide semiconductor device.

[0078] The silicon carbide semiconductor device according to the second embodiment can be manufactured in the same manner as in the first embodiment, and therefore description of the manufacturing method will be omitted.

[0079] As described above, even when the diode cell region is provided, the silicon carbide semiconductor device according to the second embodiment has the same effects as those of the first embodiment. Furthermore, by providing the diode cell region, it is not necessary to connect an external diode when the silicon carbide semiconductor device is used in an inverter or the like.

[0080] The present invention can be modified in various ways without departing from the spirit of the present invention, and in each of the above-described embodiments, for example, the dimensions of each part and the impurity concentration are variously set according to the required specifications, etc. Furthermore, although each of the embodiments has been described in terms of an n-type as the first conductivity type and a p-type as the second conductivity type, the present invention is equally valid even if the first conductivity type is a p-type and the second conductivity type is an n-type. [Industrial Applicability]

[0081] INDUSTRIAL APPLICABILITY As described above, the silicon carbide semiconductor device according to the present invention is useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, automobile igniters, and the like. [Explanation of symbols]

[0082] 1, 101 n + Silicon carbide substrate 2, 102 n-type silicon carbide epitaxial layer 2a First n-type silicon carbide epitaxial layer 2b Second n-type silicon carbide epitaxial layer 3, 103 p-type silicon carbide epitaxial layer 4, 104 1st p. + Type-based domain 5, 105 2nd p. + Type-based domain 6, 106 n-type high concentration region 6a Lower n-type high concentration region 6b Upper n-type high concentration region 7, 107 n + Type Source Area 8, 108 p. ++ Mold contact area 9, 109 Gate insulating film 10, 110 Gate electrode 11, 111 Interlayer insulating film 13, 113 Source electrode 14, 114 Back electrode 18, 118 trenches 20 Diode cell area 21 MOS cell area 50, 51, 150 Trench MOSFET

Claims

1. a trench provided in a first main surface of a semiconductor body including a semiconductor substrate of a first conductivity type, the trench having a plurality of longitudinal portions extending in a first direction; a first semiconductor region of a first conductivity type selectively provided on the first main surface of the semiconductor substrate and provided so as to contact side walls of at least some of the plurality of elongate portions; a second conductivity type bottom region provided so as to contact the bottom of at least some of the plurality of elongate portions; a second semiconductor region of a second conductivity type selectively provided on the first major surface of the semiconductor substrate, the second semiconductor region extending from the first major surface along a sidewall of the longitudinal portion to the bottom region; Equipped with The second semiconductor region is a semiconductor layer of a second conductivity type; a second conductivity type high concentration semiconductor region having a higher impurity concentration than the semiconductor layer, the high concentration semiconductor region being selectively provided on the first main surface of the semiconductor substrate; a second conductivity type connection region connecting the semiconductor layer and the bottom region; and the first semiconductor regions and the high concentration semiconductor regions are periodically arranged apart from each other in the first direction, 10. A silicon carbide semiconductor device, comprising: a silicon carbide substrate; a first insulating film formed on the first surface of the silicon carbide substrate; a first insulating film formed on the first surface of the silicon carbide substrate;

2. The silicon carbide semiconductor device according to claim 1 , wherein the second semiconductor regions are provided periodically in the first direction.

3. 3 . The silicon carbide semiconductor device according to claim 1 , wherein, in a plan view, a distance between the second semiconductor regions adjacent to each other in the first direction is larger than a length of the second semiconductor regions in the first direction.

4. A silicon carbide semiconductor device described in any one of claims 1 to 3, characterized in that at least a portion of the first semiconductor region is provided across a mesa region between adjacent longitudinal portions.

5. An interlayer insulating film provided on the first main surface of the semiconductor substrate; a contact hole penetrating the interlayer insulating film in a depth direction; a source electrode contacting the first semiconductor region and the second semiconductor region on the first main surface through the contact hole; The silicon carbide semiconductor device according to claim 1 , further comprising:

6. A silicon carbide semiconductor device as described in claim 1, characterized in that at least a portion of the high concentration semiconductor region is provided across a mesa region between adjacent longitudinal portions.

7. A silicon carbide semiconductor device as described in claim 1, characterized in that the high concentration semiconductor region is in contact with only one side of the adjacent longitudinal portion.

8. A trench provided on a first main surface of a semiconductor substrate including a semiconductor substrate of a first conductivity type, the trench having a plurality of longitudinal portions extending in a first direction; a plurality of mesa regions provided between adjacent longitudinal portions; a second conductivity type bottom region provided so as to contact the bottom of at least some of the plurality of elongate portions; Equipped with The mesa region is a semiconductor layer of a second conductivity type; a first semiconductor region of a first conductivity type selectively provided on the first main surface of the semiconductor substrate and provided so as to contact side walls of at least some of the plurality of elongate portions; a second conductivity type high concentration semiconductor region having a higher impurity concentration than the semiconductor layer, the high concentration semiconductor region being selectively provided on the first main surface of the semiconductor substrate; and second conductivity type connection regions that connect the semiconductor layer and the bottom region are provided periodically in the first direction; the first semiconductor regions and the high concentration semiconductor regions are periodically arranged apart from each other in the first direction, 10. A silicon carbide semiconductor device, comprising: a silicon carbide substrate; a first insulating film formed on the first surface of the silicon carbide substrate; a first insulating film formed on the first surface of the silicon carbide substrate;

9. A silicon carbide semiconductor device described in any one of claims 1 to 8, characterized in that the connection region is provided from one of the adjacent longitudinal portions to the other of the adjacent longitudinal portions.

10. A silicon carbide semiconductor device as described in any one of claims 1 to 9, characterized in that the bottom region has a higher impurity concentration than the semiconductor layer.

11. A silicon carbide semiconductor device described in any one of claims 1 to 10, characterized in that the connection region has a higher impurity concentration than the semiconductor layer.

12. A silicon carbide semiconductor device as described in any one of claims 1 to 11, characterized in that it is provided with a gate electrode embedded in one or more of the longitudinal portions via a gate insulating film.

13. The plurality of mesa regions provided between adjacent longitudinal portions are a first mesa region having the semiconductor layer and the first semiconductor region in contact with the gate insulating film; a second mesa region in which the connection region is provided across the adjacent longitudinal portions; 13. The silicon carbide semiconductor device according to claim 12, comprising:

14. A trench provided on a first main surface of a semiconductor substrate including a semiconductor substrate of a first conductivity type, the trench having a plurality of longitudinal portions extending in a first direction; a plurality of first mesa regions provided between adjacent longitudinal portions; a plurality of second mesa regions provided between adjacent longitudinal portions; a gate electrode embedded in one or more of the longitudinal portions via a gate insulating film; Equipped with The first mesa region is a first semiconductor region of a first conductivity type selectively provided on the first main surface of the semiconductor substrate and in contact with the gate insulating film; a second conductivity type semiconductor layer that is in contact with the gate insulating film below the first semiconductor region; a second conductivity type high concentration semiconductor region selectively provided on the first main surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor layer; and The second mesa region is a second semiconductor region of a second conductivity type provided from a bottom of one of the adjacent long portions to a bottom of the other of the adjacent long portions; the first semiconductor regions and the high concentration semiconductor regions are periodically arranged apart from each other in the first direction, 10. A silicon carbide semiconductor device, comprising: a silicon carbide substrate; a first insulating film formed on the first surface of the silicon carbide substrate; a first insulating film formed on the first surface of the silicon carbide substrate;

15. A silicon carbide semiconductor device as described in claim 13 or 14, characterized in that a plurality of the first mesa regions are provided between two of the second mesa regions.

16. A second conductivity type bottom region provided so as to contact the bottom of at least some of the plurality of longitudinal portions, 15. The silicon carbide semiconductor device according to claim 14, wherein the first mesa region has a connection region of the second conductivity type that connects the semiconductor layer and the bottom region.

17. The first mesa region functions as part of a MOS cell region; The silicon carbide semiconductor device according to claim 13 , wherein the second mesa region functions as a part of a diode cell region.

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