field-effect transistor

Abstract

To provide a field effect transistor having a trench gate structure and higher reliability.SOLUTION: A field effect transistor 1 includes a first semiconductor layer 10 of an n-type including an oxide gallium semiconductor, a second semiconductor layer 11 including Si and provided on the first semiconductor layer 10 through an intermediate semiconductor layer 22 of an n-type, first and second p-type semiconductor parts 13a and 13b embedded in first and second trenches 12a and 12b, respectively, a gate electrode 16 covered with a gate insulating film 15 and embedded in a third trench 14 in which one side surface and a part of a bottom surface are formed of the first p-type semiconductor part 13a, an n-type region 111 provided on a surface layer of a region between trenches of the second semiconductor layer 11, and a p-type region 112 provided in a region between the n-type region 111 and the first semiconductor layer 10 in the region between the trenches.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a field effect transistor. [Background technology]

[0002] Conventionally, a field effect transistor having a trench gate structure is known that uses β-Ga2O3 and Si as a semiconductor layer (see Patent Document 1). In the field effect transistor described in Patent Document 1, the bottom of the trench where the electric field concentrates is provided in a β-Ga2O3 layer with high dielectric breakdown field strength, so that dielectric breakdown of the semiconductor layer can be suppressed.

[0003] Also, conventionally, a field effect transistor having a trench gate structure is known in which a p-type region overlapping a gate oxide film region is provided in a semiconductor layer made of SiC (see Non-Patent Document 1). In the field effect transistor described in Non-Patent Document 1, the p-type region overlapping the gate oxide film region can alleviate the concentration of the electric field at the bottom of the trench. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 6873516 [Non-patent literature]

[0005] [Non-Patent Document 1] D. Peters et, al., “CoolSiC Trench MOSFET Combining SiC Performance with Silicon Ruggedness”, Issue 3 Power electronics Europe 2017. Summary of the Invention [Problem to be solved by the invention]

[0006] In particular, to obtain a field-effect transistor with excellent reliability, it would be ideal to alleviate the concentration of the electric field at the bottom of the trench by applying the p-type region overlapping the gate oxide film region described in Non-Patent Document 1 to the field-effect transistor described in Patent Document 1. In this case, not only the dielectric breakdown of the semiconductor layer around the bottom of the trench but also the dielectric breakdown of the gate insulating film can be suppressed, and further improvement in the reliability of the field-effect transistor can be expected.

[0007] However, since there is no p-type β-Ga2O3 with good conductivity, it is not possible to form a p-type region by converting a part of the β-Ga2O3 in the field effect transistor described in Patent Document 1 into a p-type region, as in the p-type region in SiC in the field effect transistor described in Non-Patent Document 1. For this reason, the p-type region overlapping the gate oxide film region described in Non-Patent Document 1 cannot be applied to the field effect transistor described in Patent Document 1.

[0008] An object of the present invention is to provide a field effect transistor having a trench gate structure and having higher reliability. [Means for solving the problem]

[0009] In order to achieve the above object, one aspect of the present invention provides the following field effect transistor.

[0010] [1] A semiconductor device comprising: an n-type first semiconductor layer made of a gallium oxide-based semiconductor; a second semiconductor layer made of Si provided on the first semiconductor layer via an n-type intermediate semiconductor layer; first and second p-type semiconductor portions respectively embedded in first and second trenches extending from an upper surface of the second semiconductor layer to the first semiconductor layer; a gate electrode covered with a gate insulating film and embedded in a third trench extending from an upper surface of the second semiconductor layer to the first semiconductor layer, the third trench having one side surface and a part of a bottom surface formed by the first p-type semiconductor portion; a p-type region provided in a region between the first semiconductor layer and the n-type region in the inter-trench region so as to isolate the first semiconductor layer from the n-type region; a source electrode connected to the n-type region; and a drain electrode connected to the first semiconductor layer, wherein the intermediate semiconductor layer is made of an n-type non-oxide that can maintain its n-type property when oxidized, or n-type SiC, and when the intermediate semiconductor layer is made of the n-type non-oxide, the first semiconductor layer side is partly or entirely oxidized or is not oxidized, and when the intermediate semiconductor layer is made of n-type SiC, the intermediate semiconductor layer is not oxidized. [2] The field effect transistor according to [1] above, wherein a second n-type region is provided in a region between the intermediate semiconductor layer and the p-type region in the inter-trench region. [3] The field-effect transistor according to [1] above, wherein a second p-type region is provided in a surface layer of the inter-trench region, in a region between the n-type region and the second trench. [4] The field effect transistor according to any one of the above [1] to [3], wherein the p-type semiconductor portion is made of a p-type oxide semiconductor. [5] The field-effect transistor according to [4] above, wherein the p-type oxide semiconductor is p-type NiO, CuO, or Cu2O. [6] The field-effect transistor according to any one of the above [1] to [3], wherein the intermediate semiconductor layer is made of the n-type non-oxide, and the non-oxide is one or more mixed crystals selected from the group consisting of GaN, GaP, GaAs, GaSb, and GaBi, one or more mixed crystals selected from the group consisting of InN, InP, InAs, InSb, and InBi, one or more mixed crystals selected from the group consisting of ZnS, ZnSe, and ZnTe, one or more mixed crystals selected from the group consisting of CdS, CdSe, and CdTe, or Ge. [7] The field effect transistor according to [6] above, wherein the non-oxide is GaP, GaAs, or a mixed crystal thereof. [Effects of the Invention]

[0011] According to the present invention, it is possible to provide a field effect transistor having a trench gate structure and having higher reliability. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a vertical cross-sectional view of a field effect transistor according to an embodiment of the present invention. [Figure 2] Figures 2(a) and (b) are cross-sectional TEM images of the vicinity of the interface between Si and Ga2O3 that were annealed at 400°C and 1000°C, respectively, after bonding. [Figure 3] Figures 3(a) and (b) are graphs showing the element concentration profiles near the interface between Si and Ga2O3 that were annealed at 400°C and 1000°C, respectively, after bonding. [Figure 4] 4(a) to 4(c) are vertical cross-sectional views showing an example of a manufacturing process for a field effect transistor according to an embodiment of the present invention. [Figure 5] 5(a) to 5(c) are vertical cross-sectional views showing an example of a manufacturing process for a field effect transistor according to an embodiment of the present invention. [Figure 6]6(a) and 6(b) are vertical cross-sectional views showing an example of a manufacturing process for a field effect transistor according to an embodiment of the present invention. [Figure 7] 7(a) to 7(c) are vertical cross-sectional views showing a modified example of the manufacturing process of the field effect transistor according to the embodiment of the present invention. [Figure 8] 8(a) and 8(b) are vertical cross-sectional views showing a modified example of the manufacturing process of the field effect transistor according to the embodiment of the present invention. [Figure 9] 9(a), (b), and (c) are graphs showing the off-breakdown voltage characteristics, gate characteristics, and on-characteristics of an example of a field-effect transistor according to an embodiment of the present invention, respectively. DETAILED DESCRIPTION OF THE INVENTION

[0013] (Field-effect transistor structure) 1 is a vertical cross-sectional view of a field effect transistor 1 according to an embodiment of the present invention. The field effect transistor 1 is a vertical field effect transistor having a trench gate structure.

[0014] The field-effect transistor 1 includes an n-type first semiconductor layer 10 made of a gallium oxide-based semiconductor, a second semiconductor layer 11 made of Si and provided on the first semiconductor layer 10 via an n-type intermediate semiconductor layer 22, a first p-type semiconductor portion 13a and a second p-type semiconductor portion 13b respectively embedded in a first trench 12a and a second trench 12b extending from the upper surface of the second semiconductor layer 11 to the first semiconductor layer 10, and a third p-type semiconductor portion 13b extending from the upper surface of the second semiconductor layer 11 to the first semiconductor layer 10, the third p-type semiconductor portion 13a being provided such that one side surface and a part of the bottom surface are formed by the first p-type semiconductor portion 13a. The field-effect transistor 1 includes a gate electrode 16 buried in the trench 14 and covered with a gate insulating film 15, an n-type region 111 provided in at least a part of the surface layer of the region between the second trench 12b and the third trench 14 of the second semiconductor layer 11 (hereinafter referred to as the inter-trench region) on the third trench 14 side, a p-type region 112 provided in the region between the first semiconductor layer 10 and the n-type region 111 in the inter-trench region so as to isolate the first semiconductor layer 10 from the n-type region 111, a source electrode 17 connected to the n-type region 111, and a drain electrode 18 connected to the first semiconductor layer 10. The gate electrode 16 on the left side shown in FIG. 1 is used in a field-effect transistor adjacent to the left side of the field-effect transistor 1.

[0015] The field-effect transistor 1 may be of either a normally-off type or a normally-on type, but when used as a power device, it is usually manufactured as a normally-off type from the viewpoint of safety, in order to prevent conduction between the source electrode 17 and the drain electrode 18 when the gate becomes uncontrollable due to a break in the gate circuit or the like.

[0016] In the normally-off field-effect transistor 1, by applying a voltage equal to or greater than the gate threshold voltage between the gate electrode 16 and the source electrode 17, a vertical channel is formed in the region of the p-type region 112 on the gate insulating film 15 side in the inter-trench region, allowing a current to flow between the source electrode 17 and the drain electrode 18.

[0017] The first semiconductor layer 10 is composed of a single crystal of a gallium oxide-based semiconductor having a β-type crystal structure. Here, the gallium oxide-based semiconductor refers to Ga2O3 or Ga2O3 to which elements such as Al and In are added. For example, the gallium oxide-based semiconductor has a composition represented by (Ga

[0020] , Al<> y In<> (1-x-y) )2O3 (0 < x ≤ 1, 0 ≤ y ≤ 1, 0 < x + y ≤ 1). When Al is added to Ga2O3, the bandgap widens, and when In is added, the bandgap narrows. Also, the first semiconductor layer 10, which is n-type, contains donor impurities such as Si and Sn.

[0018] Further, the first semiconductor layer 10 typically includes, as shown in FIG. 1, a layer 101 with a high donor concentration for ohmic connection to the drain electrode 18 and a layer 102 thereon. For example, layer 101 has a donor concentration of 1×10<> 18 cm<> -3 or more and 1×10<> 21 cm<> -3 or less, and layer 102 has a donor concentration of 1×10<> 15 cm<> -3 or more and 1×10<> 17 cm<> -3 or less. Also, for example, the thickness of layer 101 is 30 μm or more and 600 μm or less, and the thickness of layer 102 is 5 μm or more and 50 μm or less.

[0019] Layer 101 of the first semiconductor layer 10 typically consists of a substrate of a gallium oxide-based semiconductor. In this case, the substrate is formed by slicing a bulk crystal of a gallium oxide-based single crystal grown by a melt growth method such as the FZ (Floating Zone) method or the EFG (Edge Defined Film Fed Growth) method and polishing the surface. Also, layer 102 of the first semiconductor layer 10 is typically an epitaxial film formed using the upper surface of layer 101 as a bottom surface.

[0020] The second semiconductor layer 11 is a layer made of single crystal Si. The n-type region 111 and the p-type region 112 formed in the second semiconductor layer 11 are formed by, for example, implanting donor impurities and acceptor impurities into the second semiconductor layer 11.

[0021] The n-type region 111 formed in the second semiconductor layer 11 is the source of the field effect transistor 1. The n-type region 111 contains donor impurities such as arsenic, and is doped with, for example, 1×10 18 cm -3 That's it, 1×10 21 cm -3 With a high donor concentration of:

[0022] The p-type region 112 formed in the second semiconductor layer 11 contains an acceptor impurity such as boron, and has a concentration of, for example, 1×10 18 cm -3 That's it, 1×10 21 cm -3 With the following acceptor concentrations:

[0023] If the second semiconductor layer 11 is too thin, it becomes difficult to form the n-type region 111 and the p-type region 112, and if it is too thick, it becomes necessary to form deep first trench 12a, second trench 12b, and third trench 14. For this reason, it is preferable that the thickness D1 of the second semiconductor layer 11 is, for example, not less than 0.6 μm and not more than 1.2 μm.

[0024] The method for forming the second semiconductor layer 11 is not particularly limited, and for example, a Si single crystal may be epitaxially grown using the upper surface of the intermediate semiconductor layer 22 on the first semiconductor layer 10 as a base surface. However, in order to form a second semiconductor layer 11 with high crystal quality, it is preferable to bond a Si substrate to the first semiconductor layer 10 side by a substrate bonding technique such as surface activated bonding, and to use the Si substrate thinned by a thin film technique such as the smart cut method as the second semiconductor layer 11.

[0025] The intermediate semiconductor layer 22 is made of an n-type non-oxide that can maintain n-type when oxidized, or n-type SiC. Here, when the intermediate semiconductor layer 22 is made of an n-type non-oxide that can maintain n-type when oxidized, the non-oxidized portion is called a non-oxidized layer 221, and the oxidized portion is called an oxidized layer 222.

[0026] The oxide layer 222 of the intermediate semiconductor layer 22 is formed by the reaction of the intermediate semiconductor layer 22, which initially consists only of the non-oxide layer 221, with the first semiconductor layer 10 and being oxidized by heat applied during the manufacturing process of the field-effect transistor 1. Specifically, the non-oxide layer 221 is oxidized by oxygen released from the first semiconductor layer 10 made of a gallium oxide-based semiconductor, and the oxide layer 222 is generated from the side in contact with the first semiconductor layer 10.

[0027] If the intermediate semiconductor layer 22 is not provided and the first semiconductor layer 10 and the second semiconductor layer 11 are in direct contact, when a heat treatment of approximately 300 to 400°C or higher is performed during the manufacturing process of the field-effect transistor 1, oxygen released from the gallium oxide-based semiconductor of the first semiconductor layer 10 oxidizes the Si in the second semiconductor layer 11, resulting in the formation of Si oxide with high resistivity between the first semiconductor layer 10 and the second semiconductor layer 11, preventing sufficient current from flowing between the first semiconductor layer 10 and the second semiconductor layer 11.

[0028] Figures 2(a) and (b) are cross-sectional TEM images of the vicinity of the interface between Si and Ga2O3 that were annealed at 400°C and 1000°C after bonding. Figures 2(a) and (b) show that when annealing was performed at either 400°C or 1000°C, Si oxide (SiO x ) and thin layers with different contrasts that are thought to be the origin of the nucleation.

[0029] Figures 3(a) and (b) are graphs showing the element concentration profiles near the interface between Si and Ga2O3 that were annealed at 400°C and 1000°C, respectively, after bonding. Although it is difficult to distinguish in Figure 3(a), a layer containing both Si and O can be seen at the interface between Si and Ga2O3 in Figure 3(b), and this layer is thought to correspond to the thin layer seen in Figures 2(a) and (b).

[0030] The non-oxidized layer 221 of the intermediate semiconductor layer 22 is made of a non-oxide that does not contain oxygen, and therefore there is no risk of oxidizing the second semiconductor layer 11 made of Si to form Si oxide. Therefore, a sufficient current can flow between the intermediate semiconductor layer 22 and the second semiconductor layer 11. Furthermore, the oxidized layer 222 of the intermediate semiconductor layer 22 is n-type like the non-oxidized layer 221, and therefore a sufficient current can flow between the first semiconductor layer 10 and the intermediate semiconductor layer 22.

[0031] When the intermediate semiconductor layer 22 is made of an n-type non-oxide that can maintain its n-type when oxidized, it is typically made up of a non-oxidized layer 221 and an oxidized layer 222, as shown in Fig. 1. However, even if the entire intermediate semiconductor layer 22 is oxidized, there is no problem as long as no Si oxide is formed between the intermediate semiconductor layer 22 and the second semiconductor layer 11. That is, the intermediate semiconductor layer 22 may be made up of only the oxidized layer 222. Furthermore, when the manufacturing process of the field-effect transistor 1 is completed at a temperature at which oxidation of the non-oxidized layer 221 does not occur, the intermediate semiconductor layer 22 is made up of only the non-oxidized layer 221.

[0032] The thickness of the intermediate semiconductor layer 22 is preferably 10 nm or more. If the thickness is 10 nm or more, there is little risk that the entire intermediate semiconductor layer 22 will be oxidized by heat applied during the normal manufacturing process of the field-effect transistor 1, and it is possible to prevent Si oxide with high resistivity from being formed between the intermediate semiconductor layer 22 and the second semiconductor layer 11. On the other hand, the thicker the intermediate semiconductor layer 22, the greater the conduction loss, so the thickness of the intermediate semiconductor layer 22 is preferably, for example, 1 μm or less.

[0033] Note that SiC, one of the materials for the intermediate semiconductor layer 22, turns into SiO 2 with high resistivity when oxidized. x Therefore, when the intermediate semiconductor layer 22 is made of n-type SiC, the manufacturing process of the field-effect transistor 1 needs to be completed at a temperature at which the non-oxidized layer 221 does not oxidize, for example, at a temperature of 1000° C. or less, and the intermediate semiconductor layer 22 is made of only the non-oxidized layer 221.

[0034] The intermediate semiconductor layer 22 has the following characteristics: (1) a thermal expansion coefficient that is between the thermal expansion coefficient of the gallium oxide-based semiconductor that constitutes the first semiconductor layer 10 and the thermal expansion coefficient of Si that constitutes the second semiconductor layer 11 in order to reduce strain and prevent peeling at the interface between the intermediate semiconductor layer 22 and the first semiconductor layer 10 and the interface between the first semiconductor layer 10 and the second semiconductor layer 11 (hereinafter referred to as the first condition); (2) a thermal expansion coefficient that is between the thermal expansion coefficient of the gallium oxide-based semiconductor that constitutes the first semiconductor layer 10 and the thermal expansion coefficient of Si that constitutes the second semiconductor layer 11 in order to reduce strain and prevent peeling at the interface between the intermediate semiconductor layer 22 and the first semiconductor layer 10 and the interface between the first semiconductor layer 10 and the second semiconductor layer 11 (hereinafter referred to as the first condition); In order to reduce conduction loss in the plane, it is preferable to satisfy the following conditions: (1) the band offset (the energy difference at the bottom of the conduction band) between the gallium oxide-based semiconductor constituting the first semiconductor layer 10 and the Si constituting the second semiconductor layer 11 is small (hereinafter referred to as the second condition); and (2) in order to epitaxially grow a high-quality intermediate semiconductor layer 22 on the first semiconductor layer 10, the lattice mismatch with the Si constituting the second semiconductor layer 11 is small (hereinafter referred to as the third condition).

[0035] To satisfy the first condition, when the intermediate semiconductor layer 22 includes both the non-oxidized layer 221 and the oxidized layer 222, the thermal expansion coefficients of both the material of the intermediate semiconductor layer 22, i.e., the substance constituting the non-oxidized layer 221, and the oxide generated when the material of the intermediate semiconductor layer 22 is oxidized, i.e., the substance constituting the oxidized layer 222, are required to be between those of a gallium oxide-based semiconductor and that of Si. Furthermore, when the intermediate semiconductor layer 22 is composed only of the oxidized layer 222, the thermal expansion coefficient of the oxide generated when the material of the intermediate semiconductor layer 22 is oxidized is required to be between those of a gallium oxide-based semiconductor and that of Si. Furthermore, when the intermediate semiconductor layer 22 is composed only of the non-oxidized layer 221, the thermal expansion coefficient of the material of the intermediate semiconductor layer 22 is required to be between those of a gallium oxide-based semiconductor and that of Si.

[0036] Table 1 below shows examples of materials for the intermediate semiconductor layer 22, i.e., materials constituting the non-oxidized layer 221, and their thermal expansion coefficients, as well as oxides produced when the material for the intermediate semiconductor layer 22 is oxidized, i.e., materials constituting the oxide layer 222, and their thermal expansion coefficients. Note that the thermal expansion coefficient of ZnTe is an estimated value. In Table 1, "non-oxidized layer" refers to the material constituting the non-oxidized layer 221, and "oxidized layer" refers to the material constituting the oxide layer 222. This also applies to the following tables.

[0037] [Table 1]

[0038] The thermal expansion coefficient of Si is 2.6×10 -6 / K, and the thermal expansion coefficient of Ga2O3, a typical example of gallium oxide semiconductors, is 3.8 to 7.8 × 10 -6 / K. Therefore, when the material of the intermediate semiconductor layer 22 shown in Table 1 is used, the first condition is met or may be met regardless of whether the intermediate semiconductor layer 22 includes both the non-oxidized layer 221 and the oxidized layer 222 or includes only one of them.

[0039] To satisfy the second condition, when the intermediate semiconductor layer 22 includes both the non-oxide layer 221 and the oxide layer 222, the band offset between the conduction band of the non-oxide layer 221 and Si, and the band offset between the conduction band of the oxide layer 222 and the gallium oxide-based semiconductor, are required to be small. Furthermore, when the intermediate semiconductor layer 22 consists only of the oxide layer 222, the band offset between the conduction band of the oxide layer 222 and Si, and the band offset between the conduction band of the oxide layer 222 and the gallium oxide-based semiconductor are required to be small. Furthermore, when the intermediate semiconductor layer 22 consists only of the non-oxide layer 221, the band offset between the conduction band of the non-oxide layer 221 and Si, and the band offset between the conduction band of the non-oxide layer 221 and the gallium oxide-based semiconductor are required to be small. Regarding the band offset of the conduction band, when the intermediate semiconductor layer 22 includes both the non-oxide layer 221 and the oxide layer 222, in addition to the second condition, the conductor band offset between the non-oxide layer 221 and the oxide layer 222 is also required to be small.

[0040] When the material of the intermediate semiconductor layer 22 shown in Table 1 is used, the band offset of the conduction band between the non-oxide layer 221 and Si, the band offset of the conduction band between the oxide layer 222 and Ga2O3, which is a typical example of a gallium oxide-based semiconductor, and the band offset of the conduction band between the non-oxide layer 221 and the oxide layer 222 are shown in Table 2 below. The band offset of the conduction band between the non-oxide layer 221 and Si, and the band offset of the conduction band between the non-oxide layer 221 and Ga2O3, which is a typical example of a gallium oxide-based semiconductor, are shown in Table 3 below. The band offset of the conduction band between the oxide layer 222 and Si, and the band offset of the conduction band between the oxide layer 222 and Ga2O3, which is a typical example of a gallium oxide-based semiconductor, are shown in Table 4 below. c " means the band offset of the conduction band. Note that GaBi is a semimetal and does not have a band gap, so the value of the band offset of the conduction band is not shown.

[0041] [Table 2]

[0042] [Table 3]

[0043] [Table 4]

[0044] According to Table 2, when the intermediate semiconductor layer 22 includes both the non-oxidized layer 221 and the oxidized layer 222, it is preferable to use GaN, GaP, GaAs, GaSb, ZnS, ZnSe, or ZnTe as the material for the intermediate semiconductor layer 22 to satisfy the second condition. Furthermore, according to Table 3, when the intermediate semiconductor layer 22 is composed only of the non-oxidized layer 221, it is preferable to use GaN, GaP, GaAs, GaSb, InN, InP, InSb, ZnS, ZnSe, ZnTe, CdS, CdSe, CdTe, Ge, or 3C-SiC as the material for the intermediate semiconductor layer 22 to satisfy the second condition. Furthermore, according to Table 4, when the intermediate semiconductor layer 22 is composed only of the oxidized layer 222, it is preferable to use GaN, GaP, GaAs, GaSb, ZnS, ZnSe, or ZnTe as the material for the intermediate semiconductor layer 22 to satisfy the second condition.

[0045] Table 5 below shows the lattice mismatch between the material of the intermediate semiconductor layer 22, i.e., the substance constituting the non-oxide layer 221, and Si constituting the second semiconductor layer 11 when the material of the intermediate semiconductor layer 22 shown in Table 1 is used. The lattice mismatch (%) with Si in Table 5 is obtained by dividing the difference in lattice constant with Si by the lattice constant of Si. In calculating the lattice mismatch with Si, the lattice constant of Si(001) 5.431 or the lattice constant of Si(111) 3.84, whichever results in the smaller lattice mismatch with Si, is used as the lattice constant of Si.

[0046] [Table 5]

[0047] According to Table 5, in order to satisfy the third condition, it is preferable to use GaP, GaAs, InN, InP, ZnS, ZnSe, CdS, or Ge as the material for the intermediate semiconductor layer 22.

[0048] According to Tables 1 to 5, the substances constituting the non-oxidized layer 221 shown in Table 1, i.e., the materials of the intermediate semiconductor layer 22, satisfy or are expected to satisfy the above conditions 1 to 3 to a certain extent or more, and are therefore preferred materials for the intermediate semiconductor layer 22. Among these, GaP and GaAs are particularly preferred materials for the intermediate semiconductor layer 22 because they satisfy conditions 1 to 3 to a high degree.

[0049] For this reason, the non-oxide material for the intermediate semiconductor layer 22 that can maintain n-type when oxidized is preferably one or more mixed crystals selected from the group consisting of GaN, GaP, GaAs, GaSb, and GaBi, one or more mixed crystals selected from the group consisting of InN, InP, InAs, InSb, and InBi, one or more mixed crystals selected from the group consisting of ZnS, ZnSe, and ZnTe, one or more mixed crystals selected from the group consisting of CdS, CdSe, and CdTe, or Ge, and particularly preferably GaP, GaAs, or a mixed crystal thereof.

[0050] In a field-effect transistor having a trench gate structure, it is necessary for the n-type semiconductor layer and the p-type semiconductor layer to form a p-n junction for their operation, but it is difficult to form a p-n junction between layers made of different materials. For example, when joining an n-type intermediate semiconductor layer 22 and a p-type second semiconductor layer 11, an unintended compound layer or metal layer may be formed at the interface, or Si diffused from the p-type second semiconductor layer 11 may act as a donor in the n-type intermediate semiconductor layer 22, forming a layer with an extremely high donor concentration near the interface, which may prevent a p-n junction from being obtained.

[0051] 1, it is preferable to provide a second n-type region 113 in the region between the n-type intermediate semiconductor layer 22 and the p-type region 112 in the inter-trench region of the second semiconductor layer 11. In this case, the p-n junction is formed not between the intermediate semiconductor layer 22 and the p-type region 112, which are made of different materials, but between the second n-type region 113 and the p-type region 112, both of which are made of Si. Therefore, it is sufficient to simply form an ohmic contact interface, and the interface does not require flatness or steepness. In other words, the p-n junction can be easily formed. The second n-type region 113 contains a donor impurity such as phosphorus, and has a dopant concentration of, for example, 1×10 15 cm -3 That's it, 1×10 17 cm -3 With the following donor concentrations:

[0052] 1, a second p-type region 114 is preferably provided in the surface layer of the inter-trench region of the second semiconductor layer 11 in the region between the n-type region 111 and the second trench 12b. This allows the bulk of the field-effect transistor 1 in the p-type region 112 in the inter-trench region to be fixed to ground potential together with the source potential using the second p-type region 114. The second p-type region 114 contains acceptor impurities such as boron. The acceptor concentration of the second p-type region 114 is higher than the acceptor concentration of the p-type region 112, for example, 1×10 18 cm -3 That's it, 1×10 21 cm -3 The following is the result.

[0053] The first trench 12a and the second trench 12b reach from the upper surface of the second semiconductor layer 11 (the surface opposite to the first semiconductor layer 10) to the first semiconductor layer 10. That is, the bottoms of the first trench 12a and the second trench 12b and the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b embedded therein are located below the upper surface of the first semiconductor layer 10 (the surface on the second semiconductor layer 11 side).

[0054] The first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b are preferably made of a p-type oxide semiconductor such as NiO, CuO, or Cu2O, which is unlikely to react with the gallium oxide-based semiconductor constituting the first semiconductor layer 10. When NiO is used as the material for the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b, a high breakdown voltage can be obtained due to the large band gap of NiO, 3.7 eV. When CuO or Cu2O is used, the breakdown voltage is lower than that of NiO, but the material cost can be reduced compared to NiO. Note that these materials may be amorphous, polycrystalline, or single crystalline, or may be a composite of two or more of these.

[0055] By providing the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b, when a reverse bias is applied between the gate electrode 16 and the source electrode 17 of the field-effect transistor 1 (when the field-effect transistor 1 is off), an electric field is concentrated at the bottoms of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b. The bottoms of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b are located in the first semiconductor layer 10 made of a gallium oxide-based semiconductor with a high breakdown field strength, thereby suppressing breakdown of the semiconductor layer due to electric field concentration and increasing the breakdown voltage of the field-effect transistor 1. Furthermore, by providing the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b and concentrating the electric field in the first semiconductor layer 10, it is possible to use Si, which has a lower breakdown field strength than a gallium oxide-based semiconductor but a high electron mobility, as the material for the second semiconductor layer 11 in which a channel is formed. This reduces the channel resistance and the on-resistance of the device.

[0056] Furthermore, one side surface and a portion of the bottom surface of the third trench 14 are formed by the first p-type semiconductor portion 13a, and a portion of the bottom surface of the gate electrode 16 covered with the gate insulating film 15 in the third trench 14, for example, approximately half of the cross section shown in FIG. 1, is covered by the first p-type semiconductor portion 13a. This allows the electric field to be concentrated at the bottom of the first p-type semiconductor portion 13a, thereby reducing the electric field at the bottom of the third trench 14. This suppresses dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14, thereby improving the reliability of the field-effect transistor 1. Note that, due to concerns about increased resistance due to a phenomenon known as parasitic JFET, it is not preferable for the entire bottom surface of the gate electrode 16 covered with the gate insulating film 15 to be covered by the first p-type semiconductor portion 13a.

[0057] Since narrowing the n-type layer 102 causes a spatial modulation effect of the electric field, it is preferable that the distance between the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b, i.e., the width D10 of the trench-to-trench region, be 1.2 μm or more and 2.0 μm or less.

[0058] In addition, in order to shield the electric field to the end of the gate electrode due to the spatial modulation effect, it is preferable that the depth D7 of the first trench 12a from the interface between the first semiconductor layer 10 and the second semiconductor layer 11 be 1.6 μm or more and 3.0 μm or less.

[0059] In order to achieve further electric field relaxation due to the spatial modulation effect of the n-type layer 102, the horizontal distance D14 between the second trench 12b and the third trench 14 is preferably 0.8 μm or more and 1.2 μm or less.

[0060] The gate electrode 16 is made of, for example, polycrystalline Si doped with a high concentration of donors, tungsten, tungsten silicide which is a compound of tungsten and Si, etc. The side and bottom surfaces of the gate electrode 16 are covered with a gate insulating film 15, and the top surface thereof is covered with an insulating film 19.

[0061] The gate insulating film 15 insulates the gate electrode 16 from the first semiconductor layer 10, the second semiconductor layer 11, and the intermediate semiconductor layer 22, and the insulating film 19 insulates the gate electrode 16 from the source electrode 17. The gate insulating film 15 and the insulating film 19 are made of, for example, HfO2, Al2O3, or SiO2. The thickness of the gate insulating film 15 is, for example, 30 nm or more and 100 nm or less. The thickness of the insulating film 19 is, for example, 30 nm or more and 100 nm or less.

[0062] The source electrode 17 is made of a metal such as aluminum, and is in ohmic contact with the n-type region 111 of the second semiconductor layer 11. The drain electrode 18 is made of a metal such as titanium or aluminum, and is in ohmic contact with the first semiconductor layer 10.

[0063] There are no particular limitations on the horizontal patterns of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b (i.e., the horizontal patterns of the first trenches 12a and the second trenches 12b), the horizontal patterns of the gate insulating film 15 and the gate electrode 16 (i.e., the horizontal pattern of the third trenches 14), and the horizontal patterns of the n-type region 111 and the second p-type region 114. For example, the first trench 12a and the second trench 12b may be connected at a portion not shown in the vertical cross section of FIG.

[0064] (Field Effect Transistor Manufacturing) 4(a) to (c), 5(a) to (c), 6(a) and (b) are vertical cross-sectional views showing an example of a manufacturing process for the field-effect transistor 1. The manufacturing process shown in FIGS. 4(a) to (c), 5(a) to (c), 6(a) and (b) will be described below.

[0065] 4(a), an intermediate semiconductor layer 22 is formed on an n-type Si substrate 20 containing donor impurities such as phosphorus by MOCVD, MBE, HVPE, sputtering, ALD, etc. At this point, the intermediate semiconductor layer 22 is composed only of a non-oxidized layer 221.

[0066] 4(b), planar ion-implanted regions 21 are formed by implanting hydrogen ions into the Si substrate 20 at a predetermined depth. As will be described later, the Si substrate 20 is divided using the ion-implanted regions 21 as dividing planes, and the films separated from the Si substrate 20 become the second semiconductor layer 11. Therefore, the depth at which the ion-implanted regions 21 are formed is determined depending on the desired thickness of the second semiconductor layer 11.

[0067] The dose of hydrogen ions implanted to form the ion implantation region 21 is, for example, 2×10 16 ~8×10 16 / cm 2 The energy of the ion implantation is determined by the depth at which the ion implantation region 21 is to be formed, and for example, when the ion implantation region 21 is to be formed at a depth of about 950 nm from the surface, hydrogen ions are implanted with an energy of about 110 keV.

[0068] Next, as shown in FIG. 4(c), the surface of the intermediate semiconductor layer 22 formed on the Si substrate 20 and the surface of the layer 102 of the first semiconductor layer 10 are bonded together by surface activated bonding.

[0069] In the surface activated bonding method, for example, 5 × 10 -6 In an ultra-high vacuum chamber under a pressure of about Pa, the top surfaces of layer 102 and intermediate semiconductor layer 22, which have been planarized by a planarization process such as CMP (chemical mechanical polishing), are removed by irradiating them with an Ar atomic beam accelerated at an energy of 1.5 keV, and the exposed newly formed surfaces are brought into contact with each other and bonded.

[0070] 5(a), the Si substrate 20 is divided by smart cut, leaving the second semiconductor layer 11 on the intermediate semiconductor layer 22. At this time, since smart cut involves heat treatment, the intermediate semiconductor layer 22 is oxidized by oxygen removed from the layer 102 of the first semiconductor layer 10, and a part of the non-oxidized layer 221 on the layer 102 side is transformed into an oxidized layer 222.

[0071] In Smart Cut, a heat treatment at 400°C or higher is performed to cause hydrogen embrittlement in the ion implantation region 21, thereby dividing the Si substrate 20. The heat treatment in Smart Cut is performed, for example, for 1 to 10 minutes in an N2 or Ar atmosphere. The heat treatment may be performed in a vacuum chamber under reduced pressure, or in a furnace other than a vacuum chamber. After Smart Cut, another heat treatment (for example, at 500 to 1000°C) is performed to repair damage to the second semiconductor layer 11 caused by the ion implantation and Smart Cut. Thereafter, the surface of the second semiconductor layer 11 may be subjected to a planarization treatment such as CMP.

[0072] 5(b), acceptor impurities such as boron are ion-implanted into the second semiconductor layer 11 to form p-type regions 112. Here, the regions of the n-type second semiconductor layer 11 that are not implanted with the impurities become second n-type regions 113. Thereafter, heat treatment (for example, at 500 to 1000°C) is performed to repair damage to the second semiconductor layer 11 caused by the ion implantation. This heat treatment advances oxidation of the intermediate semiconductor layer 22, and the thickness of the oxide layer 222 increases.

[0073] Next, as shown in FIG. 5(c), after forming a second p-type region 114 and an n-type region 111 in the second semiconductor layer 11, a first trench 12a and a second trench 12b are formed in the stack of the first semiconductor layer 10, the intermediate semiconductor layer 22, and the second semiconductor layer 11, and a first p-type semiconductor portion 13a and a second p-type semiconductor portion 13b are formed in the first trench 12a and the second trench 12b, respectively.

[0074] The second p-type region 114 is formed by ion-implanting an acceptor impurity such as boron into the second semiconductor layer 11. The n-type region 111 is formed by ion-implanting a donor impurity such as arsenic into the second semiconductor layer 11.

[0075] The first trench 12a and the second trench 12b are formed by, for example, photolithography and dry etching. The first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b are formed by depositing a material in the first trench 12a and the second trench 12b by, for example, CVD (Chemical Vapor Deposition), vacuum deposition, sputtering, or the like.

[0076] 6(a), a third trench 14 is formed in the stack of the first semiconductor layer 10, the intermediate semiconductor layer 22, and the second semiconductor layer 11. The third trench 14 is formed so that a portion of the third trench 14 overlaps with the first trench 12a in the width direction. The third trench 14 is formed by, for example, photolithography and dry etching.

[0077] 6(b), a gate insulating film 15 and a gate electrode 16 are formed in the third trench 14. The gate insulating film 15 and the gate electrode 16 are formed by depositing materials in the third trench 14 by, for example, CVD, vacuum deposition, sputtering, or the like.

[0078] Thereafter, an insulating film 19, a source electrode 17, and a drain electrode 18 are formed to obtain a field effect transistor 1. The insulating film 19 is formed by depositing a material on the gate electrode 16 by, for example, CVD, vacuum deposition, sputtering, or the like. The source electrode 17 and the drain electrode 18 are formed by depositing a material on the upper surface of the second semiconductor layer 11 and the lower surface of the first semiconductor layer 10 by, for example, sputtering, or the like.

[0079] In the above example, the intermediate semiconductor layer 22 was formed on the Si substrate 20 before bonding by the surface activated bonding method, but it may also be formed on the layer 102 of the first semiconductor layer 10, or it may be formed on both the Si substrate 20 and the layer 102.

[0080] 7(a) to 7(c) and 8(a) and 8(b) are vertical cross-sectional views showing modified examples of the manufacturing process of the field-effect transistor 1. FIG.

[0081] First, as shown in FIG. 7(a), a p-type Si substrate 23 containing acceptor impurities such as boron is prepared.

[0082] 7(b), an intermediate semiconductor layer 22 is formed on the Si substrate 23 by MOCVD, MBE, HVPE, sputtering, ALD, or the like. In this case, the material of the intermediate semiconductor layer 22 is selected from materials containing elements that act as donor impurities in Si, such as GaAs containing As and GaP containing P.

[0083] After the intermediate semiconductor layer 22 is formed, elements such as As and P, which act as donor impurities in Si, diffuse from the intermediate semiconductor layer 22 into the p-type Si substrate 23, converting a part of the Si substrate 23 on the side of the intermediate semiconductor layer 22 to n-type. This n-type part of the Si substrate 23 is used as the second n-type region 113.

[0084] 7(c), planar ion implantation regions 24 are formed by implanting hydrogen ions into the Si substrate 23 at a predetermined depth. As will be described later, the Si substrate 23 is divided using the ion implantation regions 24 as dividing planes, and the films separated from the Si substrate 23 become the second semiconductor layer 11. Therefore, the depth at which the ion implantation regions 24 are formed is determined depending on the desired thickness of the second semiconductor layer 11.

[0085] The dose of hydrogen ions implanted to form the ion implantation region 24 is, for example, 2×10 16 ~8×10 16 / cm 2 The energy of the ion implantation is determined by the depth at which the ion implantation region 24 is to be formed, and for example, when the ion implantation region 24 is to be formed at a depth of about 950 nm from the surface, hydrogen ions are implanted with an energy of about 110 keV.

[0086] Next, as shown in FIG. 8(a), the surface of the intermediate semiconductor layer 22 formed on the Si substrate 23 and the surface of the layer 102 of the first semiconductor layer 10 are bonded together by surface activated bonding.

[0087] In the surface activated bonding method, for example, 5 × 10 -6 In an ultra-high vacuum chamber under a pressure of about Pa, the top surfaces of layer 102 and intermediate semiconductor layer 22, which have been planarized by a planarization process such as CMP (chemical mechanical polishing), are removed by irradiating them with an Ar atomic beam accelerated at an energy of 1.5 keV, and the exposed newly formed surfaces are brought into contact with each other and bonded.

[0088] 8(b), the Si substrate 23 is divided by Smart Cut, leaving the second semiconductor layer 11 on the intermediate semiconductor layer 22. Here, the portions of the Si substrate 23 that have not been made n-type, i.e., the portions where the second n-type regions 113 are not formed, become the p-type regions 112. At this time, because Smart Cut involves heat treatment, the intermediate semiconductor layer 22 is oxidized by oxygen that has escaped from the layer 102 of the first semiconductor layer 10, and a portion of the non-oxidized layer 221 on the layer 102 side changes into an oxidized layer 222.

[0089] In Smart Cut, a heat treatment at 400°C or higher is performed to cause hydrogen embrittlement in the ion implantation region 24, thereby dividing the Si substrate 23. The heat treatment in Smart Cut is performed, for example, for 1 to 10 minutes in an N2 or Ar atmosphere. The heat treatment may be performed in a vacuum chamber under reduced pressure, or in a furnace other than a vacuum chamber. After Smart Cut, another heat treatment (for example, at 500 to 1000°C) is performed to repair damage to the second semiconductor layer 11 caused by the ion implantation and Smart Cut. Thereafter, the surface of the second semiconductor layer 11 may be subjected to a planarization treatment such as CMP.

[0090] Thereafter, the field effect transistor 1 is manufactured through the same steps as those shown in FIGS. 5(c) to 6(b) above.

[0091] (Field-effect transistor characteristics) The following describes the simulation results of the electric field distribution, the off-state breakdown voltage characteristics, the gate characteristics, and the on-state characteristics when a reverse bias is applied to the gate electrode 16 of the field-effect transistor 1 (when it is off).

[0092] Table 6 below shows the dimensions D1 to D18 (see FIG. 1) of each part of the field effect transistor 1 used in this simulation.

[0093] [Table 6]

[0094] The material of the first semiconductor layer 10 was Ga2O3, the material of the first p-type semiconductor portion 13a and the second p-type semiconductor portion 13b was NiO, the material of the gate electrode 16 was polycrystalline Si, and the material of the gate insulating film 15 was SiO2. The material of the intermediate semiconductor layer 22 was GaAs.

[0095] The thickness of the gate insulating film 15 is 50 nm, the thickness of the first semiconductor layer 10 is 5 μm, the thickness of the intermediate semiconductor layer 22 is 10 nm, and the interface trap state density between the first semiconductor layer 10 and the second semiconductor layer 11 is 2×10 12 cm -2 / eV, the radius of curvature of the corners at both ends of the bottom of the first trench 12a and the second trench 12b shown in the cross section of FIG. 1 was 0.2 μm, the radius of curvature of the corners at both ends of the bottom of the third trench 14 was 0.15 μm, and the relative dielectric constant of the insulating film 19 was 3.9.

[0096] Table 7 below shows the donor concentration or acceptor concentration at each part of the field effect transistor 1 used in this simulation.

[0097] [Table 7]

[0098] When a voltage of 1400 V was applied to the drain electrode 18 of the above-described field-effect transistor 1 (the source electrode 17 was grounded), the electric field strengths at points P1, P2, and P3 (see FIG. 1) were approximately 7 MV / cm, 4.5 MV / cm, and 0.3 MV / cm, respectively. Here, point P1 is a point in the first semiconductor layer 10 around the bottom of the first trench 12a, point P2 is a point in the gate insulating film 15 around the bottom of the third trench 14, and point P3 is a point on the interface between the p-type region 112 and the second n-type region 113.

[0099] The electric field at point P1 was strongest inside the field-effect transistor 1, and the electric field strengths at points P2 and P3 were kept low as described above. From this, it was confirmed that when a reverse bias is applied to the gate electrode 16 of the field-effect transistor 1, the electric field is concentrated at the bottom of the first p-type semiconductor portion 13a, and the electric field is relaxed around the bottom of the third trench 14 and around the interface between the first semiconductor layer 10 and the second semiconductor layer 11. Therefore, it is possible to suppress dielectric breakdown of the first semiconductor layer 10 and the gate insulating film 15 around the bottom of the third trench 14, where the electric field is usually likely to concentrate.

[0100] 9(a), (b), and (c) are graphs showing the off-breakdown voltage characteristics, gate characteristics, and on-characteristics, respectively, of an example of the field-effect transistor 1. These characteristics are obtained when the donor concentration of the intermediate semiconductor layer 22 is 1×10 16 cm -3 In addition to the condition that the donor concentration of the intermediate semiconductor layer 22 is 1×10 17 cm -3 , 1×10 18 cm -3 This was obtained under the condition that

[0101] Fig. 9(a) is a graph showing the off-state breakdown voltage characteristics of the field-effect transistor 1. The graph in Fig. 9(a) shows the change in drain current when the gate voltage applied to the gate electrode 16 is fixed at -5 V and the drain voltage applied to the drain electrode 18 is changed.

[0102] According to FIG. 9(a), the donor concentration of the intermediate semiconductor layer 22 is 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 The maximum values ​​of the breakdown voltage when the drain voltage exceeds approximately 1400 V are 1497.6 V, 1497.7 V, and 1498.5 V, respectively, and in all cases, avalanche breakdown occurs when the drain voltage exceeds approximately 1400 V. Furthermore, when the intermediate semiconductor layer 22 is not provided and the thickness of the layer 102 of the first semiconductor layer 10 is increased by the thickness of the intermediate semiconductor layer 22, the maximum value of the breakdown voltage is 1497.9 V, which shows that providing the intermediate semiconductor layer 22 has almost no effect on the breakdown voltage characteristics.

[0103] Fig. 9(b) is a graph showing the gate characteristics of the field-effect transistor 1. The graph in Fig. 9(b) shows the change in drain current when the drain voltage applied to the drain electrode 18 is fixed at 1 V and the gate voltage applied to the gate electrode 16 is changed.

[0104] According to FIG. 9(b), the donor concentration of the intermediate semiconductor layer 22 is 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 In either case, almost the same gate characteristics are exhibited, and the gate threshold voltage is about 5 V. Furthermore, when the intermediate semiconductor layer 22 is not provided and the thickness of the layer 102 of the first semiconductor layer 10 is increased by the thickness of the intermediate semiconductor layer 22, the gate threshold voltage is also about 5 V, and it was found that providing the intermediate semiconductor layer 22 has almost no effect on the gate characteristics.

[0105] Fig. 9(c) is a graph showing the on-characteristics of the field-effect transistor 1. The graph in Fig. 9(c) shows the change in drain current when the gate voltage applied to the gate electrode 16 is fixed at 15 V and the drain voltage applied to the drain electrode 18 is changed.

[0106] According to FIG. 9(c), the donor concentration of the intermediate semiconductor layer 22 is 1×10 16 cm -3 , 1×10 17 cm -3 , 1×10 18 cm -3 In either case, the on-resistance is approximately 2.85 mΩcm when the gate voltage is 15 V and the drain voltage is 1 V. 2 In addition, when the intermediate semiconductor layer 22 is not provided and the thickness of the layer 102 of the first semiconductor layer 10 is increased by the thickness of the intermediate semiconductor layer 22, the on-resistance is approximately 2.83 mΩcm when the gate voltage is 15 V and the drain voltage is 1 V. 2 It was found that the provision of the intermediate semiconductor layer 22 had almost no effect on the on-characteristics.

[0107] From the results of FIGS. 9(a) to 9(c), even if Si or the like diffuses into the intermediate semiconductor layer 22 and the donor concentration of the intermediate semiconductor layer 22 increases, the donor concentration of the intermediate semiconductor layer 22 increases by at least 1×10 16 ~1×10 18 cm -3 It was found that within this range, there is almost no effect on the breakdown voltage characteristics, gate characteristics, and on-resistance.

[0108] (Effects of the embodiment) According to the above-described embodiment of the present invention, the bottom of third trench 14, into which gate electrode 16 is buried, is located in n-type first semiconductor layer 10 made of a gallium oxide-based semiconductor having a high breakdown field strength, and the first p-type semiconductor portion 13a alleviates the electric field around the bottom of third trench 14, thereby suppressing breakdown of first semiconductor layer 10 and gate insulating film 15 around the bottom of third trench 14 and improving the reliability of field-effect transistor 1. Furthermore, by providing intermediate semiconductor layer 22 between first semiconductor layer 10 and second semiconductor layer 11, it is possible to prevent formation of Si oxide with high resistivity between first semiconductor layer 10 and second semiconductor layer 11.

[0109] Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments and various modifications can be made without departing from the spirit and scope of the invention. Furthermore, the components of the above-described embodiments can be combined in any manner without departing from the spirit and scope of the invention.

[0110] Furthermore, the above-described embodiments do not limit the scope of the invention as claimed, and it should be noted that not all of the combinations of features described in the embodiments are necessarily essential to the means for solving the problems of the invention. [Explanation of symbols]

[0111] 1...field effect transistor, 10...first semiconductor layer, 11...second semiconductor layer, 111...n-type region, 112...p-type region, 113...second n-type region, 114...second p-type region, 12a...first trench, 12b...second trench, 13a...first p-type semiconductor portion, 13b...second p-type semiconductor portion, 14...third trench, 15...gate insulating film, 16...gate electrode, 17...source electrode, 18...drain electrode, 22...intermediate semiconductor layer, 221...non-oxide layer, 222...oxide layer

Claims

1. an n-type first semiconductor layer made of a gallium oxide-based semiconductor; a second semiconductor layer made of Si provided on the first semiconductor layer via an n-type intermediate semiconductor layer; first and second p-type semiconductor portions buried in first and second trenches, respectively, extending from an upper surface of the second semiconductor layer to the first semiconductor layer; a gate electrode covered with a gate insulating film and embedded in a third trench extending from an upper surface of the second semiconductor layer to the first semiconductor layer, the third trench having one side surface and a part of a bottom surface formed by the first p-type semiconductor portion; an n-type region provided in at least a part of the surface layer of an inter-trench region between the second trench and the third trench of the second semiconductor layer, the n-type region being on the third trench side; a p-type region provided in a region between the first semiconductor layer and the n-type region in the inter-trench region so as to isolate the first semiconductor layer from the n-type region; a source electrode connected to the n-type region; a drain electrode connected to the first semiconductor layer; Equipped with the intermediate semiconductor layer is made of an n-type non-oxide that can maintain n-type when oxidized, or n-type SiC; When the intermediate semiconductor layer is made of the n-type non-oxide, a part of or the whole of the first semiconductor layer side is oxidized or not oxidized, and when the intermediate semiconductor layer is made of n-type SiC, it is not oxidized. Field effect transistor.

2. a second n-type region is provided in a region between the intermediate semiconductor layer and the p-type region in the inter-trench region; 2. The field effect transistor of claim 1.

3. a second p-type region is provided in a surface layer of the inter-trench region, in a region between the n-type region and the second trench; 2. The field effect transistor of claim 1.

4. the p-type semiconductor portion is made of a p-type oxide semiconductor; The field effect transistor according to any one of claims 1 to 3.

5. The p-type oxide semiconductor is p-type NiO, CuO, or Cu. ２ It is O.

5. The field effect transistor of claim 4.

6. the intermediate semiconductor layer is made of the n-type non-oxide; the non-oxide is one or more mixed crystals selected from the group consisting of GaN, GaP, GaAs, GaSb, and GaBi, one or more mixed crystals selected from the group consisting of InN, InP, InAs, InSb, and InBi, one or more mixed crystals selected from the group consisting of ZnS, ZnSe, and ZnTe, one or more mixed crystals selected from the group consisting of CdS, CdSe, and CdTe, or Ge; The field effect transistor according to any one of claims 1 to 3.

7. The non-oxide is GaP, GaAs, or a mixed crystal thereof.

7. The field effect transistor of claim 6.

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