Semiconductor device and manufacturing method thereof

Abstract

To form a suitable interlayer insulation layer in a semiconductor device having a switching element and a temperature sense diode.SOLUTION: A semiconductor device has an element region and a sense region. A gate type switching element in the element region has plural gate trenches, a gate electrode, and an interlayer insulation layer covering a top face of the gate electrode. A temperature sense diode in the sense region has an anode region, a cathode region, plural first dummy trenches provided in the anode region, a first insulation layer arranged in each of the first dummy trenches, plural second dummy trenches provided in the cathode region, and a second insulation layer arranged in each of the second dummy trenches.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

[0002] Patent Document 1 discloses a trench-type switching element. A gate electrode and an interlayer insulating layer are disposed within a gate trench. The interlayer insulating layer covers the upper surface of the gate electrode. The interlayer insulating layer is disposed within a range below the upper end of the gate trench. That is, the interlayer insulating layer does not cover the upper surface of a semiconductor substrate. The upper surface of the semiconductor substrate is covered by a source electrode. The interlayer insulating layer insulates the source electrode from the gate electrode. In a manufacturing process for this switching element, after forming a gate electrode within the gate trench, an insulating layer is formed on the upper surface of the semiconductor substrate. Next, the insulating layer is etched to expose the upper surface of the semiconductor substrate. At this time, the insulating layer is left within the gate trench. The insulating layer remaining within the gate trench serves as the interlayer insulating layer. According to this manufacturing method, the interlayer insulating layer is formed within the gate trench in a self-aligned manner, eliminating the need to control the formation position of the interlayer insulating layer. This allows for narrower gate trench spacing and higher integration of switching elements. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-209807 Summary of the Invention [Problem to be solved by the invention]

[0004] A temperature sensing diode may be formed on the same semiconductor substrate as the switching element. The temperature sensing diode can detect the temperature of the switching element. Hereinafter, the region of the semiconductor substrate corresponding to the switching element may be referred to as the element region, and the region corresponding to the temperature sensing diode may be referred to as the temperature sensing region. In the manufacturing process of a semiconductor device having a switching element and a temperature sensing diode, an insulating layer is formed on the upper surface of the semiconductor substrate, resulting in a thicker insulating layer in the temperature sensing region than in the element region. The insulating layer is then etched to form contact holes in the element region and the temperature sensing region. In the element region, the contact holes are formed so that the insulating layer (i.e., the interlayer insulating layer) remains in the gate trench. When the contact holes are formed in this manner, the insulating layer in the temperature sensing region is thick, which may prevent the upper surface of the semiconductor substrate from being exposed in the contact hole formed in the temperature sensing region. In this case, an electrode contacting the temperature sensing region cannot be properly formed. Furthermore, if the etching time of the insulating layer is prolonged, the upper surface of the semiconductor substrate can be exposed from the insulating layer in the temperature sensing region, but the thickness of the interlayer insulating layer remaining in the gate trench in the element region becomes thinner. This reduces the dielectric strength of the interlayer insulating layer. For this reason, it is difficult to form an interlayer insulating layer in a self-aligned manner in a semiconductor device having a switching element and a temperature sensing diode. This specification proposes a technique for suitably forming an interlayer insulating layer in a semiconductor device having a switching element and a temperature sensing diode. [Means for solving the problem]

[0005] The semiconductor device disclosed in this specification includes a semiconductor substrate having an element region where a gate-type switching element is provided and a temperature sense region where a temperature sense diode is provided. The gate-type switching element includes a plurality of gate trenches provided on the upper surface of the semiconductor substrate, a gate electrode disposed in each of the gate trenches, and an interlayer insulating layer disposed in each of the gate trenches below the upper end of each gate trench and covering the upper surface of the gate electrode. The temperature sense diode includes a p-type anode region, an n-type cathode region in contact with the anode region, a plurality of first dummy trenches provided on the upper surface of the semiconductor substrate in the anode region, a first insulating layer disposed in each of the first dummy trenches below the upper end of each first dummy trench, a plurality of second dummy trenches provided on the upper surface of the semiconductor substrate in the cathode region, and a second insulating layer disposed in each of the second dummy trenches below the upper end of each second dummy trench. The semiconductor device further includes a surface insulating layer covering the upper surface of the semiconductor substrate, a source contact hole provided in the surface insulating layer and arranged above the element region, a source electrode arranged in the source contact hole and in contact with the interlayer insulating layer in each of the gate trenches and the upper surface of the semiconductor substrate, an anode contact hole provided in the surface insulating layer and arranged above the anode region, an anode electrode arranged in the anode contact hole and in contact with the first insulating layer in each of the first dummy trenches and the anode region, a cathode contact hole provided in the surface insulating layer and arranged above the cathode region, and a cathode electrode arranged in the cathode contact hole and in contact with the second insulating layer in each of the second dummy trenches and the cathode region.

[0006] It has been found that when an insulating layer is formed on the upper surface of a semiconductor substrate, the thickness of the insulating layer varies due to the influence of trenches. That is, in regions where trenches are provided on the upper surface of the semiconductor substrate, the insulating layer is formed not only on the upper surface of the semiconductor substrate but also within the trenches, resulting in a thinner insulating layer on the upper surface of the semiconductor substrate. In contrast, in regions where no trenches are provided on the upper surface of the semiconductor substrate, the insulating layer is thicker on the upper surface of the semiconductor substrate than in regions where trenches are provided. In the semiconductor device disclosed in this specification, a gate trench is provided in the element region, while a first dummy trench and a second dummy trench are provided in the temperature sensing region. Therefore, when forming the insulating layer in the element region and the temperature sensing region, differences in the thickness of the insulating layer can be suppressed. Therefore, the interlayer insulating layer can be formed effectively in the manufacturing process of this semiconductor device.

[0007] This specification proposes a manufacturing method for a semiconductor device having a gated switching element and a temperature sensing diode. The manufacturing method includes a semiconductor substrate processing step, an insulating layer forming step, a contact hole forming step, and an electrode forming step. The semiconductor substrate processing step includes: forming a plurality of gate trenches for the gated switching element in the upper surface of the semiconductor substrate; forming a gate electrode in each of the gate trenches below the upper end of each gate trench; forming a p-type anode region and an n-type cathode region for the temperature sensing diode in the semiconductor substrate; forming a plurality of first dummy trenches in the upper surface of the semiconductor substrate within the anode region; and forming a plurality of second dummy trenches in the upper surface of the semiconductor substrate within the cathode region. The insulating layer forming step forms an insulating layer covering the upper surface of the semiconductor substrate so that the gate trenches, the first dummy trenches, and the second dummy trenches are filled with the insulating layer.The contact hole forming step is a step of forming a source contact hole, an anode contact hole, and a cathode contact hole in the insulating layer by etching, and the contact holes are formed in the insulating layer under the following conditions: a plurality of the gate trenches are disposed in the source contact hole; the upper surface of the semiconductor substrate is exposed in the source contact hole; the insulating layer remains in the gate trenches in the source contact hole and below the upper end of each gate trench, covering the upper surface of the gate electrode; a plurality of the first dummy trenches are disposed in the anode contact hole; the upper surface of the semiconductor substrate is exposed in the source contact hole, the anode contact hole, and the cathode contact hole so as to satisfy the following conditions: the upper surface of the semiconductor substrate is exposed in the cathode contact hole; the insulating layer remains in each of the first dummy trenches in the anode contact hole, within a range below the upper ends of the first dummy trenches; a plurality of second dummy trenches are arranged in the cathode contact hole; the upper surface of the semiconductor substrate is exposed in the cathode contact hole; and the insulating layer remains in each of the second dummy trenches in the cathode contact hole, within a range below the upper ends of the second dummy trenches. The electrode formation process includes forming a source electrode in the source contact hole in contact with the insulating layer in each of the gate trenches and the upper surface of the semiconductor substrate, forming an anode electrode in the anode contact hole in contact with the insulating layer in each of the first dummy trenches and the anode region, and forming a cathode electrode in the cathode contact hole in contact with the insulating layer in each of the second dummy trenches and the cathode region.

[0008] The steps in the semiconductor substrate processing step may be performed in any order. Two or more of the steps in the semiconductor substrate processing step may be performed simultaneously. In the contact hole forming step, the source contact hole, the anode contact hole, and the cathode contact hole may be formed simultaneously or separately. In the electrode forming step, the source electrode, the anode electrode, and the cathode electrode may be formed simultaneously or separately.

[0009] In this manufacturing method, the insulating layer is formed in the state where the gate trench, the first dummy trench, and the second dummy trench are present on the upper surface of the semiconductor substrate, so that it is possible to prevent a difference in the thickness of the insulating layer when the insulating layer is formed in the element region and the temperature sensing region. Therefore, this manufacturing method makes it possible to preferably form the interlayer insulating layer. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. [Figure 2] FIG. [Figure 3] 2 is a cross-sectional view of the temperature sensing area (cross-sectional view taken along line DD in FIG. 2). [Figure 4] 1 and 2 are cross-sectional views of the element region, anode region, and cathode region (cross-sectional views taken along lines AA, BB, and CC in FIGS. 1 and 2). [Figure 5] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 6] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 7] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 8] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 9] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 10] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 11] 1A to 1C are explanatory diagrams of a method for manufacturing a semiconductor device. [Figure 12]FIG. [Figure 13] FIG. [Figure 14] FIG. 10 is an enlarged plan view of a temperature sensing region of a first modified example. [Figure 15] FIG. 10 is an enlarged plan view of a temperature sensing region of a second modified example. [Figure 16] FIG. 11 is an enlarged plan view of a temperature sensing region of a third modified example. DETAILED DESCRIPTION OF THE INVENTION

[0011] In the exemplary manufacturing method disclosed herein, the width of the first dummy trench and the width of the second dummy trench may be equal to the width of the gate trench. Also, the pitch of the first dummy trench and the pitch of the second dummy trench may be equal to the pitch of the gate trench.

[0012] Note that "equal" above means that the difference between the two target values ​​is less than or equal to the manufacturing tolerance.

[0013] This configuration can more effectively prevent the difference in thickness of the insulating layer between the element region and the temperature sensing region.

[0014] In one example of the manufacturing method disclosed in this specification, the gate trench, the first dummy trench, and the second dummy trench may be formed simultaneously.

[0015] In one example of the manufacturing method disclosed in the present specification, the semiconductor substrate processing step may further include the steps of: forming a first dummy electrode in each of the first dummy trenches within a range below an upper end of each of the first dummy trenches; and forming a second dummy electrode in each of the second dummy trenches within a range below an upper end of each of the second dummy trenches. The gate electrode, the first dummy electrode, and the second dummy electrode may be formed simultaneously.

[0016] The semiconductor device 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12. When viewed from above, the semiconductor substrate 12 has an element region 20 and a temperature sensing region 40. A gate-type switching element is provided in the element region 20. A temperature sensing diode is provided in the temperature sensing region 40. As shown in FIGS. 1 and 2, the temperature sensing diode has a p-type anode region 50 and an n-type cathode region 60. As shown in FIG. 3, the anode region 50 and the cathode region 60 are arranged inside the semiconductor substrate 12 in a range that includes the upper surface 12a of the semiconductor substrate 12. The anode region 50 and the cathode region 60 are in contact with each other.

[0017] FIG. 4 shows cross sections of a semiconductor device in the element region 20, the anode region 50, and the cathode region 60. In FIGS. 4 to 11, the left diagram shows a cross section taken along line AA in FIG. 1, the center diagram shows a cross section taken along line BB in FIG. 2, and the right diagram shows a cross section taken along line CC in FIG. 2. As shown in FIG. 4, a surface insulating layer 14 is provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIGS. 1 and 2, a source contact hole 26, an anode contact hole 56, and a cathode contact hole 66 are provided in the surface insulating layer 14. The source contact hole 26 is located above the element region 20. The anode contact hole 56 is located above the anode region 50. The cathode contact hole 66 is located above the cathode region 60.

[0018] A source electrode 28 is provided in the source contact hole 26. The source electrode 28 is in contact with the upper surface 12a of the semiconductor substrate 12 within the source contact hole 26. An anode electrode 58 is provided in the anode contact hole 56. The anode electrode 58 is in contact with the upper surface 12a of the semiconductor substrate 12 (i.e., the anode region 50) within the anode contact hole 56. A cathode electrode 68 is provided in the cathode contact hole 66. The cathode electrode 68 is in contact with the upper surface 12a of the semiconductor substrate 12 (i.e., the cathode region 60) within the cathode contact hole 66. A drain electrode 16 is provided on the lower surface 12b of the semiconductor substrate 12. The drain electrode 16 is in contact with substantially the entire lower surface 12b.

[0019] A plurality of gate trenches 22 are provided in the upper surface 12a of the semiconductor substrate 12 in the element region 20. The plurality of gate trenches 22 are arranged in a source contact hole 26. The plurality of gate trenches 22 extend parallel to one another on the upper surface 12a. The inner surface of each gate trench 22 is covered with a gate insulating film 23. A gate electrode 24 is arranged in each gate trench 22. The gate electrode 24 is insulated from the semiconductor substrate 12 by the gate insulating film 23. An interlayer insulating layer 25 is arranged in the gate trench 22 and above the gate electrode 24. The interlayer insulating layer 25 covers the upper surface of the gate electrode 24. The interlayer insulating layer 25 is arranged in a range below the upper end of the gate trench 22. Therefore, the interlayer insulating layer 25 does not contact the upper surface 12a of the semiconductor substrate 12. A source electrode 28 contacts the upper surface of the interlayer insulating layer 25. The interlayer insulating layer 25 insulates the gate electrode 24 from the source electrode 28.

[0020] A source region 30, a contact region 32, and a body region 34 are provided inside the semiconductor substrate 12 within the element region 20. The source region 30 is an n-type region with a high concentration of n-type impurities. The contact region 32 is a p-type region with a high concentration of p-type impurities. The source region 30 and the contact region 32 are arranged in a range including the upper surface 12a of the semiconductor substrate 12. The source region 30 and the contact region 32 are in contact with the source electrode 28. The source region 30 and the contact region 32 are arranged in a range sandwiched between two gate trenches 22 (hereinafter referred to as the inter-trench range). In each inter-trench range, the source regions 30 and the contact regions 32 are alternately provided along a direction parallel to the gate trenches 22. The source region 30 and the contact region 32 are in contact with the gate insulating film 23 on the side surface of the gate trench 22. The source region 30 has approximately the same thickness as the cathode region 60. The contact region 32 has approximately the same thickness as the anode region 50. The body region 34 is a p-type region having a lower p-type impurity concentration than the contact region 32. The body region 34 contacts the source region 30 and the contact region 32 from below. The body region 34 contacts the gate insulating film 23 below the source region 30 and the contact region 32.

[0021] A drift region 36 is provided below the body region 34. The drift region 36 is an n-type region having a lower n-type impurity concentration than the source region 30. The drift region 36 contacts the body region 34 from below. The drift region 36 contacts the gate insulating film 23 below the body region 34. The drift region 36 is distributed across the element region 20 and the temperature sensing region 40. The drift region 36 contacts the anode region 50 and the cathode region 60 from below within the temperature sensing region 40.

[0022] A drain region 38 is provided below the drift region 36. The drain region 38 is an n-type region with a higher n-type impurity concentration than the drift region 36. The drain region 38 is distributed across the element region 20 and the temperature sensing region 40. The drain region 38 contacts the drift region 36 from below within the element region 20 and the temperature sensing region 40. The drain region 38 contacts the drain electrode 16 within the element region 20 and the temperature sensing region 40.

[0023] As shown in FIGS. 2 and 4 , a plurality of dummy trenches 52 are provided in the upper surface 12a of the semiconductor substrate 12 in the anode region 50. The dummy trenches 52 extend parallel to one another. The plurality of dummy trenches 52 are disposed within the anode contact hole 56. Each dummy trench 52 has approximately the same depth as the gate trench 22. Each dummy trench 52 extends from the upper surface 12a through the anode region 50 to the drift region 36. The width of the dummy trench 52 is equal to the width of the gate trench 22. The pitch of the dummy trenches 52 (i.e., the distance between the center lines of two trenches) is equal to the pitch of the gate trenches 22.

[0024] The inner surface of the dummy trench 52 is covered with an insulating film 53. A dummy electrode 54 is disposed in the dummy trench 52. The dummy electrode 54 is insulated from the semiconductor substrate 12 by the insulating film 53. An insulating layer 55 is disposed in the dummy trench 52 above the dummy electrode 54. The insulating layer 55 covers the upper surface of the dummy electrode 54. The insulating layer 55 is disposed within a range below the upper end of the dummy trench 52. Therefore, the insulating layer 55 does not contact the upper surface 12a of the semiconductor substrate 12.

[0025] As shown in FIGS. 2 and 4 , a plurality of dummy trenches 62 are provided in the upper surface 12a of the semiconductor substrate 12 in the cathode region 60. The dummy trenches 62 extend parallel to one another. The plurality of dummy trenches 62 are disposed within the cathode contact holes 66. Each dummy trench 62 has approximately the same depth as the gate trenches 22. Each dummy trench 62 extends from the upper surface 12a through the cathode region 60 to the drift region 36. The width of the dummy trenches 62 is equal to the width of the gate trenches 22. The pitch of the dummy trenches 62 is equal to the pitch of the gate trenches 22.

[0026] The inner surface of the dummy trench 62 is covered with an insulating film 63. A dummy electrode 64 is disposed in the dummy trench 62. The dummy electrode 64 is insulated from the semiconductor substrate 12 by the insulating film 63. An insulating layer 65 is disposed in the dummy trench 62 above the dummy electrode 64. The insulating layer 65 covers the upper surface of the dummy electrode 64. The insulating layer 65 is disposed within a range below the upper end of the dummy trench 62. Therefore, the insulating layer 65 does not contact the upper surface 12a of the semiconductor substrate 12.

[0027] Within the element region 20, a MOSFET (metal-oxide-semiconductor field effect transistor) is formed by a source region 30, a contact region 32, a body region 34, a drift region 36, a drain region 38, a gate electrode 24, a source electrode 28, a drain electrode 16, etc. Within the temperature sensing region 40, a pn diode is formed by an anode region 50, a cathode region 60, an anode electrode 58, and a cathode electrode 68. The forward voltage drop of the pn diode changes depending on the temperature of the semiconductor substrate 12. Therefore, the temperature of the semiconductor substrate 12 can be detected using the pn diode. Because the temperature sensing region 40 is disposed adjacent to the element region 20, the temperature of the MOSFET can be detected by the pn diode.

[0028] Next, a method for manufacturing the semiconductor device 10 will be described. Figure 5 shows the semiconductor substrate 12 before processing. The semiconductor substrate 12 before processing has a drain region 38 and a drift region 36. The method for manufacturing the semiconductor device 10 includes a semiconductor substrate processing step, an insulating layer forming step, a contact hole forming step, and an electrode forming step.

[0029] (Semiconductor substrate processing process) First, as shown in FIG. 6 , a body region 34 is formed in the element region 20 by selectively implanting p-type impurities into the upper surface 12a of the semiconductor substrate 12. Next, a contact region 32 and an anode region 50 are formed by selectively implanting p-type impurities into the upper surface 12a of the semiconductor substrate 12. That is, the contact region 32 and the anode region 50 are formed simultaneously. Note that in other embodiments, the contact region 32 and the anode region 50 may be formed in separate steps. Next, a source region 30 and a cathode region 60 are formed by selectively implanting n-type impurities into the upper surface 12a of the semiconductor substrate 12. That is, the source region 30 and the cathode region 60 are formed simultaneously. Note that in other embodiments, the source region 30 and the cathode region 60 may be formed in separate steps.

[0030] 7, the upper surface 12a of the semiconductor substrate 12 is selectively etched to form a gate trench 22, a dummy trench 52, and a dummy trench 62 in the upper surface 12a. The gate trench 22 is formed to penetrate the body region 34 and reach the drift region 36. The dummy trench 52 is formed to penetrate the anode region 50 and reach the drift region 36. The dummy trench 62 is formed to penetrate the cathode region 60 and reach the drift region 36.

[0031] Next, as shown in FIG. 8 , a thin insulating film is formed by thermal oxidation to cover the inner surfaces of the gate trench 22, the dummy trench 52, and the dummy trench 62. The insulating film in the gate trench 22 is the gate insulating film 23, the insulating film in the dummy trench 52 is the insulating film 53, and the insulating film in the dummy trench 62 is the insulating film 63. A thin insulating film is also formed on the upper surface 12a of the semiconductor substrate 12. Next, a gate electrode 24, a dummy electrode 54, and a dummy electrode 64 are formed in the gate trench 22, the dummy trench 52, and the dummy trench 62. More specifically, first, a polysilicon layer is formed on the semiconductor substrate 12 so as to fill the gate trench 22, the dummy trench 52, and the dummy trench 62. Next, the polysilicon layer is etched to remove the polysilicon layer on the upper surface 12a and in the upper parts of each trench. The polysilicon layer is left in the lower parts of each trench. The polysilicon layer remaining in the gate trench 22 becomes the gate electrode 24 , the polysilicon layer remaining in the dummy trench 52 becomes the dummy electrode 54 , and the polysilicon layer remaining in the dummy trench 62 becomes the dummy electrode 64 .

[0032] (Insulating layer formation process) Next, as shown in FIG. 9, a thick insulating layer 14a is formed on the semiconductor substrate 12 by CVD (chemical vapor deposition). The portion of the insulating layer 14a that covers the upper surface 12a is the surface insulating layer 14. The gate trench 22, the dummy trench 52, and the dummy trench 62 are filled with the insulating layer 14a. In the gate trench 22, the insulating layer 14a covers the upper surface of the gate electrode 24. In the dummy trench 52, the insulating layer 14a covers the upper surface of the dummy electrode 54. In the dummy trench 62, the insulating layer 14a covers the upper surface of the dummy electrode 64.

[0033] (Contact hole formation process) Next, as shown in FIG. 10 , a mask layer 70 is formed on the insulating layer 14a, and the insulating layer 14a is partially etched through the mask layer 70. This forms contact holes 26, 56, and 66 in the insulating layer 14a. In the source contact hole 26, the insulating layer 14a on the upper surface 12a is removed to expose the upper surface 12a. A plurality of gate trenches 22 are also disposed in the source contact hole 26. In the source contact hole 26, the insulating layer 14a is left in the gate trench 22 so that the upper end of the insulating layer 14a remaining in the gate trench 22 is located below the upper end of the gate trench 22 (i.e., the upper surface 12a). The insulating layer 14a remaining in the gate trench 22 covers the upper surface of the gate electrode 24. The insulating layer 14a remaining in the gate trench 22 becomes the interlayer insulating layer 25. In the anode contact hole 56, the insulating layer 14a on the upper surface 12a is removed to expose the upper surface 12a. A plurality of dummy trenches 52 are arranged in the anode contact hole 56. In the anode contact hole 56, the insulating layer 14a is left in the dummy trench 52 so that the upper ends of the insulating layer 14a remaining in the dummy trench 52 are located within a range below the upper ends of the dummy trenches 52 (i.e., the upper surfaces 12a). The insulating layer 14a remaining in the dummy trench 52 becomes the insulating layer 55. In the cathode contact hole 66, the insulating layer 14a on the upper surface 12a is removed to expose the upper surface 12a. A plurality of dummy trenches 62 are arranged in the cathode contact hole 66. In the cathode contact hole 66, the insulating layer 14a is left in the dummy trench 62 so that the upper ends of the insulating layer 14a remaining in the dummy trench 62 are located within a range below the upper ends of the dummy trenches 62 (i.e., the upper surfaces 12a). The insulating layer 14 a remaining in the dummy trenches 62 becomes the insulating layer 65 .

[0034] (Electrode formation process) Next, as shown in FIG. 11 , a source electrode 28, an anode electrode 58, and a cathode electrode 68 are formed. More specifically, first, a metal layer is formed on the surface insulating layer 14 so as to fill the contact holes 26, 56, and 66. Next, the metal layer on the surface insulating layer 14 is etched to separate the metal layer in the source contact hole 26, the metal layer in the anode contact hole 56, and the metal layer in the cathode contact hole 66 from one another. The metal layer in the source contact hole 26 becomes the source electrode 28, the metal layer in the anode contact hole 56 becomes the anode electrode 58, and the metal layer in the cathode contact hole 66 becomes the cathode electrode 68. The source electrode 28 is in contact with each interlayer insulating layer 25 and the upper surface 12a of the semiconductor substrate 12. The anode electrode 58 is in contact with each insulating layer 55 and the anode region 50. The cathode electrode 68 is in contact with each insulating layer 65 and the cathode region 60.

[0035] Next, a drain electrode 16 is formed on the lower surface 12b of the semiconductor substrate 12. This completes the semiconductor device 10 shown in FIGS.

[0036] 12 and 13 show, as a comparative example, the manufacturing process of a semiconductor device in which dummy trenches 52 and 62 are not present in the temperature sensing region 40. During the process of forming the insulating layer 14a, the growth rate of the insulating layer 14a on the upper surface 12a is slower near the trenches than in areas where no trenches are present. This is thought to be because the CVD source gas is consumed by the growth of the insulating layer 14a in the trenches, making it difficult for the insulating layer 14a to grow on the upper surface 12a near the trenches. In FIG. 12, since no dummy trenches are present in the temperature sensing region 40, the thickness T2 of the insulating layer 14a on the upper surface 12a in the temperature sensing region 40 is thicker than the thickness T1 of the insulating layer 14a on the upper surface 12a in the device region 20. Therefore, when the contact holes 26, 56, and 66 are subsequently formed, a thin insulating layer 14a may remain on the upper surface 12a within the contact holes 56 and 66, preventing the upper surface 12a from being exposed, as shown in FIG. 13. In this case, when forming electrodes thereafter, the anode electrode 58 cannot be brought into contact with the anode region 50 with low resistance, and the cathode electrode 68 cannot be brought into contact with the cathode region 60 with low resistance. Furthermore, although the upper surface 12 a can be exposed in the contact holes 56, 66 by lengthening the etching time, in that case the interlayer insulating layer 25 becomes thinner in the element region 20, which causes a problem of a decrease in the breakdown voltage of the interlayer insulating layer 25.

[0037] In contrast, in the manufacturing method of this embodiment, since the dummy trenches 52, 62 are present in the temperature sensing region 40, the thickness T2 of the insulating layer 14a in the temperature sensing region 40 is substantially equal to the thickness T1 of the insulating layer 14a in the element region 20, as shown in FIG. 9. Therefore, when the upper surface 12a is exposed in the contact holes 26, 56, 66, as shown in FIG. 10, an appropriate thickness of the interlayer insulating layer 25 can be left in the gate trench 22. Therefore, according to this manufacturing method, the anode electrode 58 and the cathode electrode 68 can be brought into contact with the anode region 50 and the cathode region 60 with low resistance while ensuring the withstand voltage of the interlayer insulating layer 25.

[0038] In the above-described embodiment, the width of the dummy trenches is equal to the width of the gate trenches, and the pitch of the dummy trenches is equal to the pitch of the gate trenches. However, the width of the dummy trenches may be different from the width of the gate trenches, and the pitch of the dummy trenches may be different from the pitch of the gate trenches. Also, in the above-described embodiment, the depth of the dummy trenches is equal to the depth of the gate trenches, but the depth of the dummy trenches may be different from the depth of the gate trenches. Thus, even if the dimensions and pitch of the dummy trenches and the gate trenches are different, providing a dummy trench in the temperature sensing region can prevent the insulating layer 14a from becoming thick on the upper surface 12a in the temperature sensing region 40. However, if the shape and pitch of the gate trenches are equal to the shape and pitch of the dummy trenches, the difference in thickness of the insulating layer between the element region and the temperature sensing region can be reduced.

[0039] Furthermore, in the above-described embodiment, the gate trenches are formed simultaneously with the dummy trenches, but the gate trenches and the dummy trenches may be formed in separate steps.

[0040] In the above-described embodiment, a dummy electrode is formed in the dummy trench, but it is not necessary to form a dummy electrode in the dummy trench. For example, the entire dummy trench may be filled with the insulating layer 14a without forming a dummy electrode. Even with this configuration, it is possible to prevent the insulating layer 14a from becoming thick on the upper surface 12a in the temperature sensing region 40.

[0041] 14, the dummy trenches 52 and 62 may extend in a direction different from that shown in FIG. 2. As shown in FIG. 15, the dummy trench 52 may extend to the outside of the anode contact hole 56, and the dummy trench 62 may extend to the outside of the cathode contact hole 66. As shown in FIG. 16, the dummy trenches 52 and 62 may be connected to each other.

[0042] The dummy trench 52 is an example of a first dummy trench. The insulating layer 55 is an example of a first insulating layer. The dummy trench 62 is an example of a second dummy trench. The insulating layer 65 is an example of a second insulating layer.

[0043] Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples exemplified above. The technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings simultaneously achieves multiple objectives, and achieving one of these objectives itself has technical utility. [Explanation of symbols]

[0044] 14: surface insulating layer, 20: element region, 22: gate trench, 24: gate electrode, 25: interlayer insulating layer, 26: source contact hole, 28: source electrode, 50: anode region, 52: dummy trench, 55: insulating layer, 56: anode contact hole, 58: anode electrode, 60: cathode region, 62: dummy trench, 65: insulating layer, 66: cathode contact hole, 68: cathode electrode

Claims

1. A semiconductor device, The semiconductor substrate has an element region (20) in which a gate-type switching element is provided and a temperature sensing region (40) in which a temperature sensing diode is provided, The gate-type switching element is a plurality of gate trenches (22) provided on the upper surface of the semiconductor substrate; a gate electrode (24) disposed within each of the gate trenches; an interlayer insulating layer (25) disposed within each of the gate trenches in a range below the upper end of each of the gate trenches and covering the upper surface of the gate electrode; and The temperature sensing diode a p-type anode region (50); an n-type cathode region (60) in contact with the anode region; a plurality of first dummy trenches (52) disposed in the top surface of the semiconductor substrate within the anode region; a first insulating layer (55) disposed within each of the first dummy trenches and below the upper end of each of the first dummy trenches; a plurality of second dummy trenches (62) disposed on the top surface of the semiconductor substrate within the cathode region; a second insulating layer (65) disposed within each of the second dummy trenches in a range below the upper end of each of the second dummy trenches; and a surface insulating layer (14) covering the top surface of the semiconductor substrate; a source contact hole (26) provided in the surface insulating layer and arranged above the element region; a source electrode (28) disposed in the source contact hole and in contact with the interlayer insulating layer in each of the gate trenches and the upper surface of the semiconductor substrate; an anode contact hole (56) provided in the surface insulating layer and located above the anode region; an anode electrode (58) disposed in the anode contact hole and in contact with the first insulating layer and the anode region in each of the first dummy trenches; a cathode contact hole (66) provided in the surface insulating layer and disposed above the cathode region; a cathode electrode (68) disposed in the cathode contact hole and in contact with the second insulating layer and the cathode region in each of the second dummy trenches; further comprising Semiconductor device.

2. A method of manufacturing a semiconductor device having a gate-type switching element and a temperature sensing diode, comprising: The method includes a semiconductor substrate processing step, an insulating layer forming step, a contact hole forming step, and an electrode forming step, The semiconductor substrate processing step includes: a step of forming a plurality of gate trenches in the upper surface of a semiconductor substrate, the gated switching elements having the gate trenches; forming a gate electrode within each of the gate trenches below the upper end of each of the gate trenches; forming a p-type anode region and an n-type cathode region of the temperature sensing diode in the semiconductor substrate; forming a plurality of first dummy trenches in the top surface of the semiconductor substrate within the anode region; forming a plurality of second dummy trenches in the top surface of the semiconductor substrate within the cathode region; and In the insulating layer forming step, an insulating layer covering the upper surface of the semiconductor substrate is formed such that the gate trench, the first dummy trench, and the second dummy trench are filled with the insulating layer; The contact hole forming step is a step of forming a source contact hole, an anode contact hole, and a cathode contact hole in the insulating layer by etching, and is performed under the following conditions: A plurality of the gate trenches are disposed within the source contact hole; The top surface of the semiconductor substrate is exposed in the source contact hole. the insulating layer remains in the gate trenches in the source contact holes and below the upper ends of the gate trenches, covering the upper surfaces of the gate electrodes; A plurality of the first dummy trenches are disposed within the anode contact hole. The upper surface of the semiconductor substrate is exposed in the anode contact hole. the insulating layer remains in the first dummy trenches in the anode contact hole and in a range below the upper end of each of the first dummy trenches; A plurality of the second dummy trenches are disposed within the cathode contact hole. The upper surface of the semiconductor substrate is exposed in the cathode contact hole. the insulating layer remains in the second dummy trenches in the cathode contact hole and in a range below the upper end of each of the second dummy trenches; forming the source contact hole, the anode contact hole, and the cathode contact hole so as to satisfy the condition: The electrode forming step includes forming a source electrode in the source contact hole in contact with the insulating layer in each of the gate trenches and the upper surface of the semiconductor substrate, forming an anode electrode in the anode contact hole in contact with the insulating layer in each of the first dummy trenches and the anode region, and forming a cathode electrode in the cathode contact hole in contact with the insulating layer in each of the second dummy trenches and the cathode region. Manufacturing method.

3. a width of the first dummy trench and a width of the second dummy trench are equal to a width of the gate trench; a pitch of the first dummy trench and a pitch of the second dummy trench are equal to a pitch of the gate trench; The method of claim 2.

4. 4. The manufacturing method according to claim 2, wherein the gate trench, the first dummy trench, and the second dummy trench are formed simultaneously.

5. The semiconductor substrate processing step includes: forming a first dummy electrode within each of the first dummy trenches and below the upper end of each of the first dummy trenches; forming a second dummy electrode within each of the second dummy trenches and below an upper end of each of the second dummy trenches; and the gate electrode, the first dummy electrode, and the second dummy electrode are simultaneously formed; The method according to claim 2 or 3.

Images