Semiconductor device and manufacturing method thereof

Abstract

To provide a semiconductor device capable of reducing a contact resistance with a metal electrode.SOLUTION: A semiconductor device includes: a semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer: a first electrode electrically connected to the first semiconductor layer on a front surface side or a back surface side of the semiconductor part; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor part; a gate electrode facing the second semiconductor layer, in the semiconductor part or on the front surface side of the semiconductor part; an interlayer insulating film electrically insulating the gate electrode and the second electrode from each other on the front surface side of the semiconductor part; and a third semiconductor layer of the first conductivity type including a first region in contact with the second semiconductor layer and the second electrode on the front surface side of the semiconductor part, and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction that is toward the second electrode from the first semiconductor layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] In power semiconductor devices, such as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), metal electrodes often form contacts that come into contact with both n-type and p-type semiconductors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-27229 Summary of the Invention [Problem to be solved by the invention]

[0004] An embodiment of the present invention provides a semiconductor device capable of reducing contact resistance with a metal electrode and a method for manufacturing the same. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment comprises: a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on the front or back side of the semiconductor portion; a second electrode electrically connected to the second semiconductor layer on the front side of the semiconductor portion; a gate electrode facing the second semiconductor layer within the semiconductor portion or on the front side of the semiconductor portion; an interlayer insulating film electrically insulating the gate electrode and the second electrode on the front side of the semiconductor portion; a first region in contact with the second semiconductor layer and the second electrode on the front side of the semiconductor portion; and a third semiconductor layer of a first conductivity type having a first region in contact with the second semiconductor layer and the second electrode on the front side of the semiconductor portion; [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view showing a schematic structure of a semiconductor device according to a first embodiment. [Figure 2A] 10A to 10C are cross-sectional views showing a step of forming a first contact hole. [Figure 2B] FIG. 2 is a cross-sectional view showing the epitaxial growth step of the first region. [Figure 2C] 1A to 1C are cross-sectional views showing a process of forming an insulating film. [Figure 2D] 10A to 10C are cross-sectional views showing an etching step of an insulating film. [Figure 2E] 10A to 10C are cross-sectional views showing a step of forming a second contact hole. [Figure 2F] 10A to 10C are cross-sectional views showing a step of forming a p-type contact layer. [Figure 2G] 10A to 10C are cross-sectional views showing a step of forming a source electrode. [Figure 3] FIG. 10 is a cross-sectional view showing the structure of a semiconductor device according to a comparative example. [Figure 4] FIG. 10 is a cross-sectional view showing a schematic structure of a semiconductor device according to a second embodiment. [Figure 5A] 1A to 1C are cross-sectional views showing a process of forming a conductive film. [Figure 5B] 10A to 10C are cross-sectional views showing a step of forming a second contact hole. [Figure 6] FIG. 10 is a cross-sectional view showing a schematic structure of a semiconductor device according to a third embodiment. [Figure 7A] 1A to 1C are cross-sectional views showing a process for forming a heavy metal film. [Figure 7B] 10A to 10C are cross-sectional views showing a process of etching a heavy metal film. [Figure 8] FIG. 10 is a cross-sectional view showing a schematic structure of a semiconductor device according to a fourth embodiment. [Figure 9] FIG. 10 is a cross-sectional view showing a schematic structure of a semiconductor device according to a fifth embodiment. [Figure 10A] 1A to 1C are cross-sectional views showing a process of forming a conductive film. [Figure 10B]1A to 1C are cross-sectional views showing a process of forming an insulating film. [Figure 10C] 10A to 10C are cross-sectional views showing an etching step of an insulating film. [Figure 10D] 1A to 1C are cross-sectional views showing a process for forming a heavy metal film. [Figure 10E] 10A to 10C are cross-sectional views showing a process of etching a heavy metal film. [Figure 10F] 10A to 10C are cross-sectional views showing an etching step of an insulating film. [Figure 10G] 10A to 10C are cross-sectional views showing a step of forming a second contact hole. [Figure 11] FIG. 10 is a cross-sectional view showing a schematic structure of a semiconductor device according to a sixth embodiment. [Figure 12] FIG. 13 is a cross-sectional view showing a schematic configuration of a semiconductor device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings, but the present invention is not limited to the embodiment.

[0008] (First embodiment) FIG. 1 is a cross-sectional view showing a schematic structure of a semiconductor device according to a first embodiment. The semiconductor device 1 shown in FIG. 1 is a power MOSFET having a trench gate structure. The semiconductor device 1 includes a semiconductor portion 10, a drain electrode 20 (first electrode), a source electrode 30 (second electrode), a gate electrode 40, and an interlayer insulating film 50. Hereinafter, the arrangement and configuration of each part may be described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are mutually orthogonal and represent the X-direction, Y-direction, and Z-direction, respectively. In addition, the Z-direction may be described as upward, and the opposite direction as downward.

[0009] The semiconductor portion 10 is, for example, a silicon substrate. + A buffer layer 11, an n-type drift layer 12 (first semiconductor layer), a p-type base layer 13 (second semiconductor layer), a p-type contact layer 14 (fourth semiconductor layer), and an n +A diffusion layer 15 (third semiconductor layer) is provided in this order. + The diffusion layer 15 is not limited to a diffusion layer as long as it is a semiconductor layer containing n-type impurities.

[0010] n + The buffer layer 11 is provided on the drain electrode 20. + The n-type impurity concentration of the buffer layer 11 is higher than the n-type impurity concentration of the n-type drift layer 12.

[0011] The n-type drift layer 12 is + The n-type drift layer 12 is electrically connected to the drain electrode 20 via the buffer layer 11. When the semiconductor device 1 is turned off, the n-type drift layer 12 is depleted by a drain voltage applied between the drain electrode 20 and the source electrode 30. Therefore, the thickness of the n-type drift layer 12 is designed to satisfy a predetermined withstand voltage condition.

[0012] The p-type base layer 13 is provided on the n-type drift layer 12. The p-type base layer 13 contains a p-type impurity at a concentration higher than the concentration of the n-type impurity in the n-type drift layer 12. The p-type base layer 13 is electrically connected to the source electrode 30. The p-type base layer 13 also faces the gate electrode 40 via a gate insulating film 41.

[0013] The p-type contact layer 14 is provided between the n-type drift layer 12 and the source electrode 30. The concentration of the p-type impurity contained in the p-type contact layer 14 is higher than the concentration of the p-type impurity contained in the p-type base layer 13. The bottom of the p-type contact layer 14 may be located in the n-type drift layer 12 or in the p-type base layer 13.

[0014] n + The diffusion layer 15 has a first region 151 and a second region 152. The first region 151 is provided on the p-type base layer 13. The first region 151 faces the gate electrode 40 with the gate insulating film 41 interposed therebetween.

[0015] The second region 152 is provided on the side surface of the interlayer insulating film 50 so as to protrude from the first region 151. That is, the second region 152 is located between the interlayer insulating film 50 and the source electrode 30 in the X direction, and between the source electrode 30 and the first region 151 in the Z direction. Here, the Z direction corresponds to a first direction from the n-type drift layer 12 toward the source electrode 30. Furthermore, the X direction corresponds to a second direction orthogonal to the Z direction. The first region 151 and the second region 152 are electrically connected to the source electrode 30.

[0016] 1, a plurality of second regions 152 and a plurality of interlayer insulating films 50 are provided in the X direction, and a distance D1 between the second regions 152 that face each other in the X direction with the source electrode 30 sandwiched therebetween is smaller than a distance D2 between the side surfaces of the interlayer insulating films 50 that face each other in the X direction with the source electrode 30 sandwiched therebetween. In other words, the distance D1 corresponds to the length of the portion of the source electrode 30 that is sandwiched between the second regions 152 that face each other in the X direction. The distance D2 corresponds to the length of the portion of the source electrode 30 that is sandwiched between the side surfaces of the interlayer insulating films 50 that face each other in the X direction.

[0017] In this embodiment, the n-type impurity concentration of the first region 151 and the second region 152 is higher than the n-type impurity concentration of the n-type drift layer 12. Furthermore, the semiconductor device 1 according to this embodiment is an n-channel MOSFET. Therefore, the first region 151 and the second region 152 are n-type semiconductors. Conversely, if the semiconductor device 1 is a p-channel MOSFET, the first region 151 and the second region 152 are p + This becomes the diffusion layer.

[0018] The drain electrode 20 is n-type on the back surface side of the semiconductor portion 10. + It is in contact with the buffer layer 11. The drain electrode 20 contains a metal such as aluminum (Al).

[0019] The source electrode 30 is provided on the surface side of the semiconductor portion 10. The source electrode 30 has a barrier metal layer 301 and a metal layer 302. The barrier metal layer 301 is formed between the interlayer insulating film 50, the n+ The metal layer 302 is in contact with the diffusion layer 15, the p-type base layer 13, and the p-type contact layer 14. The barrier metal layer 301 contains, for example, titanium nitride (TiN). The metal layer 302 is in contact with the p-type contact layer 14 and the n-type base layer 13 via the barrier metal layer 301. + It is electrically connected to the diffusion layer 15. The metal layer 302 contains, for example, aluminum.

[0020] The gate electrode 40 is + The gate electrode 40 is a trench gate that penetrates the first region 151 of the diffusion layer 15 and the p-type base layer 13 and terminates at the n-type drift layer 12. The gate electrode 40 is electrically insulated from the semiconductor portion 10 via a gate insulating film 41. The gate electrode 40 is made of, for example, polysilicon. The gate insulating film 41 is, for example, a silicon oxide (SiO2) film.

[0021] The interlayer insulating film 50 is provided on the semiconductor portion 10. The interlayer insulating film 50 electrically insulates the gate electrode 40 from the source electrode 30. The interlayer insulating film 50 is, for example, a silicon oxide film.

[0022] In the semiconductor device 1 configured as described above, when a predetermined voltage is applied between the gate electrode 40 and the source electrode 30, a channel 42 is generated on the side surface of the gate insulating film 41. This forms a current path from the drain electrode 20 to the source electrode 30, turning on the semiconductor device 1.

[0023] A method for manufacturing the semiconductor device 1 according to the present embodiment will be described below with reference to FIGS. 2A to 2G.

[0024] First, as shown in FIG. 2A, a first contact hole 60 is formed through an interlayer insulating film 50 formed on the semiconductor portion 10. The first contact hole 60 can be formed by, for example, RIE (Reactive Ion Etching). Before forming the first contact hole 60, the semiconductor portion 10 is provided with the gate electrode 40, the gate insulating film 41, and the n-type semiconductor layer 42. +The first region 151 of the diffusion layer 15 has already been formed.

[0025] Next, as shown in FIG. 2B, the first region 151 is selectively epitaxially grown to form an epitaxial region 151a. + The diffusion layer is formed not only on the surface of the semiconductor portion 10 but also on the inner wall surface of the first contact hole 60 , in other words, on the side surface of the interlayer insulating film 50 .

[0026] 2C, an insulating film 70 is formed on the surfaces of the interlayer insulating film 50 and the epitaxial region 151a. The insulating film 70 is, for example, a silicon oxide film. This silicon oxide film can be formed by, for example, CVD (Chemical Vapor Deposition).

[0027] 2D, a portion of the insulating film 70 is etched. The insulating film 70 is etched by, for example, RIE. By this etching, only the portion of the insulating film 70 formed on the side surface of the interlayer insulating film 50 remains.

[0028] Next, as shown in FIG. 2E, a second contact hole 61 is formed. The second contact hole 61 can be formed by, for example, RIE. The second contact hole 61 penetrates the epitaxial region 151a and terminates midway through the p-type base layer 13. At this time, the insulating film 70 remaining on the side surface of the interlayer insulating film 50 functions as a mask, so that a portion of the epitaxial region 151a located on the side surface of the interlayer insulating film 50 and below the insulating film 70 remains. This remaining portion is an n + This becomes the second region 152 of the diffusion layer 15 .

[0029] 2F, the insulating film 70 is removed, and the p-type contact layer 14 is formed at the bottom of the second contact hole 61. The p-type contact layer 14 can be formed, for example, by injecting p-type impurities such as boron (B) from above the second contact hole 61 and performing a heat treatment such as annealing.

[0030] Next, as shown in FIG. 2G, a barrier metal layer 301 is formed on the inner surface of the second contact hole 61 and on the surface of the interlayer insulating film 50, and a metal layer 302 is formed on the barrier metal layer 301. This completes the source electrode 30. Thereafter, the drain electrode 20 is also formed. This completes the semiconductor device 1 shown in FIG.

[0031] Here, a semiconductor device according to a comparative example to be compared with the semiconductor device according to the first embodiment will be described.

[0032] 3 is a cross-sectional view showing the structure of a semiconductor device according to a comparative example. In this comparative example, the same components as those in the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0033] In the semiconductor device 100 according to this comparative example, the work function difference with the metal contained in the source electrode 30 is different between the p-type semiconductor and the n-type semiconductor. Therefore, the contact resistance of one polarity may be high. For example, if the polarity that increases the contact resistance is the same as the polarity of the channel (n-type semiconductor), the on-resistance of the semiconductor device 100 increases. In this comparative example, as shown in FIG. + The diffusion layer 15 is composed of only the first region 151. + The contact resistance increases because the contact area between the diffusion layer 15 and the source electrode 30 is small, which results in an increase in the on-resistance of the semiconductor device 100.

[0034] On the other hand, in the semiconductor device 1 according to this embodiment, as shown in FIG. + The diffusion layer 15 has not only the first region 151 but also the second region 152. Therefore, compared to the comparative example, n + The contact area between the diffusion layer 15 and the source electrode 30 is enlarged. This reduces the contact resistance, which in turn reduces the on-resistance. In addition, since the second region 152 is provided on the side surface of the interlayer insulating film 50, the contact with the source electrode 30 is reduced without increasing the thickness of the first region 151. This allows the n+ The area of ​​the diffusion layer 15 can be increased.

[0035] (Second embodiment) 4 is a cross-sectional view showing a schematic structure of the semiconductor device according to the second embodiment. In this embodiment, the same components as those in the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0036] 4, the semiconductor device 2 according to this embodiment differs from the first embodiment in the material of the second region 152. In the first embodiment, the second region 152 is formed by epitaxially growing the first region 151. Therefore, the material of the second region 152 is single crystal silicon containing n-type impurities, just like the first region 151.

[0037] On the other hand, in this embodiment, the second region 152 is formed of a material different from that of the first region 151. The material of the second region 152 is, for example, polysilicon containing n-type impurities. A manufacturing method of the semiconductor device 2 according to the second embodiment will be described below with reference to FIGS. 5A and 5B. Note that the following description will focus on manufacturing steps that differ from those of the first embodiment.

[0038] 5A, a polysilicon film 152a containing n-type impurities is formed on the inner surface of the first contact hole 60 and on the upper surface of the interlayer insulating film 50. The polysilicon film 152a can be formed by, for example, CVD using polysilicon containing n-type impurities as a film forming material.

[0039] Next, as shown in FIG. 5B, a second contact hole 61 is formed. The second contact hole 61 can be formed by RIE, as in the first embodiment. The polysilicon film 152a is also etched by this RIE, but a part of it remains on the side surface of the interlayer insulating film 50. This remaining part becomes n + This becomes the second region 152 of the diffusion layer 15 .

[0040] Thereafter, the p-type contact layer 14, the source electrode 30, and the drain electrode 20 are formed in the same manner as in the first embodiment, thereby completing the semiconductor device 2 shown in FIG.

[0041] According to the present embodiment described above, n + As in the first embodiment, the diffusion layer 15 has not only the first region 151 but also the second region 152 formed on the side surface of the interlayer insulating film 50. As a result, n + The contact area between the diffusion layer 15 and the source electrode 30 increases, thereby reducing the contact resistance, and as a result, the on-resistance can be reduced.

[0042] In this embodiment, after the polysilicon film 152a is formed, the second contact hole 61 is formed. Therefore, the step of forming the insulating film 70 (see FIG. 2C) described in the first embodiment is not necessary. This makes it possible to shorten the manufacturing time compared to the first embodiment.

[0043] (Third embodiment) 6 is a cross-sectional view showing a schematic structure of a semiconductor device according to the third embodiment. In this embodiment, the same components as those in the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0044] In the semiconductor device 3 according to this embodiment, as shown in FIG. 6, the silicide region 16 is formed on the contact surface with the source electrode 30. Specifically, n + A silicide region 16 is formed on the surface where the diffusion layer 15, the p-type base layer 13, and the p-type contact layer 14 contact the source electrode 30. + Buffer layers 11 to n + The diffusion layer 15 contains heavy metals 17 .

[0045] The silicide region 16 is formed of a compound of a heavy metal and silicon, such as at least one of platinum (Pt), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and gold (Au).

[0046] The heavy metals 17 have diffused from the silicide regions 16 into each layer of the semiconductor portion 10. The heavy metals 17 cause lattice defects in the semiconductor portion 10. This shortens the carrier lifetime in the semiconductor portion 10, thereby increasing the switching speed of the semiconductor device 3. As a result, the switching loss of the semiconductor device 3 can be reduced.

[0047] Here, a method for manufacturing the semiconductor device 3 according to the third embodiment will be described. In this embodiment, the manufacturing process up to the formation of the p-type contact layer 14 (see FIG. 2F) is the same as in the first embodiment, and therefore the description will be omitted. Hereinafter, the manufacturing process after the formation of the p-type contact layer 14 will be described with reference to FIGS. 7A and 7B.

[0048] As shown in FIG. 7A, a heavy metal film 16a is formed on the inner surface of the second contact hole 61 and on the upper surface of the interlayer insulating film 50. The heavy metal film 16a can be formed by, for example, CVD. Subsequently, a heat treatment such as annealing is performed. As a result, the layer (n + Silicon contained in the diffusion layer 15, the p-type base layer 13, and the p-type contact layer 14 is silicided by the heavy metal such as platinum contained in the heavy metal film 16a.

[0049] Next, as shown in FIG. 7B, the heavy metal film 16a is etched. The heavy metal film 16a can be removed by wet etching using aqua regia as a chemical solution, for example. As a result, n + Silicide regions 16 are exposed on the surfaces of the diffusion layer 15, the p-type base layer 13, and the p-type contact layer 14. Subsequently, when heat treatment is performed again, heavy metals 17 such as platinum contained in the silicide regions 16 diffuse into each layer of the semiconductor portion 10.

[0050] Thereafter, the source electrode 30 and the drain electrode 20 are formed in the same manner as in the first embodiment, thereby completing the semiconductor device 3 shown in FIG.

[0051] In the present embodiment described above, as in the first embodiment, n + The diffusion layer 15 has not only the first region 151 but also the second region 152 formed on the side surface of the interlayer insulating film 50. As a result, n + Since the contact area between the diffusion layer 15 and the source electrode 30 is increased, the contact resistance can be reduced. As a result, the on-resistance can be reduced. In this embodiment, n, which is a lifetime killer element, is used. + The element (Pt) of the heavy metal 17 attached to the diffusion layer 15 is silicided and aggregated to form n + This can hinder contact between the diffusion layer 15 and the source electrode 30, resulting in high resistance. + By providing the second region 152 in the diffusion layer 15 and increasing the contact area, the contact resistance can be reduced.

[0052] Furthermore, in this embodiment, the heavy metal 17 contained in the silicide region 16 diffuses into each layer of the semiconductor portion 10, thereby making it possible to increase the switching speed of the semiconductor device compared to the first embodiment. This reduces not only the on-resistance but also the switching loss, making it possible to further improve the electrical characteristics of the semiconductor device.

[0053] (Fourth embodiment) FIG. 8 is a cross-sectional view showing a schematic structure of a semiconductor device according to the fourth embodiment.

[0054] 8, in the semiconductor device 4 according to this embodiment, the second region 152 is made of polysilicon containing n-type impurities, as in the second embodiment. Furthermore, the silicide region 16 described in the third embodiment is formed in layers (the first region 151, the p-type base layer 13, and the p-type contact layer 14) in contact with the source electrode 30 in the semiconductor portion 10 including this second region 152. Furthermore, each layer of the semiconductor portion 10 contains heavy metal 17 diffused from the silicide region 16.

[0055] Here, a method for manufacturing the semiconductor device 4 according to the fourth embodiment will be described. In this embodiment, as in the third embodiment, the silicide region 16 is formed between the process of forming the p-type contact layer 14 and the process of forming the source electrode 30. In the process of forming the silicide region 16, a heavy metal film 16a is formed, and silicon contained in the layer in contact with the heavy metal film 16a is silicided by annealing. Next, the heavy metal film 16a is etched to expose the silicide region 16. Another heat treatment is performed to diffuse the heavy metal 17, such as platinum, contained in the silicide region 16.

[0056] In the present embodiment described above, similarly to the second embodiment, the second region 152 + It is possible to reduce the contact resistance between the diffusion layer 15 and the source electrode 30. As a result, it is possible to reduce the on-resistance.

[0057] Furthermore, in this embodiment, the heavy metal 17 contained in the silicide region 16 diffuses into each layer of the semiconductor portion 10, thereby making it possible to increase the switching speed of the semiconductor device compared to the second embodiment. This reduces not only the on-resistance but also the switching loss, making it possible to further improve the electrical characteristics.

[0058] (Fifth embodiment) FIG. 9 is a cross-sectional view showing a schematic structure of a semiconductor device according to the fifth embodiment.

[0059] 9, in the semiconductor device 5 according to this embodiment, the second region 152 is made of polysilicon containing n-type impurities, as in the fourth embodiment. On the other hand, the silicide region 16 is not formed. However, heavy metals 17 such as platinum are contained in each layer of the semiconductor portion 10.

[0060] A method for manufacturing the semiconductor device 5 according to this embodiment will now be described with reference to FIGS. 10A to 10G.

[0061] 10A, a polysilicon film 152a is formed on the inner surface of the first contact hole 60 and on the upper surface of the interlayer insulating film 50. The polysilicon film 152a can be formed by CVD using polysilicon containing n-type impurities as a film forming material, for example.

[0062] 10B, an insulating film 71 is formed on the polysilicon film 152a. At this time, the first contact hole 60 is filled with the insulating film 71. The insulating film 71 is, for example, a silicon oxide film. This silicon oxide film can be formed by, for example, CVD.

[0063] 10C, a portion of the insulating film 71 is etched. The etching of the insulating film 71 may be wet etching or dry etching. By this etching, the portion of the polysilicon film 152a formed on the upper surface of the interlayer insulating film 50 is exposed.

[0064] 10D, a heavy metal film 16a is formed on the upper surfaces of the polysilicon film 152a and the insulating film 71. Subsequently, a heat treatment such as annealing is performed. As a result, the polysilicon contained in the polysilicon film 152a that is in contact with the heavy metal film 16a is silicided by the heavy metal, such as platinum, contained in the heavy metal film 16a.

[0065] 10E, the heavy metal film 16a is etched with, for example, aqua regia, thereby exposing the silicide region 16 on the surface of the polysilicon film 152a. Subsequently, when heat treatment is performed again, the heavy metal 17 such as platinum contained in the silicide region 16 is etched from the polysilicon film 152a to the first region 151, the p-type base layer 13, the n-type drift layer 12, the n ... base layer 13, the n-type drift layer 12, the n-type base layer 13, the n-type base layer 13, the n-type drift layer 12, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n-type base layer 13, the n- + It diffuses into the buffer layer 11 .

[0066] 10F, the insulating film 71 is selectively etched with respect to the polysilicon film 152a, thereby exposing the polysilicon film 152a.

[0067] Next, as shown in FIG. 10G, a second contact hole 61 is formed. The second contact hole 61 can be formed by RIE, as in the second embodiment. The polysilicon film 152a including the silicide region 16 is also etched by this RIE, but a part of it remains on the side surface of the interlayer insulating film 50. This remaining part becomes n + This becomes the second region 152 of the diffusion layer 15 .

[0068] Thereafter, the p-type contact layer 14, the source electrode 30, and the drain electrode 20 are formed in the same manner as in the first embodiment, thereby completing the semiconductor device 5 shown in FIG.

[0069] According to the present embodiment described above, n + The diffusion layer 15 is formed by the second region 152. + Since the contact area between the diffusion layer 15 and the source electrode 30 increases, the contact resistance can be reduced. + No silicide region 16 is formed on the contact surface between the diffusion layer 15 and the source electrode 30. Therefore, according to this embodiment, it is possible to reduce the on-resistance compared to the fourth embodiment.

[0070] Furthermore, in this embodiment, the heavy metal 17 diffuses into each layer of the semiconductor portion 10, thereby increasing the switching speed of the semiconductor device as in the fourth embodiment. This reduces not only the on-resistance but also the switching loss, making it possible to further improve the electrical characteristics.

[0071] (Sixth embodiment) 11 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the sixth embodiment. Hereinafter, the same components as those in the first to fifth embodiments described above will be given the same reference numerals, and detailed description thereof will be omitted.

[0072] The semiconductor device 6 according to this embodiment is a power MOSFET having a planar gate structure as shown in Fig. 11. This semiconductor device 6 differs from the power MOSFETs having a trench gate structure described in the first to fifth embodiments in that a gate electrode 40 is provided in an interlayer insulating film 50.

[0073] On the other hand, in the semiconductor device 6 according to this embodiment, similarly to the semiconductor devices according to the above-described embodiments, n + The diffusion layer 15 has a first region 151 formed on the surface of the semiconductor portion 10 and a second region 152 formed on the side surface of the interlayer insulating film 50. + A sufficient contact area between the diffusion layer 15 and the source electrode 30 can be ensured.

[0074] Therefore, according to this embodiment, even if the semiconductor device is a power MOSFET having a planar gate structure, the contact resistance can be reduced.

[0075] In this embodiment, the second region 152 is made of single crystal silicon containing n-type impurities, just like the first region 151, but may be made of polysilicon containing n-type impurities.

[0076] Furthermore, each layer of the semiconductor section 10 may contain a heavy metal 17 such as platinum. In this case, not only the on-resistance but also the switching loss can be reduced.

[0077] (Seventh embodiment) 12 is a cross-sectional view showing a schematic configuration of a semiconductor device according to the seventh embodiment. Hereinafter, components similar to those in the first to fifth embodiments described above will be given the same reference numerals, and detailed description will be omitted. The semiconductor devices described in the first to fifth embodiments are vertical MOSFETs in which the drain electrode 20 is disposed on the opposite side of the semiconductor portion 10 from the source electrode 30.

[0078] On the other hand, the semiconductor device 7 according to this embodiment is an LD (laterally diffused) MOSFET, as shown in FIG. 12. This semiconductor device 7 is a lateral MOSFET in which the drain electrode 20 is disposed on the same surface of the semiconductor portion 10 as the source electrode 30. The drain electrode 20 of the semiconductor device 7 has a barrier metal layer 201 and a metal layer 202. The barrier metal layer 201 contains titanium nitride, similar to the barrier metal layer 301. Furthermore, the metal layer 202 contains aluminum, similar to the metal layer 302.

[0079] Between the drain electrode 20 and the n-type drift layer 12, + A diffusion layer 18 is formed. + The concentration of the n-type impurity contained in the diffusion layer 18 is higher than the concentration of the n-type impurity contained in the n-type drift layer 12.

[0080] Also, n + An n-type semiconductor layer 19 is formed between the diffusion layer 18 and the p-type base layer 13. The concentration of n-type impurities contained in the n-type semiconductor layer 19 is higher than the concentration of n-type impurities contained in the n-type drift layer 12. + The concentration is lower than the concentration of the n-type impurity contained in the diffusion layer 18 .

[0081] On the other hand, on the source electrode 30 side, as in the semiconductor device according to each of the above-described embodiments, n + The diffusion layer 15 has a first region 151 formed on the surface of the semiconductor portion 10 and a second region 152 formed on the side surface of the interlayer insulating film 50.+ A sufficient contact area between the diffusion layer 15 and the source electrode 30 can be ensured.

[0082] Therefore, according to this embodiment, even if the semiconductor device is a lateral MOSFET, the contact resistance can be reduced. Note that in this embodiment, the second region 152 is single-crystal silicon containing n-type impurities, just like the first region 151, but it may also be polysilicon containing n-type impurities.

[0083] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents.

[0084] In each of the embodiments described above, the relative level of the impurity concentration between each semiconductor region can be confirmed using, for example, a scanning capacitance microscope (SCM). Note that the carrier concentration in each semiconductor region can be considered to be equal to the concentration of activated impurities in each semiconductor region. Therefore, the relative level of the carrier concentration between each semiconductor region can also be confirmed using an SCM. Furthermore, the impurity concentration in each semiconductor region can be measured using, for example, SIMS (secondary ion mass spectrometry).

[0085] The impurity concentration and heavy metal concentration in each semiconductor region of each embodiment can be measured by, for example, SIMS (Secondary Ion Mass Spectrometry).The heavy metal concentrations in multiple regions can also be compared using energy dispersive X-ray analysis (EDX).

[0086] The semiconductor device and the manufacturing method thereof described in the claims may have the configurations described in the following appendices. (Appendix 1) a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on the front or back side of the semiconductor portion; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor portion; a gate electrode facing the second semiconductor layer in the semiconductor portion or on the surface side of the semiconductor portion; an interlayer insulating film that electrically insulates the gate electrode and the second electrode on the surface side of the semiconductor portion; a third semiconductor layer of a first conductivity type having a first region in contact with the second semiconductor layer and the second electrode on the surface side of the semiconductor portion, and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction from the first semiconductor layer toward the second electrode; A semiconductor device comprising: (Appendix 2) 2. The semiconductor device of claim 1, wherein the first region and the second region include single crystal silicon. (Appendix 3) 2. The semiconductor device of claim 1, wherein the first region includes single crystal silicon and the second region includes polysilicon. (Appendix 4) 4. The semiconductor device according to claim 1, wherein a heavy metal is contained in the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. (Appendix 5) 5. The semiconductor device according to claim 4, wherein the heavy metal is at least one of platinum (Pt), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and gold (Au). (Appendix 6) 6. The semiconductor device according to claim 1, wherein the second electrode has a barrier metal layer in contact with the second semiconductor layer, the interlayer insulating film, and the third semiconductor layer. (Appendix 7) Further, a fourth semiconductor layer of the second conductivity type is provided on the bottom of the second electrode, 7. The semiconductor device according to claim 1, wherein a bottom portion of the fourth semiconductor layer is located within the first semiconductor layer. (Appendix 8) 6. The semiconductor device according to claim 4, wherein the second region includes a silicide of the heavy metal. (Appendix 9) a plurality of the second regions and a plurality of the interlayer insulating films are provided in the second direction; 9. The semiconductor device according to claim 1, wherein the distance between the second regions that face each other in the second direction across the second electrode is smaller than the distance between the side surfaces of the interlayer insulating films that face each other in the second direction across the second electrode. (Appendix 10) a first electrode electrically connected to a first semiconductor layer is formed on a front surface or a back surface of a semiconductor part including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer; forming a second electrode electrically connected to the second semiconductor layer on the surface side of the semiconductor portion; forming a gate electrode facing the second semiconductor layer in the semiconductor portion or on the surface side of the semiconductor portion; forming an interlayer insulating film on the surface side of the semiconductor portion to electrically insulate the gate electrode and the second electrode; forming a third semiconductor layer of a first conductivity type having a first region in contact with the second semiconductor layer and the second electrode on the surface side of the semiconductor portion, and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction from the first semiconductor layer toward the second electrode; A method for manufacturing a semiconductor device. (Appendix 11) 11. The method for manufacturing a semiconductor device according to claim 10, wherein the second region is formed by epitaxially growing the first region containing single crystal silicon. (Appendix 12) 11. The method for manufacturing a semiconductor device according to claim 10, wherein the second region is formed by depositing a polysilicon film on a side surface of the interlayer insulating film. (Appendix 13) forming a contact hole in the interlayer insulating film for forming the second electrode; forming a heavy metal film on the inner surface of the contact hole; 13. The method for manufacturing a semiconductor device according to claim 10, wherein the heavy metal film is heat-treated to diffuse the heavy metal contained in the heavy metal film into the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. (Appendix 14) forming a contact hole in the interlayer insulating film for forming the second electrode; forming a polysilicon film on the inner surface of the contact hole and on the upper surface of the interlayer insulating film; Filling the contact holes with an insulating film; forming a heavy metal film on the polysilicon film formed on the upper surface of the interlayer insulating film and on the insulating film; heat-treating the heavy metal film to diffuse the heavy metal contained in the heavy metal film into the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; 13. The method for manufacturing a semiconductor device according to claim 10, further comprising etching the polysilicon film formed on the upper surfaces of the heavy metal film, the insulating film, and the interlayer insulating film. [Explanation of symbols]

[0087] 1 to 7: Semiconductor device 10: Semiconductor Department 12: n-type drift layer 12 (first semiconductor layer) 13: p-type base layer (second semiconductor layer) 14: p-type contact layer (fourth semiconductor layer) 15:n + Diffusion layer (third semiconductor layer) 16a: Heavy metal film 17: Heavy Metal 20: Drain electrode (first electrode) 30: Source electrode (second electrode) 40: Gate electrode 50: Interlayer insulating film 60: First contact hole 61: Second contact hole 151:First area 152:Second area 152a: Polysilicon film 301: Barrier metal layer

Claims

1. a semiconductor portion including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on the front or back side of the semiconductor portion; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor portion; a gate electrode facing the second semiconductor layer in the semiconductor portion or on the surface side of the semiconductor portion; an interlayer insulating film that electrically insulates the gate electrode and the second electrode on the surface side of the semiconductor portion; a third semiconductor layer of a first conductivity type having a first region in contact with the second semiconductor layer and the second electrode on the surface side of the semiconductor portion, and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction from the first semiconductor layer toward the second electrode; Equipped with the first region has an upper portion in the first direction, The upper portion has a portion that contacts the second region and a portion that does not contact the second region.

2. The semiconductor device of claim 1 , wherein said first region and said second region comprise single crystal silicon.

3. 2. The semiconductor device of claim 1, wherein said first region comprises monocrystalline silicon and said second region comprises polysilicon.

4. The semiconductor device according to claim 1 , wherein a heavy metal is contained in said first semiconductor layer, said second semiconductor layer, and said third semiconductor layer.

5. 5. The semiconductor device according to claim 4, wherein the heavy metal is at least one of platinum (Pt), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and gold (Au).

6. The semiconductor device according to claim 1 , wherein said second electrode has a barrier metal layer in contact with said second semiconductor layer, said interlayer insulating film, and said third semiconductor layer.

7. a fourth semiconductor layer of the second conductivity type provided on a bottom of the second electrode; The semiconductor device according to claim 1 , wherein a bottom of said fourth semiconductor layer is located in said first semiconductor layer.

8. The semiconductor device according to claim 4 , wherein said second region includes a silicide of said heavy metal.

9. a plurality of the second regions and a plurality of the interlayer insulating films are provided in the second direction; 2. The semiconductor device according to claim 1, wherein the distance between the second regions facing each other in the second direction across the second electrode is smaller than the distance between the side surfaces of the interlayer insulating film facing each other in the second direction across the second electrode.

10. a first electrode electrically connected to a first semiconductor layer is formed on a front surface or a back surface of a semiconductor section including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type in contact with the first semiconductor layer; forming a second electrode electrically connected to the second semiconductor layer on the surface side of the semiconductor portion; forming a gate electrode facing the second semiconductor layer in the semiconductor portion or on the surface side of the semiconductor portion; forming an interlayer insulating film on the surface side of the semiconductor portion to electrically insulate the gate electrode and the second electrode; a third semiconductor layer of a first conductivity type having a first region in contact with the second semiconductor layer and the second electrode on the surface side of the semiconductor portion, and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction from the first semiconductor layer toward the second electrode, the first region having an upper portion in the first direction, the upper portion having a portion in contact with the second region and a portion not in contact with the second region; A method for manufacturing a semiconductor device.

11. 11. The method for manufacturing a semiconductor device according to claim 10, wherein the second region is formed by epitaxially growing the first region containing single crystal silicon.

12. The method for manufacturing a semiconductor device according to claim 10 , wherein the second region is formed by depositing a polysilicon film on a side surface of the interlayer insulating film.

13. forming a contact hole in the interlayer insulating film for forming the second electrode; forming a heavy metal film on the inner surface of the contact hole; 11. The method for manufacturing a semiconductor device according to claim 10, wherein the heavy metal film is heat-treated to diffuse the heavy metal contained in the heavy metal film into the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

14. forming a contact hole in the interlayer insulating film for forming the second electrode; forming a polysilicon film on the inner surface of the contact hole and on the upper surface of the interlayer insulating film; Filling the contact holes with an insulating film; forming a heavy metal film on the polysilicon film formed on the upper surface of the interlayer insulating film and on the insulating film; heat-treating the heavy metal film to diffuse the heavy metal contained in the heavy metal film into the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer; 11. The method for manufacturing a semiconductor device according to claim 10, further comprising etching said heavy metal film, said insulating film, and said polysilicon film formed on the upper surfaces of said interlayer insulating film.

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