System and method for distributed rendering using two-level binning

Abstract

A system (100) and method (300) for distributed rendering using two-level binning includes processing primitives (208) of a frame (202) to be rendered on a first graphics processing unit (GPU) chiplet (106-1) in a set of GPU chiplets (106) to generate visibility information (408) of primitives for each coarse bin (204, 510, 512, 514, 516, 518) and providing the visibility information (408) to other GPU chiplets in the set of GPU chiplets (106). Each coarse bin (204, 510, 512, 514, 516, 518) is assigned to one of the GPU chiplets in the set of GPU chiplets and rendered on the assigned GPU chiplet (106) based on the corresponding visibility information (408).

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application is related to and claims priority to the following co-pending application: U.S. Provisional Patent Application No. 63 / 131,976 (Attorney Docket No. 1458-200579-PR), entitled "Coarse / Hybrid / Two-Level Binning as a Mechanism for Distributed Rendering," which is incorporated herein by reference in its entirety. [Background technology]

[0002] A traditional graphics pipeline for processing three-dimensional (3D) graphics consists of a sequence of programmable shaders and fixed-function hardware blocks. A software application generates frames for rendering by the graphics pipeline and provides the frames to a command processor at the front end of the graphics pipeline, which is typically implemented in a graphics processing unit (GPU). The frames are subdivided into primitives, such as triangles or patches, that represent portions of objects within the image represented by the frame. For example, a primitive may represent a portion of a 3D model of an object visible in the frame. The graphics pipeline processes each primitive in response to a draw call and provides the processed primitive to a shader subsystem, which performs shading of the primitive. The graphics pipeline also performs primitive and binner rasterization, grouping primitives into bins or tiles associated with different portions of the frame. The bins of primitives are then provided to the shader subsystem for additional shading before being rendered on the display. Binning is a technique for increasing efficiency and speed in rendering images. Summary of the Invention [Means for solving the problem]

[0003] Example 1: A method including: processing primitives of a frame to be rendered on a first graphics processing unit (GPU) chiplet in a set of GPU chiplets to generate visibility information for the primitives for each of a plurality of coarse bins; providing the visibility information to other GPU chiplets in the set of GPU chiplets; assigning each of the plurality of coarse bins to one of the GPU chiplets in the set of GPU chiplets; and rendering each of the plurality of coarse bins on the assigned GPU chiplet based on the corresponding visibility information.

[0004] Example 2: The method of claim 1, wherein rendering each of the plurality of coarse bins includes processing visibility primitives and pixel phases for each of the plurality of coarse bins.

[0005] Example 3: The method of claim 1, wherein the visibility information includes primitives processed for each of a plurality of coarse bins.

[0006] Example 4: The method of claim 1, further comprising culling, by the first GPU chiplet, invisible primitives from primitives of the rendered frame.

[0007] Example 5: The method of claim 1, wherein allocating each of the plurality of coarse bins includes statically distributing each of the plurality of coarse bins to each of the GPU chiplets in the set of GPU chiplets.

[0008] Example 6: The method of claim 1, wherein allocating each of the plurality of coarse bins includes dynamically distributing each of the plurality of coarse bins to each of the GPU chiplets in the set of GPU chiplets based on workload balancing.

[0009] Example 7: The method of claim 1, wherein rendering each of the multiple coarse bins on an assigned GPU chiplet is performed in parallel.

[0010] Example 8: A non-transitory computer-readable storage medium embodying a set of executable instructions, the set of executable instructions for operating at least one graphics processing unit (GPU) chiplet to generate visibility information for primitives that intersect with each of a plurality of coarse bins that represent the geometry of a frame to be rendered, and providing the visibility information to the set of GPU chiplets, wherein each GPU chiplet of the set of GPU chiplets renders at least one of the coarse bins based on the corresponding visibility information.

[0011] 9. The non-transitory computer-readable storage medium of claim 8, wherein each GPU chiplet of the set of GPU chiplets renders at least one of the coarse bins by processing the visible geometry and pixel phases of each of the coarse bins.

[0012] Example 10: The non-transitory computer-readable storage medium of claim 8, wherein the visibility information includes primitives processed for each of a plurality of coarse bins.

[0013] Example 11: The non-transitory computer-readable storage medium of claim 8, further comprising a set of executable instructions for operating at least one graphics processing unit (GPU) chiplet to cull invisible primitives from geometry of a rendered frame.

[0014] Example 12: The non-transitory computer-readable storage medium of Example 8, wherein each GPU chiplet of the set of GPU chiplets is assigned to render at least one of the plurality of coarse bins based on a static distribution of the plurality of coarse bins.

[0015] 13. The non-transitory computer-readable storage medium of claim 8, wherein each GPU chiplet of the set of GPU chiplets is assigned to render at least one of the plurality of coarse bins based on a dynamic distribution of the plurality of coarse bins to balance the workload of the set of GPU chiplets.

[0016] 14. The non-transitory computer-readable storage medium of claim 8, wherein one GPU chiplet in a set of GPU chiplets renders at least one of the coarse bins in parallel with another GPU chiplet in the set of GPU chiplets that renders at least one of the other coarse bins.

[0017] Example 15: A system comprising: a first graphics processing unit (GPU) chiplet operating in a visibility mode to generate visibility information for each of a plurality of coarse bins representing the geometry of a frame to be rendered; and a set of GPU chiplets operating in a coarse bin rendering mode, wherein each GPU chiplet of the set of GPU chiplets receives visibility information for one of the plurality of coarse bins from the first GPU chiplet and renders one of the plurality of coarse bins based on the corresponding visibility information.

[0018] Example 16: The system of claim 15, wherein each GPU chiplet of the set of GPU chiplets renders one of the plurality of coarse bins by processing the visibility geometry and pixel phases of one of the plurality of coarse bins.

[0019] Example 17: The system of claim 15, wherein the set of GPU chiplets renders multiple coarse bins in parallel.

[0020] Example 18: The system of claim 15, wherein each GPU chiplet of the set of GPU chiplets is assigned to render one of the plurality of coarse bins based on a static distribution of the plurality of coarse bins.

[0021] Example 19: The system of claim 15, wherein each GPU chiplet of the set of GPU chiplets is assigned to render one of a plurality of coarse bins based on a dynamic distribution of the plurality of coarse bins to balance the workload of the set of GPU chiplets.

[0022] Example 20: The system of claim 15, wherein the first GPU chiplet culls invisible primitives from the geometry of the frame being rendered to generate the visibility information.

[0023] The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings, in which: The use of the same reference numbers in different drawings indicates similar or identical items. [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 is a block diagram illustrating a processing system employing multiple GPU chiplets, according to some embodiments. [Figure 2] FIG. 2 illustrates an example of two-level binning 200 of a frame 202 rendered by a processing system, such as the processing system of FIG. 1, according to some embodiments. [Figure 3] 2 is a block diagram of a method of distributed rendering in a processing system, such as the processing system of FIG. 1, using two-level binning, according to some embodiments. [Figure 4] FIG. 2 is a block diagram of static distribution of coarse bins during rendering by multiple GPU chiplets, such as the GPU chiplet of FIG. 1, according to some embodiments. [Figure 5]FIG. 2 is a block diagram of dynamic distribution of coarse bins during rendering by multiple GPU chiplets, such as the GPU chiplet of FIG. 1, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0025] To render a frame (i.e., to prepare a frame for transfer to and display on a display device such as a display panel), a GPU converts information about three-dimensional (3D) objects into a two-dimensional (2D) image frame for display. This process, at least in some cases, requires significant processing power and memory resources. In some cases, to reduce rendering time, a GPU renders primitives using a binning process, in which the GPU divides an image frame into regions, identifies primitives that intersect with a given region, and places the identified primitives into bins that correspond to the given region. Thus, each region of a frame is associated with a corresponding bin, and a bin contains primitives or portions of primitives that intersect with the associated bin. The GPU renders a frame bin by bin by rendering pixels of primitives that intersect with the region of the frame that corresponds to the bin. This allows the GPU to render frames more efficiently, at least in some cases, by requiring fewer memory accesses, increasing cache usage, etc.

[0026] One example of a binning process is single-level binning, in which a GPU receives a sequence of primitives and advantageously segments the primitives into temporally related primitive batches. Sequential primitives are captured until a predetermined condition, such as a batch full condition, a state storage full condition, or a dependency on a previously rendered primitive is determined. When performing primitive batch binning (PBB), an image frame displaying rendered primitives is divided into several blocks. Each block in the image frame is associated with a respective bin. Each primitive in the received sequence of primitives in the batch intersects one or more bins. For each received primitive in the batch, an initial bin intercept is calculated, which is the top-leftmost bin of the image frame that the primitive intersects. After the batch is closed, the first bin for processing is identified. Primitives that intercept the identified bin are processed. For each primitive identified in intercepting bins, the next bin intercept is identified and pixels contained in the primitives enclosed by the identified bins are sent for detailed rasterization. The next bin intercept is the next top-left most bin in raster order that is intersected by the processed primitive.

[0027] Another example of a binning process is two-level binning, or “hybrid binning,” in which two types of binning are performed: coarse-level binning and fine-level binning. In some embodiments, coarse-level binning uses large bins (e.g., 32 bins in total to cover the entire display area), which reduces binning overhead. Visibility information for each coarse bin (i.e., which primitives are visible in the bin) is generated during rendering of the first coarse bin (i.e., coarse bin 0) and used to render the other coarse bins. After coarse-level binning, fine-level binning is performed sequentially for each coarse bin. In some embodiments, fine-level binning involves dividing each coarse bin into smaller “fine” bins, such as by performing PBB and further binning each coarse bin into an array of fine bins (e.g., each having a size of 64×64 pixels) during PBB-based fine-level binning. Each coarse bin is then rendered using rendering information, such as visibility information, generated for the corresponding coarse bin. In some embodiments, two-level binning occurs at the top of the graphics processing pipeline (e.g., before vertex processing and rasterization), as opposed to single-level binning, which occurs in the middle of the graphics processing pipeline (e.g., after vertex processing but before pixel shading).

[0028] Generally, in both single-level binning and two-level binning, each coarse bin is processed sequentially (i.e., one bin at a time) by the GPU. This can be inefficient in situations where there is no interdependence between bins, i.e., where each bin can be processed without requiring input from the processing of any other bin. Therefore, it is desirable to introduce parallelism into bin processing to increase the speed and efficiency of rendering images and therefore improve the user experience.

[0029] Chiplets have been successfully used in CPU architectures to reduce manufacturing costs and improve yields because the heterogeneous computing characteristics of CPUs naturally lend themselves to separating CPU cores into separate units that do not require much intercommunication. GPU processing, on the other hand, generally involves parallel processing. However, the geometry that GPUs process includes not only sections of fully parallel work, but also work that requires synchronous ordering between different sections. Therefore, GPU programming models that spread sections of work on different threads are often inefficient because it is difficult to distribute parallelism across multiple different working groups and chiplets. In particular, synchronizing the memory contents of shared resources across the entire system to provide applications with a coherent view of memory is difficult and computationally expensive. Additionally, from a logical perspective, applications are written in terms of the system having only a single GPU. That is, even though traditional GPUs contain many GPU cores, applications are programmed to address a single device. Therefore, it is desirable to use chiplet technology in GPUs to perform parallel bin processing without requiring expensive high-speed interconnects between GPU chiplets.

[0030] 1-5 illustrate systems and methods that use two-level binning by GPU chiplets to provide parallel processing without requiring high-speed interconnects between GPU chiplets. The disclosed systems and methods utilize two-level binning, in which rendering is decomposed into two phases: a visibility phase and a coarse-bin rendering phase. During the visibility phase, the geometry of a draw call is processed by a first GPU chiplet in a set of GPU chiplets to generate visibility information, while other GPU chiplets remain free to process unrelated workloads, such as pixel workloads from a previous two-level binning pass. The visibility information generated by the first GPU chiplet specifies which primitives are processed for each coarse bin. In some cases, if sufficient resources are available, the pixel phase of the first bin may be rendered by the first GPU chiplet during the visibility phase. During the coarse bin rendering phase of two-level binning, each GPU chiplet renders its assigned coarse bin based on visibility information from the first GPU chiplet by processing the visible geometry of the assigned bin and its pixel phase. The distribution of coarse bins to the GPU chiplets can be either static or dynamic, depending on design considerations and workload balancing, as described in more detail below. The parallel processing performed by the GPU chiplets increases rendering speed and maximizes the processing bandwidth of the GPU chiplets.

[0031] 1 is a block diagram illustrating a processing system 100 employing multiple GPU chiplets, according to some embodiments. In the illustrated example, system 100 includes a central processing unit (CPU) 102 for executing instructions and an array 104 of one or more GPU chiplets, such as the illustrated three GPU chiplets 106-1, 106-2, and 106-N (collectively GPU chiplets 106). In various embodiments, as used herein, the term "chiplet" refers to any device that includes, but is not limited to, the following characteristics: 1) a chiplet includes active silicon dies that contain a portion of the computational logic used to solve a complete problem (i.e., the computational workload is distributed across multiple active silicon dies), 2) chiplets are packaged together as a monolithic unit on the same substrate, and 3) the programming model maintains the notion that these individual computational dies are a single monolithic unit (i.e., each chiplet is not exposed as a separate device to an application that uses the chiplet to process a computational workload). In various embodiments, the array of one or more GPU chiplets 104 comprises any cooperating collection of hardware and / or software that performs functions and calculations associated with accelerated graphics processing tasks, data parallel tasks, nested data parallel tasks in an accelerated manner in conjunction with resources such as conventional CPUs, conventional graphics processing units (GPUs), and combinations thereof.

[0032] In various embodiments, CPU 102 is connected to system memory 110, such as dynamic random access memory (DRAM), via bus 108. However, system memory 110 may also be implemented using other types of memory, including static random access memory (SRAM), non-volatile RAM, etc. In the illustrated embodiment, CPU 102 communicates with system memory 110 and also with GPU chiplet 106-1 via bus 108, which may be implemented as a peripheral component interconnect (PCI) bus, PCI-E bus, or other type of bus. However, some embodiments of system 100 include GPU chiplet 106-1 that communicates with CPU 102 through a direct connection or via other buses, bridges, switches, routers, etc.

[0033] As illustrated, CPU 102 includes several processes, such as executing one or more applications 112 to generate graphics commands and user mode drivers 116 (or other drivers, such as kernel mode drivers). In various embodiments, one or more applications 112 include applications that utilize the capabilities of GPU chiplet 106, such as applications that generate work in system 100 or an operating system (OS). Application 112 may include one or more graphics instructions that instruct GPU chiplet 106 to render a graphical user interface (GUI) and / or a graphics scene. For example, the graphics instructions may include instructions that define a set of one or more graphics primitives to be rendered by GPU chiplet 106.

[0034] In some embodiments, application 112 utilizes graphics application programming interface (API) 114 to invoke user mode driver 116 (or a similar GPU driver). User mode driver 116 issues one or more commands to one or more GPU chiplets array 104 to render one or more graphics primitives into a displayable graphics image. Based on the graphics instructions issued by application 112 to user mode driver 116, user mode driver 116 generates one or more graphics commands that specify one or more operations of GPU chiplets 106 to perform graphics rendering. In some embodiments, user mode driver 116 is part of application 112 running on CPU 102. For example, user mode driver 116, in some embodiments, is part of a gaming application running on CPU 102. Similarly, in some embodiments, a kernel mode driver (not shown) is part of an operating system running on CPU 102.

[0035] In the illustrated embodiment of FIG. 1 , passive crosslinks 118 communicatively couple GPU chiplets 106 (i.e., GPU chiplets 106-1 through 106-N) to one another. While three GPU chiplets 106 are shown in FIG. 1 , the number of GPU chiplets in chiplet array 104 is a design choice and varies in other embodiments. In various embodiments, passive crosslinks 118 include interconnect chips or other similar technology for inter-chiplet communication. As a general operational overview, CPU 102 is communicatively coupled to a single GPU chiplet (i.e., GPU chiplet 106-1) via bus 108. CPU-GPU transactions or communications from CPU 102 to array 104 of chiplets 106 are received by GPU chiplet 106-1. Any inter-chiplet communications are then routed through passive crosslinks 118, as appropriate, to access memory channels on other GPU chiplets 106. In this manner, the GPU chiplet-based system 100 includes GPU chiplets 106 that are addressable from a software developer's perspective as a single monolithic GPU (e.g., the CPU 102 and any associated applications / drivers are unaware of the chiplet-based architecture), thus avoiding the need for any chiplet-specific considerations on the part of the programmer or developer.

[0036] FIG. 2 illustrates an example of two-level binning 200 of a frame 202 rendered by a processing system, such as the processing system 100 of FIG. 1. In two-level binning, two types of binning are performed: coarse level binning and fine level binning. In some embodiments, the coarse level binning uses large bins 204 (e.g., a total of four bins to cover the entire display area), which reduces binning overhead. Visibility information for primitives (e.g., primitive 208) that are visible in each coarse bin is generated during rendering of the first coarse bin 204-1 and used to render the other coarse bins 204. Fine level binning is performed for each coarse bin 204 after the coarse level binning. In some embodiments, the fine level binning involves dividing each coarse bin into smaller bins 206 by performing PBB, e.g., binning each coarse bin into a 4×4 array of fine bins 206 during PBB-based fine level binning. Each fine bin 206 is then rendered using rendering information, such as visibility information, generated for the corresponding coarse bin.

[0037] 3 is a block diagram of a method 300 of distributed rendering using two-level binning in a processing system, such as processing system 100 of FIG. 1. As shown in block 302, an instruction to render a frame is initially received at one of GPU chiplets 106, such as GPU chiplet 106-1 of processing system 100. GPU chiplet 106-1 then processes the geometry of the frame by dividing the image frame into regions, identifying primitives that intersect with the predetermined regions, and assigning the identified primitives to coarse bins that correspond to the predetermined regions, as shown in block 304. As part of processing the geometry of the frame, a decision is made in block 306 regarding whether to process all geometry data or only the position data provided with the instruction. A minimum vertex shader is executed in block 308 in response to a determination that only position data is to be processed. Otherwise, a full shader is executed in block 310 to process all of the provided data. In block 312, the GPU chiplet 106-1 applies culling to remove primitives that are identified but are not visible in the rendered frame (i.e., invisible primitives). In block 314, the GPU chiplet 106-1 generates coarse per-bin visibility information.

[0038] In some embodiments, a determination is made whether sufficient resources are available to GPU chiplet 106-1 to execute the pixel phase of a coarse bin, as shown in block 316. If sufficient resources are available, then a determination is made in block 318 as to whether a minimal shader was executed in block 306. If sufficient resources are available and a minimal shader was not executed, then GPU chiplet 106-1 executes the pixel phase of any coarse bins in block 320. For example, if pixel processing and vertex processing are performed by the same shader hardware, then if it is determined that there are sufficient shader resources to process the vertices and pixels, then the system proceeds with pixel processing.

[0039] While GPU chiplet 106-1 is performing the visibility phase of two-level binning, other GPU chiplets are available to execute other workloads that do not directly depend on the visibility information being generated by GPU chiplet 106-1. For example, in some embodiments, GPU chiplet 106-2 processes pixel workloads or asynchronous computation workloads from a previous two-level binning pass while GPU chiplet 106-1 is performing the visibility phase of two-level binning, because these processes do not require input from the visibility phase performed by GPU 106-1. In block 322, GPU chiplet 106-1 provides visibility information to each of the other GPU chiplets 106 that specifies which primitives are processed per bin. In block 324, each GPU chiplet 106 operating in coarse-bin rendering mode renders its assigned coarse bin by processing the bin's visible geometry and its pixel phase. Once all of the coarse bins assigned to GPU chiplet 106-1 have been processed in the coarse bin rendering phase, GPU chiplet 106-1 becomes available to receive instructions to render the next frame (i.e., the second pass) and begins processing the geometry of the next frame while the other GPU chiplets 106 are still rendering the coarse bins assigned to them during the first pass.

[0040] 4 is a block diagram of a static distribution 400 of coarse bins during rendering by multiple GPU chiplets, such as GPU chiplet 106 of FIG. 1. During a visibility phase 402 of two-level binning, GPU chiplet 106-1 operates in visibility mode to process the geometry of the frame being rendered, while culling any invisible primitives, to generate visibility information 408 for each coarse bin. Also during the visibility phase 402, other GPU chiplets 106 in processing system 100 are running other workloads that are not dependent on the visibility information being generated by GPU chiplet 106-1. During a coarse bin rendering phase 404, each coarse bin is assigned to one of the GPU chiplets 106, regardless of the GPU chiplet's 106's current workload or availability. For example, GPU chiplet 106-1 is always assigned to render coarse bins 410 and 412, GPU chiplet 106-2 is always assigned to render coarse bins 414 and 416, and GPU chiplet 106-3 is always assigned to render coarse bins 418 and 420. A static distribution of coarse bins 410-420 may result in inefficiencies if some of the coarse bins 410-422 have smaller workloads and require less processing time because some of the GPU chiplets 106 may be idle for some time while the remaining GPU chiplets 106 complete the rendering of their respective coarse bins. However, a static distribution of coarse bins requires minimal processing resources to distribute the bins and may avoid the additional complexity of dynamically distributing the coarse bins among the GPU chiplets 106.

[0041] 5 is a block diagram of dynamic distribution 500 of coarse bins during rendering by multiple GPU chiplets, such as GPU chiplet 106 of FIG. 1. During the visibility phase 402 of two-level binning, GPU chiplet 106-1 operates in visibility mode to process the geometry of the frame being rendered, while culling any non-visible primitives, to generate visibility information 408 for each coarse bin. Additionally, during the visibility phase 402, other GPU chiplets 106 in the processing system 100 are running other workloads that are not dependent on the visibility information being generated by GPU chiplet 106-1. During the coarse bin rendering phase 304, each coarse bin is assigned to one of the GPU chiplets 106 based on the current workload or availability of the GPU chiplet 106. For example, each of the first three coarse bins 510, 512, and 514 is assigned to a GPU chiplet 106-1, a GPU chiplet 106-2, and a GPU chiplet 106-3. The remaining coarse bins 416 and 418 are assigned to either a GPU chiplet 106-1, a GPU chiplet 106-2, or a GPU chiplet 106-3 based on the coarse bin workloads already assigned to each of the GPU chiplets 106 and based on the coarse bin workloads being assigned to balance the workloads of the GPU chiplets 106.

[0042] 5, GPU chiplet 106-1 is assigned coarse bin 510, which has a relatively large workload, and GPU chiplet 106-2 is assigned coarse bin 512, which has a relatively small workload compared to the workload of coarse bin 510. To balance the overall workload of GPU chiplet 106-2 with the workload of GPU chiplet 106-1 and minimize downtime of GPU chiplet 106 during coarse bin rendering phase 504, coarse bin 516, which has a medium workload, is assigned to GPU chiplet 106-2. Similarly, coarse bin 518, which has a relatively small workload, is assigned to GPU chiplet 106-3 based on the medium workload of coarse bin 514 already assigned to GPU chiplet 106-3 and the relatively small workload of coarse bin 518. Thus, although dynamic distribution of coarse bins to each of the GPU chiplets 106 requires additional logic and processing to analyze the workload of the coarse bins and determine the most efficient distribution among the GPU chiplets 106, the dynamic distribution maximizes efficient use of the GPU chiplets 106 by balancing the workload of the GPU chiplets.

[0043] In some embodiments, the above-described apparatus and techniques are implemented in a system that includes one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the processing system 100 and GPU chiplet 106 described above with reference to FIGS. 1-4 . Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools are typically represented as one or more software programs. The one or more software programs include code executable by a computer system for operating the computer system to operate on code representing the circuits of one or more IC devices to perform at least a portion of a process for designing or adapting a manufacturing system for manufacturing the circuits. This code may include instructions, data, or a combination of instructions and data. The software instructions representing the design or manufacturing tools are typically stored in a computer-readable storage medium accessible to the computing system. Similarly, code representing one or more stages of the design or manufacture of the IC devices is stored in and accessed from the same or a different computer-readable storage medium.

[0044] A computer-readable storage medium includes any non-transitory storage medium or combination of non-transitory storage media that can be accessed by a computer system during use to provide instructions and / or data to the computer system. Such storage media may include, but are not limited to, optical media (e.g., compact discs (CDs), digital versatile discs (DVDs), Blu-ray discs), magnetic media (e.g., floppy disks, magnetic tape, magnetic hard drives), volatile memory (e.g., random access memory (RAM) or cache), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or micro-electromechanical systems (MEMS)-based storage media. The computer-readable storage medium (e.g., system RAM or ROM) may be internal to the computing system, the computer-readable storage medium (e.g., a magnetic hard drive) may be permanently attached to the computing system, the computer-readable storage medium (e.g., an optical disk or Universal Serial Bus (USB)-based flash memory) may be removably attached to the computing system, or the computer-readable storage medium (e.g., network-accessible storage (NAS)) may be coupled to the computer system via a wired or wireless network.

[0045] In some embodiments, certain aspects of the techniques described above are implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied in a non-transitory computer-readable storage medium. The software may include instructions and specific data that, when executed by one or more processors, operate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium may include, for example, a magnetic or optical disk storage device, a solid-state storage device such as flash memory, a cache, a random access memory (RAM), or other non-volatile memory device(s). The executable instructions stored on the non-transitory computer-readable storage medium may be implemented as source code, assembly language code, object code, or other form of instructions that can be interpreted or otherwise executed by one or more processors.

[0046] In addition to the above, it should be noted that not all activities or elements described in the summary description are required, that some of the particular activities or devices may not be required, that one or more additional activities may be performed, and that one or more additional elements may be included. Furthermore, the order in which the activities are listed is not necessarily the order in which they are performed. Also, the concepts have been described with reference to specific embodiments. However, those skilled in the art will recognize that various modifications and variations can be made without departing from the scope of the invention as set forth in the claims. Accordingly, the specification and drawings should be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention.

[0047] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and features from which any benefit, advantage, or solution may arise or be manifested are not construed as critical, essential, or essential features of any or all claims. Moreover, the specific embodiments described above are illustrative only, since the disclosed invention may be modified and practiced in different, but similar manners apparent to those skilled in the art having the benefit of the teachings herein. No limitations are intended to the details of construction or design herein shown, other than as described in the appended claims. It is therefore apparent that the specific embodiments described above may be altered or modified, and that all such variations are considered within the scope of the disclosed invention. Accordingly, the protection sought herein is set forth in the appended claims.

Claims

1. 1. A method (300) comprising: processing primitives of a frame (202) to be rendered on a first graphics processing unit (GPU) chiplet (106-1) in a set of GPU chiplets (106) to generate visibility information (408) for primitives for each of a plurality of coarse bins (204, 204-1, 510, 512, 514, 516, 518); providing the visibility information (408) to other GPU chiplets in the set of GPU chiplets (106); assigning each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) to a GPU chiplet in the set of GPU chiplets (106); and rendering each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) on the assigned GPU chiplet (106) based on the corresponding visibility information (408). Method (300).

2. Rendering each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) includes processing visibility primitives and pixel phases for each of the plurality of coarse bins (204, 510, 512, 514, 516, 518). The method (300) of claim 1.

3. the visibility information (408) includes primitives processed for each of the plurality of coarse bins (204, 510, 512, 514, 516, 518); The method (300) of claim 1 or 2.

4. The method of claim 3, further comprising: a first GPU chiplet (106-1) culling invisibility primitives from the primitives (208) of the frame (202) being rendered; The method (300) of any one of claims 1 to 3.

5. allocating each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) includes statically distributing each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) to each GPU chiplet in the set of GPU chiplets (106); The method (300) of any one of claims 1 to 4.

6. assigning each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) includes dynamically distributing each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) to each GPU chiplet in the set of GPU chiplets (106) based on workload balancing. The method (300) of any one of claims 1 to 4.

7. Rendering each of the plurality of coarse bins (204, 510, 512, 514, 516, 518) on the assigned GPU (106) chiplets is performed in parallel. The method (300) of any of claims 1 to 6.

8. A computer-readable storage medium embodying a set of executable instructions, comprising: The set of executable instructions includes: generating visibility information (408) for primitives that intersect with each of a plurality of coarse bins (204, 510, 512, 514, 516, 518) representing the geometry of a frame (202) to be rendered; providing the visibility information (408) to a set of GPU chiplets (106), each GPU chiplet of the set of GPU chiplets rendering at least one of the coarse bins (204, 510, 512, 514, 516, 518) based on the corresponding visibility information (408); on at least one graphics processing unit (GPU) chiplet (106); A computer-readable storage medium.

9. each GPU chiplet of the set of GPU chiplets renders at least one of the plurality of coarse bins by processing visibility geometry and pixel phases for each of the coarse bins; 9. The computer-readable storage medium of claim 8.

10. The set of executable instructions includes: causing at least one GPU chiplet (106) to cull invisible primitives from the geometry of the frame (202) being rendered; 10. The computer-readable storage medium of claim 9.

11. each GPU chiplet of the set of GPU chiplets is assigned to render at least one of the plurality of coarse bins based on a static distribution of the plurality of coarse bins or based on a dynamic distribution of the plurality of coarse bins to balance workloads of the set of GPU chiplets; The computer-readable storage medium according to any one of claims 8 to 10.

12. any GPU chiplet (106) in the set (106) of GPU (106-1) chiplets renders at least one of the coarse bins (204, 510, 512, 514, 516, 518) in parallel with another GPU chiplet (106) in the set (106) of GPU chiplets rendering at least one of the other coarse bins (204, 510, 512, 514, 516, 518); The computer-readable storage medium according to any one of claims 8 to 11.

13. A system (100), comprising: a first graphics processing unit (GPU) chiplet (106-1) operating in a visibility mode to generate visibility information (408) for each of a plurality of coarse bins (204, 510, 512, 514, 516, 518) representing the geometry of a frame (202) to be rendered; a set of GPU chiplets (106) operating in a coarse bin rendering mode, each GPU chiplet of the set of GPU chiplets (106) receiving the visibility information (408) for one of the plurality of coarse bins (204, 510, 512, 514, 516, 518) from the first GPU chiplet (106-1) and rendering the one of the plurality of coarse bins (204, 510, 512, 514, 516, 518) based on the corresponding visibility information (408); System (100).

14. each GPU chiplet in the set of GPU chiplets is assigned to render one of the plurality of coarse bins based on a static distribution of the plurality of coarse bins or based on a dynamic distribution of the plurality of coarse bins to balance workloads of the set of GPU chiplets; The system (100) of claim 13.

15. the first GPU (106-1) chiplet culls invisible primitives from the geometry of the frame (202) being rendered to generate the visibility information (408); The system (100) of claim 13 or 14.

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