Semiconductor Devices

Abstract

To enable power gating by providing a holding circuit on a logic circuit.SOLUTION: A holding circuit has a first terminal, a node, a capacitive element, and first to third transistors. The first transistor controls a conduction state between the first terminal and an input terminal of a logic circuit. The second transistor controls a conduction state between an output terminal of the logic circuit and the node. The third transistor controls a conduction state between the node and the input terminal of the logic circuit. A gate of the first transistor and a gate of the second transistor are electrically connected with each other. During a data retention time period, the node becomes in an electrically floating state. A voltage of the node is held by the capacitive element.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention disclosed in the specification, drawings, and claims of this application (hereinafter referred to as the present specification, etc.) One aspect of the invention is a semiconductor device (for example, a sequential circuit, a holding circuit, a memory circuit, a logic circuit, etc.), The present invention relates to a driving method thereof, a manufacturing method thereof, etc. For example, one embodiment of the present invention is a storage device, a processing device, an imaging device, a display device, The present invention relates to a display device, a light-emitting device, a power storage device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0002] To reduce the power consumption of semiconductor devices, power gating and clock gating are used. This is done to stop circuits that do not need to be operated. Flip-flop (FF) is one of the sequential circuits (memory circuits that retain a state) that are often included in semiconductor devices. Therefore, reducing the power consumption of FFs leads to a reduction in the power consumption of semiconductor devices incorporating FFs. In a typical FF, the data stored in it is lost when the power is cut off.

[0003] A transistor in which a semiconductor region is formed using an oxide semiconductor (hereinafter referred to as an OS transistor) The off-state current of the MOSFET is extremely small, so data can be stored even when the power is cut off. For example, Patent Documents 1-3 propose a holding circuit capable of holding an OS By incorporating a holding circuit using transistors into the FF, power gating of the FF can be achieved. For example, Non-Patent Document 1 describes that FF and SRAM can be A retention circuit using OS transistors is provided to perform power gating of the processor. It is stated that [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-257192 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-9297 [Patent Document 3] Japanese Patent Application Laid-Open No. 2013-175708 [Non-patent literature]

[0005] [Non-Patent Document 1] H. Tamura et al., “Embedded SRAM and Cortex-M0 Core with Backup Circuits Using a 60-nm Crystalline Oxide Semiconductor for Power Gating,” IEEE COOL Chips XVII, Apr. 2014. Summary of the Invention [Problem to be solved by the invention]

[0006] An object of one embodiment of the present invention is to provide a novel semiconductor device or a method for driving the novel semiconductor device. Alternatively, an object of one aspect of the present invention is to enable power gating. and to retain data without supplying power, reduce power consumption, and Examples of advantages include facilitating design and facilitating modeling.

[0007] The description of multiple problems does not preclude the existence of each problem. It is not necessary to solve all of these problems. Furthermore, problems other than those listed may not be solved by the description of this specification, etc. These problems will become apparent from the above and can also be problems of one embodiment of the present invention. [Means for solving the problem]

[0008] One aspect of the present invention is a logic circuit having a first circuit and a second circuit, the first circuit comprising: The second circuit has 1st to nth input terminals and a first output terminal (n is an integer of 2 or more), a +1 input terminal, a first node, a first capacitance element, and first to third transistors; The first circuit selects one of the first to nth input terminals and outputs the same logic as the selected input terminal. The capacitor has a function of outputting logic data from the first output terminal, and the capacitor is electrically connected to the first node. The first transistor controls the conduction state between the (n+1)th input terminal and the first input terminal. The second transistor controls the conduction state between the first output terminal and the first node. The third transistor controls the conduction state between the first node and the first input terminal. The gate of the first transistor and the gate of the second transistor are electrically connected. The second transistor and the third transistor are connected to each other, and the semiconductor regions of the second transistor and the third transistor are formed of an oxide semiconductor layer. It has been done.

[0009] In the above embodiment, the first capacitance element and the first to third transistors form a first circuit. In the above embodiment, the first transistor may be a semiconductor. The region may be formed of an oxide semiconductor layer. In this case, The oxide semiconductor layer preferably has crystals oriented in the c-axis direction.

[0010] In the logic circuit according to the above aspect, the first circuit has a selection circuit and a first logic circuit. The first logic circuit has an (n+2)th input terminal and a first output terminal, and the first logic circuit It has the function of outputting data of the same logic as the n+2 input terminal from the first output terminal, and the selection circuit is , and a second output terminal, and the selection circuit selects one of the first to n-th input terminals as the second output terminal. and the second output terminal is electrically connected to the (n+2)th input terminal. It's fine. [Effects of the Invention]

[0011] According to one embodiment of the present invention, a novel semiconductor device or a method for operating the novel semiconductor device is provided. Alternatively, one embodiment of the present invention enables power gating. This makes it possible to retain data without supplying power, and reduces power consumption. , it becomes possible to reduce the size or to simplify the design.

[0012] The description of multiple effects does not preclude the existence of other effects. It is not necessary to have all of the effects exemplified above. Problems, effects, and novel features other than those described above will become apparent from the description and drawings of this specification. It becomes clear that: [Brief explanation of the drawings]

[0013] [Figure 1] 1A and 1B are block diagrams showing examples of the configuration of a logic circuit and the circuit 10 shown in FIG. [Figure 2] A, B: Block diagram showing an example of a logic circuit configuration. [Figure 3] FIG. 1 is a block diagram showing an example of the configuration of a logic circuit. [Figure 4] FIG. 1 is a circuit diagram showing an example of the configuration of a scan flip-flop (SFF). [Figure 5] FIG. 1 is a circuit diagram showing an example of the configuration of an SFF. [Figure 6] 1 is a timing chart showing an example of operation of the SFF. [Figure 7] 1 is a timing chart showing an example of operation of the SFF. [Figure 8] FIG. 1 is a circuit diagram showing an example of the configuration of an SFF. [Figure 9] FIG. 1 is a circuit diagram showing an example of the configuration of an SFF. [Figure 10] FIG. 1 is a circuit diagram showing an example of the configuration of an SFF. [Figure 11] FIG. 1 is a circuit diagram showing an example of the configuration of an SFF. [Figure 12] FIG. 1 is a circuit diagram showing an example of the configuration of an SFF. [Figure 13] FIG. 1 is a block diagram showing an example of the configuration of a processing device. [Figure 14] FIG. 2 is a block diagram showing an example of the configuration of a processor core. [Figure 15] A diagram showing the SFF device structure. [Figure 16] 1A is a flowchart showing an example of a method for manufacturing an electronic component, and FIG. 1B is a schematic perspective view showing an example of the configuration of an electronic component. [Figure 17] AF: Diagram showing an example of electronic equipment. [Figure 18] 18A: A plan view showing an example of the configuration of a transistor. BD: Cross-sectional views of the transistor in FIG. [Figure 19] A: Enlarged view of the transistor in Figure 18B. B: Energy band diagram of the transistor. [Figure 20] AC: Cross-sectional views showing examples of transistor configurations. [Figure 21] A and B are cross-sectional views showing examples of transistor configurations. [Figure 22] FIG. 1 is a cross-sectional view showing an example of the configuration of a chip. [Figure 23] FIG. 1 is a cross-sectional view showing an example of the configuration of a chip. DETAILED DESCRIPTION OF THE INVENTION

[0014] In this specification, a semiconductor device is a device that utilizes semiconductor characteristics, and is a semiconductor element ( It refers to a circuit that includes a semiconductor (transistor, diode, etc.), or a device that has such a circuit. It refers to any device that can function by utilizing the characteristics of the device. For example, an integrated circuit, a device equipped with an integrated circuit, The chip is an example of a semiconductor device. Electronic devices and the like may themselves be semiconductor devices or may include semiconductor devices.

[0015] In addition, when it is explicitly stated in this specification that X and Y are connected, is when X and Y are electrically connected and when X and Y are functionally connected. and the case where X and Y are directly connected are considered to be disclosed in this specification and the like. Therefore, the present invention is not limited to predetermined connection relationships, for example, connection relationships shown in drawings or text. Connections other than those shown in the drawings or text are also considered to be described in the drawings or text. X and Y are the object (e.g., device, element, circuit, wiring, electrode, terminal, conductive film, layer, etc.) (etc.)

[0016] A transistor has three terminals called the gate, source, and drain. The source is a node that functions as a control node that controls the conduction state of a transistor. The two input / output nodes that function as the source or drain are determined by the type of transistor and the terminals. Depending on the level of the applied potential, one side becomes the source and the other side becomes the drain. In this specification, the terms source and drain can be used interchangeably. In addition, in this specification and the like, the two terminals other than the gate may be referred to as the first terminal and the second terminal. There is a match.

[0017] Depending on the circuit configuration and device structure, a node may be a terminal, wiring, electrode, conductive layer, conductor, or insulator. It is possible to call them pure regions, etc. Also, terminals, wiring, etc. can be called nodes. It is possible to do this.

[0018] Voltage is the voltage between a certain potential and a reference potential (e.g., ground potential (GND) or source potential). Therefore, voltage can be replaced with electric potential. Therefore, even if it is described as ground potential, it does not necessarily mean 0 It may not mean V.

[0019] In this specification, the terms "film" and "layer" may be used interchangeably. can be used interchangeably depending on the situation. For example, the term "conductive layer" For example, it may be possible to change the term "insulating film" to "conductive film." It may be possible to change the term to "insulating layer."

[0020] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion of elements. In such cases, it is not intended to limit the number or order of items. It is not something that can be done.

[0021] In this specification, for example, the clock signal CLK is abbreviated as signal CLK, CLK, etc. This may include other components (e.g., signals, voltages, potentials, circuits, elements, The same applies to electrodes, wiring, etc.

[0022] In the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, the scale is not necessarily limited to that. The drawings are only a schematic representation of an ideal example. The figures are not limited to the shapes or values ​​shown in the drawings. For example, the signal due to noise may be signal, voltage, or current variations, or timing errors can include current variations, etc.

[0023] In this specification, the terms "above" and "below" that indicate the positional relationship between components are used. , may be used for convenience in explaining with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those used above, but can be rephrased appropriately depending on the situation.

[0024] The layout of each circuit block in the block diagram shown in the drawings is for the purpose of explanation only. Although it is shown that different circuit blocks are used to realize different functions, the actual circuit blocks In some cases, different functions can be realized within the same circuit block. In addition, the function of each circuit block is specified for the purpose of explanation, and Although it is shown as a circuit block, in actual circuit blocks it is one circuit block. In some cases, the processing to be performed is provided to be performed by multiple circuit blocks.

[0025] The following describes embodiments of the present invention. However, it is possible to combine the embodiments described in this specification as appropriate. It is also possible to combine multiple configuration examples (operation examples, manufacturing examples) in one embodiment. When examples of configurations (including method examples) are shown, the configuration examples can be combined with each other as appropriate. Furthermore, the present invention can be embodied in many different forms, and it is understood that the spirit and scope of the present invention are not to be construed as limiting the scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. There is no.

[0026] First Embodiment <<Logic circuit configuration example>> FIG. 1A shows an example of the configuration of a logic circuit. The logic circuit 100 shown in FIG. 1A holds data (state). Depending on the circuit structure, it can also be called a sequential circuit. The logic circuit 100 is a semiconductor device capable of clock gating and power gating. The logic circuit 100 includes a circuit 10 and a circuit RC1. The circuit RC1 converts data into Circuit RC1 is a holding circuit that has the function of reading the state (data) of circuit 10. The circuit RC1 has the function of reading and storing the data. It has the function of reading.

[0027] <Circuit 10> The circuit 10 has terminals D1-Dn (n is an integer of 2 or more), a terminal Q, a terminal QB, and a terminal EN. Terminals D1-Dn are data input terminals. Terminals Q and QB are data output terminals. The terminal EN is a terminal to which a control signal E0 is input. The circuit 10 may be any logic circuit. 10 selects one of the terminals D1-Dn according to the logic of the terminal EN, and It is sufficient if the device has an arithmetic function that outputs data with the same logic as the data input to the device from terminal Q. Terminal QB is a terminal that outputs data that is the inverse of the logic of terminal Q. In the example of Figure 1A, The circuit 10 does not necessarily have to have the terminal QB.

[0028] 1B shows an example of the configuration of the circuit 10. The circuit 10 shown in FIG. 1B includes a selection circuit 20 and a circuit 3. 0. The terminal T1 of the selection circuit 20 is electrically connected to the terminal T2 of the circuit 30. Terminal T1 is the output terminal of selection circuit 20, and terminal T2 is the input terminal of circuit 30.

[0029] The signal E0 is a control signal for the selection circuit 20. The selection circuit 20 selects the terminal D1 according to the signal E0. -Dn and electrically connect it to the terminal T1.

[0030] The circuit 30 may be a logic circuit. The circuit 30 has the same logic as the data input to the terminal T2. It is sufficient if the circuit has a calculation function that can output data from terminal Q. For example, circuit 3 0 is a sequential circuit whose internal state is updated by a control signal such as a clock signal CLK. For example, the circuit 30 may be a latch, a flip-flop, a shift register, a counter, or the like. The circuit may be a counter circuit, a frequency divider circuit, or the like.

[0031] <Circuit RC1> The circuit RC1 includes a node FN, a terminal D0, a terminal T0, a switch SW1, a switch SW2, and a switch The input terminals are a switch SW3 and a capacitance element C1. The terminals D0 and T0 are input terminals.

[0032] The node FN is a node that can be in an electrically floating state, and the data ( One terminal of the capacitance element C1 is connected to the node FN, The other terminal is electrically connected to the terminal T0. The capacitance element C1 maintains the voltage of the node FN. A signal or a constant voltage can be input to terminal T0. For example, the low power supply voltage of the circuit 10 may be input to the terminal T0.

[0033] Switch SW1 controls the conduction state between terminals D0 and D1, and switch SW2 controls the conduction state between terminals D0 and D1. The signal E2 controls the conduction state between Q and node FN. The switch SW3 controls the conduction state between the node FN and the terminal D1. The signal E3 controls the on / off of the switch SW3.

[0034] (normal operation) When the circuit 10 processes the input data, the switch SW3 is turned off. SW1 can be turned on as needed. The data processed by the circuit 10 is the data at the terminal D1. If the data processed by the circuit 10 does not include If the data of terminal D1 is included, switch SW1 should be turned on. The state of switch SW2 can be either on or off. In the example of FIG. 1A, signal E2 turns on switch SW2. 2 is also turned on in conjunction with switch SW1. Switch SW1 and switch SW2 may be turned off by setting different signals. By sharing the control signals, the number of wiring and elements can be reduced, leading to a reduction in power consumption. do.

[0035] (Backup (evacuation) operation) To back up the state of circuit 10, input signals such as CLK to circuit 10 as needed. Stop the power supply so that the logic (state) of terminal Q does not change. Next, switch SW2 The node FN is electrically connected to the terminal Q. Therefore, the logic of node FN is the same as that of terminal Q. If the logic of terminal Q is "1", If the logic of terminal Q is "0", node FN also becomes "0". By turning off switches SW2 and SW3 and leaving node FN in an electrically floating state, the The backup is completed and the circuit RC1 enters a data holding state.

[0036] Once the backup is complete, it becomes possible to cut off the power supply to the circuit 10. That is, by providing the circuit RC1, the clock gating and power gating of the circuit 10 can be performed. This makes it possible to

[0037] (Restore operation) When restoring the state of the circuit 10, power is supplied to the circuit 10 and the signal E0 is , the circuit 10 is put into a state in which the data at the terminal D1 can be output from the terminal Q. Since 1 is electrically connected to node FN, its logic level is the same as that of node FN. Therefore, the circuit 10 outputs data of the same logic as the data held at the node FN from the terminal Q. In other words, the state of the logic circuit 100 is restored.

[0038] Switch SW3 is turned off. If necessary, the supply of signal CLK can be resumed to reset the logic The circuit 100 is now ready for normal operation. Before the supply of the signal CLK is resumed, If the logic of the child Q needs to be the same as the logic of the node FN during the data retention period, Before turning off switch SW3, a control signal such as signal CLK is supplied to operate circuit 10 normally. Then, the data at terminal D1 can be written to terminal Q.

[0039] Circuit RC1 can retain data while circuit 10 is power-gated. To retain data for a long time using circuit RC1, The potential fluctuation (especially the potential drop) of the electrically floating node FN must be suppressed as much as possible. As one of the means for achieving this, the switches SW2 and SW3 are in a non-conducting state. One of the advantages of using transistors with extremely low drain current (off-state current) is that they are

[0040] To reduce the off-state current of a transistor, for example, the semiconductor region should be made into a region with a wide energy cap. It can be made of a semiconductor. The energy gap of the semiconductor must be 2.5 eV or more, or 2. Preferably, the electron transport potential is 7 eV or more, or 3 eV or more. For example, the switches SW2 and SW3 have semiconductor regions made of oxide semiconductors. The transistor is normalized by the channel width. The leakage current of the OS transistor is measured at a source-drain voltage of 10 V and room temperature (approximately 25°C). ) in the state of 10 × 10 -21 A / μm (10 zeptoA / μm) or less. The leakage current of the OS transistors applied to the switches SW2 and SW3 is ℃) at 1 × 10 -18 A or less, or 1 x 10 -21 A or less, or 1 x 10 - 24 A or less is preferable. Alternatively, the leakage current is 1×10 at 85°C. -15 A or below, or 1×10 -18 A or less, or 1 x 10 -21 It is preferable that it is A or less.

[0041] Oxide semiconductors have a large energy gap, making it difficult for electrons to be excited, and the effective mass of holes Therefore, OS transistors are semiconductors with a large capacitance. Compared to transistors, avalanche breakdown is less likely to occur. By suppressing hot carrier degradation caused by This allows the device to be driven at a high drain voltage. By applying an OS transistor to RC1, the signal potential level and input timing can be controlled. For example, the node can be set to the data retention state. It also becomes possible to drive the FN voltage to a higher level.

[0042] The oxide semiconductor of the OS transistor contains at least one of In, Ga, Sn, and Zn. It is preferable that the oxide contains one or more elements. -Sn-Ga-Zn oxide, In-Ga-Zn oxide, In-Sn-Zn oxide, In- Al-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Z n-oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide , Sn-Mg oxide, In-Mg oxide, In-Ga oxide, In oxide, Sn oxide Zn oxide, etc. In addition, elements or compounds other than the constituent elements of these oxides are added to these oxides. For example, an oxide semiconductor containing SiO2 can be used.

[0043] In addition, the OS transistor has a gate insulating layer that is approximately 11 nm thick in terms of equivalent oxide thickness. Even when the channel length is shortened to about 50 nm, excellent off-current characteristics and subthreshold Therefore, OS transistors can be used to construct logic circuits. This allows for a thicker gate insulating layer than that of a typical Si transistor. The leakage current through the gate insulating layer is reduced, and the electrical characteristics due to the variation in the thickness of the gate insulating layer are improved. The OS transistor will be described in detail in Embodiment 4.

[0044] There are no particular restrictions on the transistors that make up the switch SW1 and the circuit 10, and standard A typical transistor applied to a cell can be used, for example, The transistor may be formed of a group 14 element (Si, Ge, C). A typical example of a transistor is a transistor in which the semiconductor region is formed from silicon ( In addition, in order to improve the mobility of Si transistors, Alternatively, a strained transistor in which Ge is added to a semiconductor region made of Si may be used.

[0045] Switch SW1, like switches SW2 and SW3, is made up of an OS transistor. Alternatively, it may be configured as a CMOS circuit such as an analog switch. By using OS transistors, the logic circuit can be improved by adding the circuit RC1 as described below. It is possible to make the area overhead of the circuit 100 zero. Analog switch (a switch in which an n-type transistor and a p-type transistor are connected in parallel) In the case of the above, stacking an n-type OS transistor on a p-type Si transistor In this case, the surface area of ​​the logic circuit 100 is smaller than when the analog switch is configured only with Si transistors. Analog switches are also called transfer gates. It is being done.

[0046] In the logic circuit 100, the circuit configuration of the circuit 10 is not changed by providing the circuit RC1. For example, in the configuration example shown in FIG. 1B, the selection circuit 20 includes a selector or A common circuit called a multiplexer can be applied. General sequential circuits such as latches and flip-flops can be applied. Since the circuit RC1 can be stacked on the It is possible to provide the circuit RC1 without any modifications.

[0047] As described above, the holding circuit of this embodiment can reduce the circuit configuration and layout of the logic circuit. A backup function can be added to the logic circuit without changing the program. This circuit provides a backup function to the logic circuitry without substantially degrading performance during normal operation. It is also possible to stack a holding circuit in the area where the logic circuit is formed. Therefore, the area overhead caused by adding a holding circuit can be reduced to zero. be.

[0048] <Modification of holding circuit> The logic circuit 101 shown in FIG. 2A has a circuit RC2 instead of the circuit RC1. The inverter 42 is added to the circuit RC1. The output terminal is electrically connected to the QB terminal, and the output terminal is electrically connected to the switch SW2. The logic inverted data of the child QB is stored in the circuit RC2. Therefore, the circuit RC2 is , the data of the same logic as terminal Q is held, and the held data can be written to terminal D1. It is possible. It is advisable that the inverter 42 supplies power only during backup operation.

[0049] The logic circuit 102 shown in Figure 2B has a circuit RC3 instead of the circuit RC1. The circuit RC1 is configured by adding inverters 43 and 44. The terminal is electrically connected to the switches SW1 and SW3, and the output terminal is electrically connected to terminal D1. The input terminal of the inverter 44 is electrically connected to the terminal D0, and the output terminal of the inverter 44 is The switch SW2 is electrically connected to the terminal QB and the node FN. By backup operation, circuit RC3 operates in the same logic as terminal QB. The data written to terminal D1 by the restore operation is The logic of node FN is inverted by data 43. In other words, the data of the same logic as terminal Q is Data can be written to terminal D1.

[0050] The circuit 10 shown in FIGS. 2A and 2B may not have the terminal Q.

[0051] <Modification of logic circuit> The logic circuit 103 shown in FIG. 3 is a modified example of the logic circuit 101. The circuit 10 is a one-input circuit. Circuit 15 is a logic circuit. Circuit 15 is a device with the same logic as terminal D1. The circuit 15 may have a calculation function capable of outputting the data as needed. A control signal such as CLK may be input. The circuit 15 may also have a terminal QB. The circuit 15 may be, for example, a buffer circuit.

[0052] The circuit RC4 is a variation of the circuit RC1. The switches SW1-SW3 are connected to each other via different signals E 1-E3. As a result, during normal operation of the logic circuit 103, only the switch SW1 is SW1 can be turned on and SW1 can be turned off during backup operation.

[0053] Second Embodiment <<Configuration Example of Scan Flip-Flop>> A more specific circuit configuration example and a driving method example of the logic circuit 100 will be described. Here an example in which the logic circuit 100 is a scan flip-flop is shown. The scan flip flop (SFF) 110 shown in FIG. 4 has a scan flip flop (SFF) 11 and a circuit RC11. SFF11 has a selection circuit (SEL) 21 and a flip flop (FF) 31. The circuit RC11 is a holding circuit having a function of holding data. SFF110 can be called a scan FF with a backup function. SFF1 110 can be provided in a power domain where power gating is performed.

[0054] <Configuration Example of SFF11> FIG. 5 shows a circuit configuration example of SFF11. The SFF11 shown in FIG. 5 has SEL21, FF31 and terminals VH, VL, D, Q, QB, SD, SE, CK, RT.

[0055] The terminal VH is a power supply terminal for the high power supply voltage VDD, and the terminal VL is a power supply terminal for the low power supply voltage VSS. VDD and VSS are supplied to the inverter of SEL21, the inverter of FF31, and the N AND circuit (hereinafter referred to as "NAND"). The input of VDD to the terminal VH is performed via a power switch.

[0056] The terminals D and SD are data input terminals. The terminal D is electrically connected to the output terminal of a logic circuit (for example, a combinational circuit ), and data DIN is input. To the terminal SD, restoration data or scan test data SCNIN is input via the circuit RC11 (see FIG. 4). The terminal Q is a data output terminal. The terminal Q is for another SFF110 of the data output terminal. The terminal SD_IN is electrically connected to the data input terminal of the logic circuit. It outputs data that is the inverted logic of terminal Q. Terminal QB is the data input terminal of another logic circuit. The terminal QB may be provided as needed.

[0057] The terminals SE, CK, and RT are input terminals for control signals. The signal SEsig is input to the terminal CK. SE is electrically connected to SEL21. A clock signal CLK is input to the terminal CK. The terminal CK is electrically connected to the circuit 31a. The reset signal RSTsig is input to the terminal RT. The terminal RT is connected to the NAND of FF31. and is electrically connected.

[0058] (SEL21) SEL21 selects either terminal D or SD depending on the voltage (logic) of terminal SE, and It has the function of electrically connecting to the input terminal of F31. When performing a scan test, the signal S E is set to a high-level voltage ("H"), and terminal SD is electrically connected to the input terminal of FF31. To operate SFF11 as a flip-flop, set the SE pin to a low-level voltage ( Set it to "L" to electrically connect terminal D to the input terminal of FF31.

[0059] (FF31) The FF31 has two latches 32M and 33S and a circuit 31a. The latch 32M Latch 32S is the master latch, Latch 32M is the slave latch, and Latch 32S is the slave latch. 32S are electrically connected in series. Circuit 31a is a circuit for inputting a clock signal. , terminals CK1 and CKB1. The terminal CK1 outputs a non-inverted clock signal of the signal CLK. The terminal CKB1 is a terminal that outputs an inverted clock signal of the signal CLK. The terminals CK1 and CKB1 are electrically connected to the analog switches of FF31. It is being done.

[0060] <Holding circuit configuration example 1> The circuit RC11 shown in FIG. 4 includes terminals SD_IN, RE, BK, and PL, a node FN11, The circuit RC11 includes transistors M1-M3 and a capacitance element C11. In this circuit, the switches SW1-SW3 are configured with transistors M1-M3, respectively. In the following explanation, the terminal VH may be referred to as VH. The same applies to other terminals. Furthermore, node FN11 may be referred to as FN11.

[0061] SD_IN is the input terminal for scan test data SCNIN. BK and RE are control signals. BK is the input terminal for the signal that controls the backup operation (backup signal BK is electrically connected to the gates of transistors M1 and M2. A signal (restore signal REsig) that controls the restore operation is input to RE. RE is electrically connected to the gate of transistor M3.

[0062] One of the two terminals of the capacitance element C11 is electrically connected to FN11, and the other is connected to PL. Electrically connected. VSS is input to PL. Transistors M1-M3 are The transistor M1 is an n-type OS transistor. Transistor M2 is a pass transistor that electrically connects between Q and FN1. Transistor M3 is a pass transistor for electrically connecting FN1 to FN1. 1 and SD.

[0063] Since transistors M2 and M3 are OS transistors, FN11 stores the data "1". Even when the voltage of FN11 is held, the voltage drop of FN11 can be suppressed. Therefore, the circuit RC 11 can function as a non-volatile memory circuit for backing up the SFF11. In addition, power gating of semiconductor devices equipped with SFF110 becomes possible, This makes it possible to reduce the power consumption of the semiconductor device.

[0064] During the data retention period of the circuit RC11, the transistors M2 and M3 are completely turned off. Or, a voltage that causes the transistors M2 and M3 to When a back gate is provided to transistor 3, transistors M2 and M3 are normally off. In such a case, the voltage remains constant at the back gate. During this time, voltage is supplied to the circuit RC11, but almost no current flows. Therefore, the circuit RC11 consumes almost no power. is supplied to the circuit RC11, the circuit RC11 consumes almost no power. Therefore, the circuit RC11 can be said to be non-volatile.

[0065] <<Example of scan flip-flop operation>> 6 and 7 are timing charts showing an example of the operation of the SFF 110. When the semiconductor device incorporating the device 10 transitions from active mode to sleep mode, Figure 7 shows an example of the operation of the SFF110 when it transitions from sleep mode to active mode. 6 and 7 show an example of the operation of the SFF110 when the terminals VH, CK, Q, and SE ,SD, BK and RE, as well as the voltage (logic) changes at node FN11.,Fig. 6,Fig. In 7, the maximum value of the voltage is VDD and the minimum value is VSS. Also, t1-t10 are It represents the time.

[0066] <Active mode (normal operation mode)> In active mode, the SFF110 operates normally. It functions as a flip-flop that temporarily holds the output data of the logic circuit. The output data is input to terminal D. During normal operation, RE and BK are "L". Therefore, transistors M1-M3 are off. SE is at "L" and SEL21 Therefore, terminal D is connected to the input terminal of FF31. RT is "H". CK is connected to signal C. LK is input. When CK goes high, the voltage (logic) of Q changes.

[0067] <Scan mode> In scan mode, multiple SFF110s are electrically connected in series to form a scan chain In the circuit RC11, the transistors M1 and M2 are turned on, and the transistor M3 is turned off. Since SE is high, SD is set to the input of FF31 by SEL21. In other words, in scan mode, the output data of Q of SFF11 is This will be input to the SD of the next stage, SFF11.

[0068] (Scan test) To perform a scan test, put the device into scan mode and connect the first SFF1 in the scan chain. Input scan test data SCNIN to SD_IN of 10. Shifts the scan chain and transfers the scan test to SFF110 of the scan chain. Next, operate SFF110 normally and write the output data SCNIN of the logic circuit. The data is stored in SFF110. Then, the scan mode is switched back to scan mode. The data output from Q of the final stage SFF110 is used to calculate the logic circuit and It is possible to determine whether or not the SFF 110 is faulty.

[0069] (Backup Sequence) The backup sequence is performed by transitioning from active mode to sleep mode. The backup sequence includes clock gating (clock stop), Data backup and power gating (power off) are performed. When the supply is stopped, it goes into sleep mode.

[0070] In the example of Figure 6, at t1, clock gating of SFF11 starts, and in circuit RC11, The backup operation has started. Specifically, at t1, CK goes low and BK goes high. The period when BK is "H" is the backup operation period. As a result, FN11 is electrically connected to Q by the transistor M2. If Q is "1", FN11 remains "L", and if Q is "1", the voltage of FN11 rises In other words, while BK is at "H", the logic of FN11 is set to the same as Q. BK can be pulled up so that the voltage on FN11 can rise to a logic "1" level. At t2, BK is set to "L" to turn on transistors M1 and M2. By turning off FN11, FN11 is electrically floating and the circuit RC11 is in the data retention state. It becomes a state of mind.

[0071] At t3, the power supply is turned off and RT is set to "L". The VH voltage gradually drops from VDD, and V The power supply may be shut off at t2. Also, the power supply may be shut off as needed. The power domain configuration of the semiconductor device in which the SFF110 is incorporated and the sleep mode Depending on the amount of time the device is left in sleep mode, the amount of energy saved by shutting off the power may be greater than the amount of energy saved by shutting off the power. In this case, the power required to return from the standby mode to the active mode may be greater than the power required to return from the standby mode to the active mode. In this case, the power gating effect cannot be obtained, so the power supply is It is preferable to only stop the clock supply without shutting it down.

[0072] (Restore Sequence) The restore sequence from sleep mode to active mode involves turning the power on. The system starts up, restores data, and supplies the clock. , it goes into active mode.

[0073] At t4, the power supply is turned on. The VH voltage gradually rises from VSS to VDD. After reaching VDD, the restore operation starts. At t5, SE and RE are set to "H". T is also set to "H". The restore operation is performed while RE is "H". Transistor M3 turns on and connects FN11 and SD. If FN11 is "L", SD is "L". If FN11 is "H", the SD voltage rises and becomes "H". Set SE to "H". SE and SEL21 electrically connect SD to the input terminal of FF31. In other words, by setting RE to "H", the data held in FN11 is connected to S It is written to D.

[0074] At t5, it is also possible to set SE to "H" together with RE. If N11 is high, the voltage on SD rises to a logic 1 before SE is pulled high. It is preferable to set it to "H". This driving causes a through current to flow in SFF11. This can prevent this.

[0075] In order to write the data of FN11 to the SD card by capacity distribution, when FN11 is in the "H" state, When N11 is connected to SD, the voltage of FN11 drops due to the parasitic capacitance of SD. Therefore, the capacitance of C11 may need to be much larger than the parasitic capacitance of SD. The capacitance of 11 may be determined taking into consideration the characteristics of the logic circuit to which the data of SD is input. For example, if the threshold voltage of this logic circuit is VDD / 2, the capacitance of C11 is the parasitic capacitance of SD. It needs to be more than the amount.

[0076] After the logic of SD becomes the same as FN11, CK is set to “H” for a certain period (t7 to t8). In the example in Figure 7, CLK is input to CK for one clock. At t7, CK goes to "H". By this, the data in the latch 32M is written to the latch 32S. If SD is "1", Q is "1". Data is written to Q, and the CLK supply to SFF110 is stopped (it goes into sleep mode). At t9, SE and RE are set to "L" to complete the restore operation. SEL21 electrically connects D to the input terminal of FF31. Transistor M3 is turned off, and node FN11 is in a floating state.

[0077] After SE and RE are set to "L", at t10, a certain period (for example, one clock period) has elapsed. CLK input is resumed and SFF110 is set to active mode. SFF110 operates normally. Perform the work.

[0078] As mentioned above, SFF110 allows for high-speed data backup and restore. For example, backup and restore operations can be completed within a few clocks (2 to 5 clocks). The write operation of the circuit RC11 can be completed by switching the transistors M1-M3. The switching operation charges or discharges FN11. The switching operation of transistors M1 and M3 charges or discharges SD. Therefore, the energy required for these operations is small, similar to that of a DRAM cell. Therefore, there is no need to power the circuit RC1, which reduces the standby power of the SFF110. Similarly, power supply to circuit RC11 is not required during normal operation. Therefore, the dynamic power of SFF110 due to the provision of circuit RC11 is substantially By providing the circuit RC11, the parasitic capacitance of the transistor M1 is However, this is small compared to the parasitic capacitance of the logic circuit connected to terminal Q. Therefore, the normal operation of SFF110 is not affected, and the provision of circuit RC11 prevents the active This does not substantially degrade SFF110 performance in active mode.

[0079] Other examples of the circuit configuration of the holding circuit will be described below using a scan FF as an example.

[0080] <Holding circuit configuration example 2> The SFF112 shown in FIG. 8 includes a circuit RC12 and an SFF11. This is a modification of the circuit RC11 (FIG. 4), and is used to provide capacitive coupling between the node FN11 and the terminal RE. With this circuit configuration, the voltage of RE is By setting the voltage at node FN11 to VDD ("H"), the voltage at node FN11 can be increased. Therefore, the circuit RC12 can maintain the "H" voltage for a longer period of time than the circuit RC11. However, in this case, even if the node FN11 is held at a low voltage, Therefore, in this case, the voltage of the node FN11 rises. When a voltage of "0" is written to SD, the voltage of SD becomes a logical level of "0". The capacitance of the element C12 is set so that the capacitance of the capacitive element C12 is smaller than that of C11.

[0081] <Holding circuit configuration examples 3 and 4> The SFF113 shown in FIG. 9 includes circuits RC13 and SFF11. F114 has a circuit RC14 and SFF11.

[0082] In the circuit RC12 shown in Figure 8, the capacitance ratio of the capacitance elements C12 and C11 determines the node When a high voltage is written to FN11, if the voltage at SD exceeds the logic level of 1, In such a case, if the circuit RC13 or the circuit RC14 is used as the holding circuit, The circuit RC13 is obtained by adding a buffer 45 (hereinafter referred to as BUF45) to the circuit RC12. The input terminal of BUF45 is connected to the drain (or source) of transistor M3. ) and the output terminal of BUF45 is electrically connected to SD. The transistor 45 is preferably a high-voltage type that can withstand gate voltages exceeding VDD. It's nice.

[0083] The circuit RC14 shown in Fig. 10 is a modified example of the circuit RC13. The connection position of the capacitor C12 has been changed. One terminal of the capacitor C12 is connected to the transistor M The other terminal is electrically connected to the drain (or source) of BUF45. If necessary, BUF45 may be provided in the circuit RC14.

[0084] <Holding circuit configuration examples 5 and 6> The SFF 115 shown in FIG. 11 includes circuits RC15 and SFF 11. FF116 includes a circuit RC16 and an SFF11. A circuit RC15 and a circuit RC1 6 is a modification of the circuit RC11, in which the transistors M1- Has M3.

[0085] In the circuit RC15, the back gates of the transistors M1-M3 are electrically connected to the terminal OBG. A signal or a constant potential can be input to the OBG. A capacitance element may be connected to G. This capacitance element is charged, and transistors M1-M3 The back gate voltage of the transistors M1-M3 may be maintained. The voltage on the port can, for example, adjust the threshold voltage of transistors M1-M3. This becomes:

[0086] In the circuit RC16, the back gates are electrically connected to the gates of the transistors M1-M3. By using such a device structure, the on-current characteristics of the transistors M1 to M3 can be improved.

[0087] In the circuit RC15, the transistors M1-M3 are provided with back gates, but some of them are back gates. The transistor M1 may have no back gate. In this case, the back gate may be connected to the terminal OBG, or the gate of the transistor M1 may be connected to the terminal OBG. The same applies to the transistors M2 and M3. The same is true for circuit RC16.

[0088] <<Example of processing device configuration>> An example of a semiconductor device having a scan flip-flop will be described. The semiconductor device shown in FIG. The PU 200 has a function of executing instructions. The PU200 has multiple functional circuits integrated on a single chip. 00 includes a processor core 201, a power management unit (PMU) 202, a power switch (PS 13, the power supply circuit 210 includes the PU 200. The terminal 220 is a power supply terminal, and the power supply A power supply voltage VDD is input from the circuit 210. Terminals 221 and 222 are signal input terminals. A master clock signal MCLK is input to terminal 221. A signal IN T is input. The signal INT is an interrupt signal that requests interrupt processing. are input to the processor core 201 and the PMU 202.

[0089] <Processor core> The processor core 201 is a circuit that has the function of processing instructions. It can also be called a processing circuit or a processor (processing device). 1 has a logic circuit 240 and an SFF (scan FF) 250, etc. For example, the logic circuit 240 is a combinational circuit. For example, SFF250 is included in the register. SFF250 is included in the register. 0 and circuit RC50. SFF50 only needs to have the function of a scan FF. It can be configured using scan flip-flops available in the standard circuit library. Circuit RC50 is a backup holding circuit for SFF50, and circuits RC11-RC14 The terminal Q of the SFF 250 is electrically connected to the input terminal of the logic circuit 240. and to configure the scan chain, the SD_IN pin of other SFF250 The SFF250 is electrically connected to the processor core 201. Clock gating and power gating are possible, reducing the power consumption of the PU200. It can be reduced.

[0090] FIG. 14 shows an example of the configuration of the processor core 201. The processor core 201 shown in FIG. A control unit 231, a program counter 232, a pipeline register 233, a pipeline register 234, register file 235, ALU (arithmetic logic unit) 236, and and a data bus 237. The processor core 201 and peripherals such as the PMU 202 and cache are Data is exchanged with the edge circuit via a data bus 237 .

[0091] The control unit 231 includes a program counter 232, a pipeline register 233, a pipeline Operation of the in-register 234, register file 235, ALU 236, and data bus 237 By controlling the entire system, the instructions contained in the input application and other programs can be ALU236 has the function of decoding and executing instructions. The program counter 232 has the function of performing seed calculations. It is a register that has the function of storing addresses.

[0092] The pipeline register 233 is a register that has the function of temporarily storing instruction data. The register file 235 has a plurality of registers including general-purpose registers. Data read from in-memory or data obtained as a result of ALU236 arithmetic processing The pipeline register 234 can store the operation data of the ALU 236. Data used for processing or data obtained by ALU236 arithmetic processing etc. It is a register that has the function of automatically storing data.

[0093] <Power management> PMU202 has the function of controlling power gating, clock gating, etc. More specifically, the PMU 202 controls the processor core 201, the PSW 203, the clock control The PMU 202 has a function of controlling the processor core 2. 01 has the function of outputting control signals such as BKsig, REsig, and SEsig.

[0094] The PMU 202 has a circuit 205. The circuit 205 has a function of measuring time. The PMU 202 performs power management based on the time-related data obtained from the circuit 205. For example, by using the circuit 205 as a timer circuit, the PM U202 may generate a timer interrupt request signal. Just set it to 05.

[0095] The PSW 203 controls the supply of VDD to the PU 200 according to the control signal from the PMU 202. In the example of FIG. 13, the processor core 201 has a function of being able to operate in multiple power domains. In this case, the PSW 203 controls power supply to multiple power domains. The processor core 201 can be controlled independently of the power supply. In this case, the power domain may have a power domain in which no power is being assigned. VDD may be supplied without going through the PSW203.

[0096] The clock control circuit 204 generates a gated clock signal from the signal MCLK and outputs The clock control circuit 204 controls the processor in accordance with the control signal from the PMU 202. The power supply circuit has a function of cutting off the supply of clock signals to the clock core 201. 210 has a function to change the magnitude of VDD according to the control signal of PMU 202. That's fine.

[0097] The signal SLP is output from the processor core 201 to the PMU 202. This signal serves as a trigger for switching processor core 201 to sleep mode. According to P, the processor core 201 executes the backup sequence of SFF250. The backup sequence for SFF250 is the same as that for SFF110 shown in Figure 6. The PMU202 can perform the same backup sequence as the SLP signal. When this signal is input, it controls the control signal to transition from active mode to sleep mode. The PMU 202 controls the clock control circuit 204 and outputs the Stop supplying the clock signal to the SACOA 201. Also, the PMU 202 controls the PSW 203 and stops supplying power to the processor core 201.

[0098] The process for returning the processor core 201 from the sleep mode to the active mode is executed by the input of the signal INT. According to the signal INT, in the processor core 201, the S restore sequence of the SFF 250 is executed. The restore sequence of the SFF 250 can be executed in the same manner as the restore sequence of the SFF 110 shown in FIG. 7. When the signal INT is input, the PMU 202 outputs a control signal for transitioning from the sleep mode to the active mode to the functional circuit to be controlled. The PMU 202 controls the PSW 20 3 to resume supplying power to the processor core 201, and also controls the clock control circuit 204 to resume supplying the clock signal to the processor core 201.

[0099] The backup sequence may be made executable by triggering on the signal INT or the interrupt request signal of the PMU 202. Also, the restore sequence may be made executable by triggering on the interrupt request signal of the PMU 2 02.

[0100] <<Device Structure of SFF250>> FIG. 15 shows the device structure of the SFF 250. In FIG. 15, the circuit RC50 has the same circuit configuration as the circuit RC 11 (FIG. 4). The transistors M1 - M3 are OS transistors. The SFF 250 can have a three - dimensional device structure in which the circuit RC50 is stacked on the SFF50. [[ID=​​​​​​are the first wiring layer, the kth wiring layer, The k+1th wiring layer and the hth wiring layer are the same. k is an integer equal to or greater than 1, and h is an integer equal to or greater than k+2. The terminals D, SD, Q, SE, and CK of SFF50 are on the wiring layer W. k Circuit RC5 The terminal SD_IN of 0 is on the wiring layer W h It is set up in.

[0101] The FET layer 260 is provided with SFF50 transistors. The transistors can be fabricated using a standard CMOS process. k to the conductor Therefore, the transistors in the FET layer 260 are electrically connected. k+1 -W h of The conductor electrically connects the SFF50 and the circuit RC50.

[0102] The number of elements in the RC50 circuit is much smaller than that in the SFF50 circuit. No changes to the circuit configuration and layout of the SFF50 are required to achieve this. 50 is a highly versatile backup circuit. Since the circuit RC50 can be provided within the area, even if the circuit RC50 is mounted, the SFF The area overhead of 250 is zero.

[0103] <<An integrated circuit incorporating the RC50 circuit>> Therefore, in the processor core 201 shown in FIG. 13, the circuit RC50 is not affected by the arrangement of the SFF50. The SFF50 can be positioned to allow efficient scan testing without impacting the system. In other words, by using the circuit RC50 as a backup circuit, The integrated circuit can be easily designed and testability can be ensured.

[0104] In the processor core 201, like the SFF50, other standard cells such as NAND circuits are used. The FET layer 260 and the wiring layer W1-W k The wiring layer W1-W k circuit Conductors are formed to connect RC50 to terminals SD and Q, so other standards The cell wiring must be laid out to bypass these conductors, which The area of ​​the processor core 201 may increase. It is one of the standard cells that is often installed, but the SFF250 by installing the circuit RC50 Therefore, the area overhead of the processor core 201 is 0. This is due only to changes in the layout of the wiring between standard cells, and the processor core 20 The area overhead of circuit RC5 can be suppressed to less than a few percent. We confirmed this by designing a processor core equipped with IEEE 802.11b. We confirmed that the processor core installed in the RC50 is energy-efficient.

[0105] <Processor core area and power> We designed a processor core equipped with a scan flip-flop with the RC50 circuit. Let us call the SA-CORE an "OS-FF equipped processor" and use a scan For comparison, we will refer to a scan FF without the RC50 circuit. We have designed a CPU core equipped with this technology. We call this processor core the "Si-FF equipped processor." We will do so.

[0106] The designed processor core is a RISC processor core. The circuit configuration of the Si-FF equipped processor is the same as that of the Si-FF equipped processor except for the presence or absence of the circuit RC50. All circuits except for circuit RC50 are composed of Si transistors. The design rule for the OS transistor is 60 nm channel length. The processor core was designed using the Si-FF. The area of ​​the OS-FF processor is 275 μm x 272 μm. The OS-FF occupies nearly half of the logic circuit of the processor core. Even if each scan flip-flop is equipped with a circuit RC50, the area overhead is limited to 3%. It is assumed.

[0107] In the simulation, the dynamic range of the Si-FF processor was The dynamic power consumption of the OS-FF processor is 19μA / MHz. The dynamic power consumption is 19μA / MHz, and the dynamic power consumption is not increased by incorporating the RC50 circuit. In addition, when power gating is performed, the standby power consumption of the processor equipped with OS-FF is 0 It was estimated to be .03μA.

[0108] The performance of the designed OS-FF was confirmed by simulation. When the length is 65 nm and the threshold voltage is 1.6 V, the The retention time is over 30 days. It was confirmed that FF has sufficient retention performance as a non-volatile memory circuit.

[0109] In the simulation, the backup time of the OS-FF at an operating frequency of 50 MHz and The power consumption and restore time are two clocks. Since the overhead time due to the scheduling operation is sufficiently short, OS-FF It has been confirmed that the performance of

[0110] Simulation results show the power saving effect of power gating on processors with OS-FF. The active period is 1msec, the sleep period is 1msec, and the The power consumption was estimated for each operating condition of 100 seconds. 1.2V. Under operating condition 1 (active period 1msec, sleep period 1msec) The power consumption is 570 μW. The power consumption under operating condition 3 (active period 1 msec, The power consumption during the sleep period (100 seconds) is 0.05 μW. Gating can effectively reduce the power consumption of processors equipped with OS-FF. It was confirmed that...

[0111] The scan FF of this embodiment has a holding circuit, and thus has the following excellent effects: In this scan FF, the area overhead caused by the holding circuit is 0. By providing a holding circuit, power consumption during normal operation is approximately Low power consumption and high speed buffering are possible without any degradation in normal operation performance. It is possible to back up and restore data without supplying power. In addition, this scan FF can be designed by directly using the scan FF in the circuit library. Therefore, an integrated circuit equipped with this scan FF can be ,Even if a scan chain is constructed using this scan FF, testability is not impaired. .

[0112] Thus, this scanning FF is highly suitable for normally-off computing. Even with this scan FF installed, there is almost no increase in the dynamic power consumption of the integrated circuit or degradation in performance. Therefore, it is possible to prevent this from occurring. The power consumption of integrated circuits can be effectively reduced by power gating while maintaining performance. It is possible to do this.

[0113] Here, the sequential circuit is explained as a scan FF, but the above-mentioned effect can be obtained with other sequential circuits. You can get results.

[0114] Third Embodiment In this embodiment, an electronic component and an electronic device including the electronic component are used as an example of a semiconductor device. We will explain about the equipment, etc.

[0115] <Example of how to manufacture electronic components> FIG. 16A is a flowchart showing an example of a method for manufacturing an electronic component. This electronic component is also called a package or IC package. There are multiple standards and names depending on the shape of the device. I will explain about this.

[0116] Semiconductor devices made up of transistors are assembled through a post-assembly process and then printed on a printed circuit board. The assembly is completed by assembling multiple detachable parts. Specifically, the element substrate obtained in the previous process is After the substrate is formed (step S1), the back surface of the substrate is ground (step S2). By making the film thinner, warping of the substrate during pre-processing can be reduced, and components can be made smaller.

[0117] The back surface of the substrate is ground and a dicing process is performed to separate the substrate into multiple chips. Die bonding involves picking up individual chips, mounting them on a lead frame, and bonding them together. The die bonding process is performed (step S3). The adhesive method should be selected according to the product. For example, adhesives can be made with resin or tape. In the die bonding process, the chip may be mounted on the interposer and bonded. In the wire bonding process, the leads of the lead frame and the electrodes on the chip are connected by metal wires. Electrical connection is made with thin wires (step S4). The thin metal wires are silver wires or gold wires. Wire bonding can be used in ball bonding and wedge bonding. Either of the above is acceptable.

[0118] The wire-bonded chip is then sealed with epoxy resin or other materials in a molding process. (Step S5). The molding process fills the interior of the electronic component with resin. It can reduce damage to the built-in circuitry and wires caused by external mechanical forces. It is also possible to reduce the deterioration of characteristics due to moisture and dust. Then, the leads are cut and shaped (step S6). This prevents the leads from rusting and allows for more reliable soldering when mounting on a printed circuit board later. The surface of the package is printed (marked) (Step S7). After the process (step S8), the electronic component is completed (step S9). By incorporating such a semiconductor device, it is possible to provide a small electronic component with low power consumption. do.

[0119] A perspective schematic diagram of the completed electronic component is shown in FIG. 16B. In FIG. 16B, 16B shows a perspective schematic diagram of a QFP (Quad Flat Package). As shown in FIG. 7, the electronic component 7000 has leads 7001 and a circuit portion 7003. The unit 7003 includes, for example, the scan flip-flop (SFF) of the second embodiment and other logic circuits. The electronic component 7000 is mounted on, for example, a printed circuit board 7002. A plurality of such electronic components 7000 are combined together, and each is electrically connected to a printed circuit board 7002. The completed circuit board 7004 is For example, the electronic component 7000 is a RAM for storing data. Random access memory, CPU, MCU (microcontroller unit), FPGA, It can be used in processing units that perform various processes, such as line ICs. By incorporating product 7000, it is possible to reduce the power consumption of electronic devices. This makes it easier to miniaturize the sub-devices.

[0120] Therefore, the electronic component 7000 is suitable for digital signal processing, software radio, avionics (communications electronic equipment related to aviation, such as communication equipment, navigation systems, autopilots, and flight management systems; ASIC prototyping, medical image processing, speech recognition, cryptography, bioinformatics (bioinformatics), mechanical device emulators, and radio telescopes in radio astronomy It can be applied to electronic components (IC chips) in a wide range of electronic devices. Such electronic devices include display devices, personal computers (PCs), and devices equipped with recording media. Image playback devices (recording media such as DVD, Blu-ray disc, flash memory, HDD, etc.) and devices having a display unit for displaying images). Other electronic devices that can use the electronic component according to an embodiment of the present invention include a mobile phone. Telephones, game consoles including portable ones, portable data terminals, e-book terminals, cameras (video cameras, Digital still cameras, etc.), wearable display devices (head-mounted, goggles, Glasses, armbands, bracelets, necklaces, etc.), navigation systems, audio playback Live equipment (car audio, digital audio players, etc.), copiers, facsimiles, Examples include printers, printer-combined devices, automated teller machines (ATMs), and vending machines. Specific examples of these electronic devices are shown in Figure 17.

[0121] The portable game machine 900 shown in FIG. 17A includes a housing 901, a housing 902, a display unit 903, and a display 904, a microphone 905, a speaker 906, operation keys 907, and a stylus 9 It has 08 etc.

[0122] The mobile information terminal 910 shown in FIG. 17B includes a housing 911, a housing 912, a display unit 913, and a display unit The display unit 913 is attached to the housing 911. The display unit 914 is provided in the housing 912. and the housing 912 are connected, and the angle between the housing 911 and the housing 912 is adjusted by the connecting portion 915. Therefore, the connection between the housing 911 and the housing 912 at the connection portion 915 can be changed. It may be configured to switch the image displayed on the display unit 913 according to the angle. Also, a display device with a touch panel may be used for the display unit 913 and / or the display unit 914. .

[0123] The notebook PC 920 shown in FIG. 17C includes a housing 921, a display unit 922, a keyboard 923, and a pointing device 924, etc.

[0124] The electric refrigerator 930 shown in FIG. 17D includes a housing 931, a refrigerator door 932, and a freezer door 933, etc.

[0125] The video camera 940 shown in FIG. 17E includes a housing 941, a housing 942, a display unit 943, an operation key 944, a lens 945, and a connection part 946, etc. The operation key 944 and the lens 945 are provided on the housing 941, and the display unit 943 is provided on the housing 942. Then the housing 941 and the housing 942 are connected by the connection part 946, and the connection part 94 6 has a structure that enables the angle between the housing 941 and the housing 942 to be changed. The angle of the housing 942 with respect to the housing 941 may be used to change the orientation of the image displayed on the display unit 943, switch the display / non-display of the image, etc.

[0126] The automobile 950 shown in FIG. 17F includes a vehicle body 951, wheels 952, a dashboard 953, and headlights 954, etc.

[0127] [Embodiment 4] In this embodiment, an oxide semiconductor, an OS transistor, etc. will be described.

[0128] <<Configuration Example 1 of OS Transistor>> FIG. 18A shows an example of the structure of an OS transistor. 18B is a cross-sectional view taken along line y1-y2, and FIG. 18C is a cross-sectional view taken along line x1-x2. 18D is a cross-sectional view taken along the line x3-x4. is sometimes called the channel length direction, and the x1-x2 line direction is sometimes called the channel width direction. 18B is a cross-sectional view of an OS transistor in the channel length direction, and FIG. 18C is a cross-sectional view of an OS transistor in the channel length direction. 18D is a cross-sectional view of an OS transistor taken along a channel width direction. To clarify the device structure, some components are omitted in FIG. 18A.

[0129] The OS transistor 501 is formed on an insulating surface. The insulating layer 511 is formed on the surface of the substrate 510. The OS transistor 501 includes: The insulating layer 514 and the insulating layer 515 are covered with O The OS transistor 501 can also be regarded as a component of the OS transistor 501. an insulating layer 512, an insulating layer 513, oxide semiconductor (OS) layers 521-523, a conductive layer 530, The insulating layer 513 functions as a gate insulating layer. The conductive layer 530 functions as a gate electrode. The S layer 522 and the OS layer 523 are collectively referred to as the OS layer 520 .

[0130] As shown in FIGS. 18B and 18C, the OS layer 520 includes an OS layer 521, an OS layer 522, an OS layer 523, an OS layer 524, an OS layer 525, an OS layer 526, an OS layer 527, an OS layer 528, an OS layer 529, an OS layer 530, an OS layer 531, an OS layer 532, an OS layer 533, The insulating layer 513 covers the laminated portion. The conductive layer 531 overlaps the laminated portion via the insulating layer 513. 2 is provided on a stack of OS layers 521 and 523. In the example of FIG. 18, the conductive layer The OS layers 541 and 542 are also in contact with the insulating layer 512. The OS layer 523 is The OS layer 523 is formed to cover the conductive layers 541 and 542. It is in contact with the top surface of layer 522.

[0131] In the OS layer 520, the channel of the stacked portion of the OS layers 521-523 is formed through the insulating layer 513. A conductive layer 530 is formed so as to surround the panel in the width direction (see FIG. 18C). Therefore, the gate electric field is applied to this stacked portion from both the vertical and lateral directions. In the OS transistor 501, the gate electric field is the electric field generated by the conductive layer 530 (gate electrode The electric field formed by the voltage applied to the gate electrode (layer) is called the gate electric field. , the entire stack of OS layers 521-523 can be electrically surrounded. A channel may be formed in the entire (bulk) of 22. The capacitor 501 can have a high on-current.

[0132] In this specification, a transistor capable of electrically surrounding a semiconductor by a gate electric field is used. The transistor structure is called "surrounded channel (s-channel)" The OS transistor 501 has an s-channel structure. The nel structure allows a large current to flow between the source and drain of the transistor, In this state, the drain current (on-state current) can be increased.

[0133] By forming the OS transistor 501 in an s-channel structure, the side surface of the OS layer 522 Since a gate electric field can be applied to the conductive layer, it becomes easier to control the channel formation region. In a structure in which the insulating layer 530 extends below the OS layer 522 and faces the side surface of the OS layer 521, As a result, the subthreshold voltage of the OS transistor 501 is The swing value (also called the S value) can be reduced, suppressing the short channel effect. Therefore, this structure is suitable for miniaturization.

[0134] The OS transistor can have a three-dimensional device structure, such as the OS transistor 501. By miniaturizing OS transistors, the channel length can be reduced to less than 100 nm. This allows the circuit area to be reduced. The channel length of the OS transistor is set to less than 65 nm. It is preferable that the channel length is 30 nm or less, and more preferably 20 nm or less. Both should be set to 10 nm.

[0135] The conductor that functions as the gate of the transistor is the gate electrode, and the source of the transistor is the The conductor that functions as the source electrode is the transistor's drain. The electrode, the region that functions as the source of the transistor, is the source region, and the transistor's drain region is the In this specification, the gate electrode is referred to as the gate, and the drain is referred to as the The drain electrode or drain region is referred to as the drain, and the source electrode or source region is referred to as the source. There are cases where this happens.

[0136] The channel length is, for example, the length of the semiconductor (or transistor) The area where the gate electrode overlaps with the gate electrode (the area in the semiconductor through which current flows when the semiconductor is in the on state), refers to the distance between the source and drain in the region where the channel is formed. In a single transistor, the channel length does not necessarily have the same value in all regions. However, the channel length of a transistor may not be determined to a single value. In the specification, the channel length is any one value, maximum The value may be a minimum or average value.

[0137] The channel width is the width of the semiconductor (or transistor) when it is in the on state. In the region where the gate electrode overlaps with the current flowing part, or in the region where the channel is formed, This refers to the length of the part where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. The channel width is one of the values, the maximum value, and the minimum value in the region where the channel is formed. Or the average value.

[0138] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. The effective channel width of the channel that is actually formed is larger than the apparent channel width that is The larger the

[0139] In a transistor having a three-dimensional structure, the effective channel width is measured For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0140] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are overlapped. The apparent channel length is the length of the area where the source and drain face each other. The channel width is defined as the "surrounded channel width (SCW)". In this specification, when simply referred to as channel width, may refer to enclosed channel width or apparent channel width. In this document, when simply referring to channel width, it may refer to the effective channel width. Channel length, channel width, effective channel width, apparent channel width, enclosure channel The channel width can be determined by acquiring a cross-sectional TEM image and analyzing the image. A value can be determined.

[0141] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0142] <Substrate> The substrate 510 is not limited to being a simple support material, but also includes a substrate on which other devices such as transistors are formed. In this case, the conductive layer 530 and the conductive layer 541 of the OS transistor 501 may be a substrate. , and one of the conductive layers 542 may be electrically connected to the other devices described above.

[0143] <Base insulation layer> The insulating layer 511 serves to prevent the diffusion of impurities from the substrate 510. The insulating layer 51 preferably serves to supply oxygen to the OS layer 520. 2 is preferably an insulating film containing oxygen, and the insulating film contains oxygen in an amount greater than the stoichiometric composition. For example, TDS (Thermal Desorption Spectroscopy: Thermal Desorption Spectroscopy) showed that the surface temperature of the film was 100°C or higher. The amount of oxygen molecules released in the range of 100°C to 500°C or 700°C to 100°C is .0×10 18 [molecules / cm 3 The substrate 510 is a film on which other devices are formed. If the substrate is a polished substrate, the insulating layer 511 is polished by chemical mechanical polishing (CMP) to make the surface flat. It is preferable to perform a flattening process using a method such as mechanical polishing. It's nice.

[0144] The insulating layers 511 and 512 are made of aluminum oxide, aluminum oxynitride, or magnesium oxide. , silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide Yttrium oxide, Zirconium oxide, Lanthanum oxide, Neodymium oxide, Hafnium oxide and insulating materials such as tantalum oxide, silicon nitride, aluminum oxide nitride, or It can be formed using a mixture of these materials.

[0145] <Gate electrode> The conductive layer 530 may be made of copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), Aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel Ni, chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co) , ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt) It can be made of any metal, or their alloy, or a compound that has these as its main component. preferable.

[0146] The conductive layer 530 may have a single layer structure or a stacked structure of two or more layers. Single layer structure of aluminum film containing titanium, and double layer structure of titanium film laminated on aluminum film , a two-layer structure in which a titanium film is laminated on a titanium nitride film, and a tungsten film is laminated on a titanium nitride film. A two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. The titanium film is then laminated with an aluminum film, and the titanium film is then laminated with an aluminum film. Three-layer structure forming a titanium film, single-layer structure of Cu-Mn alloy film, Cu film on Cu-Mn alloy film A two-layer structure in which a Cu film is laminated on a Cu-Mn alloy film, and a Cu-Mn film is laminated on top of that. There are three-layer structures in which alloy films are stacked. In particular, Cu-Mn alloy films have low electrical resistance and Manganese oxide is formed at the interface with the insulating film containing oxygen, preventing Cu diffusion. preferable.

[0147] The conductive layer 530 may be made of indium tin oxide or indium oxide containing tungsten oxide. Indium zinc oxide containing tungsten oxide, Indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, and silicon oxide are added to titanium oxide. A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element may also be used.

[0148] <Gate insulating layer> The insulating layer 513 is formed of an insulating film having a single layer structure or a stacked layer structure. Aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon oxide nitride silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide Contains one or more of ammonium, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide An insulating film can be used. The insulating layer 513 may also be a stack of the above materials. The insulating layer 513 is doped with lanthanum (La), nitrogen, zirconium (Zr), etc. as impurities. The insulating layer 511 can be formed in the same manner as the insulating layer 513. The insulating layer 511 contains, for example, oxygen, nitrogen, silicon, hafnium, etc. Preferably, the insulating layer includes hafnium oxide and silicon oxide or silicon oxynitride.

[0149] Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. In addition, compared to the case where silicon oxide is used, the thickness of the insulating layer 513 can be increased. This reduces the leakage current due to the transistor current. Furthermore, hafnium oxide, which has a crystalline structure, can be used to form amorphous structures. Therefore, the off-state current is small. To form a transistor, it is preferable to use hafnium oxide having a crystalline structure. Examples of the crystal structure include monoclinic and cubic crystals. The types are not limited to these.

[0150] <Source electrode, drain electrode, back gate electrode> The conductive layers 541 and 542 can be fabricated in the same manner as the conductive layer 530. The n-alloy film has low electrical resistance, and when provided in contact with the oxide semiconductor film, Manganese oxide can be formed at the interface with the film, and the presence of manganese oxide facilitates the diffusion of Cu. Therefore, when the Cu-Mn alloy layer is used for the conductive layer 541 and the conductive layer 542, In addition, it is preferable that the conductive layer 531 (FIG. 20A) described later is also formed by the same method as the conductive layer 530. It can be made.

[0151] <Protective insulating film> The insulating layer 514 can block oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing such an insulating layer 514, the OS layer 52 Prevents oxygen from diffusing from the outside and prevents hydrogen, water, etc. from entering the OS layer 520 from the outside. The insulating layer 514 can be, for example, a nitride insulating film. The nitride insulating film may be silicon nitride, silicon nitride oxide, aluminum nitride, or nitride oxide. Aluminum, etc. In addition, oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. Instead of a nitride insulating film with a blocking effect, a material with a blocking effect against oxygen, hydrogen, water, etc. An oxide insulating film having an acid having a blocking effect against oxygen, hydrogen, water, and the like may be provided. Examples of oxide insulating films include aluminum oxide, aluminum oxynitride, gallium oxide, and oxynitride. Gallium oxide, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride There are nium etc.

[0152] The aluminum oxide film is permeable to both impurities such as hydrogen and moisture, and oxygen. Therefore, aluminum oxide is preferable for use as the insulating layer 514 because it has a high blocking effect. The aluminum film improves the electrical characteristics of the transistor during and after the transistor manufacturing process. Preventing impurities such as hydrogen and moisture, which cause fluctuations in the properties, from entering the OS layer 520 Preventing release of oxygen from the oxide semiconductor, which is the main component material constituting the insulating layer 512 It is suitable for use as a protective film that has the effect of preventing unnecessary release of oxygen. Oxygen contained in the aluminum film can also be diffused into the oxide semiconductor.

[0153] <Interlayer insulating film> In addition, an insulating layer 515 is preferably formed over the insulating layer 514. The insulating film can be formed of a single layer or a laminated structure. Nesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gas oxide Sodium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, An insulating film containing one or more of neodymium oxide, hafnium oxide, and tantalum oxide can be used. do.

[0154] <Oxide semiconductor layer> The semiconductor material of the OS layers 521-523 is typically In-Ga oxide, In-Z n oxide, In-M-Zn oxide (M is Ga, Y, Sn, Zr, La, Ce, or N The element M is, for example, an element having a high bond energy with oxygen, or It is an element whose bond energy with oxygen is higher than that of indium, or an oxide semiconductor element. The OS layers 521-523 are elements that have the function of widening the energy gap. The OS layers 521-523 are not limited to oxide layers containing indium. It can be formed of Sn oxide, Ga-Sn oxide, Zn-Mg oxide, etc. The S layer 522 is preferably formed of an In-M-Zn oxide. The OS layers 523 may each be formed of a Ga oxide.

[0155] The OS layer 522 is not limited to an oxide semiconductor containing indium. For example, an oxide containing at least one of zinc, gallium, and tin without containing indium. It may also be a semiconductor (for example, zinc tin oxide, gallium tin oxide), etc.

[0156] The OS layer 522 may be formed of, for example, an oxide with a wide energy gap. The energy gap of 522 is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2 The value is preferably 0.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0157] The OS layer 522 is preferably a CAAC-OS film, which will be described later. The OS layer 522 preferably contains Zn because the OS layer 522 may be easily crystallized if it contains Zn. .

[0158] When an interface state is formed at the interface between the OS layer 522 and the OS layer 521, chaotic states are also generated in the region near the interface. The formation of a channel region causes a change in the threshold voltage of the OS transistor 501. Therefore, OS layer 521 contains at least one of the metal elements constituting OS layer 522. As a result, the interface between the OS layer 522 and the OS layer 523 is The formation of a level becomes difficult, and the electrical characteristics of the OS transistor 501, such as the threshold voltage, vary. can be reduced.

[0159] OS layer 523 contains at least one of the metal elements constituting OS layer 522. This reduces the amount of interface scattering at the interface between the OS layer 522 and the OS layer 523. This makes it difficult for the carrier movement to be hindered, and therefore the OS transistor 501 The field effect mobility of the GaN can be increased.

[0160] The OS layer 521, the OS layer 522, and the OS layer 523 preferably contain at least indium. When the OS layer 521 is an In-M-Zn oxide, the sum of In and M is 100a. When the atomic percentage is 50 atomic %, preferably In is less than 50 atomic % and M is 50 atomic %. ic%, more preferably In is less than 25 atomic % and M is 75 atomic % When the OS layer 522 is an In-M-Zn oxide, the In and M When the sum of these is 100 atomic %, preferably In is higher than 25 atomic %. , M is less than 75 atomic %, more preferably In is higher than 34 atomic %, M is less than 66 atomic %. When the OS layer 523 is an In-M-Zn oxide, When the sum of In and M is 100 atomic %, In is preferably 50 atomic %. ic%, M is higher than 50 atomic %, and more preferably In is 25 atomic % c% or less, and M is higher than 75 atomic %. Alternatively, the OS layer 521 and / or the OS layer 523 may be formed of the same oxide. For example, the OS layer 521 and / or the OS layer 522 may not contain indium. The OS layer 523 can be made of gallium oxide.

[0161] Of the OS layers 521 to 523, the OS layer 522 preferably has the highest carrier mobility. This allows a channel to be formed in the OS layer 522 that is separated from the insulating layer 511. can.

[0162] For example, oxides containing In, such as In-M-Zn oxide, can be made more resistant to oxidation by increasing the In content. In the In-M-Zn oxide, the carrier mobility is mainly increased by the s orbital of the heavy metal. contributes to carrier conduction, and by increasing the indium content, Because of the overlap of the s orbitals, oxides with a high indium content tend to be more stable than oxides with a low indium content. Therefore, the oxide semiconductor film has a high indium content. By using a thin oxide, the carrier mobility can be increased.

[0163] When an oxide semiconductor film is formed by a sputtering method, the surface of the substrate on which the film is to be formed is heated, Or, due to the influence of space heating, the composition of the source target and the composition of the film are different. For example, when an In-Ga-Zn oxide target is used, the zinc oxide is Since it is easier to sublimate than indium oxide or gallium oxide, the source and In-Ga-Z The composition of the In-Ga-Zn oxide film is likely to differ from that of the n-oxide film. Therefore, the Zn content is lower than that of the source. It is preferable to select a source that has a high composition ratio. The difference in composition between the source and the film can be controlled by factors other than temperature. It also changes depending on the pressure and the gas used for film formation.

[0164] When the OS layer 522 is an In-M-Zn oxide formed by a sputtering method, The atomic ratio of metal elements in the target used to form a Zn oxide film is In:M:Zn, Preferred are 1:1:1, 3:1:2, or 4:2:4.1. For example, In:M:Zn= Atomic ratio of metal elements contained in semiconductor film deposited using a target of 4:2:4.1 is approximately In:M:Zn=4:2:3.

[0165] The OS layer 521 and the OS layer 523 are made of In-M-Zn oxide by sputtering. In this case, the atomic ratio I of the metal elements in the target used to form the In-M-Zn oxide film is The ratio of n:M:Zn is preferably 1:3:2 or 1:3:4.

[0166] When an oxide semiconductor film is formed by a sputtering method, a power supply for generating plasma is required. The power supply may be an RF power supply, an AC power supply, a DC power supply, or the like. The targeting gas is preferably a rare gas (typically argon), oxygen, or a mixture of rare gas and oxygen. In the case of a mixture of rare gas and oxygen, the ratio of oxygen to rare gas should be increased. In addition, the target is preferably selected appropriately according to the composition of the oxide semiconductor to be formed. Just choose.

[0167] In order to obtain a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor, It is necessary not only to evacuate the atmosphere to a high vacuum, but also to highly purify the sputtering gas. The oxygen gas or argon gas used has a dew point of -40°C or less, preferably -80°C or less, more preferably Preferably, a gas purified to a temperature of -100°C or less, more preferably -120°C or less, is used. By doing so, it is possible to prevent moisture and the like from being taken into the oxide semiconductor as much as possible.

[0168] <Energy band structure> Next, an OS layer 521, an OS layer 522, and an OS layer 523 are stacked. The function and effect of 520 will be explained using the energy band structure diagram shown in Figure 19B. FIG. 19A is an enlarged view of the channel region of OS transistor 501. 19B is a partially enlarged view of the area indicated by the dotted line z1-z2 in FIG. 19A (OS The energy band structure of the channel formation region of the transistor 501 is shown below. Although the transistor 501 will be described as an example, the same applies to the OS transistors 502-506.

[0169] In Figure 19B, Ec512, Ec521, Ec522, Ec523, and Ec513 are The conduction bands of the insulating layer 512, the OS layer 521, the OS layer 522, the OS layer 523, and the insulating layer 513 are The energy at the lower end is shown.

[0170] Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also called "electron affinity") is The energy difference between the empty level and the top of the valence band (also called the ionization potential) The energy gap is calculated by subtracting the energy gap. Measurement can be performed using a HORIBA JOBIN YVON UT-300. The energy difference between the unoccupied level and the top of the valence band was measured by ultraviolet photoelectron spectroscopy (UPS). iolet Photoelectron Spectroscopy (PHI) Measurements can be performed using a VersaProbe.

[0171] Since the insulating layers 512 and 513 are insulators, Ec513 and Ec512 are It is closer to the vacuum level (has lower electron affinity) than 1, Ec522, and Ec523.

[0172] The OS layer 522 is an oxide layer having a higher electron affinity than the OS layers 521 and 523. For example, the OS layer 522 has a higher electron affinity than the OS layers 521 and 523. 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, Preferably, an oxide having an electron affinity of 0.15 eV or more and 0.4 eV or less is used. , the energy difference between the vacuum level and the bottom of the conduction band.

[0173] When a voltage is applied to the gate (conductive layer 530) of the OS transistor 501, the OS layer 521, Of the OS layer 522 and the OS layer 523, a channel is formed in the OS layer 522 having a larger electron affinity. will be done.

[0174] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the OS layer 523 preferably contains indium gallium oxide. Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably At most, 90% or more.

[0175] Also, Ec521 is closer to the vacuum level than Ec522. Specifically, Ec521 is closer to the vacuum level than E More than 0.05eV, more than 0.07eV, more than 0.1eV or more than 0.15eV than C522 V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less at the vacuum level Preferably close.

[0176] Also, Ec523 is closer to the vacuum level than Ec522. Specifically, Ec523 is closer to the vacuum level than E More than 0.05eV, more than 0.07eV, more than 0.1eV or more than 0.15eV than C522 V or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less at the vacuum level Preferably close.

[0177] In addition, a mixed region of the OS layer 521 and the OS layer 522 is formed between the OS layer 521 and the OS layer 522. In addition, there may be a case where the OS layer 523 and the OS layer 522 are connected to each other. There may be an intermixed region of layer 522. The intermixed region has a lower interface state density and therefore The stack of OS layers 521-523 (OS layer 520) has an energy density near each interface. This results in a band structure in which the energy changes continuously (also called a continuous junction).

[0178] In the OS layer 520 having such an energy band structure, electrons pass through the OS layer 522. Therefore, the interface between the OS layer 521 and the insulating layer 512 and the interface between the OS layer 521 and the insulating layer 512 are mainly moved. Even if a level exists at the interface between the OS layer 523 and the insulating layer 513, the interface level As a result, the movement of electrons in the OS layer 520 is less likely to be hindered, and the OS transistor The on-current of the gate 501 can be increased.

[0179] 19B, the vicinity of the interface between the OS layer 521 and the insulating layer 512 and the OS layer 521 In the vicinity of the interface between the semiconductor layer 23 and the insulating layer 513, there are trap levels E due to impurities and defects. Although t502 may be formed, due to the presence of OS layer 521 and OS layer 523, The OS layer 522 can be separated from the trap level Et 502. In the channel width direction, the top and side surfaces of the OS layer 522 are in contact with the OS layer 523. The lower surface of the S layer 522 is formed in contact with the OS layer 521 (see FIG. 18C). By covering the OS layer 522 with the OS layer 521 and the OS layer 523, the trap level E The effect of t502 can be further reduced.

[0180] However, if the energy difference between Ec521 or Ec523 and Ec522 is small, O Electrons in the S layer 522 may exceed the energy difference and reach the trap level. When electrons are captured in the level, a negative fixed charge is generated at the interface of the insulating film, and the transistor The threshold voltage of the capacitor is shifted in the positive direction. and Ec522 are each 0.1 eV or more, preferably 0.15 eV In this case, the fluctuation of the threshold voltage of the OS transistor 501 is reduced, and the OS transistor This is preferable because it can improve the electrical properties of 501 .

[0181] The on-current of a transistor can be increased by reducing the factors that hinder the movement of electrons. For example, if there are no factors that hinder the movement of electrons, it is assumed that electrons will move efficiently. The movement of electrons is also hindered, for example, when the physical unevenness of the channel region is large. Alternatively, when the density of defect states in the channel region is high, the movement of electrons is also hindered.

[0182] In order to increase the on-state current of the OS transistor 501, for example, or the bottom surface (the surface to be formed, here the OS layer 521), Root Mean Square (RMS) roughness less than 1 nm, preferably It is preferably less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the area of ​​1 μm × 1 μm is 1 nm. less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably 0 The maximum height difference (PV and ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, Preferably, it is less than 7 nm.

[0183] For example, if the OS layer 522 has oxygen vacancies (V O ) at the site of oxygen vacancy. The incorporation of hydrogen atoms can form donor levels. The state in which the element has entered is called V. O It may be written as H. V O H scatters electrons, This causes a decrease in the on-state current of the transistor. The oxygen vacancy site is designed to accommodate hydrogen. Therefore, by reducing oxygen vacancies in the OS layer 522, For example, the on-state current of the OS layer 522 can be increased. At a certain depth or in a certain region of the OS layer 522, secondary ion mass spectrometry ( Measured by SIMS (Secondary Ion Mass Spectrometry) The hydrogen concentration is 2×10 20 atoms / cm 3Less than or equal to 5 x 10 19 at oms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below are some more preferred Or 5 x 10 18 atoms / cm 3 The following applies.

[0184] In order to reduce oxygen vacancies in the OS layer 522, for example, excess oxygen contained in the insulating layer 512 is , and move it to the OS layer 522 via the OS layer 521. 521 is preferably an oxygen-permeable layer (a layer that allows oxygen to pass through).

[0185] When the OS transistor 501 has an s-channel structure, the entire OS layer 522 The OS layer 522 may have a thickness of 10 nm or more and a thickness of 10 nm or more. 0 nm or less, or 10 nm or more and 30 nm or less.

[0186] In order to increase the on-state current of the transistor, the OS layer 523 may be thinned. For example, it has a region of less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the OS layer 523 may be formed by connecting the OS layer 522 to the adjacent insulator. It has a function of blocking elements other than oxygen (hydrogen, silicon, etc.) from entering. Therefore, the OS layer 523 preferably has a certain thickness. , a region having a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more The OS layer 523 may have a thickness of 100 nm or less. In order to suppress outward diffusion of oxygen, it is preferable that the material has oxygen blocking properties.

[0187] In order to improve reliability, it is preferable that OS layer 521 be thick and OS layer 523 be thin. For example, it is 10 nm or more, preferably 20 nm or more, and more preferably 40 nm or more. More preferably, the OS layer 521 has a region with a thickness of 60 nm or more. By increasing the thickness of 521, the channel is formed from the interface between the adjacent insulator and the OS layer 521. However, this may result in a decrease in productivity of the semiconductor device. Therefore, for example, it is set to 200 nm or less, preferably 120 nm or less, and more preferably The OS layer 521 may have a region with a thickness of 80 nm or less.

[0188] To provide stable electrical characteristics to an OS transistor with an oxide semiconductor channel, and reducing the impurity concentration in the oxide semiconductor to make the oxide semiconductor intrinsic or substantially intrinsic. Here, the term "substantially intrinsic" means that the carrier density of the oxide semiconductor is 1×10 1 7 / cm 3 preferably less than 1 x 10 15 / cm 3 Less than Preferably 1 x 10 13 / cm 3 It means that it is less than.

[0189] In addition, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component For example, hydrogen and nitrogen contribute to the formation of donor levels, increasing the carrier density. Moreover, silicon contributes to the formation of impurity levels in the oxide semiconductor. The impurity levels become traps and may degrade the electrical characteristics of the transistor. Therefore, in the OS layer 521, the OS layer 522, and the OS layer 523 and at their interfaces, It is preferable to reduce the impurity concentration in the

[0190] In order to make an oxide semiconductor intrinsic or substantially intrinsic, for example, in SIMS analysis, , silicon at a certain depth in the oxide semiconductor or in a certain region in the oxide semiconductor. The concentration of 1×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / c m 3 less than 1×10 18 atoms / cm 3 In addition, the hydrogen concentration The degree may be, for example, at a certain depth in the oxide semiconductor or in a certain region of the oxide semiconductor. , 2×10 20 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Below, more preferably 5 x 1 0 18 atoms / cm 3 The nitrogen concentration is, for example, 5×10 in depth or in a region of the oxide semiconductor 19 atoms / c m 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 1 8 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following do.

[0191] In addition, when an oxide semiconductor contains crystals, if silicon or carbon is contained at a high concentration, the oxide semiconductor In order to prevent the crystallinity of the oxide semiconductor from being reduced, For example, at a certain depth or in a certain region of the oxide semiconductor, Silicon concentration 1×10 19 atoms / cm 3 Less than 5 x 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 The portion that is less than In addition, for example, at a certain depth of the oxide semiconductor or In a region of the body, the carbon concentration is 1×10 19 atoms / cm 3 Less than 5, preferably x10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 It is sufficient that the part is less than the above.

[0192] In addition, a transistor using the above-described highly purified oxide semiconductor for a channel formation region can be fabricated. The off-state current of the transistor is extremely small. For example, when the voltage between the source and drain is set to 0.1 V or 5 V, , or about 10 V, the off-state current normalized by the channel width of the transistor is It is possible to reduce the current to several yA / μm to several zA / μm.

[0193] 18 shows an example in which the OS layer 520 has a three-layer structure, but is not limited to this. 520 can be a two-layer structure without OS layer 521 or OS layer 523, or Above or below the OS layer 521, or above or below the OS layer 523, a four-layer structure having any one of the oxide semiconductor layers exemplified as the OS layer 521, the OS layer 522, and the OS layer 523 can also be used. Alternatively, between any layers of the OS layer 520, above the OS layer 520, or below the OS layer 520, one or more oxide semiconductor layers exemplified as the OS layers 521 - 523 can be provided at any two or more locations to form an n-layer structure (n is an integer of 5 or more).

[0194] <<Configuration Example 2 of OS Transistor>> The OS transistor 502 shown in FIG. 20A is a modified example of the OS transistor 501. The OS transistor 502 also has an s-channel structure, similar to the OS transistor 501. The OS transistor 502 is different from the OS transistor 501 in that the shapes of the conductive layer 541 and the conductive layer 542, and the fact that the conductive layer 531 is provided on the insulating layer 511.

[0195] The conductive layer 531 functions as a back gate electrode. A certain potential may be supplied to the conductive layer 531, or the same potential or the same signal as the conductive layer 530 may be supplied, or different potentials or different signals may be supplied. The conductive layer 541 and the conductive layer 542 each function as a source electrode or a drain electrode.

[0196] The conductive layer 541 and the conductive layer 542 of the OS transistor 502 are formed from a hard mask used to form the stack of the OS layer 521 and the OS layer 5 22. Therefore, the conductive layer 541 and the conductive layer 542 do not have regions in contact with the side surfaces of the OS layer 521 and the OS layer 522. For example, through the following steps, the OS layers 521, 522, the conductive layer 54 1. 542 can be fabricated. Form two oxide semiconductor films constituting the OS layers 521 and 522. Form a single-layer or laminated conductive film on the oxide semiconductor film. Etch this conductive film to form a hard mask. Using this hard mask, etch the two oxide semiconductor films to form a stack of the OS layer 521 and the OS layer 522. Next, etch the hard mask to form the conductive layer 541 and the conductive layer 542. The conductive layer 531 can function as the back gate electrode of the OS transistor 502. The OS transistor 501 shown in FIG. 20 and the OS transistors 503 - 506 (FIGS. 18 - 21) described later can also have the conductive layer 531 provided.

[0197]

[0198] <<Configuration Examples 3 and 4 of OS Transistor>> The OS transistor 503 shown in FIG. 20B is a modified example of the OS transistor 501, and the OS transistor 504 shown in FIG. 20C is a modified example of the OS transistor 502. In the OS transistor 503 and the OS transistor 504, the OS layer 523 and the insulating layer 513 are etched using the conductive layer 530 as a mask. Therefore, the ends of the OS layer 523 and the insulating layer 513 will substantially coincide with the ends of the conductive layer 530.

[0199] <<Configuration Examples 5 and 6 of OS Transistor>> The OS transistor 505 shown in FIG. 21A is a modified example of the OS transistor 501, and the OS transistor 506 shown in FIG. 21B is a modified example of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each have the OS layer 523 and the conductive layer Layer 551 is provided between OS layer 523 and conductive layer 541, and layer 552 is provided between OS layer 523 and conductive layer 542. .

[0200] The layers 551 and 552 may be made of, for example, a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor. The layers 551 and 552 can be formed of n-type oxide semiconductor layers. Alternatively, the conductive layers 541 and 542 may be formed of a conductive material having a higher resistance than the conductive layers 541 and 542. For example, the layer 551 and the layer 552 may be a layer containing indium, tin, and oxygen, or a layer containing indium, tin, and oxygen. a layer containing indium and zinc, a layer containing indium, tungsten and zinc, a layer containing tin and zinc A layer containing lead, a layer containing zinc and gallium, a layer containing zinc and aluminum, a layer containing zinc and and fluorine containing layer, zinc and boron containing layer, tin and antimony containing layer, tin and A layer containing titanium and fluorine or a layer containing titanium and niobium may be used. These layers contain one or more of hydrogen, carbon, nitrogen, silicon, germanium, or argon. It's okay to include it.

[0201] The layers 551 and 552 may have a property of transmitting visible light. 552 transmits visible light, ultraviolet light, infrared light, or X-rays by reflecting or absorbing them. By having such a property, the transition caused by stray light can be prevented. This may help to suppress fluctuations in the electrical characteristics of the capacitor.

[0202] The layers 551 and 552 are layers that do not form a Schottky barrier between themselves and the OS layer 522. This improves the on-state characteristics of the OS transistors 505 and 506. It can be done.

[0203] The layers 551 and 552 preferably have a higher resistance than the conductive layers 541 and 542. The layers 551 and 552 have a lower resistance than the channel resistance of the OS transistors 505 and 506. For example, the resistivity of the layers 551 and 552 is preferably 0.1 Ωcm or more and 100 Ωcm or less. m or less, 0.5Ωcm to 50Ωcm or 1Ωcm to 10Ωcm By setting the resistivity of the layers 551 and 552 in the above range, the channel and drain This can reduce the electric field concentration at the boundary between the two layers. In addition, the punch-through caused by the electric field generated from the drain can be reduced. Therefore, the saturation current can be reduced even in transistors with short channel lengths. The sum characteristics can be improved. If the circuit configuration does not swap the source and drain, either layer 551 or layer 552 In some cases, it may be preferable to provide a recess (for example, on the drain side).

[0204] <<Chip device structure example 1>> Figure 22 shows the device structure of a chip consisting of OS transistors and Si transistors. FIG. 22 is a diagram for explaining the layered structure of the PU200 (FIG. 13). 22 is a diagram illustrating the layered structure of FIG. 14 in more detail. The chip is not cut along a specific cutting line.

[0205] The chip is formed on a single crystal silicon wafer 270. The FET layer 260 includes a circuit RC Semiconductor elements such as Si transistors and capacitance elements that constitute the circuits other than 50 are provided. FIG. 22 shows a typical example of a p-type Si transistor 271 and an n-type Si transistor 272. The wiring layers W1-W4 are stacked on the FET layer 260. 1 is stacked.

[0206] The FET layer 261 is a layer in which OS transistors are formed, and transistors M1-M3 are formed. The transistor M3 is shown as a representative example. The same applies to the transistors M1 and M2. Here, the structure of the transistors M1-M3 is an OS transistor. In order to provide a back gate for transistor M3, A conductive layer 280 is formed on the wiring layer W4.

[0207] Wiring layers W5 and W6 are stacked on the FET layer 261, and a capacitance element C11 is stacked on the wiring layer W6. The capacitance element C11 is provided with wiring layers W7 and W8. , 282, and an insulating layer 284. Here, the layer on which the conductive layer 281 is formed is used as a wiring layer. By providing the capacitance element C11 stacked on the FET layer 261, the capacitance element C It is easy to increase the capacitance of the capacitance element C11. However, it is also possible to provide the capacitance element C11 in the FET layer 261. In this case, the transistor The conductive layer is the same layer as the source and drain electrodes of the transistor M3, and the conductive layer is the same layer as the gate electrode of the transistor M4. By providing the capacitor element C11 on the FET layer 261, two electrodes can be formed. This reduces the number of processes, which leads to a reduction in manufacturing costs.

[0208] <<Chip device structure example 2>> It is possible to stack another FET layer on the FET layer 261 in which an OS transistor is formed. Figure 23 shows an example of a chip having such a three-dimensional device structure.

[0209] In the chip of FIG. 23, the capacitance element C11 is formed in the FET layer 261. Wiring layers W6 and W7 are stacked on the semiconductor substrate 1. An FET layer 262 is stacked on the wiring layer W7. The FET layer 262 is the layer in which the OS transistor is fabricated. In order to provide a back gate for the transistor M80, the wiring layer W7 A conductive layer 283 is formed on the surface.

[0210] Wiring layers W8 and W9 are stacked on the FET layer 262. A capacitance layer 263 is stacked on the wiring layer W9. The capacitance layer 263 is connected to the wiring layer W 10 , W 11 The capacitor layer 263 has , a plurality of capacitance elements C80 are formed. For example, the transistor M80 and the capacitance element C1 1 and 1 can form a one-transistor, one-capacitor memory cell. On layer 261, a memory cell array can be stacked.

[0211] In addition, the OS transistor in the FET layer 261 and the OS transistor in the FET layer 262 are electrically connected to each other. For example, the second oxide semiconductor layer of an OS transistor can be The second oxide semiconductor layer is an In-GaAs film formed by sputtering. In the case of Zn oxide, a target with a different atomic ratio of In:Ga:Zn may be used. For example, for transistor M3, a target of In:Ga:Zn=1:1:1 is used. For the transistor M80, a target of In:Ga:Zn=4:2:4.1 is used. The oxide semiconductor layer of the transistor M80 contains a large amount of In. On the other hand, the oxide semiconductor layer of the transistor M3 is made of In The mobility of transistor M3 is lower than that of transistor M80 because the content of Therefore, the off-state current of the transistor M3 is lower than that of the transistor M80.

[0212] The insulators used in the chips in Figures 22 and 23 include aluminum oxide and aluminum nitride oxide. Aluminum, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, nitrogen silicon oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, One or more selected from lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, etc. The insulator may contain a material such as polyimide resin, polyamide resin, or the like. Resins such as mide resin, acrylic resin, siloxane resin, epoxy resin, and phenolic resin are used. In this specification, the term "oxynitride" refers to a compound having a higher oxygen content than nitrogen. Nitrogen oxide refers to a compound that contains more nitrogen than oxygen.

[0213] The insulating layers 291-295 are formed of an insulating material that has a blocking effect against hydrogen, water, etc. It is preferable that the oxide semiconductor layer includes at least one layer containing water, hydrogen, etc. This is one of the factors that cause the generation of hydrogen and water, so by providing a blocking layer against hydrogen, water, etc. This improves the reliability of the transistor M3. Examples of insulating materials that have a blocking effect include aluminum oxide, aluminum oxynitride, and oxide. Gallium, gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide Examples include hafnium oxide nitride, yttria stabilized zirconia (YSZ), etc.

[0214] <<Oxide semiconductor structure>> Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor, polycrystalline oxide semiconductor conductors, microcrystalline oxide semiconductors, amorphous oxide semiconductors, etc. From another perspective, oxide semiconductors The oxide semiconductors are divided into amorphous oxide semiconductors and other crystalline oxide semiconductors. The oxide semiconductors include single-crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. crystalline oxide semiconductors.

[0215] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. In the above, when the crystal is trigonal or rhombohedral, it is referred to as a hexagonal system.

[0216] <caac-os> CAAC-OS, CANC(C-Axis Aligned nanocrystal The CAAC-OS can also be called an oxide semiconductor having multiple c-axis aligned layers. It is one of oxide semiconductors having crystal parts (also called pellets).

[0217] Transmission Electron Microscope (TEM) The CAAC-OS bright-field image and diffraction pattern were analyzed by a combined analysis image (high resolution) When observing the high-resolution TEM image, multiple pellets can be confirmed. In the high-resolution TEM image, the boundaries between pellets, i.e., grain boundaries, are clearly visible. Therefore, it is considered that the CAAC-OS is caused by the grain boundaries. This means that the decrease in electron mobility caused by the ion implantation is unlikely to occur.

[0218] In the out-of-plane structural analysis of CAAC-OS, 2θ is around 31°. In addition to the peak, a peak may also appear around 2θ of 36°. This indicates that some of the CAAC-OS crystals do not have a c-axis orientation. The more preferable CAAC-OS is for structural analysis using the out-of-plane method. , a peak is observed at 2θ of around 31°, but no peak is observed at 2θ of around 36°.

[0219] The in-plane method was used to irradiate the CAAC-OS with X-rays from a direction approximately perpendicular to the c-axis. When structural analysis is performed using the NMR method, a peak appears at 2θ around 56°. In the case of CAAC-OS, the 2θ is set to around 56°. The sample is fixed and analyzed while rotating around the normal vector of the sample surface (φ axis) (φ scan). In contrast, when single crystal oxidation of InGaZnO4 is performed, no clear peak appears. In the case of a semiconductor, when 2θ is fixed at around 56° and φ is scanned, the plane is equivalent to the (110) plane. Six peaks attributable to the valence crystal planes are observed. From this, it can be confirmed that the orientation of the a-axis and b-axis of CAAC-OS is irregular.

[0220] CAAC-OS is an oxide semiconductor with a low density of defect states. Examples of defects include impurity-induced defects and oxygen vacancies. C-OS can be considered an oxide semiconductor with a low impurity concentration. The oxide semiconductor can be said to have few oxygen vacancies. In addition, oxide semiconductors may become carrier traps or carrier generation sources. Oxygen vacancies in the body can become carrier traps or can trap hydrogen, which can then transfer the carriers. It may be a source of pollution.

[0221] Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, silicon and other metal elements that form oxide semiconductors tend to bond with oxygen more easily than silicon. Elements with a strong resultant force disrupt the atomic arrangement of the oxide semiconductor by taking oxygen from the oxide semiconductor, It also reduces the crystallinity. Heavy metals such as iron and nickel, argon, carbon dioxide, etc. The atomic radius (or molecular radius) of elements is large, which disrupts the atomic arrangement of oxide semiconductors. This can cause a decrease in crystallinity.

[0222] Oxide semiconductors with low defect state density (few oxygen vacancies) can reduce carrier density. Such an oxide semiconductor can be called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low defect level density. Alternatively, the CAAC-OS can be a substantially pure intrinsic oxide semiconductor. The transistor used has electrical characteristics in which the threshold voltage is negative (also known as normally-on). In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor Therefore, the electrical characteristics of a transistor using CAAC-OS are The CAAC-OS has low defect density, resulting in a highly reliable transistor. Therefore, carriers generated by light irradiation are less likely to be captured by defect levels. Therefore, a transistor using CAAC-OS can be electrically charged by irradiation with visible light or ultraviolet light. The fluctuation of the air characteristics is small.

[0223] Charges trapped in carrier traps in oxide semiconductors take a long time to be released. Therefore, when the impurity concentration is high and the defect level is low, A transistor using an oxide semiconductor with high potential density may have unstable electrical characteristics. .

[0224] <Microcrystalline oxide semiconductor> Microcrystalline oxide semiconductors are regions where crystals can be confirmed in high-resolution TEM images. The microcrystalline oxide semiconductor has a region in which no clear crystal part can be identified. The crystal part to be formed has a size of 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less. In particular, microcrystals of 1 nm to 10 nm or 1 nm to 3 nm are often An oxide semiconductor with nanocrystals is called nc-OS (nanocrystalline nc-OS is called a "Natural Oxide Semiconductor." For example, In EM images, the grain boundaries may not be clearly visible. It is possible that the origin of the pellets in OS is the same as that of the pellets in nc-OS. The crystalline part is sometimes called a pellet.

[0225] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The atomic arrangement is periodic in the region of less than 100 nm. There is no regularity in the crystal orientation between the dots. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be indistinguishable from amorphous oxide semiconductors. For example, there is an XRD device that uses X-rays with a diameter larger than that of the pellet for nc-OS. When structural analysis is performed using the out-of-plane method, No peak is detected. Also, for nc-OS, the probe diameter (e.g., When electron diffraction (also called selected area electron diffraction) is performed using an electron beam of, for example, 50 nm or more, On the other hand, for nc-OS, a halo-like diffraction pattern is observed. Nanobeam electron diffraction using an electron beam with a probe diameter close to the pellet size or smaller than the pellet size When nanobeam electron diffraction is performed on nc-OS, spots are observed. In some cases, a bright area that appears circular (ring-shaped) may be observed. Multiple spots may be observed within a patchy area.

[0226] In this way, the crystal orientation between the pellets (nanocrystals) is not regular, and therefore, nc- OS with RANC (Random Aligned nanocrystals) oxide semiconductors, or NANCs (Non-Aligned Nanocrystals) ) can also be referred to as an oxide semiconductor.

[0227] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower defect state density than the amorphous oxide semiconductor. There is no regularity in the crystal orientation between different pellets. The defect level density is higher than that of AC-OS.

[0228] <Amorphous oxide semiconductor> Amorphous oxide semiconductors are oxides in which the atomic arrangement in the film is irregular and there are no crystalline parts. Amorphous oxide semiconductors, such as quartz, are examples of amorphous oxide semiconductors. In amorphous semiconductors, no crystalline parts can be seen in high-resolution TEM images. When a semiconductor is subjected to structural analysis using an XRD device, the out-of-plane method In the analysis, no peaks indicating crystal planes were detected. When electron diffraction is performed, a halo pattern is observed. When beam electron diffraction is performed, no spots are observed, only a halo pattern is observed.

[0229] There are various views on amorphous structures. For example, A structure that does not have a crystal structure is called a completely amorphous structure. In addition, although it does not have long-range order, the order of the atoms from the nearest neighbors to the atoms is called a "structure." A structure that may have order in the range of atoms or the second nearest neighbor atoms is called an amorphous structure. Therefore, according to the strictest definition, a material with even a slight degree of order in its atomic arrangement is called a An oxide semiconductor having such a structure cannot be called an amorphous oxide semiconductor. An oxide semiconductor having distance order cannot be called an amorphous oxide semiconductor. Because of the presence of crystalline parts, for example, CAAC-OS and nc-OS are classified as amorphous oxide semiconductors. It cannot be called a conductor or a completely amorphous oxide semiconductor.

[0230] <Amorphous-like oxide semiconductor> Note that an oxide semiconductor may have a structure between an nc-OS and an amorphous oxide semiconductor. An oxide semiconductor having such a structure is particularly called an amorphous-like oxide semiconductor (a-li ke OS:amorphous-like Oxide Semiconductor ) is called

[0231] In a-like OS, voids are observed in high-resolution TEM images. In addition, there are cases where crystals can be clearly seen in high-resolution TEM images. It has a-like regions and regions where no crystals can be seen. The OS has an unstable structure. Also, because it has porosity, the a-like OS is different from the nc-OS. and CAAC-OS, which has a lower density structure. The density of nc is 78.6% or more and less than 92.3% of the density of a single crystal of the same composition. The densities of the -OS and CAAC-OS are 92.3% or more of the densities of single crystals of the same composition. The oxide semiconductor with a density of less than 78% of the single crystal can be formed by itself. The body is difficult.

[0232] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 It becomes. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 It is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 It will be less than.

[0233] In some cases, single crystals with the same composition do not exist. In such cases, crystals with different compositions at any ratio are used. By combining single crystals, the density equivalent to a single crystal of the desired composition is estimated. The density corresponding to a single crystal of a desired composition can be obtained by combining single crystals of different compositions. It is possible to estimate the ratio of the number of types of single crystals by using a weighted average. It is preferable to estimate the density by combining these factors.

[0234] Oxide semiconductors have a variety of structures, each with its own unique characteristics. The semiconductor region of the transistor is made of amorphous oxide semiconductor, a-like OS, microcrystalline oxide semiconductor, The film may be a laminated film having two or more of the above-mentioned compounds, CAAC-OS, and CAAC-OS. [Explanation of symbols]

[0235] 10: Circuit, 11: Scan Flip-Flop (SFF), 15: Circuit, 20: Selection Circuit ,21: Selection circuit (SEL), 30: Circuit, 31: Flip-flop (FF), 31a: Circuit, 32M: Latch, 32S: Latch, 42: Inverter, 43: Inverter, 44: Inverter, 45: Buffer (BUF), 50: SFF, 100: logic circuit, 101: logic circuit, 102: logic circuit, 103: logic circuit, 110: SFF, 112:SFF, 113:SFF, 114:SFF, 115:SFF, 116: SFF, 200: PU, 201: processor core, 202: power management unit (PMU), 203: Power switch (PSW), 204: clock control circuit, 205: circuit, 210: power supply circuit , 220: terminal, 221: terminal, 222: terminal, 231: control device, 232: program Counter, 233: Pipeline register, 234: Pipeline register, 235: Register file, 236: Arithmetic logic unit (ALU), 237: Data bus, 240: Logic circuit, 250:SFF, 260: FET layer, 261: FET layer, 262: FET layer, 263: capacitance layer, 270: single Crystalline silicon wafer, 271: p-type Si transistor, 272: n-type Si transistor, 280: Conductive layer, 281: Conductive layer, 282: Conductive layer, 283: Conductive layer, 284: Insulating layer, 291: insulating layer, 292: insulating layer, 293: insulating layer, 294: insulating layer, 295: insulating layer, 501: OS transistor, 502: OS transistor, 503: OS transistor, 5 04: OS transistor, 505: OS transistor, 506: OS transistor, 51 0: substrate, 511: insulating layer, 512: insulating layer, 513: insulating layer, 514: insulating layer, 515 :insulating layer, 520:OS layer, 521:OS layer, 522:OS layer, 523:OS layer, 530 : Conductive layer, 531: Conductive layer, 541: Conductive layer, 542: Conductive layer, 551: Layer, 552: Layer , 900: Portable game machine, 901: Housing, 902: Housing, 903: Display unit, 904: Display part, 905: microphone, 906: speaker, 907: operation keys, 908: stylus 910: portable information terminal, 911: housing, 912: housing, 913: display unit, 914: display part, 915: connection part, 916: operation keys, 920: notebook PC, 921: housing, 922 : Display unit, 923: Keyboard, 924: Pointing device, 930: Electric refrigeration Refrigerator, 931: Housing, 932: Refrigerator door, 933: Freezer door, 940: Video camera 941: Housing, 942: Housing, 943: Display unit, 944: Operation keys, 945: Lens, 946: Connection, 950: Automobile, 951: Body, 952: Wheel, 953: Dashboard Do, 954: Light, 7000: Electronic components, 7001: Leads, 7002: Printed circuit boards, 7003: Circuit sections, 7004: Circuit boards, BK: terminal, C1: capacitance element, C11: capacitance element, C12: capacitance element, C80: capacitance element , CK: pin, CK1: pin, CKB1: pin, D: pin, D0: pin, D1: pin, D 2: Terminal, D3: Terminal, Dn: Terminal, EN: Terminal, FN: Node, FN11: Node, M 1: transistor, M2: transistor, M3: transistor, M80: transistor, OBG: terminal, PL: terminal, Q: terminal, QB: terminal, RC1: circuit, RC2: circuit, RC 3: Circuit, RC4: Circuit, RC11: Circuit, RC12: Circuit, RC13: Circuit, RC14 : Circuit, RC15: Circuit, RC16: Circuit, RC50: Circuit, RE: Terminal, RT: Terminal, SD: terminal, SD_IN: terminal, SE: terminal, SW1: switch, SW2: switch, S W3: Switch, T0: Terminal, T1: Terminal, T2: Terminal, VH: Terminal, VL: Terminal, W1 : Wiring layer, W2: Wiring layer, W3: Wiring layer, W4: Wiring layer, W5: Wiring layer, W6: Wiring layer, W7: Wiring layer, W8: Wiring layer, W9: Wiring layer, W 10 :Wiring layer, W 11 :Wiring layer

Claims

1. 1. A semiconductor device comprising: a logic circuit; and a holding circuit having a function of holding data obtained by logically inverting data output from the logic circuit and a function of outputting the held data to the logic circuit, the holding circuit includes first to third switches, an element for holding data, and an inverter; an output terminal of the logic circuit is always electrically connected to a first terminal of the second switch via the inverter; a second terminal of the second switch is always electrically connected to an element that holds the logic-inverted data; a second terminal of the second switch is always electrically connected to a first terminal of the third switch; a second terminal of the third switch is always electrically connected to an input terminal of the logic circuit; an input terminal of the holding circuit is always electrically connected to a first terminal of the first switch; a second terminal of the first switch is always electrically connected to an input terminal of the logic circuit; the data output from the holding circuit to the logic circuit is logically inverted data of the data output from the logic circuit to the holding circuit, The first layer and the second layer are laminated together, The first layer has one of the elements included in the logic circuit, The second layer has one of the elements included in the holding circuit, a first period, a second period after the first period, and a third period after the second period; during the first period, the first and second switches are in a conductive state and the third switch is in a non-conductive state; During the second period, the first to third switches are in a non-conductive state, In the third period, the first and second switches are in a non-conductive state and the third switch is in a conductive state.

2. In claim 1, The logic circuit is a semiconductor device that is a latch, a flip-flop, a shift register, a counter circuit, or a frequency divider circuit.

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