Wiring board and manufacturing method thereof, and semiconductor device

Abstract

To provide a wiring board of which the inductance value is easily changed.SOLUTION: A wiring board comprises wiring structures 50A, 50B, 50C and 50D including: pads 20P, 22P, 24P, 26P and 28P; insulating layers 21, 23, 25, 27, 41, 43, 45 and 47 covering the pads; magnetic substance resins 51A, 51B, 51C and 51D disposed on the pads within the insulating layers; and via wires 22V, 24V, 26V and 28V penetrating the magnetic substance resins and electrically connected with the pads. An inductor is formed from the magnetic substance resin and the via wire. An epoxy-based resin, etc., containing magnetic particles is used as the magnetic substance resin. A filler of iron, iron oxide, cobalt iron oxide, silicon iron, magnetic alloy, ferrite, etc., is cited as the magnetic particle.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a wiring board, a manufacturing method thereof, and a semiconductor device. [Background technology]

[0002] Wiring boards with built-in inductors are known. For example, a wiring board can be mentioned that has a core substrate with an opening, a magnetic resin filled in the opening and having a through-hole, and a plating film formed in the through-hole. In this wiring board, the inductor is formed by the magnetic resin filled in the opening of the core substrate and the plating film (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-220504 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the method of forming an inductor in a core substrate, as in the above-described wiring board, it is difficult to finely change the inductance value because the core substrate is thick.

[0005] The present invention has been made in view of the above points, and has an object to provide a wiring board in which the inductance value can be easily changed. [Means for solving the problem]

[0006] The wiring board has a wiring structure including a pad, an insulating layer covering a part of the upper surface and a side surface of the pad, a magnetic resin disposed on the upper surface of the pad within the insulating layer, and a via wiring that penetrates the magnetic resin and is electrically connected to the pad, a lower surface of the via wiring contacts an upper surface of the pad, and the lower surface of the via wiring is flush with a lower surface of the magnetic resin; The side surface of the via wiring is in contact with the magnetic resin. [Effects of the Invention]

[0007] According to the disclosed technique, it is possible to provide a wiring board in which the inductance value can be easily changed. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are diagrams illustrating a wiring substrate according to a first embodiment. [Figure 2] 1A to 1C are views (part 1) illustrating a manufacturing process of a wiring board according to the first embodiment. [Figure 3] 5A to 5C are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment (part 2). [Figure 4] 10A to 10C are views (part 3) illustrating the manufacturing process of the wiring board according to the first embodiment. [Figure 5] 10A and 10B are diagrams illustrating a wiring substrate according to a first modified example of the first embodiment. [Figure 6] 1A to 1C are diagrams (part 1) illustrating a manufacturing process of a wiring board according to Modification 1 of the first embodiment. [Figure 7] 10A to 10C are diagrams (part 2) illustrating the manufacturing process of the wiring board according to the first modified example of the first embodiment. [Figure 8] FIG. 10 is a cross-sectional view illustrating a wiring board according to a second modification of the first embodiment. [Figure 9] FIG. 10 is a partial cross-sectional view illustrating a wiring board according to a third modified example of the first embodiment. [Figure 10] 1 is a cross-sectional view (part 1) illustrating a semiconductor device according to an application example of the first embodiment; [Figure 11] FIG. 10 is a cross-sectional view (part 2) illustrating a semiconductor device according to an application example of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant explanations may be omitted.

[0010] First Embodiment [Wiring board structure] 1A and 1B are diagrams illustrating a wiring board according to a first embodiment, in which Fig. 1A is a cross-sectional view and Fig. 1B is an enlarged view of part A in Fig. 1A. Referring to Fig. 1, the wiring board 1 is a multilayer wiring board in which wiring layers and insulating layers are laminated on both sides of a core layer 10.

[0011] Specifically, in the wiring board 1, a wiring layer 20, an insulating layer 21, a wiring layer 22, an insulating layer 23, a wiring layer 24, an insulating layer 25, a wiring layer 26, an insulating layer 27, a wiring layer 28, and a solder resist layer 29 are sequentially laminated on one surface 10a of the core layer 10. Furthermore, a wiring layer 40, an insulating layer 41, a wiring layer 42, an insulating layer 43, a wiring layer 44, an insulating layer 45, a wiring layer 46, an insulating layer 47, a wiring layer 48, and a solder resist layer 49 are sequentially laminated on the other surface 10b of the core layer 10. The laminate structure on the one surface 10a side of the core layer 10 and the laminate structure on the other surface 10b side are approximately symmetrical with respect to the core layer 10.

[0012] In this embodiment, for convenience, the solder resist layer 29 side of the wiring board 1 is referred to as the upper side or one side, and the solder resist layer 49 side is referred to as the lower side or the other side. Furthermore, the surface of each part facing the solder resist layer 29 is referred to as one side or the upper side, and the surface facing the solder resist layer 49 is referred to as the other side or the lower side. However, the wiring board 1 can be used upside down or positioned at any angle. Furthermore, a planar view refers to viewing an object from the normal direction of one surface 10a of the core layer 10, and a planar shape refers to the shape of the object viewed from the normal direction of one surface 10a of the core layer 10.

[0013] The core layer 10 may be, for example, a so-called glass epoxy substrate obtained by impregnating glass cloth with an insulating resin such as an epoxy resin. Alternatively, the core layer 10 may be a substrate obtained by impregnating a woven or nonwoven fabric such as glass fiber, carbon fiber, or aramid fiber with an epoxy resin or a polyimide resin. The thickness of the core layer 10 may be, for example, about 60 to 400 μm. The core layer 10 is provided with through holes 10x that penetrate the core layer 10 in the thickness direction. The planar shape of the through holes 10x is, for example, circular.

[0014] A through wire 11 is provided so as to cover the inner wall of the through hole 10x. The inside of the through wire 11 is filled with a resin 12. The through wire 11 may fill the through hole 10x. In this case, the resin 12 is not provided. The material of the through wire 11 may be, for example, copper (Cu). The material of the resin 12 may be, for example, an insulating resin containing an epoxy resin as a main component.

[0015] The wiring layer 20 is formed on one surface 10a of the core layer 10. The wiring layer 20 includes pads 20P and a wiring pattern. The wiring layer 40 is formed on the other surface 10b of the core layer 10. The wiring layer 40 includes pads and a wiring pattern. The wiring layer 20 and the wiring layer 40 are electrically connected by through-hole wires 11. The wiring layers 20 and 40 are each patterned into a predetermined planar shape. The wiring layers 20 and 40 may be made of, for example, copper (Cu). The thickness of the wiring layers 20 and 40 may be, for example, about 10 to 30 μm. The wiring layer 20, the wiring layer 40, and the through-hole wires 11 may be formed integrally.

[0016] The insulating layer 21 is formed on one surface 10a of the core layer 10 so as to cover the wiring layer 20. The insulating layer 21 can be made of, for example, an insulating resin whose main component is an epoxy resin or a polyimide resin. The thickness of the insulating layer 21 can be, for example, about 20 to 30 μm. Note that the thickness of the insulating layer 21 here refers to the distance from the upper surface of the wiring layer 20 to the upper surface of the insulating layer 21. The same applies to the thicknesses of the subsequent insulating layers. The insulating layer 21 can contain a filler such as silica (SiO2). The amount of filler contained in the insulating layer 21 can be appropriately set depending on the required coefficient of thermal expansion (CTE).

[0017] The wiring layer 22 is formed on one side of the insulating layer 21. The wiring layer 22 includes via wiring 22V filled in via holes 21x that penetrate the insulating layer 21 and expose the upper surfaces of the pads 20P, pads 22P formed on the upper surface of the insulating layer 21, and a wiring pattern. The wiring layer 22 also includes via wiring 22V filled in via holes 21z that penetrate the magnetic resin 51A and expose the upper surfaces of the pads 20P, and pads 22P formed on the upper surfaces of the insulating layer 21 and the magnetic resin 51A. The pads 22P are electrically connected to the pads 20P through the via wiring 22V. The via holes 21x and 21z may be recessed in the shape of an inverted truncated cone, with the diameter of the opening opening toward the insulating layer 23 being larger than the diameter of the bottom of the opening formed by the upper surface of the pads 20P. The material of the wiring layer 22 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0018] The insulating layer 23 is formed on the upper surface of the insulating layer 21 so as to cover the wiring layer 22. The material and thickness of the insulating layer 23 may be the same as those of the insulating layer 21, for example. The insulating layer 23 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 23 may be the same as those of the insulating layer 21, for example.

[0019] The wiring layer 24 is formed on one side of the insulating layer 23. The wiring layer 24 includes via wiring 24V filled in via holes 23x that penetrate the insulating layer 23 and expose the upper surfaces of the pads 22P, pads 24P formed on the upper surface of the insulating layer 23, and a wiring pattern. The wiring layer 24 also includes via wiring 24V filled in via holes 23z that penetrate the magnetic resin 51B and expose the upper surfaces of the pads 22P, and pads 24P formed on the upper surfaces of the insulating layer 23 and the magnetic resin 51B. The pads 24P are electrically connected to the pads 22P through the via wiring 24V. The via holes 23x and 23z may be recessed in the shape of an inverted truncated cone, with the diameter of the opening on the insulating layer 25 side being larger than the diameter of the bottom of the opening formed by the upper surface of the pads 22P. The material of the wiring layer 24 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0020] The insulating layer 25 is formed on the upper surface of the insulating layer 23 so as to cover the wiring layer 24. The material and thickness of the insulating layer 25 may be the same as those of the insulating layer 21, for example. The insulating layer 25 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 25 may be the same as those of the insulating layer 21, for example.

[0021] The wiring layer 26 is formed on one side of the insulating layer 25. The wiring layer 26 includes via wiring 26V filled in via holes 25x that penetrate the insulating layer 25 and expose the upper surfaces of the pads 24P, pads 26P formed on the upper surface of the insulating layer 25, and a wiring pattern. The wiring layer 26 also includes via wiring 26V filled in via holes 25z that penetrate the magnetic resin 51C and expose the upper surfaces of the pads 24P, and pads 26P formed on the upper surfaces of the insulating layer 25 and the magnetic resin 51C. The pads 26P are electrically connected to the pads 24P through the via wiring 26V. The via holes 25x and 25z may be recessed in the shape of an inverted truncated cone, with the diameter of the opening opening toward the insulating layer 27 being larger than the diameter of the bottom of the opening formed by the upper surface of the pads 24P. The material of the wiring layer 26 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0022] The insulating layer 27 is formed on the upper surface of the insulating layer 25 so as to cover the wiring layer 26. The material and thickness of the insulating layer 27 may be the same as those of the insulating layer 21, for example. The insulating layer 27 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 27 may be the same as those of the insulating layer 21, for example.

[0023] The wiring layer 28 is formed on one side of the insulating layer 27. The wiring layer 28 includes via wiring 28V filled in via holes 27x that penetrate the insulating layer 27 and expose the upper surfaces of the pads 26P, pads 28P formed on the upper surface of the insulating layer 27, and a wiring pattern. The wiring layer 28 also includes via wiring 28V filled in via holes 27z that penetrate the magnetic resin 51D and expose the upper surfaces of the pads 26P, and pads 28P formed on the upper surfaces of the insulating layer 27 and the magnetic resin 51D. The pads 28P are electrically connected to the pads 26P through the via wiring 28V. The via holes 27x and 27z may be recessed in the shape of an inverted truncated cone, with the diameter of the opening on the solder resist layer 29 side being larger than the diameter of the bottom of the opening formed by the upper surface of the pads 26P. The material of the wiring layer 28 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0024] The solder resist layer 29 is the outermost layer on one side of the wiring board 1, and is formed on the upper surface of the insulating layer 27 so as to cover the wiring layer 28. The solder resist layer 29 can be formed from, for example, a photosensitive resin such as an epoxy resin or an acrylic resin. The thickness of the solder resist layer 29 can be, for example, about 15 to 35 μm.

[0025] The solder resist layer 29 has openings 29x, and portions of the upper surfaces of the pads 28P of the wiring layer 28 are exposed at the bottom of the openings 29x. The planar shape of the openings 29x may be, for example, circular. If necessary, a metal layer may be formed on the upper surfaces of the pads 28P exposed in the openings 29x, or an anti-oxidation treatment such as an OSP (organic solderability preservative) treatment may be performed. Examples of the metal layer include an Au layer, a Ni / Au layer (a metal layer formed by laminating a Ni layer and an Au layer in this order), and a Ni / Pd / Au layer (a metal layer formed by laminating a Ni layer, a Pd layer, and an Au layer in this order).

[0026] An external connection terminal 30 is formed on the upper surface of the pad 28P exposed at the bottom of the opening 29x. The external connection terminal 30 is, for example, a solder bump. Examples of materials that can be used for the solder bump include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu. The external connection terminal 30 serves as a terminal for electrically connecting to a semiconductor chip.

[0027] The insulating layer 41 is formed on the other surface 10b of the core layer 10 so as to cover the wiring layer 40. The material and thickness of the insulating layer 41 may be the same as those of the insulating layer 21, for example. The insulating layer 41 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 41 may be the same as those of the insulating layer 21, for example.

[0028] The wiring layer 42 is formed on the other side of the insulating layer 41. The wiring layer 42 includes via wirings filled in via holes 41x that penetrate the insulating layer 41 and expose the undersides of the pads that constitute the wiring layer 40, pads formed on the underside of the insulating layer 41, and a wiring pattern. The wiring layer 42 also includes via wirings filled in via holes 41z that penetrate the magnetic resin and expose the undersides of the pads of the wiring layer 40, and pads formed on the undersides of the insulating layer 41 and the magnetic resin. The pads that constitute the wiring layer 42 are electrically connected to the pads that constitute the wiring layer 40 through the via wirings. The via holes 41x and 41z may be truncated cone-shaped recesses whose openings on the insulating layer 43 side have a diameter larger than the diameter of the bottom of the openings formed by the undersides of the pads that constitute the wiring layer 40. The material of the wiring layer 42 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0029] The insulating layer 43 is formed on the lower surface of the insulating layer 41 so as to cover the wiring layer 42. The material and thickness of the insulating layer 43 may be the same as those of the insulating layer 21, for example. The insulating layer 43 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 43 may be the same as those of the insulating layer 21, for example.

[0030] The wiring layer 44 is formed on the other side of the insulating layer 43. The wiring layer 44 includes via wirings filled in via holes 43x that penetrate the insulating layer 43 and expose the undersides of the pads that constitute the wiring layer 42, pads formed on the underside of the insulating layer 43, and a wiring pattern. The wiring layer 44 also includes via wirings filled in via holes 43z that penetrate the magnetic resin and expose the undersides of the pads of the wiring layer 42, and pads formed on the undersides of the insulating layer 43 and the magnetic resin. The pads that constitute the wiring layer 44 are electrically connected to the pads that constitute the wiring layer 42 through the via wirings. The via holes 43x and 43z may be truncated cone-shaped recesses whose openings on the insulating layer 45 side have a diameter larger than the diameter of the bottom of the openings formed by the undersides of the pads that constitute the wiring layer 42. The material of the wiring layer 44 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0031] The insulating layer 45 is formed on the lower surface of the insulating layer 43 so as to cover the wiring layer 44. The material and thickness of the insulating layer 45 may be the same as those of the insulating layer 21, for example. The insulating layer 45 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 45 may be the same as those of the insulating layer 21, for example.

[0032] The wiring layer 46 is formed on the other side of the insulating layer 45. The wiring layer 46 includes via wirings filled in via holes 45x that penetrate the insulating layer 45 and expose the undersides of the pads that make up the wiring layer 44, pads formed on the underside of the insulating layer 45, and a wiring pattern. The wiring layer 46 also includes via wirings filled in via holes 45z that penetrate the magnetic resin and expose the undersides of the pads of the wiring layer 44, and pads formed on the undersides of the insulating layer 45 and the magnetic resin. The pads that make up the wiring layer 46 are electrically connected to the pads that make up the wiring layer 44 through the via wirings. The via holes 45x and 45z may be truncated cone-shaped recesses whose openings on the insulating layer 47 side have a diameter larger than the diameter of the bottom of the openings formed by the undersides of the pads that make up the wiring layer 44. The material of the wiring layer 46 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0033] The insulating layer 47 is formed on the lower surface of the insulating layer 45 so as to cover the wiring layer 46. The material and thickness of the insulating layer 47 may be the same as those of the insulating layer 21, for example. The insulating layer 47 may contain a filler such as silica (SiO2). The content of the filler in the insulating layer 47 may be the same as those of the insulating layer 21, for example.

[0034] The wiring layer 48 is formed on the other side of the insulating layer 47. The wiring layer 48 includes via wirings filled in via holes 47x that penetrate the insulating layer 47 and expose the undersides of the pads that make up the wiring layer 46, pads formed on the underside of the insulating layer 47, and a wiring pattern. The wiring layer 48 also includes via wirings filled in via holes 47z that penetrate the magnetic resin and expose the undersides of the pads of the wiring layer 46, and pads formed on the undersides of the insulating layer 47 and the magnetic resin. The pads that make up the wiring layer 48 are electrically connected to the pads that make up the wiring layer 46 through the via wirings. The via holes 47x and 47z may be truncated cone-shaped recesses whose openings on the solder resist layer 49 side have a diameter larger than the diameter of the bottom of the openings formed by the undersides of the pads that make up the wiring layer 46. The material of the wiring layer 48 and the thickness of the wiring pattern may be the same as those of the wiring layer 20, for example.

[0035] The solder resist layer 49 is the outermost layer on the other side of the wiring board 1 and is formed on the lower surface of the insulating layer 47 so as to cover the wiring layer 48. The material and thickness of the solder resist layer 49 can be, for example, the same as those of the solder resist layer 29. The solder resist layer 49 has openings 49x, in which portions of the lower surfaces of the pads of the wiring layer 48 are exposed. The planar shape of the openings 49x can be, for example, circular. The pads of the wiring layer 48 exposed in the openings 49x can be used for electrical connection to a mounting substrate (not shown), such as a motherboard. If necessary, the aforementioned metal layer may be formed on the lower surfaces of the pads of the wiring layer 48 exposed in the openings 49x, or an anti-oxidation treatment such as OSP treatment may be performed.

[0036] 1(b), wiring board 1 has wiring structures 50A, 50B, 50C, and 50D stacked in sequence on one surface 10a of core layer 10. Note that wiring board 1 may also have wiring structures stacked in sequence on the other surface 10b of core layer 10 in the area surrounded by dashed line B in FIG. 1(a). The wiring structure in the area surrounded by dashed line B has a structure obtained by inverting the wiring structure in the area surrounded by dashed line A upside down, and therefore a description thereof will be omitted.

[0037] The wiring structure 50A includes pads 20P constituting the wiring layer 20, an insulating layer 21 covering the pads 20P, a magnetic resin 51A, and via wiring 22V constituting the wiring layer 22. The magnetic resin 51A is disposed on the pads 20P within the insulating layer 21. The via wiring 22V penetrates the magnetic resin 51A and is electrically connected to the pads 20P. The magnetic resin 51A is formed in a ring shape surrounding the via wiring 22V in a plan view. That is, the magnetic resin 51A and the via wiring 22V have a coaxial structure. The thickness of the magnetic resin 51A is equal to the thickness of the via wiring 22V. The thickness of each of the magnetic resin 51A and the via wiring 22V is, for example, approximately 20 to 30 μm.

[0038] The upper surface of the magnetic resin 51A is flush with the upper surface of the insulating layer 21, for example. This makes it easy to form the pad 22P on the upper surface of the magnetic resin 51A and the upper surface of the insulating layer 21. The upper surface of the magnetic resin 51A contacts the lower surface of the pad 22P. The lower surface of the magnetic resin 51A contacts the upper surface of the pad 20P. The inner wall surface of the magnetic resin 51A contacts the outer wall surface of the via wiring 22V. The outer wall surface of the magnetic resin 51A may be inclined in the same direction as the outer wall surface of the via wiring 22V in a cross-sectional view.

[0039] When the via wiring 22V has a circular planar shape, the diameter of the via wiring 22V on the pad 22P side is, for example, about 40 to 60 μm, and the diameter on the pad 20P side is, for example, about 25 to 45 μm. In this case, the outer diameter of the magnetic resin 51A on the pad 22P side is, for example, about 90 to 160 μm, and the outer diameter on the pad 20P side is, for example, about 75 to 145 μm.

[0040] The magnetic resin 51A and the via wiring 22V can form an inductor. For example, an epoxy resin containing magnetic particles can be used as the magnetic resin 51A. Examples of the magnetic particles include fillers such as iron, iron oxide, cobalt iron oxide, silicon iron, magnetic alloys, and ferrite.

[0041] The wiring structure 50B includes a pad 22P constituting the wiring layer 22, an insulating layer 23 covering the pad 22P, a magnetic resin 51B arranged on the pad 22P within the insulating layer 23, and a via wiring 24V that penetrates the magnetic resin 51B and is electrically connected to the pad 22P.

[0042] Pad 22P of upper wiring structure 50B is formed integrally with via wiring 22V of lower wiring structure 50A, for example. Pad 22P of upper wiring structure 50B and pad 20P of lower wiring structure 50A are electrically connected via via wiring 22V of lower wiring structure 50A. Wiring structure 50B has the same structure as wiring structure 50A. The material of magnetic resin 51B may be the same as the material of magnetic resin 51A.

[0043] The wiring structure 50C includes a pad 24P constituting the wiring layer 24, an insulating layer 25 covering the pad 24P, a magnetic resin 51C arranged on the pad 24P within the insulating layer 25, and a via wiring 26V that penetrates the magnetic resin 51C and is electrically connected to the pad 24P.

[0044] Pad 24P of upper wiring structure 50C is formed integrally with via wiring 24V of lower wiring structure 50B, for example. Pad 24P of upper wiring structure 50C and pad 22P of lower wiring structure 50B are electrically connected via via wiring 24V of lower wiring structure 50B. Wiring structure 50C has the same structure as wiring structure 50A. The material of magnetic resin 51C may be the same as the material of magnetic resin 51A.

[0045] The wiring structure 50D includes a pad 26P constituting the wiring layer 26, an insulating layer 27 covering the pad 26P, a magnetic resin 51D arranged on the pad 26P within the insulating layer 27, and a via wiring 28V that penetrates the magnetic resin 51D and is electrically connected to the pad 26P.

[0046] Pad 26P of upper wiring structure 50D is formed integrally with via wiring 26V of lower wiring structure 50C, for example. Pad 26P of upper wiring structure 50D and pad 24P of lower wiring structure 50C are electrically connected via via wiring 26V of lower wiring structure 50C. Wiring structure 50D has the same structure as wiring structure 50A. The material of magnetic resin 51D may be the same as the material of magnetic resin 51A.

[0047] Pads 28P for external connection electrically connected to via wiring 28V of wiring structure 50D are arranged on insulating layer 27 of wiring structure 50D, which is the uppermost layer. Pads 28P are formed integrally with via wiring 28V of wiring structure 50D, for example.

[0048] Via wiring 22V of wiring structure 50A, via wiring 24V of wiring structure 50B, via wiring 26V of wiring structure 50C, and via wiring 28V of wiring structure 50D have portions that overlap with one another in a planar view. To increase the inductance value, via wiring 22V of wiring structure 50A, via wiring 24V of wiring structure 50B, via wiring 26V of wiring structure 50C, and via wiring 28V of wiring structure 50D preferably overlap one another almost completely in a planar view. Here, "almost completely overlapping" refers to a situation in which the area of ​​the portion of each via wiring that protrudes from the common portion in a planar view is within 20% of the area of ​​the common portion where all of the via wirings of wiring structures 50A-50D overlap in a planar view.

[0049] Magnetic resin 51A of wiring structure 50A, magnetic resin 51B of wiring structure 50B, magnetic resin 51C of wiring structure 50C, and magnetic resin 51D of wiring structure 50D have overlapping portions in plan view. To increase the inductance value, magnetic resin 51A of wiring structure 50A, magnetic resin 51B of wiring structure 50B, magnetic resin 51C of wiring structure 50C, and magnetic resin 51D of wiring structure 50D preferably overlap each other almost completely in plan view. Here, "almost completely overlapping" refers to the case where the area of ​​the portion of each magnetic resin that protrudes from the common area in plan view is within 20% of the area of ​​the common area where all of the magnetic resins of wiring structures 50A-50D overlap in plan view.

[0050] In this way, the wiring board 1 has a wiring structure including a magnetic resin and via wiring that penetrates the magnetic resin. This allows an inductor to be formed by the magnetic resin and via wiring, eliminating the need for an external inductor component, and enabling the wiring board 1 to be made thinner and less expensive.

[0051] Although wiring board 1 may have one wiring structure, a large inductance value can be obtained by stacking multiple wiring structures. Furthermore, with wiring board 1, the number of stacked wiring structures can be determined arbitrarily, improving design freedom for obtaining a required inductance value.

[0052] Although an inductor can be formed by providing through-wiring that penetrates the magnetic resin in the core layer 10, it is difficult to change the inductance value precisely in design because the core layer 10 is thick. The insulating layers stacked above and below the core layer 10 are thinner than the core layer 10, so the inductance value can be easily changed to a desired value by changing the number of layers in the wiring structure.

[0053] [Method of manufacturing wiring board] The wiring board 1 can be manufactured by a well-known build-up method. Here, the manufacturing method of the wiring board 1 will be described, focusing on the process of forming the magnetic resin, using a partial cross-sectional view of the periphery of the magnetic resin corresponding to FIG. 1. Note that only the laminate on one surface of the core layer 10 will be described here, but the laminate on the other surface of the core layer 10 can be formed in a similar manner. Also, while an example of the process of manufacturing one wiring board is shown here, a process of manufacturing multiple parts that will become wiring boards and then dividing them into individual wiring boards may also be used.

[0054] 2 to 4 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment. First, in the process shown in Fig. 2(a), a core layer 10 having through-hole wires 11 and a resin 12 formed therein is prepared, and a wiring layer 20 including pads 20P and a wiring pattern is formed on one surface 10a of the core layer 10. The material and thickness of the wiring layer 20 are as described above. The wiring layer 20 can be formed using various wiring formation methods such as a semi-additive method or a subtractive method.

[0055] 2(b), a semi-cured film-like epoxy resin or the like is laminated on one surface 10a of the core layer 10 so as to cover the wiring layer 20 including the pads 20P and the wiring pattern, and then cured to form the insulating layer 21. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the insulating layer 21. The thickness and the like of the insulating layer 21 are as described above.

[0056] 2(c), through-holes 21y are formed in the insulating layer 21, penetrating the insulating layer 21 and exposing the top surfaces of the pads 20P of the wiring layer 20. The through-holes 21y are formed in areas where the magnetic resin 51A will be formed in a later step. The through-holes 21y can be formed by laser processing using a CO2 laser or the like, for example.

[0057] Next, in the process shown in FIGS. 3(a) and 3(b), magnetic resin 51A is formed to fill through-hole 21y. First, in the process shown in FIG. 3(a), for example, a paste-like thermosetting magnetic resin 51A is prepared, and the through-hole 21y is filled with the magnetic resin 51A by screen printing or the like, and the magnetic resin 51A is protruded from the upper surface of insulating layer 21. Then, the magnetic resin 51A is heated and cured. The material of magnetic resin 51A is as described above. It is preferable to form magnetic resin 51A in a vacuum atmosphere. This prevents voids from being generated.

[0058] 3(b), unnecessary magnetic resin 51A protruding from the upper surface of insulating layer 21 is removed by polishing or the like. The unnecessary magnetic resin 51A can be removed by, for example, buffing or roll polishing. The upper surface of magnetic resin 51A becomes flush with the upper surface of insulating layer 21, for example.

[0059] 3(c), via holes 21x are formed in the insulating layer 21, penetrating the insulating layer 21 and exposing the top surfaces of the pads 20P. Also, via holes 21z are formed in the magnetic resin 51A, penetrating the magnetic resin 51A and exposing the top surfaces of the pads 20P. The via holes 21z are formed inside the through holes 21y. The via holes 21x and 21z can be formed by, for example, a laser processing method using a CO2 laser or the like. After the via holes 21x and 21z are formed, a desmear process may be performed as necessary to remove resin residue adhering to the surfaces of the pads 20P exposed at the bottoms of the via holes 21x and 21z.

[0060] Next, in the step shown in FIG. 4(a), a wiring layer 22 is formed on one side of the insulating layer 21. The wiring layer 22 includes via wirings 22V filled in the via holes 21x, pads 22P formed on the upper surface of the insulating layer 21, and a wiring pattern. However, the pads 22P on the wiring structure 50A are formed on the upper surface of the insulating layer 21 and the upper surface of the magnetic resin 51A. The material of the wiring layer 22 and the thickness of the pads 22P and wiring pattern may be the same as, for example, the wiring layer 20. The pads 22P are electrically connected to the pads 20P through the via wirings 22V. In this step, the wiring structure 50A including the pads 20P, the insulating layer 21, the magnetic resin 51A, and the via wirings 22V is fabricated.

[0061] The wiring layer 22 can be formed using various wiring formation methods, such as a semi-additive method or a subtractive method. For example, when forming the wiring layer 22 using a semi-additive method, a seed layer of copper or the like is formed by electroless plating on the surface of the insulating layer 21, including the inner walls of the via holes 21x, the surfaces of the pads 20P exposed in the via holes 21x, the surface of the magnetic resin 51A constituting the inner walls of the via holes 21z, and the surfaces of the pads 20P exposed in the via holes 21z. Next, a plating resist pattern having openings corresponding to the shapes of the pads 22P and the wiring pattern of the wiring layer 22 is formed on the seed layer. Next, an electroplated layer of copper or the like is deposited on the seed layer exposed in the openings of the plating resist pattern by electroplating with power supplied from the seed layer. Next, the plating resist pattern is removed, and then etching is performed using the electroplated layer as a mask to remove the seed layer exposed from the electroplated layer, thereby obtaining the wiring layer 22.

[0062] 2(b) to 4(a), wiring structures 50B to 50D and a wiring layer 28 including pads 28P are formed on the wiring structure 50A. Then, a solder resist layer 29 is formed on the wiring structure 50D so as to cover the wiring layer 28 including the pads 28P. The solder resist layer 29 can be formed, for example, by applying a liquid or paste-like photosensitive epoxy insulating resin or acrylic insulating resin to the wiring structure 50D by screen printing, roll coating, spin coating, or the like so as to cover the wiring layer 28. Alternatively, the solder resist layer 29 can be formed, for example, by laminating a film-like photosensitive epoxy insulating resin or acrylic insulating resin on the wiring structure 50D so as to cover the wiring layer 28.

[0063] Next, the solder resist layer 29 is exposed and developed to form openings 29x in the solder resist layer 29 that expose portions of the upper surfaces of the pads 28P (photolithography). The openings 29x may also be formed by laser processing or blasting. In this case, the solder resist layer 29 does not need to be made of a photosensitive material. The planar shape of each of the openings 29x may be, for example, circular. The diameter of each of the openings 29x can be designed as desired to suit the connection target.

[0064] In this step, the above-mentioned metal layer may be formed on the upper surface of the pad 28P exposed at the bottom of the opening 29x by, for example, electroless plating. Alternatively, instead of forming the metal layer, an anti-oxidation treatment such as OSP treatment may be performed.

[0065] Next, external connection terminals 30 such as solder bumps are formed on the upper surfaces of the pads 28P exposed at the bottoms of the openings 29x. The external connection terminals 30 serve as terminals for electrical connection to the semiconductor chip.

[0066] <Modification 1 of the First Embodiment> In Modification 1 of the first embodiment, an example of a wiring board having a protective insulating layer is shown. Note that in Modification 1 of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0067] [Wiring board structure] 5A and 5B are diagrams illustrating a wiring board according to Modification 1 of the first embodiment, in which Fig. 5A is a cross-sectional view and Fig. 5B is an enlarged view of part C in Fig. 5A. Referring to Fig. 5, wiring board 1A differs from wiring board 1 (see Fig. 1) in that a protective insulating layer is laminated on each insulating layer.

[0068] Specifically, in the wiring board 1A, a wiring layer 20, an insulating layer 21, a protective insulating layer 31, a wiring layer 22, an insulating layer 23, a protective insulating layer 32, a wiring layer 24, an insulating layer 25, a protective insulating layer 33, a wiring layer 26, an insulating layer 27, a protective insulating layer 34, a wiring layer 28, and a solder resist layer 29 are sequentially laminated on one surface 10a of the core layer 10. In addition, a wiring layer 40, an insulating layer 41, a protective insulating layer 35, a wiring layer 42, an insulating layer 43, a protective insulating layer 36, a wiring layer 44, an insulating layer 45, a protective insulating layer 37, a wiring layer 46, an insulating layer 47, a protective insulating layer 38, a wiring layer 48, and a solder resist layer 49 are sequentially laminated on the other surface 10b of the core layer 10. The laminate structure on one surface 10a of the core layer 10 and the laminate structure on the other surface 10b are substantially symmetrical with respect to the core layer 10.

[0069] Each insulating layer and the protective insulating layer laminated thereon function as an interlayer insulating layer that insulates adjacent wiring layers. The material for each protective insulating layer can be, for example, an insulating resin containing an epoxy resin as a main component. The material for each protective insulating layer can be the same as or different from the material for each insulating layer. The thickness of each protective insulating layer can be, for example, approximately 10 to 15 μm. In each wiring structure, the protective insulating layer is preferably thinner than the insulating layer. The thinner the protective insulating layer, the thicker the magnetic resin can be, and the greater the inductance value per wiring structure can be.

[0070] As shown in Fig. 5(b), wiring board 1A has wiring structures 50E, 50F, 50G, and 50H stacked in sequence on one surface 10a of core layer 10. Note that wiring board 1A may also have wiring structures stacked in sequence on the other surface 10b of core layer 10 in the region surrounded by dashed line D in Fig. 5(a). The wiring structure in the region surrounded by dashed line D has a structure obtained by inverting the wiring structure in the region surrounded by dashed line C, and therefore a description thereof will be omitted.

[0071] The wiring structure 50E includes pads 20P that constitute the wiring layer 20, an insulating layer 21 that covers the pads 20P, a protective insulating layer 31, a magnetic resin 51A, and via wiring 22V that constitutes the wiring layer 22. The protective insulating layer 31 continuously covers the upper surface of the insulating layer 21 and the upper surface of the magnetic resin 51A.

[0072] The magnetic resin 51A is disposed on the pad 20P within the insulating layer 21. The magnetic resin 51A penetrates the insulating layer 21 but does not penetrate the protective insulating layer 31. The top surface of the magnetic resin 51A is covered with the protective insulating layer 31, and the outer wall surface of the magnetic resin 51A is covered with the insulating layer 21.

[0073] The via wiring 22V penetrates the protective insulating layer 31 and the magnetic resin 51A and is electrically connected to the pad 20P. The magnetic resin 51A is formed in a ring shape so as to surround the periphery of the via wiring 22V in a plan view. In other words, the magnetic resin 51A and the via wiring 22V have a coaxial structure. The total thickness of the magnetic resin 51A and the protective insulating layer 31 is equal to the thickness of the via wiring 22V.

[0074] In this way, a protective insulating layer may be laminated on each insulating layer to serve as an interlayer insulating layer that insulates adjacent wiring layers.

[0075] [Method of manufacturing wiring board] The manufacturing process for wiring board 1A will be described mainly focusing on the differences from the manufacturing process for wiring board 1.

[0076] 6 and 7 are diagrams illustrating a manufacturing process of a wiring board according to Modification 1 of the first embodiment. First, the same processes as those shown in FIGS. 2(a) to 3(b) of the first embodiment are performed. Then, in the process shown in FIG. 6(a), a protective insulating layer 31 is formed to continuously cover the upper surfaces of the insulating layer 21 and the magnetic resin 51A. The protective insulating layer 31 is formed, for example, by laminating a semi-cured film-like epoxy resin or the like on the upper surfaces of the insulating layer 21 and the magnetic resin 51A and then curing it. Alternatively, instead of laminating a film-like epoxy resin or the like, a liquid or paste-like epoxy resin or the like may be applied and then cured to form the protective insulating layer 31. The thickness and other properties of the protective insulating layer 31 are as described above.

[0077] Next, in the step shown in FIG. 6(b), via holes 21x are formed in the insulating layer 21 and the protective insulating layer 31, penetrating the insulating layer 21 and the protective insulating layer 31 to expose the top surfaces of the pads 20P. The pads 20P in which the via holes 21x are formed are located in the same layer as the pads 20P in which the via holes 21z are formed in the protective insulating layer 31 and the magnetic resin 51A in the step shown in FIG. 6(c), and are pads covered only by the insulating layer 21. In other words, the via holes 21x are formed so as to expose the pads on whose top surfaces the magnetic resin 51A is not formed. The via holes 21x can be formed, for example, by laser processing using a CO2 laser or the like. At this stage, the via holes are not formed in the magnetic resin 51A. After the via holes 21x are formed, a desmear process can be performed to remove resin residue adhering to the surfaces of the pads 20P exposed at the bottoms of the via holes 21x. The resin residue can be removed in this step using, for example, chemicals.

[0078] 6(c), via holes 21z are formed in the protective insulating layer 31 and the magnetic resin 51A, penetrating the protective insulating layer 31 and the magnetic resin 51A to expose the top surfaces of the pads 20P. The via holes 21z can be formed, for example, by the same method as the via holes 21x. After the via holes 21z are formed, resin residue adhering to the surfaces of the pads 20P exposed at the bottoms of the via holes 21z can be removed. The resin residue can be removed in this step by, for example, high-pressure water washing.

[0079] 7(a), a wiring layer 22 is formed on one side of the protective insulating layer 31. The wiring layer 22 includes via wirings 22V filled in the via holes 21x and 21z, pads 22P formed on the upper surface of the protective insulating layer 31, and a wiring pattern. The material of the wiring layer 22 and the thickness of the pads 22P and wiring pattern may be the same as, for example, the wiring layer 20. The pads 22P are electrically connected to the pads 20P through the via wirings 22V. In this step, a wiring structure 50E is fabricated, including the pads 20P, the insulating layer 21, the protective insulating layer 31, the magnetic resin 51A, and the via wirings 22V.

[0080] 2(b) to 3(b) and 6(a) to 7(a), wiring structures 50F to 50H and wiring layer 28 including pads 28P are formed on wiring structure 50E. Then, a solder resist layer 29 is formed on wiring structure 50H so as to cover wiring layer 28 including pads 28P.

[0081] As described above, the manufacturing process of the wiring board 1A includes a step of forming the via holes 21x and a step of removing the resin residue in the via holes 21x (step of FIG. 6(b)) between the step of forming the protective insulating layer 31 (step of FIG. 6(a)) and the step of forming the via holes 21z (step of FIG. 6(c)). This allows the removal of the resin residue in the via holes 21x (step of FIG. 6(b)) and the removal of the resin residue in the via holes 21z (step of FIG. 6(c)) to be performed independently by selecting an appropriate method for each step.

[0082] Generally, if the magnetic resin 51A has low chemical resistance, removing the resin residue using chemicals may damage the magnetic resin 51A. However, in the manufacturing process of the wiring board 1A, in the step of FIG. 6(b), the upper surface of the magnetic resin 51A is covered with the protective insulating layer 31. Therefore, even if chemicals are used to remove the resin residue in the via hole 21x, the chemicals do not come into contact with the magnetic resin 51A. Therefore, it is possible to prevent the magnetic resin 51A from being damaged by the chemicals used to remove the resin residue in the via hole 21x. On the other hand, in FIG. 6(c), the resin residue in the via hole 21z can be removed using a method such as high-pressure water washing without using chemicals, so the magnetic resin 51A is not damaged.

[0083] <Modification 2 of the First Embodiment> An example of a coreless wiring board is shown in Modification 2 of the first embodiment. Note that in Modification 2 of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0084] 8 is a cross-sectional view illustrating a wiring board according to Modification 2 of Embodiment 1. Referring to Fig. 8, wiring board 1B differs from wiring board 1 (see Fig. 1) in that wiring board 1B does not have a core layer.

[0085] Specifically, wiring board 1B has a structure in which solder resist layer 29 of wiring board 1 is formed on the top of a laminated structure that was laminated on the other surface 10b side of core layer 10 of wiring board 1. Openings 29x that expose part of the upper surfaces of the pads of wiring layer 40 are formed in solder resist layer 29 of wiring board 1B. External connection terminals 30 are formed on the upper surfaces of the pads of wiring layer 40 that are exposed at the bottom of openings 29x. Furthermore, a wiring structure having a structure similar to that of the area surrounded by dashed line B of wiring board 1 is laminated in the area surrounded by dashed line E of wiring board 1B. A wiring structure having a structure similar to that of the area surrounded by dashed line D of wiring board 1A may be laminated in the area surrounded by dashed line E of wiring board 1B.

[0086] In this way, the laminated structure of the wiring structure can be provided on a wiring board with a core or on a coreless wiring board. Even when the laminated structure of the wiring structure is provided on a coreless wiring board, an inductor can be formed by the magnetic resin and the via wiring by having a wiring structure including a magnetic resin and via wiring penetrating the magnetic resin. This eliminates the need for an external inductor component, making it possible to reduce the size and cost of the wiring board 1B. Furthermore, by stacking multiple wiring structures, a large inductance value can be obtained. Furthermore, since the number of layers of the wiring structure can be determined arbitrarily, design freedom for obtaining the required inductance value can be improved.

[0087] <Modification 3 of the First Embodiment> In the third modification of the first embodiment, an example in which via wirings of different shapes are mixed and stacked is shown. Note that in the third modification of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0088] 9 is a partial cross-sectional view illustrating a wiring board according to Modification 3 of the first embodiment, showing a cross section corresponding to FIG. 1(b). Referring to FIG. 9, wiring board 1C differs from wiring board 1 (see FIG. 1(b)) in that wiring structure 50D is not stacked on wiring structure 50C. In wiring board 1C, via wiring 28V that does not penetrate the magnetic resin is arranged on wiring structure 50C.

[0089] In this way, via wiring that penetrates the magnetic resin and via wiring that does not penetrate the magnetic resin may be mixed and laminated. By making some of the laminated via wirings via wiring that does not penetrate the magnetic resin, the inductance value can be adjusted. Note that the via wiring that does not penetrate the magnetic resin is not limited to the top layer and can be arranged in any layer. Also, via wiring that does not penetrate the magnetic resin may be arranged in multiple layers.

[0090] <Application example of the first embodiment> In the application example of the first embodiment, an example of a semiconductor device in which a semiconductor chip is mounted on a wiring substrate is shown. Note that in the application example of the first embodiment, the description of the same components as those in the already described embodiments may be omitted.

[0091] 10 is a cross-sectional view (part 1) illustrating a semiconductor device according to an application example of the first embodiment. Referring to FIG. 10, the semiconductor device 100 includes the wiring substrate 1 shown in FIG. 1, a semiconductor chip 110, electrode pads 120, bumps 130, and an underfill resin 140.

[0092] The semiconductor chip 110 is, for example, a semiconductor integrated circuit (not shown) formed on a thin semiconductor substrate (not shown) made of silicon, etc. Electrode pads 120 electrically connected to the semiconductor integrated circuit (not shown) are formed on the semiconductor substrate (not shown).

[0093] The bumps 130 are formed on the electrode pads 120 of the semiconductor chip 110 and are electrically connected to the external connection pads 28P of the wiring substrate 1 via the external connection terminals 30 of the wiring substrate 1. An underfill resin 140 is filled between the semiconductor chip 110 and the upper surface of the wiring substrate 1. The bumps 130 are, for example, solder bumps. Examples of materials that can be used for the solder bumps include an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, and an alloy of Sn, Ag, and Cu. Note that bumps to be connected to a motherboard or the like may be formed on the lower surfaces of the pads of the wiring layer 48 exposed at the bottoms of the openings 49x in the solder resist layer 49.

[0094] In this way, a semiconductor device can be realized by mounting a semiconductor chip on the wiring board according to the first embodiment. In the semiconductor device 100, a wiring board 1A may be used instead of the wiring board 1. Also, a coreless wiring board 1B may be used, as in the semiconductor device 100A shown in FIG. 11. In either case of the semiconductor device, the inductor formed by the laminated structure of the wiring structure can be arranged near the semiconductor chip, thereby improving the effects of noise reduction, etc.

[0095] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims. [Explanation of symbols]

[0096] 1, 1A, 1B, 1C wiring board 10 Core Layer 10a One side 10b The other side 10x,21y through hole 11 Through wiring 12 Resin 20,22,24,26,28,40,42,44,46,48 wiring layer 20P, 22P, 24P, 26P Pads 21, 23, 25, 27, 41, 43, 45, 47 Insulating layer 21x, 21z, 23x, 23z, 25x, 25z, 27x, 27z, 41x, 41z, 43x, 43z, 45x, 45z, 47x, 47z via holes 22V, 24V, 26V, 28V via wiring 29,49 Solder resist layer 29x,49x opening 30 External connection terminal 31, 32, 33, 34, 35, 36, 37, 38 Protective insulation layer 50A, 50B, 50C, 50D, 50E, 50F, 50G, 50H Wiring structure 51A,51B,51C,51D Magnetic resin 100,100A semiconductor device 110 Semiconductor Chips 120 electrode pads 130 Bump 140 Underfill resin

Claims

1. Pads and an insulating layer covering a part of the upper surface and a side surface of the pad; a magnetic resin disposed on an upper surface of the pad within the insulating layer; a via wiring that penetrates the magnetic resin and is electrically connected to the pad, a lower surface of the via wiring contacts an upper surface of the pad; a lower surface of the via wiring is flush with a lower surface of the magnetic resin; The wiring board, wherein the side surface of the via wiring is in contact with the magnetic resin.

2. A plurality of the wiring structures are stacked, the pads of the upper wiring structure and the pads of the lower wiring structure are electrically connected via via wirings of the lower wiring structure; the via wirings of each of the wiring structures have portions that overlap with each other in a plan view, The wiring board according to claim 1 , wherein the magnetic resins of the respective wiring structures have portions that overlap each other in a plan view.

3. 3. The wiring board according to claim 1, wherein the upper surface of said insulating layer and the upper surface of said magnetic resin are flush with each other.

4. 4. The wiring substrate according to claim 1, wherein the wiring structure includes a protective insulating layer continuously covering the upper surface of the insulating layer and the upper surface of the magnetic resin, and the via wiring penetrates the protective insulating layer and the magnetic resin and is electrically connected to the pad.

5. The wiring board according to claim 4 , wherein the protective insulating layer is thinner than the insulating layer.

6. 6. The wiring board according to claim 1, further comprising an external connection pad disposed on the wiring structure that is the uppermost layer and electrically connected to the via wiring of the wiring structure that is the uppermost layer.

7. The wiring board according to claim 6 ; a semiconductor chip disposed on the wiring substrate; The semiconductor device is configured such that the semiconductor chip is electrically connected to the external connection pads.

8. forming an insulating layer covering the pads; forming a through hole that penetrates the insulating layer and exposes an upper surface of the pad; forming a magnetic resin to fill the through-hole; forming a via hole that penetrates the magnetic resin and exposes the top surface of the pad; and filling the via hole to form a via wiring electrically connected to the pad.

9. a step of forming a protective insulating layer that continuously covers an upper surface of the insulating layer and an upper surface of the magnetic resin after the step of forming the magnetic resin, 9. The method for manufacturing a wiring board according to claim 8, wherein in the step of forming the via holes, via holes are formed that penetrate the protective insulating layer and the magnetic resin and expose upper surfaces of the pads.

10. a second pad located on the same layer as the pad and covered only by the insulating layer; Between the step of forming the protective insulating layer and the step of forming the via hole, forming a second via hole that penetrates the protective insulating layer and the insulating layer and exposes an upper surface of the second pad; The method for manufacturing a wiring board according to claim 9 , further comprising the step of removing resin residue in the second via hole using a chemical.

Images