circuit board

Abstract

A circuit board according to an embodiment includes an insulating layer including a first region and a second region, a plurality of outer layer circuit patterns arranged on the upper surfaces of the first and second regions of the insulating layer, and a solder resist including a first part arranged in the first region of the insulating layer and a second part arranged in the second region of the insulating layer, wherein at least a portion of the upper surface of the first part includes a curved surface and exposes the upper surface of the outer layer circuit pattern arranged in the first region of the insulating layer, and the second part covers the upper surface of the outer layer circuit pattern arranged in the second region of the insulating layer, and at least a portion of the upper surface of the first part is located lower than the upper surface of the outer layer circuit pattern.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board, and more particularly to a circuit board capable of supporting and protecting the circuit pattern of the outermost layer in an open area using a solder resist, and a method for manufacturing the same. [Background technology]

[0002] As electronic components become smaller, lighter, and more integrated, circuit line widths are becoming finer. In particular, as semiconductor chip design rules move toward nanometer-scale integration, the circuit line widths of package substrates or circuit boards on which semiconductor chips are mounted are becoming finer, down to a few micrometers or less.

[0003] Various methods have been proposed to increase the circuit integration density of circuit boards, i.e., to reduce the circuit line width. SAP (semi-additive process) and MSAP (modified semi-additive process) have been proposed to prevent loss of circuit line width during the etching step to form patterns after copper plating.

[0004] Since then, the ETS (Embedded Trace Substrate, hereinafter referred to as "ETS") method, which embeds copper foil in an insulating layer, has been used in the industry to realize finer circuit patterns. The ETS method embeds copper foil circuits in an insulating layer instead of forming them on the surface of the insulating layer, eliminating circuit loss due to etching and making it advantageous for finer circuit pitches.

[0005] Meanwhile, recently, improved 5G (5G) has been developed to meet the demand for wireless data traffic. th Efforts are underway to develop pre-5G (pre-5G) or 5G generation (pre-5G) communication systems, which use ultra-high frequency (mmWave) bands (sub-6 GHz, 28 GHz, 38 GHz, or higher frequencies) to achieve high data transmission rates.

[0006] In order to mitigate path loss and increase the transmission distance of radio waves in the ultra-high frequency band, integration technologies such as beamforming, massive MIMO, and array antennas are being developed for 5G communication systems. Considering that these frequency bands can be configured with hundreds of active antennas, the antenna system becomes relatively large.

[0007] Because these antennas and AP modules are patterned or mounted on a circuit board, low loss in the circuit board is very important, which means that the multiple boards that make up the active antenna system, i.e., antenna board, antenna feed board, transceiver board, and baseband board, must be integrated into one compact unit.

[0008] Furthermore, circuit boards applied to the above-mentioned 5G communication systems are manufactured in accordance with the trend toward lighter, thinner, shorter, and smaller sizes, and as a result, the circuit patterns are becoming increasingly finer.

[0009] However, conventional circuit boards including fine circuit patterns have a structure in which the outermost circuit patterns protrude above the insulating layer, which causes the outermost circuit patterns to easily collapse. Summary of the Invention [Problem to be solved by the invention]

[0010] In the embodiments, a circuit board with a new structure and a manufacturing method thereof are provided.

[0011] Also, in the embodiments, a circuit board and a manufacturing method thereof are provided that can support and protect the outermost layer circuit pattern included in the SR open area using a solder resist.

[0012] In addition, the present invention provides a circuit board including a solder resist that is subjected to exposure and development processes to expose a circuit pattern in an SR open area, and a method for manufacturing the same.

[0013] In addition, the present invention provides a circuit board including a solder resist whose surface has an upwardly convex shape, and a method for manufacturing the same.

[0014] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0015] A circuit board according to an embodiment includes an insulating layer including a first region and a second region, an outer layer circuit pattern arranged on the upper surfaces of the first and second regions of the insulating layer, and a solder resist including a first part arranged in the first region of the insulating layer and a second part arranged in the second region of the insulating layer, wherein the first part of the solder resist is arranged to expose the upper surface of the outer layer circuit pattern arranged in the first region of the insulating layer, and the second part of the solder resist is arranged to cover the outer layer circuit pattern arranged in the second region of the insulating layer, at least a portion of the upper surface of the first part of the solder resist is located lower than the upper surface of the outer layer circuit pattern, and the upper surface of the first part of the solder resist has a convex shape.

[0016] Further, the first part of the solder resist includes a highest portion located at the highest point on the upper surface of the first part of the solder resist and a lowest portion located at the lowest point on the upper surface of the first part of the solder resist, and the lowest portion is located more adjacent to the outer layer circuit pattern than the highest portion.

[0017] In addition, the highest part is located in a center region of the upper surface of the solder resist arranged between adjacent outer layer circuit patterns among the plurality of outer layer circuit patterns, and the lowest part is located in an edge region of the upper surface of the solder resist arranged between the adjacent outer layer circuit patterns, and the height of the upper surface of the solder resist between the adjacent outer layer circuit patterns decreases from the center region to the edge region.

[0018] The height of the highest portion is greater than the height of the outer layer circuit pattern, and the height of the lowest portion is less than the height of the outer layer circuit pattern.

[0019] The height of the lowest portion is in the range of 70% to 95% of the height of the outer layer circuit pattern, and the height of the highest portion is in the range of 102% to 120% of the height of the outer layer circuit pattern.

[0020] The height of the lowest part is in the range of 80% to 97% of the height of the highest part.

[0021] The second part of the solder resist includes a 2-1 part that vertically overlaps the outer layer circuit pattern and a 2-2 part that does not vertically overlap the outer layer circuit pattern, and the height of the 2-1 part is smaller than the height of the 2-2 part.

[0022] The upper surface of the 2-1 part of the solder resist has a concave shape, and the upper surface of the 2-2 part of the solder resist has a convex shape.

[0023] In addition, the insulating layer is composed of multiple layers, and the outer layer circuit pattern is arranged to protrude above the surface of the insulating layer that is arranged on the uppermost or lowermost side of the insulating layer composed of the multiple layers.

[0024] The package also includes a primer layer disposed between the upper surface of the insulating layer and the lower surface of the solder resist or the lower surface of the outer layer circuit pattern.

[0025] On the other hand, a method for manufacturing a circuit board according to an embodiment includes manufacturing an inner layer substrate, forming a topmost insulating layer having a primer layer disposed on an upper surface of the inner layer substrate, forming an outer layer circuit pattern on the primer layer of the topmost insulating layer, forming a solder resist layer on the primer layer and the outer layer circuit pattern, and partially exposing and developing the solder resist layer to form a solder resist including a first part and a second part, wherein the solder resist layer is disposed in an area vertically overlapping with the outer layer circuit pattern and includes a first part formed on the outer layer circuit pattern, and a second part formed on the primer layer and disposed in an area not vertically overlapping with the outer layer circuit pattern, wherein the height of the second part is greater than the height of the first part.

[0026] The insulating layer also includes a first region in which a first part of the solder resist is disposed and a second region in which a second part of the solder resist is disposed, the first part of the solder resist is disposed exposing an upper surface of an outer layer circuit pattern disposed in the first region of the insulating layer, the second part of the solder resist is disposed covering an outer layer circuit pattern disposed in the second region of the insulating layer, at least a portion of the upper surface of the first part of the solder resist is located lower than an upper surface of the outer layer circuit pattern, and the upper surface of the first part of the solder resist has a convex shape.

[0027] Further, the first part of the solder resist includes a highest portion located at the highest position on the upper surface of the first part of the solder resist, and a lowest portion located at the lowest position on the upper surface of the first part of the solder resist, and the lowest portion is located more adjacent to the outer layer circuit pattern than the highest portion.

[0028] In addition, the highest part is located in a center region of the upper surface of the solder resist arranged between adjacent outer layer circuit patterns among the plurality of outer layer circuit patterns, and the lowest part is located in an edge region of the upper surface of the solder resist arranged between the adjacent outer layer circuit patterns, and the height of the upper surface of the solder resist between the adjacent outer layer circuit patterns decreases from the center region to the edge region.

[0029] The height of the highest portion is greater than the height of the outer layer circuit pattern, and the height of the lowest portion is less than the height of the outer layer circuit pattern.

[0030] The height of the lowest portion is in the range of 70% to 95% of the height of the outer layer circuit pattern, and the height of the highest portion is in the range of 102% to 120% of the height of the outer layer circuit pattern.

[0031] The height of the lowest part is in the range of 80% to 97% of the height of the highest part.

[0032] The second part of the solder resist includes a 2-1 part that vertically overlaps the outer layer circuit pattern and a 2-2 part that does not vertically overlap the outer layer circuit pattern, and the height of the 2-1 part is smaller than the height of the 2-2 part.

[0033] The upper surface of the 2-1 part of the solder resist has a concave shape, and the upper surface of the 2-2 part of the solder resist has a convex shape. [Effects of the Invention]

[0034] The circuit board in this embodiment has a multi-layer structure of eight or more layers, and includes an outer layer circuit pattern disposed on an outer insulating layer located at the top of the layers and protruding above the surface of the outer insulating layer. The outer layer circuit pattern includes a first outer layer circuit pattern disposed in a first area, which is an open area where the solder resist is not disposed, and a second outer layer circuit pattern disposed in a second area where the solder resist is disposed. While the second outer layer circuit pattern can be supported and protected by the solder resist, the first outer layer circuit pattern has a problem in that it is easily destroyed by various factors due to the lack of a support layer to support it.

[0035] As a result, in the embodiment, the solder resist in the first region is not completely removed but is left to support and protect the first outer layer circuit pattern. Accordingly, in the embodiment, problems such as collapse and rubbing of the first outer layer circuit pattern in the first region can be solved by miniaturizing the outer layer circuit pattern, thereby improving product reliability. In particular, in the embodiment, problems such as collapse and frost of traces included in the first outer layer circuit pattern in the first region can be solved, thereby improving product reliability.

[0036] Meanwhile, the solder resist according to the embodiment includes a first part disposed in the first region and a second part disposed in the second region. In this case, the upper surface of the first part may have a convex shape in an upward direction. For example, the upper surface of the first part of the solder resist may have a fourth height in the outer region and a fifth height greater than the fourth height in the inner region. That is, the upper surface of the first part of the solder resist may include a highest portion having the highest height and a lowest portion having the lowest height. The lowest portion may be disposed closer to the first outer layer circuit pattern than the highest portion. This allows the upper surface of the first part of the solder resist to have a convex shape, thereby increasing its surface area. This increases the contact area with a layer (e.g., a molding layer) disposed on the first part, thereby improving bonding strength. Furthermore, the height of the lowest portion is smaller than the height of the first outer layer circuit pattern. This prevents a portion of the first part of the solder resist from remaining on the surface of the first outer layer circuit pattern, thereby improving reliability. In addition, in the embodiment, the height of the highest part of the first part of the solder resist is greater than the height of the first outer layer circuit pattern, so that the solder resist can implement the dam function of the adhesive member through the first part, thereby improving reliability.

[0037] Furthermore, the circuit board in the embodiment can be applied to a 5G communication system, thereby minimizing high-frequency transmission loss and further improving reliability. Specifically, the circuit board in the embodiment can be used at high frequencies and can reduce propagation loss. [Brief explanation of the drawings]

[0038] [Figure 1a] FIG. 10 is a diagram showing a circuit board according to a comparative example. [Figure 1b] FIG. 10 is a diagram showing a circuit board according to a comparative example. [Figure 2]FIG. 10 is a diagram showing a circuit board manufactured by the ETS method in a comparative example. [Figure 3] FIG. 2 is a diagram showing a circuit board according to an embodiment. [Figure 4a] FIG. 4 is an enlarged view of region B in FIG. 3. [Figure 4b] FIG. 4B is an enlarged view of region C in FIG. 4A. [Figure 4c] 10A to 10C are diagrams showing various modifications of the protective layer of the embodiment. [Figure 4d] 10A to 10C are diagrams showing various modifications of the protective layer of the embodiment. [Figure 5] FIG. 3 is a diagram showing a first region and a second region according to an embodiment. [Figure 6] FIG. 10 is a diagram showing the height difference of the solder resist in the second region according to the example. [Figure 7] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 8] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 9] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 10] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 11] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 12] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 13] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; [Figure 14] 1A to 1C are diagrams showing a method for manufacturing a circuit board according to an embodiment in the order of steps; DETAILED DESCRIPTION OF THE INVENTION

[0039] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar components will be designated by the same reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "unit" used in the following description are used interchangeably to facilitate the preparation of the specification and do not have any distinguishing meaning or function. Furthermore, in describing the embodiments disclosed herein, if a detailed description of related well-known technologies is deemed to hinder understanding of the embodiments disclosed herein, such detailed description will be omitted. Furthermore, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, and the accompanying drawings should not be construed as limiting the technical concepts disclosed herein, but should be understood to include all modifications, equivalents, and alternatives within the concept and technical scope of the present invention.

[0040] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0041] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that the component may be directly "coupled" or "connected" to the other component, and that there may be other components between them. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components between them.

[0042] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0043] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of any features, numbers, steps, operations, components, parts, or combinations thereof set forth in the specification, but is not to be understood as precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0044] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0045] Prior to describing this embodiment, a comparative example to be compared with this embodiment will be described.

[0046] FIG. 1 is a diagram showing a circuit board according to a comparative example.

[0047] Referring to FIG. 1(a), the circuit board according to the comparative example includes a circuit pattern manufactured by a general SAP method.

[0048] Specifically, the circuit board includes an insulating layer 10 , a circuit pattern 20 , and a protective layer 30 .

[0049] The circuit patterns 20 are disposed on the upper and lower surfaces of the insulating layer 10, respectively.

[0050] At this time, at least one of the circuit patterns 20 arranged on the surface of the insulating layer 10 includes a fine circuit pattern.

[0051] 1, the circuit pattern 20 disposed on the upper surface of the insulating layer 10 includes a fine circuit pattern. The fine circuit pattern includes traces 21, which are signal transmission wiring lines, and pads 22 for chip mounting or the like.

[0052] In this example, a support layer using a solder resist is formed for the purpose of protecting the fine circuit pattern, so the structure in the area where the fine circuit pattern is formed in the comparative example will be described.

[0053] In addition, a protective layer 30 for protecting the circuit pattern 20 is disposed on the surface of the insulating layer 10 .

[0054] In this case, the upper region of the insulating layer 10 includes a first region where the protective layer 30 is disposed and a second region which is an open region where the protective layer 30 is not disposed.

[0055] As a result, a portion of the circuit pattern 20 disposed on the upper surface of the insulating layer 10 is covered by the protective layer 30, and the remaining portion is not covered by the protective layer 30 and is exposed to the outside.

[0056] At this time, the traces 21 and pads 22 corresponding to the fine circuit pattern are disposed in the second region, which is the open region of the protective layer 30, as described above.

[0057] For example, at least one of the traces 21 and pads 22 is formed with a width / spacing of 15 μm / 15 μm or less.

[0058] At this time, if the circuit pattern formed in the open area of ​​the protective layer 30 is not a fine circuit pattern but a pattern having a width exceeding 15 μm, it may be resistant to external impact.

[0059] However, as shown in FIG. 1(b), as circuit patterns become increasingly finer, the width and spacing of the traces 21, which are the fine circuit patterns of the outermost layer, become smaller and smaller. As a result, when a fine circuit pattern protruding above the top surface of the insulating layer 10 is placed in the second region, which is the open region of the protective layer, a problem occurs in that the fine circuit pattern can easily collapse due to external impact.

[0060] That is, as shown in FIG. 1(b) B, the trace 21 corresponding to the fine circuit pattern on the outermost layer has an extremely fine pattern shape, which causes the problem of it easily collapsing or being rubbed even with a small external impact.

[0061] Recently, the ETS method has been used to form fine circuit patterns that are embedded in an insulating layer and are placed in open areas of a protective layer.

[0062] FIG. 2 is a diagram showing a circuit board manufactured by the ETS method in a comparative example.

[0063] Referring to FIG. 2, specifically, the circuit board includes an insulating layer 10A, a circuit pattern 20A, and a protective layer 30A.

[0064] The circuit patterns 20A are disposed on the upper and lower surfaces of the insulating layer 10A.

[0065] At this time, at least one of the circuit patterns 20A arranged on the surface of the insulating layer 10A includes a fine circuit pattern.

[0066] Here, when a circuit pattern is formed by the ETS method, the initially formed circuit pattern has a structure in which it is embedded in the insulating layer 10A. As a result, when the initially formed circuit pattern is formed into a fine circuit pattern, even in the comparative example, the fine circuit pattern can have a structure in which it is embedded in the insulating layer 10A.

[0067] That is, a circuit board manufactured by the ETS method includes a fine circuit pattern having a structure embedded in the surface of the insulating layer 10A, that is, traces 21A which are signal transmission wiring lines, and pads 22A for chip mounting, etc.

[0068] In addition, in the case of a circuit board manufactured by the ETS method as described above, the fine circuit pattern is embedded in the insulating layer, so that the fine circuit pattern can be protected from external impacts.

[0069] At this time, there are no major problems with using the ETS method to manufacture circuit boards with a two-layer structure (based on the number of layers in the circuit pattern) as shown in Figure 2. However, when using the ETS method to manufacture circuit boards with eight or more layers, especially ten or more, the lead time for manufacturing them is at least two months, which reduces productivity.

[0070] Furthermore, to manufacture a fine circuit pattern with an embedded structure using the ETS method, the fine circuit pattern must be formed first during the manufacturing process of a multi-layer circuit board. Recently, for application to AP modules with high integration and specifications, 8- to 10-layer circuit boards are required. However, during the ETS process, the fine circuit pattern is first formed, and then, during the subsequent multi-layer lamination process, the fine circuit pattern can be damaged due to thermal stress, making it difficult to properly implement the fine circuit pattern.

[0071] In addition, when manufacturing a circuit board using the ETS method, a separate ETS core layer is required, and in this case, an additional process of removing the ETS core layer is required.

[0072] In addition, when manufacturing circuit boards using the ETS method, there is a problem that the yield decreases due to cumulative tolerances when layers are stacked more than a certain number of times, which increases the product cost. There is also a problem that pattern damage due to stress increases because stacking processes are performed on both sides of the ETS core layer.

[0073] Recently, with the development of 5G technology, interest has been growing in circuit boards that can reflect this technology. To apply 5G technology, circuit boards must have a highly multi-layer structure, which requires finer circuit patterns. However, while the comparative example can form fine patterns, it has a problem in that it cannot stably protect the patterns.

[0074] Therefore, the present embodiment aims to provide a circuit board with a new structure that can solve the reliability problem of the fine patterns arranged on the outermost side, and a control method thereof.

[0075] FIG. 3 is a diagram showing a circuit board according to an embodiment, FIG. 4a is an enlarged view of area B in FIG. 3, FIG. 4b is an enlarged view of area C in FIG. 4a, FIGS. 4c and 4d are diagrams showing various modified examples of the protective layer of the embodiment, FIG. 5 is a diagram showing the first and second areas according to the embodiment, and FIG. 6 is a diagram showing the height difference of the solder resist in the second area according to the embodiment.

[0076] 3 and 4, the circuit board according to the embodiment may have a multi-layer structure. Preferably, the circuit board according to the embodiment may have a structure of 10 or more layers based on the number of layers of the circuit pattern. However, this is merely an example and is not limited thereto. That is, the circuit board according to the embodiment may have a number of layers less than 10, or alternatively, may have a number of layers greater than 10.

[0077] However, the circuit board in the example is intended to solve the problems of the ETS method in the comparative example, which has many problems when manufacturing a circuit board with 8 or more layers, so for comparison, the example will be described as having a 10-layer structure.

[0078] Referring to FIGS. 3, 4 a and 4 b, the circuit board 100 includes an insulating layer 110 .

[0079] Preferably, the circuit board 100 may include first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118, and 119 to implement a ten-layer structure.

[0080] In this case, of the insulating layers 110, the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, the fourth insulating layer 114, the fifth insulating layer 115, the sixth insulating layer 116, and the seventh insulating layer 117 may be internal insulating layers arranged on the inside in the laminated structure of the insulating layers, the eighth insulating layer 118 may be the uppermost insulating layer (first outermost insulating layer) arranged on top of the internal insulating layers, and the ninth insulating layer 119 may be the lowermost insulating layer (second outermost insulating layer) arranged below the internal insulating layers.

[0081] The first insulating layer 111 may be a core insulating layer disposed at the center of the laminated structure of the insulating layers 110. The second insulating layer 112, the fourth insulating layer 114, the sixth insulating layer 116, and the eighth insulating layer 118 may be upper insulating layers disposed in this order above the first insulating layer 111. The third insulating layer 113, the fifth insulating layer 115, the seventh insulating layer 117, and the ninth insulating layer 119 may be lower insulating layers disposed in this order below the first insulating layer 111.

[0082] The insulating layer 110 is a substrate on which electrical circuits that can be rewired are organized, and can include any printed circuit board, wiring board, or insulating substrate made of insulating material on whose surface a circuit pattern can be formed.

[0083] For example, at least one of the insulating layers 110 may be rigid or flexible. For example, at least one of the insulating layers 110 may include glass or plastic. In particular, at least one of the insulating layers 110 may include chemically strengthened / semi-strengthened glass such as soda lime glass or aluminosilicate glass, or may include reinforced or ductile plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), or polycarbonate (PC), or may include sapphire.

[0084] At least one of the insulating layers 110 may include an optically isotropic film. For example, at least one of the insulating layers 110 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optically isotropic polycarbonate (PC), an optically isotropic polymethyl methacrylate (PMMA), or the like.

[0085] In addition, at least one of the insulating layers 110 may be partially curved. That is, at least one of the insulating layers 110 may be partially flat and partially curved. In particular, at least one of the insulating layers 110 may be curved with a curved end or may be bent or folded with a surface including a random curvature.

[0086] At least one of the insulating layers 110 may be a flexible substrate having flexibility. At least one of the insulating layers 110 may be a curved or bent substrate. In this case, at least one of the insulating layers 110 may represent electrical wiring connecting circuit components based on a circuit design as a wiring diagram, thereby reproducing electrical conductors on the insulator. At least one of the insulating layers 110 may mount electrical components and form wiring connecting the components in a circuit, and may mechanically fix components other than those that electrically connect the components.

[0087] A circuit pattern may be disposed on the surface of the insulating layer 110 .

[0088] That is, the circuit pattern 110 can be disposed on the surface of each of the first to ninth insulating layers 111, 112, 113, 114, 115, 116, 117, 118, and 119 that constitute the insulating layer 110.

[0089] Here, the circuit patterns may include an inner layer circuit pattern 120 and outer layer circuit patterns 130, 140. The inner layer circuit pattern 120 may be a circuit pattern disposed inside the insulating layer 110 in the laminated structure of the circuit board, and the outer layer circuit patterns 130, 140 may be circuit patterns disposed on the outermost side of the insulating layer 110 in the laminated structure of the circuit board.

[0090] The inner layer circuit pattern 120 may include a first circuit pattern 121, a second circuit pattern 122, a third circuit pattern 123, a fourth circuit pattern 124, a fifth circuit pattern 125, a sixth circuit pattern 126, and a seventh circuit pattern 127.

[0091] The first circuit pattern 121 may be disposed on the upper surface of the first insulating layer 111 and may be covered by the second insulating layer 112. The second circuit pattern 122 may be disposed on the lower surface of the first insulating layer 111 and may be covered by the third insulating layer 113. The third circuit pattern 123 may be disposed on the upper surface of the second insulating layer 112 and may be covered by the fourth insulating layer 114. The fourth circuit pattern 124 may be disposed on the lower surface of the third insulating layer 113 and may be covered by the fifth insulating layer 115. The fifth circuit pattern 125 may be disposed on the upper surface of the fourth insulating layer 114 and may be covered by the sixth insulating layer 116. The sixth circuit pattern 126 may be disposed on the lower surface of the fifth insulating layer 115 and may be covered by the seventh insulating layer 117. The seventh circuit pattern 127 may be disposed on the upper surface of the sixth insulating layer 116 and may be covered by the eighth insulating layer 118. The eighth circuit pattern 128 may be disposed on the lower surface of the seventh insulating layer 117 and may thereby be covered by the ninth insulating layer.

[0092] The outer layer circuit pattern may be disposed on the surface of the outermost insulating layer disposed on the outermost side of the insulating layers 110. Preferably, the outer layer circuit pattern may include a lower outer layer circuit pattern 130 disposed on the lower surface of the ninth insulating layer 119 disposed on the lowermost side of the insulating layers 110.

[0093] In addition, the outer layer circuit pattern may include an upper outer layer circuit pattern 140 disposed on the upper surface of the eighth insulating layer 118 disposed on the uppermost one of the insulating layers 110 .

[0094] At least one of the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 may be formed to protrude above the surface of the insulating layer. Preferably, the lower outer layer circuit pattern 130 may be formed to protrude below the lower surface of the ninth insulating layer 119. Also, the upper outer layer circuit pattern 140 may be formed to protrude above the upper surface of the eighth insulating layer 118.

[0095] That is, the upper surface of the lower outer layer circuit pattern 130 may be located on the same plane as the lower surface of the ninth insulating layer 119. The lower surface of the upper outer layer circuit pattern 140 may be located on the same plane as the upper surface of the primer layer 150, which is disposed on the upper surface of the eighth insulating layer 180.

[0096] In other words, a primer layer 150 may be disposed on the upper surface of the eighth insulating layer 180 and the upper outer layer circuit pattern 140 .

[0097] That is, the upper outer layer circuit pattern 140 may include a fine circuit pattern. Preferably, the upper outer layer circuit pattern 140 may be a fine circuit pattern having a line width of 10 μm or less and an interval between patterns of 10 μm or less. Therefore, if the upper outer layer circuit pattern 140 is directly disposed on the eighth insulating layer 118, the contact area between the eighth insulating layer 118 and the upper outer layer circuit pattern 140 is small, which may cause the second outer layer circuit pattern 150 to separate from the eighth insulating layer 118.

[0098] Therefore, in the embodiment, a primer layer 150 is disposed between the upper outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 may improve adhesion between the upper outer layer circuit pattern 140 and the eighth insulating layer 118. The primer layer 150 may be disposed to entirely cover the upper surface of the eighth insulating layer 118. The upper outer layer circuit pattern 140 may be partially disposed on the primer layer 150. Therefore, in the embodiment, the upper surface of the primer layer 150 may include a first portion that contacts the upper outer layer circuit pattern 140 and a second portion that contacts the lower surface of the solder resist 160 (described below). That is, the primer layer 150 may serve to strengthen adhesion between the eighth insulating layer 118 and the upper outer layer circuit pattern 140 when the upper outer layer circuit pattern 140 is formed by the SAP process. The primer layer 150 may include, but is not limited to, a polyurethane-based resin, an acrylic-based resin, and a silicone-based resin.

[0099] 3 shows that no primer layer is disposed between the ninth insulating layer 119 and the lower outer layer circuit pattern 130, the primer layer may also be disposed between the ninth insulating layer 119 and the lower outer layer circuit pattern 130. However, the lower outer layer circuit pattern 130 may not be a fine circuit pattern, and therefore the primer layer between the ninth insulating layer 119 and the lower outer layer circuit pattern 130 may be selectively omitted.

[0100] In conclusion, when a fine circuit pattern is disposed on an inner layer, the primer layer may be omitted since the fine circuit pattern is covered by at least one of the insulating layers 110. On the other hand, in an embodiment, when a fine circuit pattern is disposed on the outermost layer, there is no insulating layer covering the fine circuit pattern, so the primer layer 150 is disposed to improve the adhesive strength between the fine circuit pattern and the insulating layer.

[0101] In the following description, the upper outer layer circuit pattern 140 is described as being formed as a fine circuit pattern. However, the embodiment is not limited thereto, and the lower outer layer circuit pattern 130 may also be formed as a fine circuit pattern. Therefore, it will be apparent that the structure for improving reliability, such as strengthening the bonding strength and preventing collapse of the upper outer layer circuit pattern 140, described below, can also be applied to the lower outer layer circuit pattern 130.

[0102] The inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 are wirings that transmit electrical signals and may be formed of a metal material with high electrical conductivity. To this end, the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). In addition, the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 may be made of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0103] At least one of the inner layer circuit pattern 120, the lower outer layer circuit pattern 130, and the upper outer layer circuit pattern 140 can be manufactured using a conventional circuit board manufacturing process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP), and detailed description thereof will be omitted here.

[0104] Preferably, the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 are outermost layer circuit patterns disposed on the outermost side of the circuit board, and therefore can be formed by a SAP (Semi Additive Process) method.

[0105] Meanwhile, vias V may be disposed in the insulating layer 110. The vias V may be disposed in each insulating layer, thereby serving to electrically connect circuit patterns disposed on different layers to each other.

[0106] A first via V1 may be disposed in the first insulating layer 111. The first via V1 may electrically connect a first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 to a second circuit pattern 122 disposed on the lower surface of the first insulating layer 111.

[0107] A second via V2 may be disposed in the second insulating layer 112. The second via V2 may electrically connect a first circuit pattern 121 disposed on the upper surface of the first insulating layer 111 to a third circuit pattern 123 disposed on the upper surface of the second insulating layer 112.

[0108] A third via V3 may be disposed in the third insulating layer 113. The third via V3 may electrically connect the second circuit pattern 122 disposed on the lower surface of the first insulating layer 111 to the fourth circuit pattern 124 disposed on the lower surface of the third insulating layer 113.

[0109] A fourth via V4 may be disposed in the fourth insulating layer 114. The fourth via V4 may electrically connect a third circuit pattern 123 disposed on the upper surface of the second insulating layer 112 to a fifth circuit pattern 125 disposed on the upper surface of the fourth insulating layer 114.

[0110] A fifth via V5 may be disposed in the fifth insulating layer 115. The fifth via V5 may electrically connect a fourth circuit pattern 124 disposed on the lower surface of the third insulating layer 113 to a sixth circuit pattern 126 disposed on the lower surface of the fifth insulating layer 115.

[0111] A sixth via V6 may be disposed in the sixth insulating layer 116. The sixth via V6 may electrically connect a fifth circuit pattern 125 disposed on the upper surface of the fourth insulating layer 114 to a seventh circuit pattern 127 disposed on the upper surface of the sixth insulating layer 116.

[0112] A seventh via V7 may be disposed in the seventh insulating layer 117. The seventh via V7 may electrically connect a sixth circuit pattern 126 disposed on the lower surface of the fifth insulating layer 115 to an eighth circuit pattern 128 disposed on the lower surface of the seventh insulating layer 117.

[0113] An eighth via V8 may be disposed in the eighth insulating layer 118. The eighth via V8 may electrically connect the seventh circuit pattern 127 disposed on the upper surface of the sixth insulating layer 116 to the upper outer layer circuit pattern 140 disposed on the upper surface of the primer layer 150.

[0114] A ninth via V9 may be disposed in the ninth insulating layer 119. The ninth via V9 may electrically connect an eighth circuit pattern 128 disposed on the lower surface of the seventh insulating layer 117 to a lower outer layer circuit pattern 130 disposed on the lower surface of the ninth insulating layer 119.

[0115] The vias V may be formed by filling the interior of via holes formed in the respective insulating layers with a metal material.

[0116] The via hole may be formed by any one of mechanical, laser, and chemical processing methods. When the via hole is formed by mechanical processing, methods such as milling, drilling, and routing may be used. When the via hole is formed by laser processing, methods such as UV or CO2 laser may be used. When the via hole is formed by chemical processing, the insulating layer 110 may be opened using a chemical containing aminosilane, ketones, etc.

[0117] On the other hand, laser processing is a cutting method that focuses optical energy on the surface to melt and vaporize part of the material to create the desired shape, and can easily process complex shapes created by computer programs, as well as composite materials that are difficult to cut using other methods.

[0118] In addition, the laser processing has the advantage that the cutting diameter can be as small as 0.005 mm, and the range of thickness that can be processed is wide.

[0119] The laser processing drill is preferably a YAG (Yttrium Aluminum Garnet) laser, a CO2 laser, or an ultraviolet (UV) laser. The YAG laser is a laser that can process both the copper foil layer and the insulating layer, while the CO2 laser is a laser that can process only the insulating layer.

[0120] After the via holes are formed, the interiors of the via holes may be filled with a conductive material to form the first to ninth vias V1, V2, V3, V4, V5, V6, V7, V8, and V9. The metal material forming the first to ninth vias V1, V2, V3, V4, V5, V6, V7, V8, and V9 may be any one selected from the group consisting of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd), and the conductive material may be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjet printing, and dispensing.

[0121] Meanwhile, a protective layer may be disposed on the outermost side of the circuit board 100. Preferably, a first protective layer 160 may be disposed on the eighth insulating layer 118 (preferably, on the primer layer 150). Also, a second protective layer 175 may be disposed on the bottom of the ninth insulating layer 119.

[0122] The first protective layer 160 and the second protective layer 175 may be formed as at least one layer using at least one of SR (Solder Resist), oxide, and Au. Preferably, the first protective layer 160 and the second protective layer 175 may be solder resist.

[0123] Meanwhile, a first protective layer 160 is disposed on the primer layer 150. The first protective layer 160 may play a role in supporting the upper outer layer circuit pattern 140 disposed on the primer layer 150 and protecting the surface of the upper outer layer circuit pattern 140.

[0124] That is, the first protective layer 160 may partially overlap the upper outer layer circuit pattern 140 disposed on the primer layer 150. The area of ​​the first protective layer 160 may be smaller than the area of ​​the eighth insulating layer 118. The area of ​​the first protective layer 160 may be smaller than the area of ​​the primer layer 150. The first protective layer 160 may be partially or entirely disposed on the primer layer 150 and the upper outer layer circuit pattern 140, and may include an open region exposing the surface of the upper outer layer circuit pattern 140.

[0125] Specifically, the first protective layer 160 may include an open region shaped like a hole, that is, the open region of the first protective layer 160 may overlap the first region R1 in a vertical direction to expose the first region R1.

[0126] The first region R1 may be a region above the primer layer 150 and the upper outer layer circuit pattern 140 where the first protective layer 160 is not disposed (ie, an open region of the first protective layer).

[0127] That is, the first region R1 may be a region where the first protective layer 160 is not disposed, so that the upper outer layer circuit pattern 140 is electrically connected to a component such as a chip. As a result, the upper outer layer circuit pattern 140 disposed on the first region R1 may be exposed to the outside without a protective layer to protect it.

[0128] Specifically, the first region R1 is provided with upper circuit patterns 140, including device mounting pads on which chip devices are mounted, core pads or BGA pads that function as dies for connecting to an external board, and traces that serve as signal transmission wiring. The first protective layer 160 has open regions in the first region R1 that expose the surfaces of the upper outer layer circuit patterns 140 corresponding to the device mounting pads, core pads, and BGA pads.

[0129] That is, the circuit board includes a first region R1 and a second region R2. The first region R1 may be an open region where the surface of the upper circuit pattern 140 is to be exposed through the first protective layer 160, and the second region R2 may be a buried region where the surface of the upper circuit pattern 140 is covered by the first protective layer 160.

[0130] The first region R1 is an area in which first pads 142 and traces 141 for electrically connecting with components such as chips in the upper outer layer circuit pattern 140, and second pads (not shown) corresponding to core pads or BGA pads that function as a die for bonding to an external board, etc., are arranged.

[0131] The upper outer layer circuit pattern 140 disposed in the first region R1 may experience reliability problems such as collapse or abrasion due to various factors. Furthermore, the traces 141a constituting the upper outer layer circuit pattern 140 are fine circuit patterns having a line width W1 of 10 μm or less and spacing of 10 μm or less, and are disposed on the primer layer 150. As a result, the traces 141 disposed on the first region R1 may be easily collapsed or abraded by various small external impacts.

[0132] Therefore, in this embodiment, in order to improve the reliability of the upper outer layer circuit pattern 140 arranged on the first region R1, a first protective layer 160 is also arranged on the primer layer 150 corresponding to the first region R1.

[0133] That is, the first protective layer 160 may be disposed on the upper surface of the primer layer 150 in a region where the upper outer layer circuit pattern 140 is not disposed. For example, the first protective layer 160 may be disposed on the upper surface of the primer layer 150, and thus may be disposed between the upper outer layer circuit patterns 140 on the first region R1.

[0134] In this case, the upper outer layer circuit pattern 140 includes a first outer layer circuit pattern disposed in the first region R1 and a second outer layer circuit pattern formed in the second region R2.

[0135] The upper surface of the primer layer 150 may include a first upper surface corresponding to the first region R1 and a second upper surface corresponding to the second region R2.

[0136] In this case, the first protective layer 160 is disposed entirely on the primer layer 150 without dividing the first region R1 and the second region R2. That is, the first protective layer 160 may be disposed in the region between the first outer layer circuit patterns and the region between the second outer layer circuit patterns.

[0137] Thus, the first protective layer 160 includes a first part disposed in the first region R1 and a second part disposed in the second region R2.

[0138] In this case, the first passivation layer 160 may have different heights in different regions.

[0139] In the first region R1, the surface of the upper outer layer circuit pattern 140 should be exposed to the outside, and in the second region R2, the surface of the upper outer layer circuit pattern 140 should be covered with a protective layer.

[0140] The first protective layer 160 may include a first part disposed in the first region R1 and a second part disposed in the second region R2, and the first and second parts may have different heights.

[0141] For example, the top surface of the first part disposed in the first region R1 may be located lower than the top surface of the second part disposed in the second region R2.

[0142] Also, the upper surface of the second part may be positioned higher than the upper surface of the first part.

[0143] In this case, the top surface of the first protective layer 160 may have a curve.

[0144] For example, the top surface of the first protective layer 160 may have a concave shape in the downward direction in a region that vertically overlaps with the upper outer layer circuit pattern 140. For example, the top surface of the first protective layer 160 may have a concave shape in the upward direction in a region that does not vertically overlap with the upper outer layer circuit pattern 140.

[0145] In other words, the height of the upper surface of first protective layer 160 in the area overlapping with upper outer layer circuit pattern 140 may be smaller than the height of the area not overlapping with upper outer layer circuit pattern 140 .

[0146] In this case, the first protective layer 160 includes a first part in a first region R1 and a second part in a second region R2. The first part of the first protective layer 160 exposes the first outer layer circuit pattern. Therefore, the first part of the first protective layer 160 may be selectively disposed in a region that does not vertically overlap the first outer layer circuit pattern. Therefore, the top surface of the first part of the first protective layer 160 may have an upwardly convex shape. For example, the first part of the first protective layer 160 may be disposed between adjacent first outer layer circuit patterns among the plurality of first outer layer circuit patterns.

[0147] Meanwhile, the second part of the first protective layer 160 is disposed to cover the second outer layer circuit pattern. Thus, the second part of the first protective layer 160 includes a 2-1 part disposed in an area vertically overlapping with the upper outer layer circuit pattern 140 and a 2-2 part other than the 2-1 part. The 2-1 part of the first protective layer 160 may have a concave shape on the bottom side. The 2-2 part of the first protective layer 160 may have a convex shape on the top side.

[0148] The first protective layer 160 will be described in detail below.

[0149] The first protective layer 160 may be disposed on the primer layer 150. The first protective layer 160 may be a solder resist.

[0150] The first protective layer 160 may be disposed between the upper outer layer circuit patterns 140 on the primer layer 150. That is, the upper outer layer circuit patterns 140 are disposed at regular intervals on the primer layer 150. The first protective layer 160 may be disposed on an area of ​​the upper surface of the primer layer 150 where the upper outer layer circuit patterns 140 are not disposed. The first protective layer 160 may also be selectively disposed on the upper outer layer circuit patterns 140.

[0151] In the following description, the first protective layer 160 is described as a solder resist 160.

[0152] The solder resist 160 may be disposed on an area of ​​the upper surface of the primer layer 150 where the upper outer layer circuit pattern 140 is not disposed.

[0153] Therefore, the lower surface of the solder resist 160 may be in direct contact with the upper surface of the primer layer 150. Also, the solder resist 160 may have a structure in which it is in direct contact with the upper outer layer circuit pattern 140.

[0154] For example, the first part of the solder resist 160 arranged in the first region R1 may be in direct contact with the side surface of the upper outer layer circuit pattern 140.

[0155] Furthermore, the second part of the solder resist 160 disposed in the second region R2 may be in direct contact with the side surface of the upper outer layer circuit pattern 140. Furthermore, the second part of the solder resist 160 disposed in the second region R2 may be in direct contact with the top surface of the upper outer layer circuit pattern 140. That is, the second part of the solder resist 160 disposed in the second region R2 may protrude by a certain height above the top surface of the upper outer layer circuit pattern 140 and be disposed to cover the upper outer layer circuit pattern 140. In particular, the second part of the solder resist 160 disposed in the second region R2 may be disposed to surround the side surface and top surface of the upper outer layer circuit pattern 140.

[0156] At this time, the solder resist 160 may have different heights for each part, and the height of each part of the solder resist 160 may be determined by the height of the upper outer layer circuit pattern 140.

[0157] The upper outer layer circuit pattern 140 may be disposed on the insulating layer 110 with the first height H1. Herein, the insulating layer 110 may refer to the insulating layer disposed on the uppermost side of a plurality of insulating layers. However, for convenience of explanation, this will be referred to as the insulating layer 110 hereinafter. Meanwhile, a primer layer 150 may be disposed between the insulating layer 110 and the upper outer layer circuit pattern 140. In this case, the upper outer layer circuit pattern 140 may be disposed on the primer layer 150 with the first height H1. Also, the term "height" described below may correspond to "thickness."

[0158] The first height H1 of the upper outer layer circuit pattern 140 may be 12 μm±2 μm. For example, the first height H1 of the upper outer layer circuit pattern 140 may be in the range of 10 μm to 14 μm.

[0159] The second part of the solder resist 160 may be disposed at a certain height above the upper outer layer circuit pattern 140. In this case, the height of the second part of the solder resist 160 may vary depending on the position. That is, the upper surface of the second part of the solder resist 160 may be a curved surface, a rounded surface, or an uneven surface instead of a flat surface.

[0160] At this time, the second part of the solder resist 160 is disposed to cover the upper outer layer circuit pattern 140 in order to stably protect the upper outer layer circuit pattern 140. At this time, the height of the second part of the solder resist 160 may be 7 μm to 17 μm. If the height of the second part of the solder resist 160 is less than 7 μm, the upper outer layer circuit pattern 140 embedded in the second part of the solder resist 160 cannot be stably protected from various factors. Also, if the height of the second part of the solder resist 160 is greater than 17 μm, the overall thickness of the circuit board may increase. Also, if the height of the second part is greater than 17 μm, the manufacturing cost of the circuit board may increase.

[0161] As described above, the second part of the solder resist 160 includes a 2-1 part and a 2-2 part. The highest portion 160-2 of the 2-1 part of the solder resist 160 may have a second height H2. The lowest portion 160-1 of the 2-2 part of the solder resist 160 may have a third height H3. Each of the second height H2 and the third height H3 may be in the range of 7 μm to 17 μm.

[0162] Meanwhile, the difference ΔH between the second height H2 and the third height H3 may be 1 μm to 7 μm. For example, the third height H3 may be in the range of 80% to 97% of the second height H2. For example, the third height H3 may be in the range of 85% to 95% of the second height H2. The third height H3 may be in the range of 88% to 92% of the second height H2.

[0163] Meanwhile, the first part of the solder resist 160 may be disposed in the first region R1. Preferably, the first part of the solder resist 160 may be disposed between the first outer layer circuit patterns of the upper outer layer circuit pattern 140 located in the first region R1.

[0164] In this case, the upper surface of the first part of the solder resist 160 may have an upwardly convex shape. That is, as shown in FIG. 4b, a portion of the upper surface of the first part of the solder resist 160 may be higher than the upper surface of the first outer layer circuit pattern. In addition, a portion of the upper surface of the solder resist 160 may be lower than the upper surface of the first outer layer circuit pattern. For example, the lowest portion of the upper surface of the first part of the solder resist 160 may have a fourth height H4 that is smaller than the first height H1. For example, the highest portion of the upper surface of the first part of the solder resist 160 may have a fifth height H5 that is larger than the first height H1. In this case, the fourth height H4 may be 70% to 95% of the first height H1. For example, the fourth height H4 may be 75% to 90% of the first height H1. In this case, the fourth height H4 may be 75% to 88% of the first height H1. If the fourth height H4 is less than 70% of the first height H1, the first outer layer circuit pattern may not be stably supported by the first part. If the fourth height H4 is more than 95% of the first height H1, some solder resist may remain on the surface of the first outer layer circuit pattern, which may cause reliability problems.

[0165] Meanwhile, the fifth height H5 may be 102% to 120% of the first height H1. The fifth height H5 may be 105% to 118% of the first height H1. The fifth height H5 may be 108% to 115% of the first height H1. If the fifth height H5 is less than 102% of the first height H1, the dam function of the first part, which will be described later, may not be realized. If the fifth height H5 is greater than 120% of the first height H1, the fourth height H4 increases accordingly, which may cause the solder resist 160 to remain on the surface of the first outer layer circuit pattern, resulting in reliability problems. Meanwhile, the fourth height H4 may be the height of a portion of the upper surface of the first part of the solder resist 160 located in an edge region. For example, the fourth height H4 may be the height of an edge portion of the first part of the solder resist 160. That is, the height of the top surface of the first part of the solder resist 160 may decrease as it approaches the first outer circuit pattern and increase as it moves away from the first outer circuit pattern. Thus, the top surface of the first part of the solder resist 160 may have the highest fifth height H5 in the central region, but is not limited to this. However, the lowest portion of the second part of the solder resist 160 having the fourth height H4 may be located closer to the first outer circuit pattern than the highest portion.

[0166] Meanwhile, the difference between the fourth height H4 and the fifth height H5 may be 1 μm to 7 μm. For example, the fourth height H4 may be in the range of 80% to 97% of the fifth height H5. For example, the fourth height H4 may be in the range of 85% to 95% of the fifth height H5. For example, the fourth height H4 may be in the range of 88% to 92% of the fifth height H5.

[0167] Meanwhile, a photo solder resist film may be used as the solder resist 160. The solder resist 160 may have a structure in which a resin and a filler are mixed.

[0168] For example, the solder resist 160 may contain fillers such as BaSO4, SiO2, and Talc, and the content thereof may be 20% to 35% by weight.

[0169] At this time, if the content of the filler contained in the solder resist 160 is less than 20 wt %, the upper outer layer circuit pattern 140 may not be stably protected by the solder resist 160. Also, if the content of the filler contained in the solder resist 160 is more than 35 wt %, some of the filler may remain on the upper outer layer circuit pattern 140 when the solder resist 160 is developed, which may cause reliability problems or require an additional process to remove the filler.

[0170] On the other hand, the upper surface of the second part of the solder resist 160 in the embodiment is a portion that has not been exposed or developed.

[0171] The upper surface of the first part of the solder resist 160 is the portion that has been exposed and developed.

[0172] Therefore, the filler may be partially exposed on the top surface of the first part of the solder resist 160. However, the filler may not be directly exposed on the top surface of the second part of the solder resist 160.

[0173] Therefore, the surface roughness of the first part of the solder resist 160 may be different from the surface roughness of the second part of the solder resist 160. For example, the surface roughness of the first part may be greater than the surface roughness of the second part of the solder resist 160.

[0174] Meanwhile, as described above, the first outer layer circuit pattern includes pads. An adhesive member, such as a solder ball, is disposed on the pads for mounting devices. In this embodiment, a portion of the top surface of the first part of the solder resist 160 is positioned higher than the top surface of the first outer layer circuit pattern. Therefore, the first part of the solder resist 160 functions to support the first outer layer circuit pattern disposed in the first region, and also functions as a dam that fixes the position of the adhesive member disposed on the first outer layer circuit pattern.

[0175] Meanwhile, as shown in FIG. 4c, the height of the highest and lowest portions of the solder resist 160a may be selectively changed.

[0176] That is, the height of the lowest portion of the solder resist 160a may have a fourth height H4' that is the same as the height H1 of the first outer layer circuit pattern. Also, the height of the highest portion of the solder resist 160a may have a fifth height H5' that is greater than the height H1 of the first outer layer circuit pattern. However, because the height of the lowest portion is the same as the first height H1 as described above, solder resist may remain on the first outer layer circuit pattern, and therefore an additional process may be performed to remove it.

[0177] As shown in FIG. 4d, the height of the peaks and valleys of the solder resist 160b may be selectively changed.

[0178] That is, the height of the lowest portion of the solder resist 160b may have a fourth "height H4" that is smaller than the height H1 of the first outer layer circuit pattern. Also, the height of the highest portion of the solder resist 160b may have a fifth "height H5" that is smaller than the height H1 of the first outer layer circuit pattern. However, if the height H5" of the highest portion is smaller than the first height H1, the fourth "height H4" is also reduced accordingly, which may cause a problem with the support function of the embodiment. Also, if the height H5" of the highest portion is smaller than the first height H1, the dam function of the adhesive member disposed on the first outer layer circuit pattern cannot be realized, which may cause a reliability problem such that the adhesive member changes position when disposed.

[0179] Therefore, in the embodiment, as shown in FIG. 4b, the height of the highest part of the solder resist 160 is greater than the height of the first outer layer circuit pattern, and the height of the lowest part of the solder resist 160 is less than the height of the first outer layer circuit pattern.

[0180] The circuit board in this embodiment has a multi-layer structure of eight or more layers, and includes an outer layer circuit pattern disposed on an outer insulating layer located at the top of the layers and protruding above the surface of the outer insulating layer. The outer layer circuit pattern includes a first outer layer circuit pattern disposed in a first area, which is an open area where the solder resist is not disposed, and a second outer layer circuit pattern disposed in a second area where the solder resist is disposed. While the second outer layer circuit pattern can be supported and protected by the solder resist, the first outer layer circuit pattern has a problem in that it is easily destroyed by various factors due to the lack of a support layer to support it.

[0181] As a result, in the embodiment, the solder resist in the first region is not completely removed but is left to support and protect the first outer layer circuit pattern. Accordingly, in the embodiment, problems such as collapse and rubbing of the first outer layer circuit pattern in the first region can be solved by miniaturizing the outer layer circuit pattern, thereby improving product reliability. In particular, in the embodiment, problems such as collapse and frost of traces included in the first outer layer circuit pattern in the first region can be solved, thereby improving product reliability.

[0182] Meanwhile, the solder resist according to the embodiment includes a first part disposed in the first region and a second part disposed in the second region. In this case, the upper surface of the first part may have a convex shape in an upward direction. For example, the upper surface of the first part of the solder resist may have a fourth height in the outer region and a fifth height greater than the fourth height in the inner region. That is, the upper surface of the first part of the solder resist may include a highest portion having the highest height and a lowest portion having the lowest height. The lowest portion may be disposed closer to the first outer layer circuit pattern than the highest portion. This allows the upper surface of the first part of the solder resist to have a convex shape, thereby increasing its surface area. This increases the contact area with a layer (e.g., a molding layer) disposed on the first part, thereby improving bonding strength. Furthermore, the height of the lowest portion is smaller than the height of the first outer layer circuit pattern. This prevents a portion of the first part of the solder resist from remaining on the surface of the first outer layer circuit pattern, thereby improving reliability. In addition, in the embodiment, the height of the highest part of the first part of the solder resist is greater than the height of the first outer layer circuit pattern, so that the solder resist can implement the dam function of the adhesive member through the first part, thereby improving reliability.

[0183] Furthermore, the circuit board in the embodiment can be applied to a 5G communication system, thereby minimizing high-frequency transmission loss and further improving reliability. Specifically, the circuit board in the embodiment can be used at high frequencies and can reduce propagation loss.

[0184] Meanwhile, in the embodiment, when forming the solder resist 160 as described above, various methods can be used to remove a portion of the solder resist 160 from the first region R1. For example, the portion of the solder resist 160 can be removed by a physical method or a chemical method. For example, the solder resist 160 can be removed by methods such as plasma or sandblasting.

[0185] However, when the solder resist 160 is removed using a physical or chemical method, the upper outer layer circuit pattern 140 is also removed during the removal process, resulting in deformation of the upper outer layer circuit pattern 140. For example, the upper outer layer circuit pattern 140 may have a triangular cross section due to a portion of the solder resist 160 being removed during the removal process. Furthermore, if the upper portion of the upper outer layer circuit pattern 140 has a triangular shape, adhesive members such as solder balls cannot be stably attached to the upper outer layer circuit pattern 140, which may result in reliability issues. Furthermore, removing the protective layer using the physical or chemical method requires expensive equipment, which may increase manufacturing costs.

[0186] Meanwhile, in this embodiment, a thinning method using an exposure and development process is applied to remove the solder resist 160 so that each region has a desired height. Furthermore, the exposure and development process does not cause deformation of the upper outer layer circuit pattern 140, and the cross-sectional shape of the upper outer layer circuit pattern 140 can maintain a rectangular shape.

[0187] 7 to 14 are diagrams showing the manufacturing method of the circuit board according to the embodiment in the order of steps.

[0188] Referring to FIG. 7, in this embodiment, a process for manufacturing an inner layer board 100-1 that manufactures the inner portion of the circuit board 100 can be performed.

[0189] The steps for manufacturing the inner substrate 100-1 will now be briefly described.

[0190] The inner substrate 100-1 may include one insulating layer, or alternatively, may include multiple insulating layers.

[0191] 7, the inner substrate 100-1 is shown to have a seven-layer insulating layer structure, but is not limited thereto. For example, the inner substrate 100-1 may include fewer than seven insulating layers, or alternatively, may include more than seven insulating layers.

[0192] The inner substrate 100-1 may include the remaining insulating layers excluding the insulating layers arranged on the outermost layers of the circuit board 100. For example, the inner substrate 100-1 may include the remaining insulating layers excluding the insulating layer arranged on the top and bottom of the circuit board 100.

[0193] To briefly explain the process of manufacturing the inner substrate 100-1, the first insulating layer 111 is prepared first.

[0194] After the first insulating layer 111 is prepared, a first via V1 is formed in the first insulating layer 111, and a first circuit pattern 121 and a second circuit pattern 122 are formed on the upper and lower surfaces of the first insulating layer 111, respectively.

[0195] Thereafter, a second insulating layer 112 is formed on the first insulating layer 111, and a third insulating layer 113 is formed under the first insulating layer 111.

[0196] Next, a second via V2 is formed in the second insulating layer 112, and a third circuit pattern 123 is formed on the upper surface of the second insulating layer 112. Further, a third via V3 is formed in the third insulating layer 113, and a fourth circuit pattern 124 is formed below the lower surface of the third insulating layer 113.

[0197] Thereafter, a fourth insulating layer 114 is formed on the second insulating layer 112, and a fifth insulating layer 115 is formed under the third insulating layer 113.

[0198] Next, a fourth via V4 is formed in the fourth insulating layer 114, and a fifth circuit pattern 125 is formed on the upper surface of the fourth insulating layer 114. Further, a fifth via V5 is formed in the fifth insulating layer 115, and a sixth circuit pattern 126 is formed below the lower surface of the fifth insulating layer 115.

[0199] Thereafter, a sixth insulating layer 116 is formed on the fourth insulating layer 114, and a seventh insulating layer 117 is formed under the fifth insulating layer 115.

[0200] Next, a sixth via V6 is formed in the sixth insulating layer 116, and a seventh circuit pattern 127 is formed on the upper surface of the sixth insulating layer 116. Further, a seventh via V7 is formed in the seventh insulating layer 117, and an eighth circuit pattern 128 is formed below the lower surface of the seventh insulating layer 117.

[0201] The process for manufacturing the inner substrate 100-1 is well known in the art to which the present invention pertains, and therefore a detailed description thereof will be omitted.

[0202] 8, after the inner substrate 100-1 is manufactured, an eighth insulating layer 118 corresponding to the first outermost insulating layer is formed on the upper surface of the inner substrate 100-1, and a ninth insulating layer 119 corresponding to the second outermost insulating layer is formed under the lower surface of the inner substrate 100-1.

[0203] When the eighth insulating layer 118 and the ninth insulating layer 119 are stacked, a primer layer 150 may be disposed on an upper surface of the eighth insulating layer 118 and a lower surface of the ninth insulating layer 119, respectively, and a metal layer 155 may be disposed on the primer layer 150. The metal layer 155 may serve to planarize the eighth insulating layer 118 and the ninth insulating layer 119 so that they have a uniform height. For example, the metal layer 155 may be disposed to improve the stacking reliability of the eighth insulating layer 118 and the ninth insulating layer 119.

[0204] The primer layer 150 may serve to enhance the adhesive strength between the eighth insulating layer 118 and the ninth insulating layer 119 and the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 disposed above and below the eighth insulating layer 118 and the ninth insulating layer 119. That is, if the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 were disposed without the primer layer 150, the adhesive strength between the eighth insulating layer 118 and the upper outer layer circuit pattern 140 would be weak, and they may be separated from each other.

[0205] 8 illustrates the primer layer 150 being disposed on the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119, but this is not limiting. For example, the primer layer 150 may be selectively disposed on the surface of an insulating layer on which a fine circuit pattern is disposed. That is, if only the lower outer layer circuit pattern 130 is a fine circuit pattern, the primer layer 150 may be disposed only on the lower surface of the ninth insulating layer 119. Also, if only the upper outer layer circuit pattern 140 is a fine circuit pattern, the primer layer 150 may be disposed only on the upper surface of the eighth insulating layer 118. Also, if both the lower outer layer circuit pattern 130 and the upper outer layer circuit pattern 140 are fine circuit patterns, the primer layer 150 may be disposed on both the upper surface of the eighth insulating layer 118 and the lower surface of the ninth insulating layer 119.

[0206] 9, after the eighth insulating layer 118 and the ninth insulating layer 119 are disposed, via holes VH are formed in the eighth insulating layer 118 and the ninth insulating layer 119. In this case, the via holes VH may be formed not only in the eighth insulating layer 118 and the ninth insulating layer 119 but also in the primer layer 150 and the metal layer 155, respectively.

[0207] 10, once the via holes VH are formed, an etching process may be performed to remove the metal layer 155 disposed on the primer layer 150. For example, after the via holes VH are formed, a flash etching process may be performed to remove the metal layer 155, thereby exposing the surface of the primer layer 150.

[0208] 11 , a via V formation process may be performed to fill the via holes VH, thereby forming an upper outer layer circuit pattern 140 on the upper surface of the eighth insulating layer 118 and a lower outer layer circuit pattern 130 on the lower surface of the ninth insulating layer 119. In this embodiment, the lower outer layer circuit pattern 130 is a general circuit pattern rather than a fine circuit pattern. However, the present invention is not limited thereto, and the lower outer layer circuit pattern 130 may also be a fine circuit pattern, along with the second outer layer circuit pattern. Therefore, if the lower outer layer circuit pattern 130 is a general circuit pattern, the primer layer 150 between the ninth insulating layer 119 and the lower outer layer circuit pattern 130 may be omitted.

[0209] An upper outer layer circuit pattern 140 is disposed on the upper surface of the eighth insulating layer 118. The upper outer layer circuit pattern 140 disposed on the upper surface of the eighth insulating layer 118 may include a portion disposed in the open region R1 of the first protective layer 160 and a portion disposed in the placement region R3 of the first protective layer 160. Traces and pads, which are wiring lines for signal transmission, may be disposed in the respective regions R1 and R2.

[0210] Specifically, the first region R1 may include a trace 141 and a first pad 142. The first pad 142 may be a mounting pad on which an element is mounted. The first region R1 may also include a second pad (not shown). The second pad may be a BGA pad or a core pad. In particular, the second pad may have a width greater than that of the first pad 142.

[0211] Next, in an embodiment, a solder resist 160 (first protective layer) is disposed on the primer layer 150 so as to cover the upper outer layer circuit pattern 140. The solder resist layer formed at this time may be disposed in both the first region R1 and the second region R2, and may be formed to have a height greater than that of the upper outer layer circuit pattern 140.

[0212] Specifically, the upper outer layer circuit pattern 140 may be disposed on the insulating layer 110 with the first height H1. The insulating layer 110 may refer to the insulating layer disposed on the uppermost side of a plurality of insulating layers. However, for convenience of explanation, this will be referred to as the insulating layer 110 hereinafter. Meanwhile, a primer layer 150 may be disposed between the insulating layer 110 and the upper outer layer circuit pattern 140. In this case, the upper outer layer circuit pattern 140 may be disposed on the primer layer 150 with the first height H1. Also, the term "height" described below may correspond to "thickness."

[0213] The first height H1 of the upper outer layer circuit pattern 140 may be 12 μm±2 μm. For example, the first height H1 of the upper outer layer circuit pattern 140 may be in the range of 10 μm to 14 μm.

[0214] At this time, the solder resist 160 may be disposed on the upper outer layer circuit pattern 140 with a certain height.

[0215] At this time, the solder resist 160 is disposed to cover the upper outer layer circuit pattern 140 in order to stably protect the upper outer layer circuit pattern 140. At this time, the height of the solder resist 160 may be 7 μm to 17 μm. If the height of the solder resist 160 is less than 7 μm, the upper outer layer circuit pattern 140 embedded in the solder resist 160 cannot be stably protected from various factors. Also, if the height of the solder resist 160 is greater than 17 μm, the overall thickness of the circuit board may increase. Also, if the height of the solder resist 160 is greater than 17 μm, the manufacturing cost of the circuit board may increase.

[0216] Meanwhile, the solder resist 160 may have different heights depending on the position.

[0217] That is, the solder resist 160 may be divided into a first portion disposed on the upper outer layer circuit pattern 140 and a second portion disposed on the primer layer 150. The top surface of the first portion of the solder resist 160 may have a different shape from the top surface of the second portion of the solder resist 160. For example, the top surface of the first portion of the solder resist 160 may have a concave shape. However, the embodiment is not limited thereto, and the top surface of the first portion of the solder resist 160 may have a flat shape. For example, the top surface of the second portion of the solder resist 160 may have a convex shape. That is, the top surface of the second portion of the solder resist 160 may be positioned higher than the top surface of the first portion of the solder resist 160.

[0218] In this case, the highest portion of the second portion of the solder resist 160 may have a second height H2. In addition, the lowest portion of the first portion of the solder resist 160 may have a third height H3. In this case, the second height H2 and the third height H3 may each be in the range of 7 μm to 17 μm.

[0219] Meanwhile, the difference ΔH between the second height H2 and the third height H3 may be 1 μm to 7 μm. For example, the third height H3 may be in the range of 80% to 97% of the second height H2. For example, the third height H3 may be in the range of 85% to 95% of the second height H2. The third height H3 may be in the range of 88% to 92% of the second height H2.

[0220] That is, the solder resist 160 includes a negative photoresist (negative PR), which has a specific swelling phenomenon depending on the environment.

[0221] For example, the shape of the upper surface of the solder resist 160 can be controlled depending on the environment and exposure time after the lamination process. That is, in the embodiment, the environment and exposure time after the lamination process of the solder resist 160 are controlled to adjust the degree of moisture absorption of the negative photoresist, thereby changing the upper surface of the solder resist 160 into a desired shape.

[0222] At this time, moisture adsorbed to the solder resist 160 gathers between the circuit patterns due to its inherently high surface tension (capillary effect). For example, the adsorbed moisture gathers more in the area where the upper outer layer circuit pattern 140 is not disposed than in the area where the upper outer layer circuit pattern 140 is disposed. As a result, the solder resist 160 has a flat or concave shape in the area where the upper outer layer circuit pattern 140 is disposed, and has a convex shape due to upward swelling caused by a swelling phenomenon in the area where the upper outer layer circuit pattern 140 is not disposed.

[0223] 12, in an embodiment, an exposure process may be performed to thin specific areas of the solder resist 160.

[0224] The exposure may be performed only on the second region R2 of the first region R1 and the second region R2 of the solder resist 160.

[0225] Here, the portion exposed to light is hardened and is not thinned in the subsequent development process.

[0226] 13, a development process may be performed on the portion that has not been hardened in the exposure process. At this time, the solder resist 160 formed in the developed portion may have a height sufficient to expose the upper outer layer circuit pattern 140.

[0227] The developing process may include thinning the unexposed areas using an organic alkaline compound containing tetramethylammonium hydroxide (TMAH) or trimethyl-2-hydroxyethylammonium hydroxide (choline).

[0228] Through the above process, the solder resist 160 in this embodiment includes a first part in the first region R1 where the thinning has been performed and a second part in the second region R2 where the thinning has not been performed. As described above, due to the swelling phenomenon, a height difference occurs in the second part of the solder resist 160 between the region where the upper outer layer circuit pattern 140 is disposed and the region where the upper outer layer circuit pattern 140 is not disposed. That is, the top surface of the second part of the solder resist 160 has a concave shape in the region where the upper outer layer circuit pattern 140 is disposed and a convex shape in the region where the upper outer layer circuit pattern 140 is not disposed.

[0229] Meanwhile, in an embodiment, as shown in Fig. 14, an additional process may be performed on the top surface of the second part of the solder resist 160. For example, the top surface of the second part of the solder resist 160 may have different heights depending on the position, and a process for planarizing the top surface may be further performed. For example, in an embodiment, a process for polishing the top surface of the second part of the solder resist 160 may be performed to planarize the second part of the solder resist 160.

[0230] The circuit board in this embodiment has a multi-layer structure of eight or more layers, and includes an outer layer circuit pattern disposed on an outer insulating layer located at the top of the layers and protruding above the surface of the outer insulating layer. The outer layer circuit pattern includes a first outer layer circuit pattern disposed in a first area, which is an open area where the solder resist is not disposed, and a second outer layer circuit pattern disposed in a second area where the solder resist is disposed. While the second outer layer circuit pattern can be supported and protected by the solder resist, the first outer layer circuit pattern has a problem in that it is easily destroyed by various factors due to the lack of a support layer to support it.

[0231] As a result, in the embodiment, the solder resist in the first region is not completely removed but is left to support and protect the first outer layer circuit pattern. Accordingly, in the embodiment, problems such as collapse and rubbing of the first outer layer circuit pattern in the first region can be solved by miniaturizing the outer layer circuit pattern, thereby improving product reliability. In particular, in the embodiment, problems such as collapse and frost of traces included in the first outer layer circuit pattern in the first region can be solved, thereby improving product reliability.

[0232] Meanwhile, the solder resist according to the embodiment includes a first part disposed in the first region and a second part disposed in the second region. In this case, the upper surface of the first part may have a convex shape in an upward direction. For example, the upper surface of the first part of the solder resist may have a fourth height in the outer region and a fifth height greater than the fourth height in the inner region. That is, the upper surface of the first part of the solder resist may include a highest portion having the highest height and a lowest portion having the lowest height. The lowest portion may be disposed closer to the first outer layer circuit pattern than the highest portion. This allows the upper surface of the first part of the solder resist to have a convex shape, thereby increasing its surface area. This increases the contact area with a layer (e.g., a molding layer) disposed on the first part, thereby improving bonding strength. Furthermore, the height of the lowest portion is smaller than the height of the first outer layer circuit pattern. This prevents a portion of the first part of the solder resist from remaining on the surface of the first outer layer circuit pattern, thereby improving reliability. In addition, in the embodiment, the height of the highest part of the first part of the solder resist is greater than the height of the first outer layer circuit pattern, so that the solder resist can implement the dam function of the adhesive member through the first part, thereby improving reliability.

[0233] Furthermore, the circuit board in the embodiment can be applied to a 5G communication system, thereby minimizing high-frequency transmission loss and further improving reliability. Specifically, the circuit board in the embodiment can be used at high frequencies and can reduce propagation loss.

[0234] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0235] Although the above description has focused on the embodiments, these are merely illustrative and are not intended to limit the scope of the embodiments. Those skilled in the art will appreciate that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments may be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; a plurality of circuit patterns disposed on the insulating layer; a protective layer disposed on the insulating layer and the plurality of circuit patterns; the upper surface of the protective layer includes a plurality of recesses and a plurality of protrusions, Each of the plurality of protrusions is provided between the plurality of recesses, the plurality of protrusions overlap with the separation regions between the plurality of circuit patterns along the vertical direction, The plurality of recesses overlap the circuit pattern along the vertical direction.

2. the protective layer includes a first part having a first thickness and a second part having a second thickness greater than the first thickness; the plurality of recesses and the plurality of protrusions are provided on an upper surface of the second part of the protective layer, The circuit board according to claim 1 , wherein the plurality of protrusions and the plurality of recesses are positioned higher than an upper surface of the circuit pattern with respect to an upper surface of the insulating layer.

3. The circuit board according to claim 1 , wherein the recessed portion and the protruding portion of the protective layer have curved surfaces.

4. 3. The circuit board according to claim 2, wherein the circuit patterns include a plurality of first circuit patterns spaced apart from each other across the first part of the protective layer, and a plurality of second circuit patterns disposed within the second part of the protective layer.

5. The circuit board according to claim 4 , wherein the upper surface of the first part of the protective layer includes a plurality of protrusions disposed between the plurality of first circuit patterns.

6. The circuit board according to claim 5 , wherein an uppermost end of the first part of the protective layer is positioned lower than upper surfaces of the plurality of first circuit patterns with respect to an upper surface of the insulating layer.

7. The circuit board according to claim 5 , wherein uppermost ends of the plurality of protrusions of the second part do not overlap the plurality of second circuit patterns along the up-down direction.

8. 8. The circuit board according to claim 7, wherein the height of the bottom end of the recess of the second part is in the range of 80% to 97% of the height of the top end of the protrusion of the second part.

9. The circuit board according to claim 8, wherein a difference in height between the top end of the convex portion and the bottom end of the concave portion ranges from 1 um to 7 um.

10. further comprising a primer layer disposed between the insulating layer and the plurality of circuit patterns; The circuit board according to claim 1 , wherein the plurality of circuit patterns are disposed on the primer layer.

11. a via penetrating at least a portion of the insulating layer from the upper surface of the insulating layer toward the lower surface of the insulating layer; The circuit board of claim 10 , wherein the via is disposed further through the primer layer.

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