Operational amplifier

Abstract

To provide an operational amplifier capable of realizing both of increasing high-frequency noise tolerance and increasing oscillation tolerance, without increasing an input bias current or equivalent input noise voltage.SOLUTION: An operational amplifier includes an input differential pair 101 configured to be capable of differentially amplifying an input signal, and an output circuit 102 for amplifying the output and output it. The output circuit 102 includes a base-grounded amplifier circuit 152, and a low-speed current mirror circuit 151 for supplying current for the base-grounded amplifier circuit 152. High-frequency noise tolerance and oscillation tolerance are increased by setting the cut-off frequency of the low-speed current mirror circuit 151 equal to or lower than a unity-gain frequency of the operational amplifier for decreasing the speed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an operational amplifier, and particularly to an operational amplifier that improves high-frequency noise resistance, oscillation resistance, etc. without causing an increase in input bias current or input-referred noise voltage.

Background Art

[0002] In an operational amplifier, it is well known that when high-frequency noise is mixed into the input terminals, the output voltage fluctuates greatly. To solve this problem, for example, Patent Document 1 discloses a method of inserting a low-pass filter LPF at the input terminals of an operational amplifier, which is known as one of the typical countermeasures against high-frequency noise. The high-frequency noise countermeasure technique disclosed in this Patent Document 1 will be generally described below while referring to FIGS. 26 to 28. First, FIG. 26 shows a circuit configuration example of a conventional operational amplifier before applying the high-frequency noise countermeasure technique disclosed in Patent Document 1. This conventional circuit is mainly composed of an input differential pair 301 consisting of transistors Q1 and Q2, and an output circuit 302 consisting of transistors Q3 to Q6 and an amplification amplifier AO.

[0003] FIG. 27 shows a circuit configuration example when the high-frequency noise countermeasure is applied to the conventional circuit shown in FIG. 26. That is, the operational amplifier shown in FIG. 27 has a configuration in which a low-pass filter LPF1 is provided between the inverting input terminal INM and the base of transistor Q1, and a low-pass filter LPF2 is provided between the non-inverting input terminal INP and the base of transistor Q2. The high-frequency noise resistance of the operational amplifier having such a configuration will be described below while comparing it with a conventional circuit without the high-frequency noise countermeasure. First, an experimental circuit for comparing the high-frequency noise resistance will be described while referring to the experimental circuit example shown in FIG. 28.

[0004] This experimental circuit is designed to observe the change in the DC output voltage Vout when a high-frequency signal RF is applied via capacitor CA1 connected to the non-inverting input terminal of operational amplifier OP1. The smaller the change in the DC output voltage Vout, the stronger the high-frequency noise immunity is considered to be.

[0005] Figure 29 shows the results of a comparative verification of the experimental circuit described above with and without high-frequency noise countermeasures compared to the conventional circuit, as indicated by characteristic curves showing the change in output voltage with respect to input frequency. The following explanation of these comparative verification results will refer to this figure. First, in Figure 29, the horizontal axis represents the frequency of the input high-frequency signal, and the vertical axis represents the output voltage of the operational amplifier. Furthermore, in the same figure, the solid characteristic curve represents the change in output voltage with respect to input frequency in a conventional circuit without high-frequency noise countermeasures (see Figure 26). Also in the same figure, the dotted characteristic curve represents the change in output voltage with respect to input frequency in a conventional circuit with the aforementioned high-frequency noise countermeasures (see Figure 27).

[0006] The characteristic curve shown in Figure 29 plots the DC output voltage Vout of the operational amplifier OP1 when the voltage amplitude of the high-frequency signal RF is kept constant at 0.2Vpp and the frequency is swept from 10MHz to 3.5GHz in the experimental circuit shown in Figure 28. As shown in Figure 29, it can be confirmed that inserting a low-pass filter (LPF) into the input stage improves high-frequency noise immunity and suppresses fluctuations in the operational amplifier's output voltage Vout.

[0007] However, inserting a low-pass filter in the input stage presents a problem in that it impairs the oscillation immunity of the operational amplifier. This issue will be explained below, with reference to the characteristic curve shown in Figure 30. First, Figure 30 is a characteristic curve showing the dependence of the phase margin, which is an indicator of oscillation immunity, on the load capacitance CL, with the horizontal axis representing the load capacitance CL and the vertical axis representing the phase margin. Generally, in electronic circuits, the lower the phase margin, the more prone the circuit is to oscillation.

[0008] In Figure 30, the solid characteristic curve represents the change in phase margin with respect to load capacitance in a conventional operational amplifier without a low-pass filter (LPF) (see Figure 26). The dotted characteristic curve in the same figure represents the change in phase margin with respect to load capacitance in a conventional operational amplifier with a low-pass filter (LPF) in the input stage (see Figure 27). According to the figure, it can be seen that adding a low-pass filter (LPF) reduces the phase margin, making oscillation more likely.

[0009] The reason why the phase margin decreases when a low-pass filter (LPF) is added is that the poles generated by the low-pass filter (LPF) cause the phase characteristics of the operational amplifier to rotate at low frequencies. Thus, operational amplifiers that have a low-pass filter (LPF) inserted at the input terminal to improve high-frequency noise immunity (RF noise immunity) suffer from the problem of reduced oscillation immunity in exchange for improved RF noise immunity.

[0010] A solution to the above-mentioned problems is disclosed, for example, in Patent Document 2. Figure 31 shows an example of a circuit configuration of a conventional operational amplifier with high-frequency noise countermeasures disclosed in Patent Document 2. The measures disclosed in Patent Document 2 will be outlined below with reference to this figure. The operational amplifier shown in Figure 31 has a configuration that includes input differential pairs for low frequencies and input differential pairs for high frequencies.

[0011] In other words, the low-frequency input differential pair is constructed using a tail current source ITAIL, transistors Q101 and Q102, and low-pass filters LPF1 and LPF2. In such a low-frequency input differential pair, high-frequency signals containing high-frequency noise are attenuated by the low-pass filters LPF1 and LPF2.

[0012] On the other hand, a high-frequency input differential pair is constructed using transistors Q111 and Q112 and a capacitor C101. In such a high-frequency input differential pair, the capacitor C101 is placed between the emitters of transistor Q111 and Q112, allowing the high-frequency signal to travel between both emitters of transistors Q111 and Q112. Therefore, the emitters of transistors Q111 and Q112 are connected AC-wise, enabling them to operate as a differential pair.

[0013] The circuit operation when high-frequency noise is applied to this high-frequency input differential pair is described below. First, in the conventional circuit shown in Figure 26, the input differential pair has its emitters connected to each other, so high-frequency noise is rectified at this emitter node. This rectification action generates a DC voltage that causes the differential pair to become unbalanced, and this unbalanced DC voltage produces an unintended DC output voltage.

[0014] On the other hand, in the operational amplifier shown in Figure 31, the emitters of the high-frequency input differential pair are not DC-common, but are only AC-connected by capacitor C101. Therefore, this high-frequency input differential pair does not generate a rectified DC voltage at the emitter when high-frequency noise is applied. As a result, the operational amplifier shown in Figure 31 does not experience fluctuations in output voltage even when high-frequency noise is applied, thus improving its high-frequency noise immunity.

[0015] Furthermore, the operational amplifier shown in Figure 31 does not experience a decrease in oscillation immunity even when high-frequency noise immunity is improved. In this operational amplifier, poles are generated by the low-frequency input differential pair's low-pass filters LPF1 and LPF2, causing the phase to shift. On the other hand, the high-frequency input differential pair has a high-pass filter configuration, generating a zero point and causing the phase to return. As a result, this zero point cancels out the phase shift caused by the low-pass filter, improving the reduction of the phase margin. Thus, in the operational amplifier shown in FIG. 31, even when the low-pass filters LPF1 and LPF2 for high-frequency noise countermeasures are provided, it does not lead to a decrease in oscillation resistance, and both high-frequency noise resistance and oscillation resistance are achieved.

Prior Art Documents

Patent Documents

[0016]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0017] However, in the operational amplifier disclosed in Patent Document 2 described above, since it is a configuration in which transistors Q111 and Q112 of the high-frequency input differential pair are added to the conventional circuit configuration (see FIG. 31), there is a problem that the input-referred noise voltage increases. Hereinafter, the increase in this input-referred noise voltage will be generally explained. For example, in the operational amplifier shown in FIG. 31, assume a case where the collector currents of transistors Q101 and Q102 of the low-frequency input differential pair and transistors Q111 and Q112 of the high-frequency input differential pair all flow at a magnitude of ITAIL / 2. Here, ITAIL is the magnitude of the output current of the tail current source ITAIL.

[0018] In this case, the operational amplifier shown in FIG. 31 has a 2-fold input bias current and a 21 / 2 They increase respectively by multiples. Such an increase in the input bias current and the input-referred noise voltage causes a problem of generating an error in the output voltage.

[0019] The present invention has been made in view of the above actual situation, and provides an operational amplifier that enables both improvement in high-frequency noise resistance and improvement in oscillation resistance without causing an increase in the input bias current and the input-referred noise voltage.

Means for Solving the Problems

[0020] To achieve the object of the present invention, the operational amplifier according to the present invention is an operational amplifier having an input differential pair configured to differentially amplify an input signal and an output circuit that amplifies and outputs the output of the input differential pair, wherein the output circuit has a grounded-base amplifier circuit and buffer amplifier and a low-speed current mirror circuit that supplies current to the grounded-base amplifier circuit, wherein the low-speed current mirror circuit is configured such that its cut-off frequency is set to be equal to or lower than the unity-gain frequency of the operational amplifier to be made low-speed the law of nature, The cutoff frequency is set to 1 / 10 or less of the unity gain frequency of the operational amplifier. The input differential pair comprises a first and second PNP type differential pair transistor, the emitters of the first and second differential pair transistors interconnected, and a constant current source provided between this connection point and the positive power supply terminal. The collector of the first differential pair transistor is connected to the negative power supply terminal via a first differential pair resistor, and the collector of the second differential pair transistor is connected to the negative power supply terminal via a second differential pair resistor. The base of the first differential pair transistor is connected to the inverting input terminal, and the base of the second differential pair transistor is connected to the non-inverting input. The common-base amplifier circuit has first and second amplification transistors, which are NPN bipolar transistors, the bases of the first and second amplification transistors are connected to each other, and a first constant voltage source is provided between the connection point and the negative power supply terminal, the emitter of the first amplification transistor is connected to the connection point between the collector of the first differential pair transistor and the first differential pair resistor, and the emitter of the second amplification transistor is connected to the connection point between the collector of the second differential pair transistor and the second differential pair resistor. The low-speed current mirror circuit comprises first and second current mirror transistors, which are PNP bipolar transistors, and a capacitor for slowing down the current. The bases of the first and second current mirror transistors are interconnected and connected to the collector of the first current mirror transistor. The collector of the first current mirror transistor is connected to the collector of the first amplification transistor, and the collector of the second current mirror transistor is connected to the collector of the second amplification transistor. The emitters of the first and second current mirror transistors are both connected to the positive power supply terminal, and the capacitor for slowing down the current is connected in series between the collector of the first current mirror transistor and the negative power supply terminal. The collector of the second amplification transistor is connected to the input stage of the buffer amplifier, and the output stage of the buffer amplifier is connected to the amplification output terminal. Between the input stage and the output stage, a phase compensation capacitor and a phase compensation resistor are provided, connected in series from the input stage side in the order of the phase compensation capacitor and the phase compensation resistor. A high-pass filter is provided between the bases of the first and second amplification transistors and the collector of the second amplification transistor. The high-pass filter comprises a high-pass resistor and a high-pass capacitor, and is provided connected in series from the collector side of the second amplification transistor in the order of the high-pass capacitor and the high-pass resistor, and the capacitance value CX2 of the high-pass capacitor is set to a value that satisfies the inequality CX2 ≥ Cc with respect to the capacitance value Cc of the phase compensation capacitor. and is thus configured.

Effects of the Invention

[0021] According to the present invention, by reducing the speed of the current mirror circuit used in the output circuit, the phase as an operational amplifier can be adjusted so that oscillation suppression becomes possible. Therefore, by using it in combination with countermeasures against high-frequency noise, it is possible to achieve both improvement in high-frequency noise resistance and improvement in oscillation resistance without causing an increase in the input bias current and the input-referred noise voltage. [Brief explanation of the drawing]

[0022] [Figure 1] This is a circuit diagram showing a first basic circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 2] This is a circuit diagram showing a second basic circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 3] This is a circuit diagram showing a third basic circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 4] This is a circuit diagram showing a fourth basic circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 5] This is a circuit diagram showing a fifth basic circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 6] This is a circuit diagram showing a first specific circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 7] This is a circuit diagram showing a second specific circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 8] This is a circuit diagram showing a third specific circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 9] This is a circuit diagram showing a fourth specific circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 10] This is a circuit diagram showing a fifth specific circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 11] This is a circuit diagram showing a sixth specific circuit configuration example of an operational amplifier in an embodiment of the present invention. [Figure 12] This circuit diagram shows a sixth basic circuit configuration example, obtained by changing the type of transistor in the first basic circuit configuration example shown in Figure 1. [Figure 13] This circuit diagram shows a seventh basic circuit configuration example, obtained by changing the type of transistor in the first basic circuit configuration example shown in Figure 1. [Figure 14]This circuit diagram shows an eighth basic circuit configuration example, where the type of transistor is changed in the first basic circuit configuration example shown in Figure 1. [Figure 15] This is a circuit diagram showing a ninth basic circuit configuration example, obtained by changing the type of transistor in the first basic circuit configuration example shown in Figure 1. [Figure 16] This is a circuit diagram showing a tenth basic circuit example, which is the first basic circuit configuration example shown in Figure 1 with a high-pass filter added. [Figure 17] This is a circuit diagram showing the seventh specific circuit configuration example, which is a specific circuit example of the tenth basic circuit configuration example shown in Figure 16. [Figure 18] This circuit diagram shows an eleventh basic circuit example, which is the first basic circuit configuration example shown in Figure 1 with a high-pass filter added. [Figure 19] This circuit diagram shows a twelfth basic circuit example, which is the first basic circuit configuration example shown in Figure 1 with a high-pass filter added. [Figure 20] This circuit diagram shows a 13th basic circuit example, which is the first basic circuit configuration example shown in Figure 1 with a high-pass filter added. [Figure 21] This is a circuit diagram showing the eighth specific circuit configuration example, which is a specific circuit example of the eleventh basic circuit configuration example shown in Figure 18. [Figure 22] This is a circuit diagram showing the ninth specific circuit configuration example, which is a specific circuit example of the twelfth basic circuit configuration example shown in Figure 19. [Figure 23] This is a characteristic curve showing the characteristics of the output voltage change with respect to frequency change of the operational amplifier in an embodiment of the present invention. [Figure 24] This is a characteristic curve showing the phase margin change characteristics with respect to load capacitance changes in an operational amplifier equipped with a low-speed current mirror circuit according to an embodiment of the present invention. [Figure 25] This is a characteristic curve showing the phase margin change characteristics with respect to load capacitance changes in an operational amplifier equipped with a low-speed current mirror circuit and a high-pass filter according to an embodiment of the present invention. [Figure 26]This circuit diagram shows an example of a conventional operational amplifier circuit configuration that does not have high-frequency noise countermeasures. [Figure 27] Figure 26 is a circuit diagram showing an example of a circuit configuration when high-frequency noise countermeasures are applied to the conventional circuit shown. [Figure 28] This is a circuit diagram showing an example of the circuit configuration of an experimental circuit used to measure the high-frequency noise immunity of an operational amplifier. [Figure 29] Figure 26 and Figure 27 are characteristic curves showing the output voltage fluctuation characteristics with respect to frequency changes as an indicator of high-frequency noise immunity for the operational amplifiers shown. [Figure 30] Figure 26 and Figure 27 are characteristic curves showing the phase margin change characteristics in response to changes in load capacitance, which serve as an indicator of oscillation immunity for the operational amplifiers shown. [Figure 31] This circuit diagram shows an example of a conventional operational amplifier circuit configuration that achieves both high-frequency noise immunity and oscillation immunity. [Modes for carrying out the invention]

[0023] Hereinafter, embodiments of the present invention will be described with reference to Figures 1 to 25. The components, arrangements, etc., described below are not intended to limit the present invention and can be modified in various ways within the scope of the spirit of the present invention. First, a first basic circuit configuration example of the operational amplifier in an embodiment of the present invention will be described with reference to Figure 1. The operational amplifier in the embodiment of the present invention is broadly composed of an input differential pair 101 and an output circuit 102. In this respect, it is basically the same as the conventional design, but as will be described later, the output circuit 102 has a different configuration from the conventional design.

[0024] The input differential pair 101 is mainly composed of first and second differential pair transistors 1 and 2 (labeled "Q1" and "Q2" respectively in Figure 1), which are PNP bipolar transistors. The first and second differential transistors 1 and 2 have their emitters connected to each other, and a constant current source 60 is connected between this connection point and the positive power supply terminal 81. An external power supply voltage VCC is applied to the positive power supply terminal 81.

[0025] On the other hand, the collector of the first differential pair transistor 1 is connected to the negative power supply terminal 82 via the first resistor (labeled "R1" in Figure 1) 41, which serves as the first load, and the collector of the second differential pair transistor 2 is connected via the second resistor (labeled "R2" in Figure 1) 42, which serves as the second load. Furthermore, the base of the first differential pair transistor 1 is connected to the inverting input terminal (labeled "INM" in Figure 1) 83, and the base of the second differential pair transistor 2 is connected to the non-inverting input terminal (labeled "INP" in Figure 1) 84. The collectors of the first and second transistors 1 and 2 are connected to the input stage of the output circuit 102, as described below.

[0026] The output circuit 102 is mainly composed of a low-speed current mirror circuit (labeled "SCMP" in Figure 1) 151, a common-base amplifier circuit 152, and a buffer amplifier (labeled "AO" in Figure 1) 153. The common-base amplifier circuit 152 is configured with third and fourth transistors (labeled "Q3" and "Q4" respectively in Figure 1) 3 and 4, which serve as the first and second amplification transistors using NPN bipolar transistors.

[0027] The bases of the third and fourth transistors 3 and 4 are connected to each other, and a first constant voltage source 61 is provided between the connection point and the negative power supply terminal 82. Furthermore, the emitter of the third transistor 3 is connected to the connection point between the collector of the differential pair first transistor 1 and the first resistor 41, and the emitter of the fourth transistor 4 is connected to the connection point between the collector of the differential pair second transistor 2 and the second resistor 42.

[0028] Furthermore, the input stage of the buffer amplifier 153 is connected to the collector of the fourth transistor 4, and the output stage of this buffer amplifier 153 is connected to the amplification output terminal (labeled "OUT" in Figure 1) 85. In addition, a phase compensation capacitor (labeled "Cc" in Figure 1) 54 and a phase compensation resistor (labeled "Rz" in Figure 1) 46 are connected in series between the input and output stages of the buffer amplifier 153, starting from the input stage side. In this first basic circuit configuration example, a folded cascode amplifier circuit is formed by the input differential pair 101 and the common-base amplifier circuit 152 described above.

[0029] On the other hand, the low-speed current mirror circuit 151 serves as the current source for the common-base amplifier circuit 152. Unlike the current mirror circuit used in conventional output circuits, it is specifically designed to be slower (narrower bandwidth) by providing a pole, as will be described later. First, the power supply for the low-speed current mirror circuit 151 is provided from the positive power supply terminal 81, with the input stage connected to the collector of the third transistor 3 and the output stage connected to the collector of the fourth transistor 4. In Figure 1, P1 to P4 are terminals for power supply connection and input / output connection of the low-speed current mirror circuit 151. For the sake of explanation, P1 will be referred to as the "input stage reference terminal," P2 as the "output stage reference terminal," P3 as the "input terminal," and P4 as the "output terminal." The specific parts of the low-speed current mirror circuit 151 to which these terminals are connected will be explained in the specific circuit configuration example described later.

[0030] In such a configuration, it is preferable that the low-speed current mirror circuit 151 has a cutoff frequency set to approximately 1 / 10 of the unity gain frequency of the operational amplifier in order to achieve low speed. In this way, by setting the cutoff frequency of the current mirror circuit to about 1 / 10 of the unity gain frequency of the operational amplifier, the phase of the operational amplifier can be slightly corrected at a frequency that is about an order of magnitude lower than the unity gain frequency of the operational amplifier. As a result, the phase margin increases, which improves oscillation immunity.

[0031] Next, we will explain the second basic circuit configuration example with reference to Figure 2. Note that components identical to those in the first basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This second example of a basic circuit configuration is an example in which a low-pass filter is provided on the input side of the input differential pair 101 as a measure against high-frequency noise, as shown in the first example of a basic circuit configuration in Figure 1, and the remaining part has the same configuration as the basic circuit shown in Figure 1.

[0032] Specifically, a first low-pass filter (labeled "LPF1" in Figure 2) 71 is provided in series between the inverting input terminal 83 and the base of the first differential transistor 1, and a second low-pass filter (labeled "LPF2" in Figure 2) 72 is provided in series between the non-inverting input terminal 84 and the base of the second differential transistor 2. This second basic circuit configuration example, in addition to using the low-speed current mirror circuit 151, also utilizes the first and second low-pass filters 71 and 72 to achieve both improved high-frequency noise immunity and improved oscillation immunity.

[0033] Next, we will explain the third basic circuit configuration example with reference to Figure 3. Note that components identical to those in the first basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This third basic circuit configuration example is an example in which a low-pass filter is provided between the input terminals of the input differential pair 101 as a measure against high-frequency noise, as shown in the first basic circuit configuration example in Figure 1, and the remaining part has the same configuration as the basic circuit shown in Figure 1. In other words, in this third basic circuit configuration example, a third low-pass filter (labeled "LPF3" in Figure 3) 73 is provided between the inverting input terminal 83 and the non-inverting input terminal 84. This achieves both improved high-frequency noise immunity and improved oscillation immunity, similar to the second basic circuit configuration example.

[0034] Next, we will explain the fourth basic circuit configuration example with reference to Figure 4. Note that components identical to those shown in any of Figures 1 to 3 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This fourth basic circuit configuration example applies the circuit configuration shown in Figure 3 to the circuit configuration shown in Figure 2 as a measure against high-frequency noise.

[0035] In other words, the first and second low-pass filters 71 and 72 are provided in the same manner as described in the second basic circuit configuration example shown in Figure 2. Furthermore, the third low-pass filter 73 is connected to the bases of the first and second transistors 1 and 2, on the downstream side of the first and second low-pass filters 71 and 72, that is, on the base side of the first and second transistors 1 and 2. This configuration achieves both further improvements in high-frequency noise immunity and improved oscillation immunity.

[0036] Next, we will explain the fifth basic circuit configuration example with reference to Figure 5. Note that components identical to those in the basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. The fifth basic circuit configuration example includes a common-base amplifier circuit 152A using a PNP bipolar transistor, with a low-speed current mirror circuit 151A positioned at the common-base input of the folded cascode. Specifically, the common-base amplifier circuit 152A is configured as follows, using 11 and 12 transistors (labeled "Q11" and "Q12" respectively in Figure 5) 11 and 12, which are first and second amplification transistors using PNP-type bipolar transistors.

[0037] First, the bases of the 11th and 12th transistors 11 and 12 are connected to each other, and a second constant voltage source 62 is provided between this connection point and the positive power supply terminal 81. This second constant voltage source 62 is provided such that its positive terminal is connected to the positive power supply terminal 81 and its negative terminal is connected to the bases of the 11th and 12th transistors 11 and 12. Furthermore, the emitters of the 11th and 12th transistors 11 and 12 are both connected to the positive power supply terminal 81.

[0038] The low-speed current mirror circuit (indicated as "SCMN" in Figure 5) 151A has its input stage connected to the connection point between the collector of the first differential pair transistor 1 and the first resistor 41 via the input stage reference terminal P7 (corresponding to the input stage reference terminal P1 in Figure 1), and its output stage connected to the connection point between the collector of the second differential pair transistor 2 and the second resistor 42 via the output stage reference terminal P8 (corresponding to the output stage reference terminal P2 in Figure 1). On the other hand, the power supply side of the input stage of the low-speed current mirror circuit 151A is connected to the collector of the 11th transistor 11 via input terminal P5 (corresponding to input terminal P3 in Figure 1), and the power supply side of the output stage of the low-speed current mirror circuit 151A is connected to the collector of the 12th transistor 12 via output terminal P6 (corresponding to output terminal P4 in Figure 1). More specific circuit connections will be explained in the specific circuit configuration example described later. Furthermore, in this configuration as well, the oscillation immunity is improved, just as in the first basic circuit configuration example.

[0039] Next, we will explain the first specific circuit configuration example with reference to Figure 6. Note that components identical to those in the basic circuit configuration example shown in Figure 2 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This first specific circuit configuration example corresponds to the second basic circuit configuration example shown in Figure 2, and in particular, it shows a specific circuit configuration example of a low-speed current mirror circuit (labeled "SCM1" in Figure 6) 151.

[0040] In this configuration example, the low-speed current mirror circuit 151 is composed of fifth and sixth transistors (labeled "Q5" and "Q6" respectively in Figure 6) 5 and 6, which serve as first and second transistors for the current mirror using PNP bipolar transistors, and a capacitor 51 for slowing down the current (labeled "CX1" in Figure 6). The bases of the fifth and sixth transistors 5 and 6 are connected to each other, and the point of connection between them is connected to the collector of the fifth transistor 5, so that the fifth transistor 5 is in a so-called diode connection state. Furthermore, the emitter of the fifth transistor 5 is connected to the positive power supply terminal 81 via the input stage reference terminal P1, and the emitter of the sixth transistor 6 is connected to the positive power supply terminal 81 via the output stage reference terminal P2.

[0041] Furthermore, the collector of the fifth transistor 5, which forms the input stage of the current mirror circuit, is connected to the collector of the third transistor 3 via input terminal P3, and the collector of the sixth transistor 6, which forms the output stage of the current mirror circuit, is connected to the collector of the fourth transistor 4 and the input terminal of the buffer amplifier 153 via output terminal P4. On the other hand, the slow-down capacitor 51 is connected between the connection point between the collectors of the third and fifth transistors 3 and 5 and the negative power supply terminal 82.

[0042] As mentioned earlier, the capacitor 51 for reducing the speed is used to set the cutoff frequency of the current mirror circuit to about 1 / 10 of the unity gain frequency of the operational amplifier. Therefore, the required capacitance value CX1 is preferably set to the value obtained by Equation 1 below.

[0043] CX1 ≈ 10 × gmQ5 / (2·π·fu)···Equation 1

[0044] Here, CX1 is the capacitance value of the slow-down capacitor 51, gmQ5 is the transconductance of the fifth transistor 5, and fu is the unity-gain frequency of the operational amplifier. By setting the capacitance value of the slow-down capacitor 51 to the value described above, the cutoff frequency of the current mirror circuit can be set to about 1 / 10 of the unity gain frequency of the operational amplifier. As a result, the phase of the operational amplifier can be slightly corrected at a frequency about an order of magnitude lower than the unity gain frequency of the operational amplifier, increasing the phase margin and thus improving oscillation immunity. For example, if the transconductance gmQ5 = 100 μA / V and the unity gain frequency fu = 10 MHz, the capacitance value CX1 of the slowdown capacitor 51 will be CX1 ≈ 15.9 pF.

[0045] Figure 23 shows an example of characteristics demonstrating high-frequency noise immunity, specifically, an example of the output change characteristics of an operational amplifier in an embodiment of the present invention in response to input frequency changes, along with an example of the same characteristics for a conventional circuit. The following description will explain this figure. In Figure 23, the horizontal axis represents frequency, and the vertical axis represents the output voltage of the operational amplifier. In the figure, the dotted characteristic curve represents the characteristic curve showing the change in output voltage with respect to frequency in a conventional circuit without a low-pass filter (see Figure 26).

[0046] Furthermore, in the same figure, the solid characteristic curve represents the characteristic curve showing the change in output voltage with respect to frequency change of the operational amplifier in the embodiment of the present invention shown in Figures 2 and 6. The solid characteristic curve showing the characteristics of the operational amplifier in the embodiment of the present invention is in almost identical condition to the characteristic curve showing similar characteristics of a conventional circuit with a low-pass filter (see Figure 27). The characteristics described above were obtained using the experimental circuit shown in Figure 28. As shown in Figure 23, it can be confirmed that the operational amplifier in the embodiment of the present invention has high-frequency noise immunity and that fluctuations in the output voltage Vout are suppressed.

[0047] Next, Figure 24 shows an example of a characteristic that illustrates the dependence of the phase margin on the load capacitance CL, which is an indicator of oscillation immunity. This figure will be explained below. In Figure 24, the horizontal axis represents the load capacity, and the vertical axis represents the phase margin. Furthermore, in the same figure, the solid characteristic curve represents the characteristic curve showing the change in phase margin with respect to the change in load capacitance of the operational amplifier (see Figure 6) in the embodiment of the present invention. In Figure 24, "SCM" refers to the low-speed current mirror circuit 151.

[0048] Furthermore, in Figure 24, the dashed-dot line represents the characteristic curve showing the change in phase margin in response to changes in load capacitance in a conventional circuit without a low-pass filter (see Figure 26). Furthermore, in the same figure, the dotted characteristic curve also represents the characteristic curve of a conventional circuit equipped with a low-pass filter (see Figure 27), showing similar characteristics. As shown in Figure 24, in the operational amplifier according to the embodiment of the present invention using the low-speed current mirror circuit 151, it can be confirmed that the phase margin is reliably increased and the oscillation immunity is improved. In other words, in this first specific circuit configuration example, since the input differential pair 101 is the same as in the conventional circuit (see Figures 26 and 27), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0049] Next, we will explain a second specific circuit configuration example with reference to Figure 7. Note that components identical to those in the first specific circuit configuration example shown in Figure 6 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This second specific circuit configuration example is based on the first specific circuit configuration example shown in Figure 6, but with the addition of a low-speed current mirror circuit (indicated as "SCM2" in Figure 7) 151B, which reduces the potential difference across the low-speed capacitor 51, enabling the use of a low-voltage capacitor and reducing the chip size. Specifically, in the low-speed current mirror circuit 151B, one end of the low-speed capacitor 51 is connected to the connection point between the collectors of the third and fifth transistors 3 and 5, while the other end is connected to the positive power supply terminal 81.

[0050] In the first specific circuit configuration example shown in Figure 6, the potential difference across the slow-down capacitor 51 is VCC-VEE-1Vbe, whereas in this second specific circuit configuration example, the potential difference across the slow-down capacitor 51 is 1Vbe ≈ 0.7V. Here, 1Vbe is the base-emitter potential difference of the fifth transistor 5, which is typically around 0.7V.

[0051] By reducing the potential difference across the low-speed capacitor 51 in this way, it becomes possible to use a low-voltage capacitor. Since low-voltage capacitors have a large capacitance value per unit area, a large capacitance can be obtained in a small area, thus enabling miniaturization of the chip size. The capacitance value of the slow-down capacitor 51 is by no means small, as shown earlier in Equation 1. Therefore, when the capacitance value required for the slow-down capacitor 51 is large, this second specific circuit configuration example becomes effective. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0052] Next, we will explain a third specific circuit configuration example with reference to Figure 8. Note that components identical to those in the first specific circuit configuration example shown in Figure 6 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This third specific circuit configuration example incorporates a low-speed current mirror circuit (labeled "SCM3" in Figure 8) 151C designed to reduce transconductance. To explain in more detail, the low-speed current mirror circuit 151C is composed of fifth and sixth transistors 5 and 6, a low-speed capacitor 51, and first and second adjustment resistors 43 and 44 (labeled "RX11" and "RX12" respectively in Figure 8).

[0053] This low-speed current mirror circuit 151C differs from the configuration shown in Figure 6 in that, as described below, it has first and second adjustment resistors 43 and 44 between the emitters of the fifth and sixth transistors 5 and 6 and the positive power supply terminal 81. The remaining parts have the same configuration as the circuit configuration example shown in Figure 6.

[0054] Specifically, one end of the first adjustment resistor 43 is connected to the positive power supply terminal 81 via the input stage reference terminal P1, and one end of the second adjustment resistor 44 is connected to the positive power supply terminal 81 via the output stage reference terminal P2. The other end of the first adjustment resistor 43 is connected to the emitter of the fifth transistor 5, and the other end of the second adjustment resistor 44 is connected to the emitter of the sixth transistor 6. By providing the first and second adjustment resistors 43 and 44 in this manner, the transconductance of the current mirror circuit is reduced, allowing the capacitance value of the slow-down capacitor 51 to be reduced, ultimately enabling a reduction in chip size. Furthermore, reducing the capacitance value of the capacitor reduces the probability of the capacitor itself failing.

[0055] The capacitance value CX1 of the slow-down capacitor 51 in this circuit configuration example can be determined by the following equation 2.

[0056] CX1 ≈ {10 × gmQ5 / (1 + RX11 × gmQ5)} / (2·π·fu)···Equation 2

[0057] Here, gmQ5 is the transconductance of the fifth transistor 5, and RX11 is the resistance value of the first adjustment resistor 43. For example, if the transconductance gmQ5 of the fifth transistor 5 is 100 μA / V and the unity gain frequency fu is 10 MHz, the difference in capacitance value CX1 of the slow-down capacitor 51 with or without the adjustment resistor 43 is as follows. In other words, the capacitance value of the slow-down capacitor 51 in the first specific circuit configuration example shown in Figure 6 is calculated using Equation 1 above, and the capacitance value CX1 = 15.9pF. In contrast, if the resistance value of the first adjustment resistor 43 is set to RX11 = 10kΩ, the capacitance value of the slowing capacitor 51 in this third specific circuit configuration example is calculated using equation 2 above, and the capacitance value CX1 = 8.0pF.

[0058] Thus, in this third specific circuit configuration example, by providing the first and second adjustment resistors 43 and 44, it is possible to reduce the capacitance value of the slowing capacitor 51 to about half compared to the first specific circuit configuration example which does not have the first and second adjustment resistors 43 and 44. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0059] Next, we will explain the fourth specific circuit configuration example with reference to Figure 9. Note that components identical to those in the specific circuit configuration example shown in Figure 8 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This fourth specific circuit configuration example includes a low-speed current mirror circuit (labeled "SCM4" in Figure 9) 151D, and the remaining portion has the same configuration as the circuit configuration example shown in Figure 8.

[0060] In other words, in the low-speed current mirror circuit 151D in this fourth specific circuit configuration example, the connection of the low-speed capacitor 51 has been modified so that the potential difference across its terminals is smaller compared to the specific circuit configuration example shown in Figure 8. Specifically, as explained earlier in Figure 7, a further detailed explanation will be omitted here.

[0061] Thus, by applying the connection configuration shown in Figure 7 to the connection of the speed-reducing capacitor 51, the potential difference across the speed-reducing capacitor 51 can be reduced, making it possible to use a low-voltage capacitor and thus miniaturizing the speed-reducing capacitor 51. Furthermore, by providing the first and second adjustment resistors 43 and 44, the capacitance value of the speed-reducing capacitor 51 can be reduced as shown in Equation 2. Combined with reducing the potential difference across the speed-reducing capacitor 51, this allows for further reduction of the chip size compared to the second and third specific circuit configuration examples. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0062] Next, we will explain the fifth specific circuit configuration example with reference to Figure 10. Note that components identical to those shown in the circuit configuration example in Figure 5 or Figure 6 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This fifth specific circuit configuration example is a specific circuit example of the fifth basic circuit configuration example shown earlier in Figure 5, and has a configuration in which a low-speed current mirror circuit 151E is provided at the base-grounded input portion of the folded cascode, while the remaining portion has the same configuration as the circuit configuration example shown in Figure 5.

[0063] To explain in more detail, the low-speed current mirror circuit 151E is composed of 13th and 14 transistors (labeled "Q13" and "Q14" respectively in Figure 10) 13 and 14, which serve as the first and second transistors for the current mirror using NPN bipolar transistors, and a capacitor 51 for slowing down the current (labeled "CX3" in Figure 10). The 13th transistor 13 and the 14th transistor 14 are connected at their bases and also connected to the collector of the 13th transistor 13, so that the 13th transistor 13 is in a so-called diode connection.

[0064] Furthermore, the emitter of the 13th transistor 13 is connected to the collector of the first differential pair transistor 1 via the input stage reference terminal P7, and the emitter of the 14th transistor 14 is connected to the collector of the second differential pair transistor 2 via the output stage reference terminal P8. On the other hand, the collector of the 13th transistor 13 is connected to the collector of the 11th transistor 11 via the input terminal P5, and the collector of the 14th transistor 14 is connected to the collector of the 12th transistor 12 via the output terminal P6. Here, the input stage reference terminal P7 corresponds to the input stage reference terminal P1 in Figure 6, the output stage reference terminal P8 corresponds to the output stage reference terminal P2 in Figure 6, the input terminal P5 corresponds to the input terminal P3 in Figure 6, and the output terminal P6 corresponds to the output terminal P4 in Figure 6. The slow-down capacitor 51 is connected between the connection point between the collectors of the 11th and 13th transistors 11 and 13 and the positive power supply terminal 81. Furthermore, the connection point between the collectors of the 12th and 14th transistors 12 and 14 is connected to the input stage of the buffer amplifier 153.

[0065] In this configuration, the current mirror circuit is slowed down by the slow-down capacitor 51, as before, and its capacitance value CX3 can be determined based on the following equation 3.

[0066] CX3 ≈ {10 × gmQ13 / (1 + R1 × gmQ13)} / (2·π·fu) ···Equation 3

[0067] Here, gmQ13 is the transconductance of the 13th transistor 13, R1 is the resistance of the first resistor 41, and fu is the unity gain frequency of the operational amplifier. For example, if the transconductance gmQ13 = 100 μA / V, the unity gain frequency fu = 10 MHz, and the resistance R1 = 10 kΩ, then the capacitance value CX3 of the slow-down capacitor 51 will be approximately 8 pF.

[0068] Here, we compare the third specific circuit configuration example shown in Figure 8 with the fifth specific circuit configuration example shown in Figure 10. Both designs are based on the same technical concept: by adding a resistor on the emitter side of the low-speed current mirror circuit to reduce the transconductance, the capacitance value CX1 or CX3 of the low-speed capacitor 51 can be reduced. However, in the third specific circuit configuration example shown in Figure 8, it is necessary to add new adjustment resistors 43 and 44, whereas in the fifth specific circuit configuration example shown in Figure 10, the existing first and second resistors 41 and 42 are utilized. Therefore, the fifth specific circuit configuration example requires fewer elements to achieve the same circuit operation and function compared to the third specific circuit example, enabling further miniaturization of the chip size.

[0069] The high-frequency noise immunity in this fifth specific circuit configuration example is as shown in Figure 23, and the oscillation immunity is as shown in Figure 24. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0070] Next, we will explain the sixth specific circuit configuration example with reference to Figure 11. Note that components identical to those in the fifth specific circuit configuration example shown in Figure 10 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This sixth specific circuit configuration example incorporates a low-speed current mirror circuit (indicated as "SCM12" in Figure 11) 151F, which reduces the potential difference across the low-speed capacitor 51 compared to the configuration example shown in Figure 10. This allows for the use of low-voltage capacitors and reduces the chip size. Specifically, in the low-speed current mirror circuit 151F, one end of the low-speed capacitor 51 is connected to the connection point between the collectors of the 11th and 13th transistors 11 and 13, while the other end is connected to the negative power supply terminal 82.

[0071] In the sixth specific circuit configuration example, the potential difference across the slow-down capacitor 51 is as follows, compared to the fifth specific circuit configuration example mentioned earlier. In the case of the fifth specific circuit configuration example mentioned above, if we let Vdif be the potential difference across the slow-down capacitor 51, then Vdif = VCC - VEE - 1Vbe - VR1. In contrast, in the case of the sixth specific circuit configuration example, the potential difference Vdif across the slow-down capacitor 51 is Vdif = 1Vbe + VR1 ≈ 1V. Here, 1Vbe is the base-emitter potential difference of the 13th transistor 13, which is typically around 0.7V. Also, VR1 is the magnitude of the voltage drop across the first resistor 41, which is assumed to be, for example, around 0.3V. By reducing the potential difference across the low-speed capacitor 51 in this way, it becomes possible to use a low-voltage capacitor. Since low-voltage capacitors have a large capacitance value per unit area, a large capacitance can be obtained in a small area, thus enabling miniaturization of the chip size.

[0072] The capacitance value CX3 of the slow-down capacitor 51 is by no means small, as shown earlier in Equation 3. Therefore, when the capacitance value required for the slow-down capacitor 51 is large, this sixth specific circuit configuration example becomes effective. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0073] Next, we will explain the sixth basic circuit configuration example with reference to Figure 12. Note that components identical to those in the basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This sixth basic circuit configuration example includes an input differential pair 101A, which is constructed using transistors with a different polarity than those in the first basic circuit configuration example. In other words, in this sixth basic circuit configuration example, the first and second transistors 1A and 2A for the differential pair that constitute the input differential pair 101A are NPN type bipolar transistors.

[0074] Therefore, in this sixth basic circuit configuration example, the connection configuration of the first and second differential pair transistors 1A and 2A between the positive power supply terminal 81 and the negative power supply terminal 82 is the reverse of the connection configuration in the first basic circuit configuration example shown in Figure 1. Specifically, the emitters of the first and second differential transistors 1A and 2A are connected to each other, and a constant current source 60 is connected between this connection point and the negative power supply terminal 82. On the other hand, the collector of the first differential transistor 1A is connected to the positive power supply terminal 81 via the first resistor 41, and the second differential transistor 2A is connected to the positive power supply terminal 81 via the second resistor 42. The collector of the first differential pair transistor 1A is connected to the power supply side of the input stage of the low-speed current mirror circuit 151 via the input stage reference terminal P1, and the collector of the second differential pair transistor 2A is connected to the power supply side of the output stage of the low-speed current mirror circuit 151 via the output stage reference terminal P2.

[0075] On the other hand, the collector of the third transistor 3 is connected to the input stage of the low-speed current mirror circuit 151, and the collector of the fourth transistor 4 is connected to the output stage of the low-speed current mirror circuit 151, as in the first basic circuit configuration example. However, unlike the first basic circuit configuration example, the emitters of the third and fourth transistors 3 and 4 are both connected to the negative power supply terminal 82. A first constant voltage source 61 is provided between the bases of the third and fourth transistors 3 and 4 and the negative power supply terminal 82, such that the bases of the third and fourth transistors 3 and 4 are the positive terminals. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0076] Next, we will explain the seventh basic circuit configuration example with reference to Figure 13. Note that components identical to those in the basic circuit configuration example shown in Figure 12 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This seventh basic circuit configuration example has a configuration in which a common-base amplifier circuit 152B, which is constructed using a PNP type bipolar transistor, is provided instead of the common-base amplifier circuit 152 in the basic circuit configuration example shown in Figure 12.

[0077] In other words, the fifth and sixth transistors (labeled "Q5" and "Q6" respectively in Figure 13), which are first and second amplification transistors using PNP-type bipolar transistors, have their bases connected to each other, and a second constant voltage source 62 is provided between the connection point and the positive power supply terminal 81, with its positive terminal facing the positive power supply terminal 81. Furthermore, the emitter of the fifth transistor 5 is connected to the collector of the first differential pair transistor 1A, and the emitter of the sixth transistor 6 is connected to the collector of the second differential pair transistor 2A.

[0078] Furthermore, the collector of the fifth transistor 5 is connected to the power supply side of the input stage of the low-speed current mirror circuit 151A via the input terminal P5, and the collector of the sixth transistor 6 is connected to the power supply side of the output stage of the low-speed current mirror circuit 151A via the output terminal P6. Furthermore, the input stage reference terminal P7 and output stage reference terminal P8 of the low-speed current mirror circuit 151A are both connected to the negative power supply terminal 82. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0079] Next, we will explain the eighth basic circuit configuration example with reference to Figure 14. Note that components identical to those in the basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This eighth basic circuit configuration example uses CMOS transistors instead of bipolar transistors in the remaining configuration of the first basic circuit configuration example, excluding the low-speed current mirror circuit 151. In this eighth basic circuit configuration example, the low-speed current mirror circuit 151 is based on the circuit configuration shown in the specific circuit configuration example in Figure 6, and the fifth and sixth transistors, which serve as the first and second transistors for the current mirror, are also PMOS transistors.

[0080] First, the input differential pair 101B is constructed using first and second MOS transistors 31 and 32 (labeled "M1" and "M2" respectively in Figure 14) which are p-channel MOS transistors used as first and second transistors for the differential pair. The sources of the first and second MOS transistors 31 and 32 are interconnected, and a constant current source 60 is provided between the connection point and the positive power supply terminal 81. Furthermore, a first resistor 41 is connected between the drain of the first MOS transistor 31 and the negative power supply terminal 82, and a second resistor 42 is connected between the drain of the second MOS transistor 32 and the negative power supply terminal 82.

[0081] Furthermore, in the output circuit 102, the common-base amplifier circuit 152C is constructed using n-channel MOS transistors as the first and second amplification transistors, respectively, with third and fourth MOS transistors (labeled "M3" and "M4" in Figure 14) 33 and 34. The gates of the third and fourth MOS transistors 33 and 34 are connected, and a first constant voltage source 61 is provided between the connection point and the negative power supply terminal 82 such that the positive terminal is located on the gate side of the third and fourth MOS transistors 33 and 34.

[0082] Furthermore, the source of the third MOS transistor 33 is connected to the drain of the first MOS transistor 31, and the source of the fourth MOS transistor 34 is connected to the drain of the second MOS transistor 32. The drain of the third MOS transistor 33 is connected to the input stage of the low-speed current mirror circuit 151, and the drain of the fourth MOS transistor 34 is connected to the output stage of the low-speed current mirror circuit 151. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0083] Next, we will explain the ninth basic circuit configuration example with reference to Figure 15. Note that components identical to those in the basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. The basic circuit configuration example in Figure 9 has a configuration in which an input differential pair 101C using an active load is provided instead of the input differential pair 101 in the first basic circuit configuration example (see Figure 1).

[0084] In other words, the active load is composed of transistors 21 and 22, which are NPN bipolar transistors (denoted as "Q21" and "Q22" respectively in Figure 15). Specifically, first, the bases of the 21st and 22nd transistors 21 and 22 are connected, and a third constant voltage source 63 is provided between the connection point and the negative power supply terminal 82 such that the positive terminal is located on the base side of the 21st and 22nd transistors 21 and 22. Furthermore, the collector of the 21st transistor 21 is connected to the collector of the first differential pair transistor 1, and the collector of the 22nd transistor 22 is connected to the collector of the second differential pair transistor 2.

[0085] The emitters of transistors 21 and 22 are both connected to the negative power supply terminal 82. Furthermore, just like in the first specific circuit configuration example (see Figure 6), it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0086] Next, we will explain the tenth basic circuit configuration example with reference to Figure 16. Note that components identical to those in the basic circuit configuration example shown in Figure 1 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. The tenth basic circuit configuration example is the first specific circuit configuration example, but with the addition of a high-pass filter to improve oscillation immunity. In other words, a high-pass filter (indicated as "HPF" in Figure 16) 110 is provided between the bases of the third and fourth transistors 3 and 4 and the collector of the fourth transistor 4.

[0087] Figure 17 shows the seventh specific circuit configuration example, which is a concrete example of the tenth basic circuit configuration example shown in Figure 16. This specific circuit configuration example will be explained below with reference to the same figure. Furthermore, a detailed explanation of the oscillation immunity of the high-pass filter 110 in the tenth basic circuit configuration example will be replaced by the explanation of the specific circuit configuration example shown in Figure 17. Furthermore, components identical to those in the first specific circuit configuration example shown in Figure 6 are given the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences.

[0088] First, the specific circuit configuration example shown in Figure 17 is a configuration in which low-pass filters 71 and 72 are added to the input side of the input differential pair 101, in addition to the basic circuit configuration example in Figure 16. The high-pass filter 110 consists of a high-pass resistor (labeled "RX1" in Figure 17) 45 and a high-pass capacitor (labeled "CX2" in Figure 17) 52.

[0089] Specifically, a high-pass capacitor 52 and a high-pass resistor 45 are connected in series between the collector of the fourth transistor 4 and the bases of the third and fourth transistors 3 and 4, starting from the collector side of the fourth transistor 4. In this specific circuit configuration example, the inclusion of the high-pass filter 110 significantly improves oscillation immunity in regions where the load capacitance CL is large, for example, in regions where CL = 1 nF. Therefore, the capacitance value CX2 of the high-pass capacitor 52 is set based on the following equation 4.

[0090] CX2≧Cc...Formula 4

[0091] Here, Cc is assumed to be the capacitance value of the phase compensation capacitor 54 provided between the input and output of the buffer amplifier 153. As shown in Equation 4, the capacitance value CX2 of the high-pass capacitor 52 must be equal to or greater than the capacitance value (phase compensation capacitance value) Cc of the phase compensation capacitor 54. Thus, the reason for setting the capacitance value CX2 to be equal to or greater than the phase compensation capacitance value Cc is to generate an AC signal at the bases of the third and fourth transistors 3 and 4 that is greater than or equal to the signal amplitude generated across the phase compensation capacitance value Cc.

[0092] Figure 25 shows a characteristic curve illustrating the phase margin change characteristics in response to changes in load capacitance, which is used to verify oscillation immunity. The following explanation will describe this figure. In the figure, the horizontal axis represents the change in load capacity, and the vertical axis represents the change in phase margin. Furthermore, in Figure 25, the solid characteristic curve shows the phase margin change characteristics with respect to load capacitance in the specific circuit configuration example shown in Figure 17. In addition, in Figure 25, the dashed-dotted characteristic curve shows the phase margin change characteristics with respect to load capacitance in the case of only the low-speed current mirror circuit 151, as in the first specific circuit example shown in Figure 6.

[0093] Furthermore, in Figure 25, the dashed-dot characteristic curve shows the phase margin change characteristics with respect to load capacitance in a conventional circuit without a low-pass filter (see Figure 26). Also in Figure 25, the dotted characteristic curve shows the phase margin change characteristics with respect to load capacitance in a conventional circuit with a low-pass filter (see Figure 27). As shown in Figure 25, in a configuration that includes a low-speed current mirror circuit 151 as shown in the specific circuit configuration example in Figure 17, it can be confirmed that by further using a high-pass filter, the phase margin at high load capacitance is further improved compared to the first specific circuit configuration example shown in Figure 6.

[0094] Furthermore, the high-frequency noise immunity in the specific circuit configuration example shown in Figure 17 can be obtained to the same characteristics as those previously described for the high-frequency noise immunity of the first specific circuit configuration example (Figure 6) with reference to Figure 23. Furthermore, just like in the first specific circuit configuration example mentioned earlier, it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage.

[0095] Next, we will explain the 11th basic circuit configuration example with reference to Figure 18. Note that components identical to those shown in the basic circuit configuration example in Figure 5 or Figure 16 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This eleventh basic circuit configuration example has a configuration in which a high-pass filter 110 is added to the fifth basic circuit configuration example shown in Figure 5. In other words, the high-pass filter 110 is provided between the bases of the 11th and 12th transistors 11 and 12 and the collector of the 12th transistor 12. Furthermore, achieving both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or input-referred noise voltage is possible, similar to the tenth basic circuit configuration example (see Figure 16) and the specific circuit configuration example shown in Figure 17.

[0096] Next, we will explain the 12th basic circuit configuration example with reference to Figure 19. Note that components identical to those shown in the basic circuit configuration example in Figure 12 or Figure 16 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This twelfth basic circuit configuration example has a configuration in which a high-pass filter 110 is added to the sixth basic circuit configuration example shown in Figure 12. In other words, the high-pass filter 110 is provided in series between the bases of the third and fourth transistors 3 and 4 and the collector of the fourth transistor 4. Furthermore, achieving both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or input-referred noise voltage is possible, similar to the tenth basic circuit configuration example (see Figure 16) and the specific circuit configuration example shown in Figure 17.

[0097] Next, we will explain the 13th basic circuit configuration example with reference to Figure 20. Note that components identical to those shown in the basic circuit configuration example in Figure 13 or Figure 16 are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This 13th basic circuit configuration example has a configuration in which a high-pass filter 110 is added to the 7th basic circuit configuration example shown in Figure 13. In other words, the high-pass filter 110 is provided between the bases of the fifth and sixth transistors 5 and 6 and the collector of the sixth transistor 6. Furthermore, achieving both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or input-referred noise voltage is possible, similar to the tenth basic circuit configuration example (see Figure 16) and the specific circuit configuration example shown in Figure 17.

[0098] Next, we will explain the eighth specific circuit configuration example with reference to Figure 21. Note that components identical to those in the specific circuit configuration example shown in Figure 10, or the basic circuit configuration example shown in Figure 18, are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This eighth specific circuit configuration example is a concrete example of the eleventh basic circuit configuration example shown in Figure 18, and has a configuration in which a high-pass filter 110 is added to the fifth specific circuit configuration example shown in Figure 10.

[0099] In other words, the high-pass filter 110 is provided by connecting a high-pass resistor 45 and a high-pass capacitor 52 in series from the base side of the 11th and 12th transistors 11 and 12 to the collector of the 12th transistor 12. Furthermore, achieving both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or input-referred noise voltage is possible, similar to the tenth basic circuit configuration example (see Figure 16) and the specific circuit configuration example shown in Figure 17.

[0100] Next, we will explain the ninth specific circuit configuration example with reference to Figure 22. Note that components identical to those in the specific circuit configuration example shown in Figure 6, and the basic circuit configuration example shown in Figure 12 or Figure 19, are denoted by the same reference numerals, and their detailed explanations are omitted. The following explanation will focus on the differences. This ninth specific circuit configuration example is a specific circuit example of the twelfth basic configuration example shown in Figure 19, and has a configuration in which first and second low-pass filters 71 and 72 are provided on the input side of the input differential pair 101A together with the high-pass filter 110. Furthermore, the low-speed current mirror circuit 151 basically has the configuration shown in Figure 6, but the connections of the emitter sides of the third and fourth transistors 3 and 4 and the emitter sides of the fifth and sixth transistors 5 and 6 are different, as described below.

[0101] In other words, the emitters of the third and fourth transistors 3 and 4 are both connected to the negative power supply terminal 82. Furthermore, the emitter of the fifth transistor 5 is connected to the collector of the first differential pair transistor 1A, and the emitter of the sixth transistor 6 is connected to the emitter of the second differential pair transistor 2A.

[0102] Furthermore, the high-pass filter 110 is provided by connecting a high-pass resistor 45 and a high-pass capacitor 52 in series from the base side of the third and fourth transistors 3 and 4 to the collector of the fourth transistor 4. In this configuration, unlike the specific circuit configuration example shown in Figure 21, an NPN bipolar transistor is used for the input differential pair 101A; however, the oscillation immunity is the same as that of the specific circuit configuration example shown in Figure 21.

[0103] Therefore, just as with the tenth basic circuit configuration example (see Figure 16) and the specific circuit configuration example shown in Figure 17, it is possible to achieve both improved high-frequency noise immunity and improved oscillation immunity without increasing the input bias current or the input-referred noise voltage. [Industrial applicability]

[0104] This can be applied to operational amplifiers where improved high-frequency noise immunity and oscillation immunity are desired, without increasing the input bias current or input-referred noise voltage. [Explanation of symbols]

[0105] 51…Capacitor for reducing speed 52... High-pass capacitor 101, 101A, 101B, 101C… Input differential pairs 102…Output circuit 110... High-pass filter 151, 151A, 151B, 151C, 151D, 151E, 151F… Low-speed current mirror circuit 152, 152A, 152B, 152C... Common-base amplifier circuits

Claims

1. An operational amplifier comprising an input differential pair configured to differentially amplify an input signal, and an output circuit that amplifies and outputs the output of the input differential pair, The output circuit includes a common-base amplifier circuit and a buffer amplifier, as well as a low-speed current mirror circuit that supplies current to the common-base amplifier circuit. The aforementioned low-speed current mirror circuit is configured to be slower by setting its cutoff frequency to be below the unity gain frequency of the operational amplifier. The cutoff frequency is set to 1 / 10 or less of the unity gain frequency of the operational amplifier. The input differential pair comprises first and second PNP type differential pair transistors, the emitters of the first and second differential pair transistors interconnected, and a constant current source provided between this connection point and the positive power supply terminal. The collector of the first differential pair transistor is connected to the negative power supply terminal via a first differential pair resistor, and the collector of the second differential pair transistor is connected to the negative power supply terminal via a second differential pair resistor. The base of the first differential pair transistor is connected to the inverting input terminal, and the base of the second differential pair transistor is connected to the non-inverting input. The common-base amplifier circuit has first and second amplification transistors, which are NPN bipolar transistors, the bases of the first and second amplification transistors are connected to each other, and a first constant voltage source is provided between the connection point and the negative power supply terminal, the emitter of the first amplification transistor is connected to the connection point between the collector of the first differential pair transistor and the first differential pair resistor, and the emitter of the second amplification transistor is connected to the connection point between the collector of the second differential pair transistor and the second differential pair resistor. The low-speed current mirror circuit comprises first and second current mirror transistors, which are PNP-type bipolar transistors, and a capacitor for slowing down the current. The bases of the first and second current mirror transistors are interconnected and connected to the collector of the first current mirror transistor. The collector of the first current mirror transistor is connected to the collector of the first amplification transistor, and the collector of the second current mirror transistor is connected to the collector of the second amplification transistor. The emitters of the first and second current mirror transistors are both connected to the positive power supply terminal, and the capacitor for slowing down the current is connected in series between the collector of the first current mirror transistor and the negative power supply terminal. The collector of the second amplification transistor is connected to the input stage of the buffer amplifier, and the output stage of the buffer amplifier is connected to the amplification output terminal. Between the input stage and the output stage, a phase compensation capacitor and a phase compensation resistor are provided, connected in series from the input stage side in the order of the phase compensation capacitor and the phase compensation resistor. A high-pass filter is provided between the bases of the first and second amplification transistors and the collector of the second amplification transistor. The operational amplifier is characterized in that the high-pass filter comprises a high-pass resistor and a high-pass capacitor, and is provided connected in series from the collector side of the second amplification transistor in the order of the high-pass capacitor and the high-pass resistor, and the capacitance value CX2 of the high-pass capacitor is set to a value that satisfies the inequality CX2 ≥ Cc with respect to the capacitance value Cc of the phase compensation capacitor.

2. An operational amplifier comprising an input differential pair configured to differentially amplify an input signal, and an output circuit that amplifies and outputs the output of the input differential pair, The output circuit includes a common-base amplifier circuit and a buffer amplifier, as well as a low-speed current mirror circuit that supplies current to the common-base amplifier circuit. The aforementioned low-speed current mirror circuit is configured to be slower by setting its cutoff frequency to be below the unity gain frequency of the operational amplifier. The cutoff frequency is set to 1 / 10 or less of the unity gain frequency of the operational amplifier. The input differential pair comprises first and second PNP type differential pair transistors, the emitters of the first and second differential pair transistors interconnected, and a constant current source provided between this connection point and the positive power supply terminal. The collector of the first differential pair transistor is connected to the negative power supply terminal via a first differential pair resistor, and the collector of the second differential pair transistor is connected to the negative power supply terminal via a second differential pair resistor. The base of the first differential pair transistor is connected to the inverting input terminal, and the base of the second differential pair transistor is connected to the non-inverting input. The common-base amplifier circuit has first and second amplification transistors, which are PNP bipolar transistors, the bases of the first and second PNP amplification transistors are connected to each other, and a second constant voltage source is provided between the connection point and the positive power supply terminal, and the emitters of the first and second PNP amplification transistors are both connected to the positive power supply terminal. The low-speed current mirror circuit has first and second current mirror transistors, which are NPN bipolar transistors. The bases of the first and second NPN current mirror transistors are interconnected and connected to the collector of the first NPN current mirror transistor. The collector of the first NPN current mirror transistor is connected to the collector of the first PNP amplification transistor, and the collector of the second NPN current mirror transistor is connected to the collector of the second PNP amplification transistor. Meanwhile, the emitter of the first NPN current mirror transistor is connected to the connection point between the collector of the first differential pair transistor and the first differential pair resistor, and the emitter of the second NPN current mirror transistor is connected to the connection point between the collector of the second differential pair transistor and the second differential pair resistor. The collector of the second amplification transistor is connected to the input stage of the buffer amplifier, and the output stage of the buffer amplifier is connected to the amplification output terminal. Between the input stage and the output stage, a phase compensation capacitor and a phase compensation resistor are provided, connected in series from the input stage side in the order of the phase compensation capacitor and the phase compensation resistor. A high-pass filter is provided between the bases of the first and second amplification transistors and the collector of the second amplification transistor. The operational amplifier is characterized in that the high-pass filter comprises a high-pass resistor and a high-pass capacitor, and is provided connected in series from the collector side of the second amplification transistor in the order of the high-pass capacitor and the high-pass resistor, and the capacitance value CX2 of the high-pass capacitor is set to a value that satisfies the inequality CX2 ≥ Cc with respect to the capacitance value Cc of the phase compensation capacitor.

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