Semiconductor die coupling techniques in stacked memory architectures

Abstract

Methods, systems, and devices are described for semiconductor die bonding techniques in stacked memory architectures. A semiconductor system may include a semiconductor unit formed of multiple semiconductor dies, each of which may be separately and separably manufactured. Each semiconductor die may include a respective portion of a circuit associated with the semiconductor unit. The multiple semiconductor dies may be coupled to a carrier, and each semiconductor die may be coupled (e.g., electrically and communicatively coupled) to at least one other semiconductor die. At least some of the semiconductor dies may be coupled to a respective set of one or more memory arrays, and each memory array may be operable based on the coupling between the multiple semiconductor dies.

Description

Technical Field

[0001] Cross-reference This patent application claims priority to U.S. Patent Application No. 18 / 776,197, filed Jul. 17, 2024, by Bhushan et al. entitled "TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES", and U.S. Patent Application No. 63 / 588,642, filed Oct. 6, 2023, by Bhushan et al. entitled "TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES", each of which has been assigned to the assignee of this specification and each of which is hereby expressly incorporated by reference in its entirety.

[0002] The following relates to one or more systems for memory, including techniques for semiconductor die coupling in a stacked memory architecture.

Background Art

[0003] Memory devices are widely used in devices such as computers, user devices, wireless communication devices, cameras, and digital displays to store information. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, often one of the states represented by logic 1 or logic 0. In some embodiments, a single memory cell can support two or more states, and any one of these can be stored. To access the stored information, the memory device can read the state (e.g., sense, detect, acquire, identify) from the memory cell. To store information, the memory device can write the state (e.g., program, set, assign) to the memory cell. ​​

[0004] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive random-access RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technology, negative OR (NOR) memory devices, and negative AND (NAND) memory devices. Memory cells can be described in terms of volatile or non-volatile configurations. Non-volatile memory cells can maintain their stored logical state for extended periods even without an external power supply. Volatile memory cells can lose their stored state when disconnected from an external power supply. [Brief explanation of the drawing]

[0005] [Figure 1] Examples of systems supporting semiconductor die coupling techniques in stacked memory architectures, as disclosed herein, are shown. [Figure 2] Examples of systems supporting semiconductor die coupling techniques in stacked memory architectures, as disclosed herein, are shown. [Figure 3] Examples of interface architectures supporting semiconductor die coupling techniques in stacked memory architectures are shown by embodiments disclosed herein. [Figure 4A] Examples of semiconductor components and die assemblies that support semiconductor die coupling techniques in stacked memory architectures, as disclosed herein, are shown. [Figure 4B] Examples of semiconductor components and die assemblies that support semiconductor die coupling techniques in stacked memory architectures, as disclosed herein, are shown. [Figure 5] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 6] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 7] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 8] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 9] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 10] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 11] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 12] Examples of operations for forming a semiconductor system using semiconductor die coupling techniques in a stacked memory architecture, as disclosed herein, are shown. [Figure 13] A flowchart illustrating a method for supporting semiconductor die coupling techniques in stacked memory architectures, as disclosed herein, is shown. [Figure 14] A flowchart illustrating a method for supporting semiconductor die coupling techniques in stacked memory architectures, as disclosed herein, is shown. [Modes for carrying out the invention]

[0006] Some memory systems may include a stack of semiconductor dies, which may include one or more memory dies (e.g., array dies) or one or more stacks of stacked memory dies, stacked together with logic dies capable of accessing a set of memory arrays distributed across one or more memory dies. Such a stacked architecture is a high-bandwidth memory (HBM) system or is Combined Dynamic Random Access Memory (D It can be implemented as part of a RAM system and, among many embodiments, can support memory-centric logic solutions such as graphics processing units (GPUs). In some embodiments, the HBM system may include a stack of memory dies located on top of the logic dies (e.g., positioned, placed). In some embodiments, 3D stacked memory The system may be closely coupled (e.g., physically coupled, electrically coupled, directly coupled) to a processor such as a GPU or other host as part of a physical memory map accessible to the processor. Such coupling may involve an HBM system or 3D stacked memory One or more processors implemented on the same semiconductor die as at least a part of the system (for example, as part of a logic die), or an HBM system or 3D stacked memory A die that is directly coupled (e.g., fused) to another die that includes at least a part of the system, or an HBM system or 3D stacked memory It may include one or more processors implemented on a die that is coupled in a different way (e.g., via a silicon interposer or other intermediary component) to another die containing at least a portion of the system. Unlike cache-based memory, 3D stacked memory The system cannot be supported at the external memory level that has the same physical address. For example, 3D stacked memory The system may be associated with a dedicated base address and located within the dedicated base address. 3D stacked memory No part of the system will overlap within its dedicated base address.

[0007] Some semiconductor dies (e.g., logic dies) may contain multiple components, such as interface blocks (e.g., memory interface blocks, interface circuits), logic blocks, controllers, processors, and other components. In some embodiments, such dies may have a relatively low manufacturing yield, which may be related to the relative size or complexity of integrating multiple components on the same die. For example, if at least one of the components of a die fails an evaluation procedure, the die may be rejected (e.g., discarded) during the manufacturing process. That is, even if most of the components of a die can meet the evaluation, the failure of just one component may cause the die to be rejected. Therefore, the probability that each component of a relatively complex or relatively large die will meet the evaluation may be relatively low, and thus the yield of such dies may be relatively low.

[0008] According to the embodiments disclosed herein, semiconductor components (e.g., semiconductor units, semiconductor subsystems, logic units, logic parts of HBM systems) 3D stacked memoryThe logic portion of a system (a heterogeneous semiconductor device) can be formed by bonding multiple semiconductor die portions (e.g., relatively small dies, each containing a subset of the components of a logic unit) to a carrier and interconnecting them. At least some, if not all, of the die portions may individually satisfy evaluation (e.g., they may be good-quality dies before interconnection (KGD)). In some embodiments, the die portions may be referred to as "chiplets" (e.g., logic chiplets), and each chiplet may contain its own portion of a circuit that can be otherwise associated with the function of a relatively larger die. For example, such a semiconductor component may be formed in which, among many examples of circuit subdivision, the first chiplet contains a memory interface circuit, the second chiplet contains a processor circuit, and the third chiplet contains a logic circuit. Multiple chiplets may be interconnected with conduction paths (e.g., via a redistribution layer (RDL) through the back side of at least some of the chiplets) and with one or more through-silicon vias (TSVs) in each of the chiplets, which may include various semiconductor manufacturing techniques for bonding the chiplets. At least some of the chiplets may be further coupled with one or more memory dies (e.g., stacked memory dies). In some embodiments, one or more stacked memory dies may have dedicated conduction paths for power supply signals or other signals (e.g., for a power distribution network (PDN) using through-reconstruction vias (TRVs)) that bypass the chiplets (e.g., bypass one or more dies of the logic layers).

[0009] By supporting the subdivision and coupling of multiple chiplets (e.g., multiple chiplets constituting a multi-die semiconductor unit), relatively small wafer portions can be rejected (e.g., based on the rejection of chiplets that failed evaluation), which can support improved wafer yield. Thus, the manufacturing yield of multi-die semiconductor units (e.g., logic units) can be improved compared to the yield of single-die semiconductor units (e.g., based on improved yield due to the interconnection of relatively small KGD chiplets). Furthermore, dedicated conduction paths (e.g., dedicated conduction paths for power supply to one or more memory dies) may have lower resistance and cannot occupy area within the substrate of other dies (e.g., other dies in a single-die logic system), which can support increased semiconductor circuit area, increased wafer circuit yield, and improved memory system performance.

[0010] In addition to the applicability of the systems described herein, semiconductor die coupling techniques in stacked memory architectures can generally be implemented to support artificial intelligence or machine learning applications, among many types of computationally intensive applications. As the use of artificial intelligence increases to support machine learning applications, analytical applications, decision-making applications, or other related applications, electronic devices that support artificial intelligence applications and processes may be required. For example, artificial intelligence applications may involve accessing relatively large amounts of data for analytical purposes and may benefit from memory systems that can store relatively large amounts of data effectively and efficiently, or access the stored data relatively quickly. Implementing the techniques described herein can support artificial intelligence and machine learning techniques by supporting improved device yield and interoperability, including, for example, coupling semiconductor units (e.g., logic dies in HBM systems) from relatively small semiconductor die portions (rather than as a single monolithic unit). 3D stacked memoryThis includes supporting artificial intelligence and machine learning techniques by forming logic dies in a system. Such techniques allow for the rejection of relatively small components and the acceptance of the remaining relatively small components, which can improve the manufacturing yield of devices that support artificial intelligence and machine learning techniques. Furthermore, the yield of such devices can be improved based on dedicated vias for power supply to the memory array (e.g., instead of power supply through circuits on other dies), which can support an increase in the circuit density of the wafer. In addition, the techniques herein can improve the power efficiency of memory arrays (e.g., memory arrays in a tightly coupled stack of array dies), which can support improved performance and reduced latency of stacked memory architectures.

[0011] Features of this disclosure are illustrated and described in relation to the system and die. Features of this disclosure are further illustrated and described in relation to the interface architecture, semiconductor components, die assembly, exemplary manufacturing techniques, and flowcharts.

[0012] Figure 1 shows an example of a system 100 supporting semiconductor die coupling techniques in a stacked memory architecture according to embodiments disclosed herein. System 100 may include a portion of an electronic device such as a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a vehicle, or other system. System 100 includes a host system 105, a memory system 110, and one or more channels 115 that couple the host system 105 with the memory system 110 (for example, to provide a communicable coupling). System 100 may include one or more memory systems 110, but embodiments of one or more memory systems 110 may be described in terms of a single memory system 110.

[0013] The host system 105 can be an example of a processing system (e.g., a circuit, one or more processors, an application processing system, a processing circuit, one or more processing components) that uses memory to execute processes (e.g., applications, functions, computations). Examples of the processing system include, among others, a processing system in a computing device, a mobile computing device, a wireless communication device, a graphics processing device, a wearable device, an Internet-connected device, a vehicle control device, a system on a chip (SoC), or other fixed or portable electronic devices. The host system 105 can include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., peripheral components, input / output controllers not shown). The components of the host system 105 can be coupled to each other using a bus 135.

[0014] [[ID=丙]] The external memory controller 120 may be configured to enable communication of information (e.g., data, commands, control information, configuration information) between components of the system 100 (e.g., between components of the host system 105 and the memory system 110, such as the processor 125). For example, the external memory controller 120 may generate commands to write data to the memory system 110, read data from the memory system 110, or communicate with the memory system 110 in a different way (e.g., in response to or to support an application of the host system 105). The external memory controller 120 may process (e.g., convert, transform) communications exchanged between the host system 105 and the memory system 110. In some embodiments, the external memory controller 120, or other components of the system 100, or related functions described herein may be performed by or part of the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software (e.g., instructions) implemented by the processor 125, or other components of the system 100 or host system 105, or any combination thereof. Although the external memory controller 120 is shown outside the memory system 110, in some embodiments, the external memory controller 120 or its functions as described herein may be implemented by one or more components of the memory system 110 (e.g., memory system controller 155, local memory controller 165), or vice versa. In various embodiments, the host system 105 or the external memory controller 120 may be referred to as the host.

[0015] Processor 125 may be operable to provide functions (e.g., control functions, processing functions) to system 100 or host system 105. Processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gates or transistor logic, discrete hardware components, or any combination thereof (e.g., any combination as one or more processing components configured individually or collectively to support the applications of host system 105). In some embodiments, processor 125 can be, among other examples, a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or an example of a system-on-chip (SoC).

[0016] In some embodiments, system 100 or host system 105 may include an input component, an output component, or a combination thereof. The input component can include, among other examples, a sensor, a microphone, a keyboard, another processor (e.g., another processor on a printed circuit board), an interface (e.g., a user interface, an interface between other devices), or a peripheral device that interfaces with system 100 via one or more peripheral components. The output component can include, among other examples, a display, an audio speaker, a printing device, another processor on a printed circuit board, or a peripheral device that interfaces with system 100 via one or more peripheral components.

[0017] The memory system 110 may be a component of system 100 capable of operating to provide physical memory locations (e.g., addresses) that system 100 (e.g., host system 105) can use or reference. The memory system 110 may include a memory system controller 155 and one or more memory dies 160 (e.g., memory chips) to support the capacity of data storage. The memory system 110 may be configured to operate with one or more different types of host systems 105 and may perform actions in response to commands provided by the host system 105 (e.g., via an external memory controller 120). For example, the memory system 110 (e.g., the memory system controller 155) may receive write commands indicating that data received from the host system 105 should be stored by the memory system 110, or read commands indicating that data stored on the memory die 160 should be provided to the host system 105, or refresh commands indicating that data stored on the memory die 160 should be refreshed by the memory system 110.

[0018] The memory system controller 155 may include components (e.g., circuits, logic, instructions) that can operate to control the operation of the memory system 110. The memory system controller 155 may include hardware, firmware, or instructions that enable the memory system 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information related to the operation of the memory system 110. The memory system controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or processors 125. In some embodiments, the memory system controller 155 may cooperate with the local memory controller 165 of the memory die 160 to control the operation of the memory system 110.

[0019] Each memory die 160 may include one or more local memory controllers 165 and one or more memory arrays 170. A memory array 170 may be a collection of memory cells, each memory cell capable of operating to store one or more bits of data. A memory array 170 may include a two-dimensional (2D) array of memory cells or a three-dimensional (3D) array of memory cells. In some embodiments, a two-dimensional (2D) memory die 160 may include a single memory array 170. In some embodiments, a three-dimensional (3D) memory die 160 may include two or more memory arrays 170, which may be stacked on top of each other or arranged side by side (for example, relative to a substrate).

[0020] The local memory controller 165 may include components (e.g., circuits, logic, instructions) that can operate to control the operation of the memory die 160. In some embodiments, the local memory controller 165 may be operable to communicate with the memory system controller 155 (e.g., to receive or send data or commands or both). In some embodiments, the memory system 110 may not include the memory system controller 155, and the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the memory system controller 155, or with other local memory controllers 165, or directly with the external memory controller 120, or the processor 125, or any combination thereof. Examples of components that may be included in the memory system controller 155, or the local memory controller 165, or both, include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for sending signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating transmitted signals, a sensing component for detecting the state of memory cells in the memory array 170, a writing component for writing states to memory cells in the memory array 170, or various other components capable of operating to support the operation of the memory system 110 described.

[0021] A host system 105 (e.g., an external memory controller 120) and a memory system 110 (e.g., a memory system controller 155) may communicate information (e.g., data, commands, control information, configuration information) using one or more channels 115. Each channel 115 may be an example of a transmission medium that carries information, and each channel 115 may include one or more signal paths (e.g., a transmission medium, a conductor, a conductive path) between terminals associated with components of system 100. For example, channel 115 may be associated with a first terminal in the host system 105 (e.g., a terminal including one or more pins, a terminal including one or more pads) and a second terminal in the memory system 110. The terminals may be examples of conducted input points or conducted output points of devices in system 100, and the terminals may be operable to function as part of channel 115. In some embodiments, at least the channel 115 between the host system 105 and the memory system 110 may include, or may be referred to as, a host interface (e.g., a physical host interface). In some embodiments, the host interface may include, or be associated with, interface circuits (e.g., signal drivers, signal latches) in the host system 105 (e.g., external memory controller 120), or in the memory system 110 (e.g., memory system controller 155), or both.

[0022] In some embodiments, channel 115 (e.g., associated signal paths and terminals) may be specialized for communicating one or more types of information. For example, channel 115 may include, among several channels, one or more command and address channels, one or more clock signal channels, one or more data channels, or a combination thereof. In some embodiments, signaling may be communicated via channel 115 using single data-rate (SDR) signaling or double data-rate (DDR) signaling. In SDR signaling, one modulation symbol of a signal (e.g., signal level) may be registered per clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols of a signal may be registered per clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0023] In some embodiments, at least a portion of the system 100 may implement a stacked die architecture in which multiple semiconductor dies are physically and communicatively coupled. In some such embodiments, the circuitry for accessing one or more memory arrays 170 (e.g., the circuitry of the memory system 110) may be distributed across multiple semiconductor dies in a stack (e.g., a stack of multiple directly coupled semiconductor dies). For example, a first die may include a set of multiple first interface blocks (e.g., memory interface blocks, instances of first interface circuits), and one or more second dies may include corresponding second interface blocks, each of which is coupled to a first interface block of the first die, and each of which is configured to access one or more memory arrays of the second die. In some embodiments, the system may include, for each set of one or more first interface blocks, a controller (e.g., at least a portion of a memory controller, interface controller, host interface controller, external memory controller 120) to support access operations via the set of first interface blocks (e.g., operations to access one or more memory arrays 170). In some embodiments, such a controller may be located on the same first die as the first interface block.

[0024] In some embodiments, the memory system 110 or system 100 (for example, an HBM system including an embodiment of the memory system 110, an embodiment including the memory system 110 and a host system 105) 3D stacked memoryThe system includes one or more array dies (e.g., memory dies 160) stacked with logic dies (e.g., logic dies including an embodiment of the host system 105, logic dies coupled with another die including the host system 105 or other components), the logic dies including interface blocks operable to access a set of memory arrays 170 distributed across one or more second dies. A system 100 or a portion of a system 100 having a stacked memory architecture may support semiconductor die coupling techniques in the stacked memory architecture. For example, a semiconductor unit (e.g., a semiconductor component, a logic unit) may be formed of multiple semiconductor die portions (e.g., chiplets, logic chiplets), which are interconnected after an evaluation procedure (e.g., as interconnections of logic chiplets that satisfy an evaluation such as KGD). At least some of the chiplets may be further coupled with one or more stacked memory arrays 170 which may similarly have power-supply-only vias (e.g., PDN through vias (TVs), TRVs). Therefore, based on forming a semiconductor unit with multiple semiconductor chiplets and dedicated vias, the memory system 110 or system 100 (for example, an HBM system) 3D stacked memory The manufacturing yield of the system can be improved, and the memory system 110 can benefit from improved power efficiency based on supplying power to one or more stacked memory arrays 170 via one or more dedicated vias.

[0025] Figure 2 shows a system 200 (e.g., semiconductor system, coupled semiconductor die system, HBM system, etc.) that supports semiconductor die coupling techniques in stacked memory architectures according to embodiments disclosed herein. 3D stacked memoryAn example of a system is shown. System 200 shows an example of a die 205 (e.g., die 205-a, semiconductor die, logic die, processor die, host die, logic unit) coupled with one or more dies 240 (e.g., dies 240-a-1 and 240-a-2, semiconductor die, memory die, array die, memory unit). Die 205 or die 240 may be formed using their respective semiconductor substrates (e.g., substrates of crystalline semiconductor materials such as silicon, germanium, silicon-germanium, gallium arsenide, or gallium nitride), or silicon-on-insulator (SOI) substrates (e.g., silicon-on-glass (SOG) substrates, silicon-on-sapphire (SOS) substrates), or epitaxial semiconductor materials formed on another substrate, among many other examples. The illustrated example of system 200 includes two dies 240, but system 200 by the technique of this description may include one or any number of dies 240, which are coupled with die 205 among several dies in a stack or other combined layout. Furthermore, the non-limiting examples of system 200 described herein are generally described in terms of applicability to memory systems, memory subsystems, memory devices, or combinations thereof, but the examples of system 200 are not limited in this way. For example, aspects of this disclosure may also be applied to any computing system, computing subsystem, processing system, processing subsystem, component, device, structure, or other type of system or subsystem used in applications such as data acquisition, data processing, data storage, networking, communications, power, artificial intelligence, system-on-a-chip, control, telemetry, sensing and surveillance, digital entertainment, or any combination thereof.

[0026] System 200 provides an example of an interface circuit between a host and memory (e.g., a circuit via a host interface, a circuit via a physical host interface), where the interface circuit is implemented on multiple semiconductor dies (e.g., a stack of directly coupled dies) (e.g., divided among multiple semiconductor dies). For example, die 205-a may include one or more sets of interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2, a memory interface block), and each die 240 may include one or more sets of interface blocks 245 (e.g., access interface blocks) and one or more memory arrays 250 (e.g., die 240-a-1 includes interface block 245-a-1 coupled with one or more sets of memory arrays 250-a-1, and die 240-a-2 includes interface block 245-a-2 coupled with one or more sets of memory arrays 250-a-2). Memory array 250 may be an example of memory array 170 and may include memory cells of various architectures, such as RAM, DRAM, SDRAM, SRAM, FeRAM, MRAM, RRAM, PCM, chalcogenide, NOR, or NAND memory cells, or any combination thereof.

[0027] In the example of system 200, it is shown that each die 240 contains one interface block 245, but a die 240 using the technique of this description may contain one or any number of interface blocks 245, each interface block 245 coupled to its own set of one or more memory arrays 250 and coupled to an interface block 220 of die 205. Thus, the interface circuit of system 200 may contain one or more interface blocks 220 of die 205, each interface block 220 coupled (e.g., communicates) to one or more interface blocks 245 of die 240 (e.g., outside die 205). In some embodiments, the coupled combination of interface block 220 and interface block 245 (coupled via a bus associated with one or more channels, such as one or more data channels, one or more control channels, one or more clock channels, one or more pseudo channels, or a combination thereof) may include, or may be referred to as, a data path associated with its own set of one or more memory arrays 250.

[0028] Several implementations Mr.The die 205 may include a host processor 210. The host processor 210 may be an example of the host system 105 or a part thereof (e.g., a processor 125, an external memory controller 120, or both). The host processor 210 may be configured to perform operations that perform storage of the memory array 250 (e.g., to support an application or other function of the host system 105 that may request access to the memory array 250). For example, the host processor 210 may receive data read from the memory array 250, or send data to write to the memory array 250, or both (e.g., according to an application or other operation of the host processor 210). Additionally or alternatively, the host processor 210 may reside outside the die 205 (for example, in the HBM embodiment), or on another semiconductor die or other component coupled to the die 205 via one or more contacts 212 (for example, externally accessible terminals of the die 205) (for example, communicatively coupled, directly coupled, bonded, coupled via another intervening component).

[0029] The host processor 210 may be configured to communicate (e.g., transmit, receive) signaling with the interface block 220 via a host interface 216 (e.g., a physical host interface), thereby implementing the channel 115 configuration described with reference to Figure 1. In some embodiments, the host interface 216 may provide a communicable coupling between the physical or functional boundary between the host system 105 and the memory system 110. For example, the host processor 210 may be configured to communicate access signaling (e.g., control signaling, access command signaling, data signaling, configuration signaling) via the host interface 216 to support access operations to the memory array 250 (e.g., read operations, write operations), among many other operations. While the example system 200 includes a single host interface 216, a system using the techniques described herein may include one or any number of host interfaces 216 to access the system's memory array 250.

[0030] In some embodiments, each host interface 216 may be coupled to its own controller 215 with a set of one or more interface blocks 220 (e.g., interface blocks 220-a-1 and 220-a-2). The controller 215 may be an example of a control circuit associated with the host system 105 (e.g., a memory controller circuit, a host interface control circuit) and may be associated with implementing one or more embodiments of an external memory controller 120, or one or more embodiments of a memory system controller 155, or any combination thereof. For example, the controller 215 may be able to operate in response to instructions (e.g., requests, commands) from the host processor 210, and may be instructed to access one or more memory arrays 250 in support of a function or application of the host processor 210, to send relevant commands (e.g., to one or more interface blocks 220) for accessing one or more memory arrays 250, and to communicate data (e.g., write data, read data) with the host processor 210.

[0031] In some embodiments, regardless of whether the host processor 210 is contained within or outside of the die 205, one or more controllers 215 may be implemented on the die 205 (e.g., the same die containing one or more interface blocks 220). In some other embodiments, the controllers 215 or associated circuitry or associated functions may be implemented outside of the die 205 (e.g., not shown, but each host interface 216 may be implemented on a separate die coupled to its respective interface block 220 via its respective terminals), and outside of the die 205 may be the same die containing the host processor 210, or a different die from the die containing the host processor 210. The interface blocks 220 may be operable via a single controller 215, or by one or more of a set of multiple controllers 215 (e.g., according to a controller multiplexing scheme). In some other embodiments, one or more controllers 215 may be contained within the host processor 210 (e.g., as a memory interface for the host processor 210, as a memory interface for the host system 105).

[0032] In some embodiments, the controller 215 may be directly coupled to one or more interface blocks 220 (not shown), while in some other embodiments, the controller 215 (e.g., host interface 216) may be coupled to a set of multiple interface blocks 220 via logic blocks 225 (e.g., logic circuits for channel sets, logic circuits for host interface 216, multiplexing circuits). For example, logic block 225 may be coupled to interface block 220-a-1 via bus 223-a-1 and to interface block 220-a-2 via bus 223-a-1. The controller 215 and one or more corresponding interface blocks 220 may communicate (e.g., cooperate) using the host interface 216 and via logic blocks 225 to perform one or more operations (e.g., scheduling operations, access operations, operations initiated by the host processor 210) that involve accessing one or more corresponding sets of memory arrays 250.

[0033] In some embodiments, a logic block 225, a controller 215, or a host interface 216, or a combination thereof, may be associated with a “channel set” corresponding to multiple memory arrays 250 (for example, for parallel access or otherwise coordinated access of multiple memory arrays 250). For example, such a channel set may be associated with multiple memory arrays 250 accessed via a single interface block 245, or multiple memory arrays 250 each accessed via their respective interface block 245, or multiple memory arrays 250 each accessed via their respective interface block 220, any of which may be associated with signaling via a single logic block 225, a single host interface 216, or a single controller 215. These and other configurations for implementing one or more channel sets in a system can support various techniques related to parallel processing and high-bandwidth data transfer, memory management operations, repair and replacement techniques, or power and heat distribution, among many techniques that leverage the described coupling of components and interfaces between multiple semiconductor dies (for example, by a high-bandwidth memory configuration of system 200, by a tightly coupled configuration of system 200). In some embodiments, such techniques may be implemented in a manner transparent to the host interface 216 or other aspects of the host system 105 (for example, in or using the logical block 225).

[0034] In some embodiments, the host interface 216 may include one or more sets of signal paths for each logical block 225 or interface block 220, so that the host processor 210 can communicate with each logical block 225 or interface block 220 via its corresponding set of signal paths (for example, according to the selection of the corresponding set for performing access operations via the logical block 225 or interface block 220 selected by the host processor 210). Additionally or alternatively, the host interface 216 may include one or more signal paths shared among a plurality of logic blocks 225 (not shown) or a plurality of interface blocks 220, and a logic block 225, an interface block 220, or the host processor 210, or any of these, may interpret, ignore, respond to, or suppress responses to signaling via the shared signal paths of the host interface 216 based on logic instructions (for example, based on address instructions, interface enable signals, or interface selection signals associated with a logic block 225 or interface block 220, which may be provided by the host processor 210, the corresponding logic block 225, or the corresponding interface block 220 depending on the direction of the signaling).

[0035] In some embodiments, the host processor 210 may decide to access an address (for example, a logical address of the memory array 250, a physical address of the memory array 250, an address of a logical block 225, an address of an interface block 220, or an address of a host interface 216 in response to an application of the host processor 210 or an application supported by the host processor 210) and may decide which controller 215 to send an access signaling to in order to access the address (for example, the controller 215, logical block 225, or interface block 220 corresponding to the address). In some embodiments, the address may be associated with a row of memory cells in the memory array 250, a column of memory cells in the memory array 250, or both. The host processor 210 may send an access signaling (for example, one or more access signals, one or more access commands) to the determined controller 215, which may then send an access signaling to the corresponding logical block 225 or interface block 220. Subsequently, the corresponding interface block 220 may send an access signal to the coupled interface block 245 in order to access the determined address (for example, the address of the corresponding memory array 250).

[0036] Die 205 may also include logic blocks 230 (e.g., shared logic blocks, central logic blocks, common logic circuits, evaluation circuits, memory system configuration circuits, memory system management circuits) which may be configured to communicate (e.g., transmit, receive) signaling with the logic blocks 225, interface blocks 220, or both of these of die 205. In some cases, logic blocks 230 may be configured to communicate information (e.g., commands, instructions, directives, data) with one or more logic blocks 225 or interface blocks 220 to facilitate the operation of system 200. For example, logic block 230 may be configured to transmit configuration signaling (e.g., initialization signaling, evaluation signaling, mapping signaling), which is received by logic blocks 225 or interface blocks 220 and may support the configuration of logic blocks 225 or interface blocks 220, or other forms of configuration that operate die 240 (e.g., via their respective interface blocks 245). A logic block 230 may be coupled to each logic block 225 and each interface block 220 via their respective buses. In some embodiments, each such bus may include its own set of one or more signal paths, so that the logic block 230 can communicate with each logic block 225 or each interface block 220 via its own set of signal paths. Additionally or alternatively, such buses may include one or more signal paths shared among multiple logic blocks 225 or interface blocks 220 (not shown).

[0037] In some embodiments, the logic block 230 may be configured to communicate (e.g., send, receive) signaling with the host processor 210 (e.g., via a bus, via a contact 212 of the host processor 210 outside the die 205), so that the logic block 230 can support an interface between the host processor 210 and the logic block 225 or interface block 220. For example, the host processor 210 may be configured to send initialization signaling (e.g., boot commands), or other configuration or operation signaling, which are received by the logic block 230 and can support the initialization, configuration, evaluation, or other operation of the logic block 225 or interface block 220. Additionally or alternatively, in some embodiments, the logic block 230 may be configured to communicate signaling (e.g., send, receive) with external components of the system 200 (e.g., via contacts 234 which may be externally accessible terminals of the die 205), so that the logic block 230 may support an interface that bypasses the host processor 210. Additionally or alternatively, the logic block 230 may communicate with the host processor 210 and with one or more memory arrays 250 of one or more dies 240 (e.g., to perform self-test operations to access the memory arrays 250). In some embodiments, such embodiments may support evaluation, configuration, or other operations of the system 200 via one or more contacts 234 accessible at the system's physical interface during manufacturing, assembly, verification, or other operations related to the system 200 (e.g., with respect to operations unrelated to the host processor, without implementing the host processor 210, before coupling with the host processor 210). Additionally or alternatively, the logic block 230 may implement one or more embodiments of the controller 215. For example, the logic block 230 may include one or more controllers 215, or may operate as one or more controllers 215 and perform operations belonging to the controller 215.

[0038] Each interface block 220 may be coupled to at least the bus 221 of the die 205 and the bus 246 of the die 240, and these buses are configured to communicate signaling with the corresponding interface block 245 (e.g., via one or more associated signal paths). For example, interface block 220-a-1 may be coupled to interface block 245-a-1 via buses 221-a-1 and 246-a-1, and interface block 220-a-2 may be coupled to interface block 245-a-2 via buses 221-a-2 and 246-a-2. In some embodiments, the die 240 may include buses such as bus 255 that bypass the operating circuitry of the die 240 (e.g., bypass the interface block 245 of a given die 240). For example, interface block 220-a-2 may be coupled to interface block 245-a-2 of die 240-a-1 via bus 255-a-1 of die 240-a-1, which can bypass interface block 245 of die 240-a-1. Such a technique can be extended for interconnection between three or more dies 240 (for example, for interconnection between multiple dies 240 via their respective buses 255).

[0039] The respective signal paths of buses 221, 246, and 255 can be coupled to each other from one die to another via various arrangements of contacts on the interface dies' surfaces (e.g., exposed contacts, the metal surfaces of each die). For example, bus 221-a-1 may be coupled to bus 246-a-1 via contact 222-a-1 on die 205-a (e.g., on its surface) and contact 247-a-1 on die 240-a-1; bus 221-a-2 may be coupled to bus 255-a-1 via contact 222-a-2 on die 205 and contact 256-a-1 on die 240-a-1; bus 255-a-1 may be coupled to bus 246-a-2 via contact 257-a-1 on die 240-a-1 and contact 247-a-2 on die 240-a-2, and so on. Each bus is represented by a single line coupled via a single contact, but it should be understood that each signal path of a given bus is associated with its respective contact and can support separate communication couplings via each signal path of a given bus. In some embodiments, the bus 255 may traverse a portion of the die 240 (e.g., in the in-plane direction, along a direction different from the thickness direction, in a waterfall arrangement, in a stepped arrangement), thereby supporting arrangements in which, among many contacts, contact 222 along the surface of the die 205 is coupled to interface blocks 245 of different dies 240 along the stacking direction (e.g., coupled via respective contacts 256 and 257 that do not overlap when viewed along the thickness direction).

[0040] The interconnection of interface contacts can be supported by various techniques. For example, in a hybrid bonding embodiment, interface contacts can be bonded by the fusion of the conductive material (e.g., conductive material) of the interface contacts (e.g., without solder or other intervening material between the contacts). For example, in an assembly configuration, the bonding of die 205-a to die 240-a-1 may include the fusion of the conductive material of contact 222-a-2 with the conductive material of contact 256-a-1, the bonding of die 240-a-1 to die 240-a-2 may include the fusion of the conductive material of contact 257-a-1 with the conductive material of contact 247-a-2, and so on. In some embodiments, such bonding may include non-operational bonding of contacts (e.g., non-communicative bonding, physical bonding), such as the fusion of contacts that are not coupled to the operating circuit of die 240-a-1 or 240-a-2, such as the fusion of contact 260-a-1 to contact 256-a-2. In some embodiments, such techniques may be implemented to improve coupling strength or uniformity (e.g., by implementing contacts 260 that cannot be in an operable coupling state with interface block 245 or interface block 220), or such coupling may be a by-effect of component repetition and may be operable or inoperable in various configurations (e.g., in die 240 having a common arrangement of contacts 256 and 257, contacts 256-a-1 and 257-a-1 provide a communication path between interface block 245-a-2 and interface block 220-a-2, but contacts 256-a-2 and 257-a-2 do not provide a communication path between interface block 245 and interface block 220).

[0041] In some embodiments, the fusion of conductive materials between dies (e.g., between contacts) may involve the fusion of other materials on one or more surfaces of the interface die. For example, in an assembly configuration, the bonding of die 205 to die 240-a-1 may involve the fusion of the dielectric material 207 (e.g., non-conductive material) of die 205-a with the dielectric material 242 of die 240-a-1, and the bonding of die 240-a-1 to die 240-a-2 may involve the fusion of the dielectric material 242 of die 240-a-1 with the dielectric material 242 of die 240-a-2. In some embodiments, such dielectric materials may include oxides, nitrides, carbides, oxynitrides, oxycarbides, or other converted or doped materials of the substrate material (e.g., semiconductor substrate material) of die 205 or die 240, among a number of materials capable of supporting such fusion. However, the bond between die 205 and die 240 may be implemented according to other techniques that may involve solder, adhesive, thermal conductive material, and other intervening materials.

[0042] In some embodiments, the dies 240 may be bonded in a stack (e.g., forming a “cube” or other structure of dies 240), and then one or more of these stacks may be bonded to a die 205 (e.g., in a stack-to-chip bonding structure). In some embodiments, each set(s) of one or more dies 240 may be bonded to each die 205 of a plurality of dies 205 formed on a wafer (e.g., a chip-to-wafer bonding structure, a stack-to-wafer bonding structure, before the wafer of the dies 205 is cut), and each set(s) of dies 240 and the respective bonded dies 205 on the wafer may be separated from each other (e.g., by cutting the wafer of at least the dies 205). In some other embodiments, each set(s) of one or more dies 240 may be bonded to each die 205 after the dies 205 have been separated from the wafer of the dies 205 (e.g., in a chip-to-chip bonding structure). In some other embodiments, each set of one or more wafers, each containing multiple dies 240, may be joined in a stack (e.g., in a wafer-to-wafer bonding structure). In various embodiments, after such a technique, the stack of dies 240 may be separated from the bonded wafer, or the stack of wafers having dies 240 may be joined with another wafer containing multiple dies 205 (e.g., in a second wafer-to-wafer bonding structure), after which the system 200 may be separated from the bonded wafer. In some other embodiments, among many examples for forming the system 200, the wafer-to-wafer bonding technique may be implemented by stacking one or more wafers of dies 240 on a wafer of dies 205 (e.g., sequentially) before separating into the system 200.

[0043] Buses 221, 246, and 255 may be implemented to provide configuration signaling (e.g., tuning signaling, logic signaling, modulation signaling, digital signaling) between interface block 220 and the corresponding interface block 245, which may include various modulation or coding techniques by the transmitting interface block (e.g., via the driver component of the transmitting interface block). In some embodiments, such signaling may be supported by clock signaling communicated over each bus (e.g., in conjunction with signal transmission) (e.g., may be accompanied by clock signaling). For example, the bus may be configured to carry one or more clock signals transmitted by interface block 220 for reception by interface block 245 (e.g., to support the clock operation of interface block 245 in order to trigger signal reception by a latch or other receiving component of interface block 245). Additionally or alternatively, the bus may be configured to carry one or more clock signals transmitted by interface block 245 for reception by interface block 220 (e.g., to support the clock operation of interface block 220 in order to trigger signal reception by a latch or other receiving component of interface block 220). Such clock signals may be associated with various signaling communications (e.g., unidirectional, bidirectional, deterministic communications), such as control signaling, command signaling, data signaling, or any combination thereof. For example, the bus may include one or more signaling paths for data bus communications according to one or more corresponding clock signals (e.g., data clock signals) (e.g., one or more data channels, DQ bus, via the data interface of the interface block), or one or more signaling paths for control bus communications according to one or more clock signals (e.g., control clock signals) (e.g., command / address (C / A) bus, via the command interface of the interface block), or any combination thereof.

[0044] Interface block 220, interface block 245, logic block 225, and logic block 230 may each contain circuits (signal circuits, multiplexing circuits, processing circuits, controller circuits, logic circuits, physical components, hardware) in various configurations (e.g., hardware configuration, logic configuration, software configuration, or instruction configuration), and the circuits support functions assigned to each block to access or otherwise manipulate the corresponding set of memory arrays 250. For example, interface block 220 may contain circuits configured to perform a first subset of operations that support access to memory arrays 250, and interface block 245 may contain circuits configured to perform a second subset of operations that support access to memory arrays 250. In some embodiments, interface blocks 220, interface block 245, and logic block 225 may support functional partitioning or functional distribution with respect to functions associated with the memory system controller 155, local memory controller 165, or both, across multiple dies (e.g., die 205 and at least one die 240). In some embodiments, the logical block 230 may be configured to coordinate or configure the modes of operation of interface block 220, interface block 245, logical block 225, or combinations thereof, and may support implementations of one or more modes of the memory system controller 155. Such operations or subsets of operations may include operations performed in response to commands from the host processor 210 or controller 215, or operations performed without commands from the host processor 210 or controller 215 (e.g., operations determined or initiated by logical block 225, operations determined or initiated by interface block 220, operations determined or initiated by interface block 245, operations determined or initiated by logical block 230), or various combinations thereof.

[0045] In some embodiments, the system 200 may include one or more instances of non-volatile storage (e.g., non-volatile storage 235 on die 205, non-volatile storage 270 on one or more dies 240, or a combination thereof). In some embodiments, a logic block 230, a logic block 225, an interface block 220, an interface block 245, or a combination thereof may be configured to communicate signaling with one or more instances of non-volatile storage. For example, a logic block 230, a logic block 225, an interface block 220, or an interface block 245 may be coupled to one or more instances of non-volatile storage via one or more buses (not shown) or their respective contacts (not shown), where applicable, each of these buses and contacts may include one or more signal paths capable of communicating signaling (e.g., command signaling, data signaling). In some embodiments, the logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, may configure one or more operations based on information (e.g., instructions, configurations, parameters) stored in one or more instances of non-volatile storage. Additionally or alternatively, in some embodiments, the logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof, may write information (e.g., configuration information, evaluation information) to be stored in one or more instances of non-volatile storage. In some embodiments, such non-volatile storage may include fuses, antifuses, or other types of one-time programmable memory elements, or any combination thereof.

[0046] In some embodiments, the system 200 may include one or more sensors (e.g., one or more sensors 237 on die 205, one or more sensors 275 on one or more dies 240, or a combination thereof). In some embodiments, logic block 230, logic block 225, interface block 220, interface block 245, or a combination thereof may be configured to receive one or more instructions based on measurements from one or more sensors of the system 200. For example, logic block 230, logic block 225, interface block 220, or interface block 245 may be coupled to one or more sensors via one or more buses (not shown) or their respective contacts (not shown). Such sensors may include temperature sensors, current sensors, voltage sensors, counters, and other types of sensors. In some embodiments, logic block 230, one or more logic blocks 225, one or more interface blocks 220, one or more interface blocks 245, or a combination thereof may configure one or more operations based on the output of one or more sensors. For example, logic block 230 may configure one or more operations of logic block 225 or interface block 220 based on signaling (e.g., instructions, data) received from one or more sensors. Additionally or alternatively, logic block 225 or interface block 220 may generate access signaling for transmission to the corresponding interface block 245 based on one or more sensors.

[0047] In some embodiments, the logic block 225, interface block 220, interface block 245, or logic block 230, or any combination thereof, may include components (e.g., transistors) formed at least partially from the doped portion of the substrate of each die. In some embodiments, the substrate of die 205 may have different characteristics (e.g., material, material properties, physical shape, or dimensions) than the substrate of die 240. Additionally or alternatively, in some embodiments, transistors formed from the substrate of die 205 may have different characteristics (e.g., manufacturing characteristics, performance characteristics, physical shape, or dimensions) than transistors formed from the substrate of die 240 (e.g., according to a different transistor architecture, according to a different transistor design).

[0048] In some embodiments, interface block 220 may support the layout of one or more components within interface block 220. For example, the layout may include pairing components to share access ports (e.g., command ports, data ports). Furthermore, in some embodiments, the layout may support a controller 215 interface (e.g., host interface 216) that is different from the interface of interface block 245 (e.g., via bus 221). For example, the host interface 216 may be synchronous and have separate channels for read and write operations, while the interface between interface block 220 and one or more interface blocks 245 may be asynchronous and support both read and write operations on the same channel. In some embodiments, signaling of the host interface 216 may be performed with deterministic timing (e.g., determinism between controller 215 and logic block 225 or one or more interface blocks 220), and the deterministic timing may be associated with a configured timing between a first signal and a second responding signal. In some embodiments, signaling between interface block 220 and one or more interface blocks 245 may be performed at a timing that is deterministic or nondeterministic, different from the timing of the host interface 216 (for example, according to a timing offset such as a phase offset, according to a different clock frequency).

[0049] A die 240 may include one or more units 265 (e.g., modules) separated from a semiconductor wafer having a pattern (e.g., a two-dimensional pattern) of units 265. Each die 240 of the system 200 is shown with a single unit 265 (e.g., unit 265-a-1 of die 240-a-1, unit 265-a-2 of die 240-a-2), but a die 240 according to the technique of this description may include any number of units 265, which may be arranged in various patterns (e.g., among many patterns, a pattern in which one or more sets of units 265 are aligned in the row direction, a pattern in which one or more sets of units 265 are aligned in the column direction). Each unit 265 includes at least its own interface block 245 circuitry, which may include a memory array(s) 250, a bus 251, a bus 246, and one or more contacts 247 corresponding to its own interface block 245. In some embodiments, where applicable, each unit 265 may also include one or more buses 255, contacts 256, contacts 257, or contacts 260 (e.g., buses or contacts associated with the respective interface blocks 245 of each unit 265 on different dies 240), which may support varying degrees of stackability or modularity between or through units 265 on other dies 240. While examples of non-volatile storage 270 and sensors 275 are shown outside of unit 265, in some other embodiments, non-volatile storage 270, sensors 275, or both may be included in unit 265 additionally or alternatively.

[0050] In some embodiments, interface block 220 may include circuitry configured to receive a first access command signaling (e.g., from a host processor 210, from a controller 215, from a logic block 225, via a host interface 216, via one or more contacts 212 from a host processor 210 or controller 215 outside the die 205, based on a request from a host application), and to send a second access command signaling to each (e.g., coupled) interface block 245 based on the received first access command signaling (e.g., in response). Thus, interface block 245 may include circuitry configured to receive a second access command signaling from each interface block 220, and, in some embodiments, to access each set of one or more memory arrays 250 based on the received second access command signaling (e.g., in response). In various embodiments, the first access command signaling may include access commands associated with certain types of operations (e.g., read operations, write operations, refresh operations, memory management operations), and the access commands may be associated with instructions for addresses (e.g., logical addresses, physical addresses) of one or more memory arrays 250. In some embodiments, the first access command signaling may include instructions for logical addresses associated with the memory arrays 250, and the circuitry of the interface block 220 may be configured to generate a second access command signaling to indicate physical addresses associated with the memory arrays 250 (e.g., row addresses, column addresses, logical-to-physical (L2P) tables, or the use of other mapping or calculation functions of the interface block 220).

[0051] In some embodiments, to support write operations of system 200, the circuitry of interface block 220 may be configured to receive a first data signaling associated with a first access command signaling (e.g., from host processor 210, controller 215, logic block 225), and to transmit a second data signaling (e.g., a second data signaling associated with a second access command signaling) based on the received first access command signaling and first data signaling. Accordingly, interface block 245 may be configured to receive the second data signaling and to write data to one or more memory arrays 250 (e.g., according to the instruction address associated with the first access command signaling) based on the received second access command signaling and second data signaling. In some embodiments, the interface block 220 may include error control functions (e.g., error detection circuits, error correction circuits, error correction code (ECC) logic, ECC engine), which support the interface block 220 generating a second data signaling based on performing error control operations using a received first data signaling (e.g., detecting or correcting errors in the first data signaling, identifying one or more parity bits to be transmitted in the second data signaling and written with the data).

[0052] In some embodiments, to support read operations of system 200, the circuitry of interface block 245 may be configured to read data from memory array 250 based on a received second access command signaling, and to transmit a first data signaling based on the read data. Accordingly, interface block 220 may be configured to receive a first data signaling and to transmit a second data signaling based on the received first data signaling (e.g., to host processor 210, controller 215, logic block 225). In some embodiments, interface block 220 may include an error control function that supports interface block 220 generating a second data signaling based on performing an error control operation using the received first data signaling (e.g., detecting or correcting an error in the first data signaling, which may include a calculation with one or more parity bits received with the first data signaling).

[0053] In some embodiments, among the many signalings, access command signaling sent to interface block 245 may be generated according to various decision or generation techniques configured in interface block 220 or logical block 225 (for example, based on the access configuration to the memory array 250 modified in interface block 220 or logical block 225) (for example, based on access command signaling received from host processor 210, based on start signaling received from host processor 210, without receiving signaling from host processor 210, or independently of signaling from host processor 210). In some embodiments, such techniques may include signaling or other cooperation with logical block 230, logical block 225, host processor 210, one or more controllers 215, one or more instances of non-volatile storage, one or more sensors, or any combination thereof. Such techniques may support interface block 220 or logical block 225 configuring the modes of access operations that each interface block 245 performs with respect to the memory array 250, among the many operations. For example, interface block 220 or logic block 225 may include evaluation circuits, access configuration circuits, signaling circuits, scheduling circuits, repair circuits, refresh circuits, error control circuits, reverse access (e.g., low hammer) mitigation circuits, and other circuits that can operate to configure operations associated with one or more dies (e.g., operations associated with die 240's access to memory array 250).

[0054] According to embodiments disclosed herein, the functionality of die 205 may be implemented as a semiconductor unit (e.g., a semiconductor system) formed of a plurality of semiconductor die portions (e.g., semiconductor chiplets, relatively small semiconductor dies, KGDs), where each die portion may include a respective portion of a circuit associated with die 205. For example, unit 280 may represent a portion of a circuit component contained in a die portion (e.g., a chiplet), and the die portion may include an integer multiple of unit 280. In some embodiments, each semiconductor die portion of the semiconductor unit may include a different respective portion of a circuit. As a non-limiting example, a semiconductor unit (e.g., having the functionality of die 205) may be formed of one or more first die portions having one or more units 280-a-1 and one or more second die portions having one or more units 280-a-2. One or more units 280-a-1 may include one or more interface blocks 220, logic blocks 225, or any combination thereof, and one or more units 280-a-2 may include a host processor 210, one or more controllers 215, logic block 230, or any combination thereof. A non-limiting example of a unit 280 is shown, but each unit 280 may include any combination of components of the die 205, or other components. For example, unit 280-a-1 may further include logic block 230, or logic block 225 may be a different unit 280 (e.g., a different unit 280 of a different chiplet, a split HBM or 3D stacked memory These may be included in different units 280 in the embodiments. In some embodiments, each set of one or more dies 240 may be stacked on a corresponding die portion (e.g., a die portion having one or more units 280-a-1), and the corresponding die portion may include circuitry for operating (e.g., controlling) each set of one or more dies 240 (e.g., unit 280-a-1 may correspond to one or more units 265 of each die 240 in its set).

[0055] According to the techniques of this specification, the first die portion and the second die portion may be formed separately (e.g., having separate substrates and cut from different wafers), and may be coupled to each other (e.g., electrically and functionally) as part of the formation of a semiconductor unit (e.g., rather than forming the die 205 from the wafer as a single monolithic unit) during the manufacturing process (e.g., after the die portions have been established as KGDs according to semiconductor manufacturing techniques). In some embodiments, the first die portion may be coupled to the second die portion via one or more conducted signal paths, the conducted signal paths may be contained in one or more conductive layers of the RDL (e.g., on the first die portion and the second die portion). One or more conducted paths may be, or include, the host interface 216, bus 231, bus 232, bus 233, or other conducted signal paths described herein. In some embodiments, one or more conduction paths may be formed simultaneously with one or more other conductors (e.g., TSV, PDN TRV) along multiple (e.g., two or more) different depths as part of the semiconductor unit manufacturing process, such as by double damascene action, triple damascene action, or a combination thereof.

[0056] Figure 3 shows an example of an interface architecture 300 supporting semiconductor die coupling techniques in a stacked memory architecture according to embodiments disclosed herein. Interface architecture 300 shows an example in which interface block 245-b (e.g., of die 240) is coupled with interface block 220-b (e.g., of die 205). Interface block 245-b may be communicatively coupled with interface block 220-b via one or more of buses 301, 302, 303, and 304, each of which may be an example of one or more signal paths of buses 221 and 246, and bus 255, where applicable. Interface block 245-b may further be coupled with one or more buses 306 (e.g., power supply bus, PDN TRV, communication bus) which may directly supply power to components of interface block 245-b or memory array 250-b (or, for example, any other components of die 240).

[0057] Interface block 245-b includes a control interface 310 (e.g., a command interface), which may be configured to communicate signaling with interface block 220-b. For example, the control interface 310 may include circuitry (e.g., receivers, one or more latches) configured to receive control signaling (e.g., modulated control signaling, access command signaling, configuration signaling, address signaling such as row address signaling or column address signaling) via bus 301-a. The control interface 310 may also include circuitry configured to receive clock signaling (e.g., clock signaling associated with the control interface 310, clock signaling having one or more phases such as true phase and complementary phase, dk_t / c signaling from interface block 220-b) via bus 302-a, and the control interface 310 may use bus 302-a to receive control signaling from bus 301-a (e.g., to trigger one or more latches). The control interface 310 may transmit (e.g., forward) control signaling and clock signaling to the interface controller 320 (for example, for the timing of other operations of interface block 245-b).

[0058] Interface block 245-b also includes two data interfaces 330 (e.g., data interfaces 330-a-1 and 330-a-2), which may also be configured to communicate with interface block 220-b and signaling. Each data interface 330 may include a corresponding bus and circuitry, the operation of which may be associated with control signaling via the control interface 310 (e.g., controlled by control signaling, coordinated by control signaling, or based on control signaling). While the example of interface block 245-b includes two data interfaces 330 associated with the control interface 310 (e.g., in a “channel pair” configuration, in a “pseudo-channel pair” configuration), the techniques of this description relating to interface block 245 may include one or any number of data interfaces 330, as well as associated buses and circuitry, for a given control interface 310 of interface block 245.

[0059] Each data interface 330 may be associated with its own data path circuit, which may include its own first-in, first-out (FIFO) and serialization / deserialization (SERDES) circuit (e.g., FIFO / SERDES 340), its own write / sense circuit 350, its own synchronization and ordering circuit (e.g., synchronization / sequential logic 360), and its own timing circuit 370, along with an interconnecting signal path (e.g., one or more buses). However, in some other embodiments, the data path circuits may be arranged in different ways or include different circuit components, which may include circuits dedicated to each data path, circuits shared between data paths, or various combinations thereof. Each data interface 330 may also be associated with its own set of one or more memory arrays 250. In some embodiments, each memory array 250 may be understood to include its own addressing circuit, such as bank logic or decoders (e.g., row decoders, column decoders), or memory cell sense amplifier circuit, among many array circuits. However, in some other embodiments, at least a portion of such a circuit may be included in the interface block 245.

[0060] Each data interface 330 may include circuitry (e.g., one or more latches, one or more drivers) configured to communicate (e.g., receive, transmit) data signaling (e.g., modulated data signaling, DQ signaling) via its own bus 303. Each data interface 330 may also include circuitry for communicating clock signaling via its own bus 304, which may support clock signal reception by the data interface 330 (e.g., a first clock signaling associated with the data interface 330, a clock signaling having one or more phases such as true phase and complementary phase, a DQS_t / c signaling from interface block 220-b, a clock signaling associated with a data receive operation or a write operation), or clock signal transmission by the data interface 330 (e.g., a second clock signaling associated with the data interface 330, an RDQS_t / c signaling to interface block 220-b, a clock signaling associated with a data transmit operation or a read operation), or both. In some embodiments, a data interface 330, bus 303, or a combination of bus 303 and bus 304 may be associated with a “pseudochannel,” and multiple pseudochannels may be associated with the same control interface 310, or with the same control bus (e.g., bus 301, or a combination of bus 301 and bus 302). In some embodiments, pseudochannels of multiple interface blocks 245 may be grouped together (functionally, logically, or electrically, e.g., via hardwired signaling paths or multiplexing circuits) to support channel sets (e.g., channel sets associated with the corresponding host interface 216). Each data interface 330 may transmit clock signaling (e.g., received clock signaling, DQS_t / c signaling) to the synchronous / sequential logic 360 via its own bus (e.g., for the timing of other operations of interface block 245-b).

[0061] The interface controller 320 may support various functions of interface block 245-b for accessing or managing the operation of the coupled memory array 250 (e.g., control functions, configuration functions). For example, among many functions, the interface controller 320 may support the coordination or configuration of access commands, latency or timing compensation, buffering of access commands (e.g., according to a FIFO or other organization scheme), mode registers or logic for configuration settings, or test functions (e.g., evaluation functions, BIST functions), or a combination thereof. With respect to each data path of interface block 245 (e.g., each data path associated with its own data interface 330), the interface controller 320 may be configured to send signaling (e.g., address signaling such as row address signaling or row activation signaling) to the respective memory array 250 via the bus. With respect to each data path of the interface block 245, the interface controller 320 can communicate signaling (for example, timing signaling and control signaling that may be based on clock signaling received from the control interface 310) with its respective timing circuit 370 and synchronous / sequential logic 360 via its respective bus.

[0062] For each data path, each timing circuit 370 may support the timing of various operations (e.g., activation, coupling, signal latching, signal driving) associated with timing signaling received from the interface controller 320. For example, the timing circuit 370 may include a timing chain (e.g., a global column timing chain) configured to generate one or more clock signals or other start signals to control the operation of its respective data path, and such signaling may include offset, differently rated, or otherwise different transitions (e.g., rising edge transitions, falling edge transitions, on / off transitions) relative to the signaling transitions from the interface controller 320 to support a given operation or combination of operations. For example, the timing circuit 370 may be configured to send signaling (e.g., address signaling such as column address signaling or column activation signaling) to each memory array 250, to send signaling (e.g., timing signaling for latches or drivers) to each write / sense circuit 350, and to send signaling (e.g., timing signaling) to each synchronization / sequence logic.

[0063] For each data path, each FIFO / SERDES340 may be configured to perform a conversion between data signaling for a first bus width (e.g., a relatively wide bus width, a data read / write (DRW) bus, a bus for communication with a write / sense circuit 350 having a relatively large number of signal paths) and data signaling for a second bus width (e.g., a relatively narrow bus width, a bus for communication with a data interface 330 having a relatively small number of signal paths). In some embodiments, such a conversion may involve changing the signaling rate between the signaling from the data interface 330 and the signaling from the write / sense circuit 350 (e.g., to maintain a given throughput). In various embodiments, the FIFO / SERDES340 may receive data signaling from the data interface 330 and transmit data signaling to the write / sense circuit 350 (e.g., to support write operations), or it may receive data signaling from the sense circuit 350 and transmit data signaling to the data interface 330 (e.g., to support read operations). In some embodiments (e.g., to support read operations), the FIFO / SERDES340 may be configured to transmit clock signaling (e.g., RDQS_t / c signaling) to the data interface 330, and the clock signaling may be forwarded to interface block 220-b.

[0064] The timing or other synchronization of operations performed by the FIFO / SERDES340 may be supported by one or more clock signals received from each synchronous / sequential logic 360, among several signalings. For example, the synchronous / sequential logic 360 may generate or adjust clock signaling to support different rate signaling on different buses (e.g., based on received clock signaling). Additionally or alternatively, the FIFO / SERDES340 may operate in one direction (e.g., in the direction of sending data to the data interface 330, in the direction of receiving data from the data interface 330), or in other modes, based on the configuration signaling received from the synchronous / sequential logic 360.

[0065] For each data path, each write / sense circuit 350 may be configured to support access to its own set of one or more memory arrays 250 (e.g., data signaling, write signaling, read signaling). For example, a write / sense circuit 350 may be coupled to the memory arrays 250 via a bus (e.g., a global input / output (GIO) bus), the bus may include its own signal path associated with each memory array 250, or a signal path shared by all memory arrays 250 in the set, in which case the memory array circuit may include a multiplexing circuit that can operate to couple the bus with one of the selected memory arrays 250. In some embodiments, the bus between the write / sense circuit 350 and the set of one or more memory arrays 250 may include the same number of signal paths as the bus between the write / sense circuit 350 and the FIFO / SERDES 340 (e.g., a bus for signaling GIO[287:0]), or the same number of signal paths as the number of columns in each memory array 250. In some other embodiments, the memory array 250 may include a number of arrays that are integer multiples of the number of signal paths in the bus, in which case the memory array circuit (e.g., each memory array 250) may include a subset of arrays of memory cells or associated circuitry and a decoding circuitry that is capable of coupling the bus.

[0066] To support write operations, the write / sense circuit 350 may be configured to drive signaling that can operate to write one or more logic states to the memory cells of the memory array 250 (for example, based on received data, based on received timing signaling, based on data signaling received via bus 303, and based on control signaling received via bus 301-a). In some embodiments, such signaling may be transmitted to support circuits of the memory array 250 or to circuits otherwise associated with the memory array 250 (for example, as the output of signals corresponding to the logic state to be written), such circuits include, among many examples, sense amplifier circuits, voltage sources, current sources, or other driver circuits that can operate to apply a bias across the memory elements of the memory cell (for example, across capacitors, across ferroelectric capacitors) or to apply charge, current, or other signaling to the memory elements of the memory cell (for example, to apply current to chalcogenides or other configurable memory materials, or to apply charge to the gates of NAND memory cells).

[0067] To support read operations, the write / sense circuit 350 may be configured to receive signaling, and the write / sense circuit 350 may be further amplified for communication via interface block 245-b. For example, the write / sense circuit 350 may be configured to receive signaling corresponding to a logic state read from the memory array 250, which has a relatively low drive strength (e.g., relatively "analog" signaling, which may have a relatively low drive strength with the sense amplifier of the memory array 250). Thus, the write / sense circuit 350 may include further sense amplifiers (e.g., data sense amplifiers (DSAs) between the signal path between the write / sense circuit and a set of one or more memory arrays, and between the respective signal paths between the write / sense circuit and FIFO / SERDES), which may each have a relatively high drive strength (e.g., for driving relatively "digital" signaling).

[0068] To support semiconductor systems having multiple dies, as in various examples of system 200, the mechanisms of the interface architecture 300 can be replicated in various numbers and arrangements. In an exemplary embodiment, each die 240 may consist of 64 instances of interface block 245-b, thereby supporting a data signaling width of 9,216 signal paths per die 240 (for example, each bus 303 of a channel pair is associated with 72 signal paths). In the case of system 200 having a stack of eight dies 240 coupled with die 205, die 205 may thus consist of 512 instances of interface block 220-b, thereby supporting an overall data signaling width of 73,738 signal paths in system 200. However, in other embodiments, die 205 and die 240 may each consist of a different number of interface blocks 220 and 245, and system 200 may consist of a different number of dies 240 per die 205.

[0069] According to the techniques of this specification, a semiconductor unit (e.g., a logic unit, a semiconductor assembly) may be formed from a plurality of relatively small semiconductor dies (e.g., chiplets, logic chiplets). A relatively small semiconductor die may include one or more interface blocks 220-b. Thus, a set of memory dies (e.g., array dies) stacked on a die portion may include one or more interface blocks 245-b along with a plurality of memory arrays 250-b. In some embodiments, each of buses 301-a, bus 302-a, bus 303, and bus 304 may include, or are examples of, TSVs, bonding pads, conduction paths, or other mechanisms that support coupling between a die portion and a set of memory dies (e.g., between logic chiplets and a stack of memory dies). Furthermore, one or more buses 306 (e.g., PDN TRV) may bypass interface block 220-b (e.g., bypass die portions), which may enable more efficient power supply to a set of memory dies (e.g., compared to power supply via interface block 220-b or other components of the logic die).

[0070] Figures 4A and 4B show examples of semiconductor components 400 and die assemblies 450 that support semiconductor die coupling techniques in a stacked memory architecture according to embodiments disclosed herein. In Figure 4A, semiconductor component 400-a (e.g., wafer, die group) may include a plurality of dies 405 (e.g., logic dies), each die 405 may include a plurality of components (e.g., subcomponents). For example, die 405 may include multiple parts of a circuit, such as an interface circuit, a memory controller circuit, a host controller circuit, and a host processor circuit, among many other examples. In some cases, die 405 may be an example of die 205, or may include die 205. Semiconductor component 400-a is shown to include four dies 405, but semiconductor component 400-a may include any number of dies 405.

[0071] As part of the manufacturing procedure, each die 405 may be evaluated to verify proper operation. Manufacturing yield may refer to the number or percentage of dies 405 that meet the evaluation (e.g., the number of "good" dies). For example, the evaluation procedure may determine whether a die 405 contains a fault 415 (e.g., a defect, error) that causes the die 405 to operate improperly. If a die 405 is found to contain a fault 415, the die 405 may be rejected (e.g., discarded). A relatively large die (e.g., die 405) may be more likely to be rejected than a relatively small die. For example, if a fault 415 is found in at least one part of the circuit of die 405, the entire die 405 may be rejected. Therefore, semiconductor component 400-a may have a relatively low yield (e.g., because each die 405 contains a fault 415).

[0072] To improve the manufacturing yield (e.g., wafer yield) of the semiconductor component 400, it may be desirable to manufacture (e.g., fabricate) relatively small portions of the die 405 (e.g., smaller dies that can be separated as individual parts of the die 405, or different parts of the die 405's circuitry separately). For example, the semiconductor component 400-b may include multiple dies 410 (e.g., chiplets, die portions), and each die 410 may be smaller than the die 405. Each die 410 may include its own portion (e.g., a subset, a portion that does not include all of the circuitry) of the die 405, and the complexity may be reduced compared to the die 405. Since the dies 410 may be individually separable, rather than the entire die 405 being rejected, relatively small dies 410 may be rejected (e.g., a faulty 415 can be separated into a relatively small portion of the die), thus improving the overall manufacturing yield (e.g., good-quality dies 410). In the illustrated embodiment, semiconductor components 400-a and 400-b may contain faults 415 in multiple identical portions of the circuit. A fault 415 in semiconductor component 400-a may cause each of the dies 405 (e.g., the entire semiconductor component 400-a) to be rejected (e.g., even if semiconductor component 400-a contains several good die portions). In contrast, the same fault 415 in semiconductor component 400-b may cause only a portion of die 410 to be rejected (e.g., die 410-a), while the other die may be acceptable (e.g., die 410-b). For example, die 410-b may be accepted on the basis of satisfying an evaluation procedure (e.g., evaluating the circuit or functionality of die 410-b) (e.g., a KGD example).

[0073] According to the embodiments described herein, to improve the manufacturing yield of semiconductor circuits, a die assembly 450 having one or more semiconductor units 420 may be formed by interconnecting relatively small dies 410 (e.g., chiplets, logic chiplets, relatively small semiconductor dies) and may otherwise support the functions of a relatively large die 405. For example, multiple dies 410 may be coupled with conductive wires 425 (e.g., via RDL) to form a semiconductor unit 420 (e.g., a unit having the functions of die 205, die 405, or other dies). In some embodiments, each die 410 may be fabricated from a different wafer or from the same wafer. In some embodiments, the semiconductor unit 420 may be functionally equivalent to die 405. The gaps between the dies 410 may be filled with one or more dielectric materials 435 (e.g., silicon oxide gap fillers) which separate each die 410 (e.g., separate the substrates of the dies 410). In some embodiments, different dies 410 may use different manufacturing techniques (e.g., different techniques for transistor formation). For example, a first manufacturing technique (e.g., memory manufacturing flow) may be used to fabricate the transistor (e.g., FinFET, planar transistor) of die 410-c (e.g., for interface block 220), and a second manufacturing technique (e.g., logic manufacturing flow, casting process) may be used to fabricate the transistor (e.g., FinFET, all-around gate transistor) of die 410-d (e.g., for host processor 210, for controller 215). Furthermore, different manufacturing techniques may involve sourcing each die 410 from different wafers, from different manufacturers, or both. In some embodiments, multiple dies 410 may be formed as part of a reconstructed KGD wafer (e.g., a KGD wafer assembly) together with conductive wires 425, dielectric material 435, and any other circuits (e.g., TRV), and the reconstructed KGD wafer may be of various sizes (e.g., 200 mm, 300 mm, or other sizes).

[0074] Figures 5 to 12 show a semiconductor system 500 (e.g., a semiconductor system of heterogeneous devices, heterogeneous dies, heterogeneous HBM systems, heterogeneous) utilizing semiconductor die coupling techniques in a stacked memory architecture according to an embodiment disclosed herein. 3D stacked memory Examples of operations for forming a system are shown. For example, Figures 5 to 12 may show a set of operations that can support the manufacture of system 100 or a part of system 100, system 200 (e.g., units supporting the functions of die 205, die 405), die assembly 450, and any other devices of this specification, such a set of operations may increase the device yield during manufacture and improve the power supply to the stacked memory die. Each of the figures may be described with reference to the x, y, and z directions of coordinate system 501. The operations shown in and described with reference to Figures 5 to 12 may be performed by a manufacturing system such as a semiconductor fabrication system configured to perform additional operations (e.g., deposition, epitaxy, bonding), removal operations (e.g., etching, trenching, planarization, polishing), modification operations (e.g., oxidation, doping, reaction, transformation), and support operations (e.g., masking, patterning, photolithography, aligning), among many operations that support the techniques described.

[0075] Figure 5 shows a portion of the semiconductor system 500 after a first set of one or more manufacturing operations has been performed. For example, the semiconductor system 500 may include dies 410-e-1 and 410-e-2 (e.g., KGD, which may be different KGDs), which can be bonded to a carrier 505.

[0076] The carrier 505 (e.g., a sacrificial silicon carrier) may include one or more material levels, such as a substrate 510 (e.g., a carrier substrate, a wafer substrate) and a bonding layer 515. The carrier 505 may provide a surface for bonding (e.g., mounting) multiple dies 410-e and may provide structural support for a semiconductor unit. Each die 410-e may include material levels such as a substrate 535 (e.g., a semiconductor substrate, a crystalline substrate) and a bonding layer 520. Although two dies 410-e are shown, any number of dies 410-e may be formed on the carrier 505 (e.g., they may be arranged along the x-direction, or along the y-direction). Each die 410-e may be an example of a die 410 (e.g., a semiconductor die, a chiplet, or a part of a semiconductor unit).

[0077] The bonding layer 515 may include one or more alignment mechanisms 545 (e.g., alignment marks, reference marks), such as alignment mechanisms 545-a-1, 545-a-3, 545-a-5, and 545-a-6. The alignment mechanisms 545 may contain a material different from the other materials of the bonding layer 515, thereby enabling visualization of proper alignment between the carrier 505 and one or more dies 410-e, or between them. In some embodiments, the alignment mechanisms 545 may contain a conductive material, which may or may not support electrical coupling (e.g., alignment mechanisms 545-a-1 and 545-a-6 may support electrical coupling, while alignment mechanisms 545-a-2, 545-a-3, 545-a-4, and 545-a-5 may not).

[0078] A first set of manufacturing operations may include bonding semiconductor dies 410-e to carrier 505 (e.g., in chip-to-wafer bonding, in face-to-face bonding). Each die 410-e may include its own circuitry 525, which includes the portion of circuitry associated with the semiconductor unit (e.g., the respective portions of the function associated with die 205 or die 405), and each circuitry 525 may have been evaluated as having acceptable performance prior to bonding in the first set of operations. In some embodiments, at least some instances of circuit 525 may each include memory interface circuits (e.g., interface block 220, interface block 245, logic block 225), memory controller circuits (e.g., logic block 230, controller 215), host controller circuits, host processor circuits (e.g., host processor 210), sensor circuits (e.g., sensor 237, sensor 275), storage circuits (e.g., memory array 250, non-volatile storage 235, non-volatile storage 270), other circuits (e.g., graphics circuits, peripheral circuits), or any combination thereof. In some embodiments, circuit 525 on one die 410 may be different from circuit 525 on another die 410 (e.g., heterogeneous chiplet configurations), or it may be the same circuit. Among the many examples of differentiation between dies 410, for example, circuit 525-a-1 may include a memory interface circuit, and circuit 525-a-2 may include a host processor circuit. In some embodiments, circuit 525-a may include circuits associated with one or more units 280-a-1, but may not include at least some of the circuits associated with one or more units 280-a-2 (for example, as in the HBM embodiment, the host system 105 or host processor 210 may be coupled separately). In some other embodiments, circuit 525-a may not include circuits associated with one or more units 280-a-1 (for example, one or more units 280-a-1 may be coupled separately), but may include circuits associated with one or more units 280-a-2 (for example, the host processor 210 and the controller 215).In some embodiments, at least a portion of the circuit 525 (e.g., one or more transistors, complementary metal-oxide-semiconductor (CMOS) circuits of the circuit 525) may be formed from a portion of the substrate 535 of the die 410-e (e.g., a doped portion of the substrate 535, a doped semiconductor material, a doped crystalline semiconductor). In some embodiments, one or more instances of the circuit 525 may include a front-end (FEOL) circuit (e.g., a transistor circuit), a back-end (BEOL) circuit (e.g., an interconnect circuit, one or more conduction paths formed on top of the transistor circuit), or both.

[0079] Each die 410-e may include a bonding layer 520, which may be located on the opposite side of the die 410-e from the substrate 535 (e.g., along the z-direction). Multiple dies 410-e may overlap at least partially along the direction from the carrier (e.g., along the z-direction, along the thickness dimension). Bonding the dies 410-e may involve bonding the front surface of the die 410-e on the side of the die 410-e from the substrate 535 (e.g., the front side of the die 410-e) to the front surface of the carrier 505 on the side of the carrier 505 from the substrate 510 (e.g., the front side of the carrier 505). The dies 410-e and the carrier 505 may be bonded according to face-to-face bonding (e.g., chip-to-wafer front-to-front fusion bonding), which may be fusion bonding of one or more materials of the bonding layer 520-a and one or more materials of the bonding layer 515 of the carrier 505. In some embodiments, bonding multiple semiconductor dies 410-e to a carrier 505 may be based on an alignment mechanism 545 for the carrier 505, an alignment mechanism 545 for the die 410-e (e.g., alignment mechanisms 545-a-2, 545-a-4, etc., included in the bonding layer 520-a), or both. In some embodiments, bonding the die 410-e to the carrier 505 may provide a mechanical bond between the die 410 and the carrier 505 without any associated electrical coupling.

[0080] Figure 6 shows a portion of the semiconductor system 500 after a second set of one or more manufacturing operations has been performed. For example, the second set of operations may include removing a portion of material from at least one die 410-e (e.g., die 410-e-1, die 410-e-2) after bonding multiple dies 410-e to a carrier 505. For example, at least a portion of the substrate 535 of the die 410-e may be removed by chemical mechanical planarization (CMP) techniques, or by other techniques such as thinning, grinding, cutting, polishing, planarization, or etching. By removing a portion of the material (e.g., excess silicon, excess substrate 535), the size of the die 410-e may be reduced from a first thickness to a second thickness (e.g., along the z-direction in a silicon thinning operation). In some embodiments, the second set of manufacturing operations may be optional and may not be performed as part of the manufacturing process (e.g., there may be no excess material to remove from the die 410-e).

[0081] Figure 7 shows a portion of the semiconductor system 500 after a third set of one or more manufacturing operations has been performed. For example, the third set of operations may include forming one or more dielectric materials 705 (e.g., silicon oxide substrate material, gap-filling material, oxide, nitride, carbide, oxynitride, oxycarbide, other converted or doped, or any other dielectric material). In some embodiments, one or more dielectric materials 705 may be formed between a plurality of dies 410-e, at least along the carriers 505. One or more dielectric materials 705 may separate each substrate 535 of the die 410-e (e.g., each chiplet). For example, one or more dielectric materials 705 may separate substrate 535-a-1 of die 410-e-1 from substrate 535-a-2 of die 410-e-2. Therefore, at least prior to the subsequent interconnection operation, each die 410-e may be electrically isolated from other dies 410-e by one or more dielectric materials 705 (for example, each die 410-e may be isolated by one or more dielectric materials 705 on each face other than the face bonded to the carrier 505). The one or more dielectric materials 705 may also provide structural support for various components of the semiconductor system 500.

[0082] Figure 8 shows a portion of the semiconductor system 500 after a fourth set of one or more manufacturing operations has been performed. For example, the fourth set of operations may include removing portions of one or more dielectric materials 705 (e.g., in some embodiments, removing excess material along with at least some dielectric material remaining on the die 410-e). For example, at least a portion of one or more dielectric materials 705 on the die 410-e (e.g., along the z direction) may be removed after forming one or more dielectric materials along at least the carriers 505. In some embodiments, removing portions of one or more dielectric materials 705 may include CMP (e.g., as silicon oxide CMP).

[0083] Figure 9 shows a portion of the semiconductor system 500 after one or more fifth sets of manufacturing operations have been performed. For example, the fifth set of operations may include forming conduction paths 906 (e.g., forming at least a portion of the RDL, forming a conduction signal path, forming at least partially the conduction path 906 on the back side of the die 410-e, forming conduction paths along various directions in the xy plane), which may include forming one or more first cavities to a first depth (e.g., from the surface of one or more dielectric materials 705, along the z direction) through one or more dielectric materials 705. In some embodiments, each of the conduction paths 906 may be in contact with at least two dies 410-e (e.g., via vias 910-a-3 and 910-a-4) (e.g., may provide electrical coupling between at least two dies 410-e).

[0084] A fifth set of operations may also include forming one or more vias 910 (e.g., TSV, forming vias 910 on the back of die 410-e, forming vias 910 through substrate 535), which may include forming one or more second cavities to a second depth through at least one or more dielectric materials 705, each second cavity may also penetrate at least a portion of die 410-e (e.g., may contact circuit 525-a, or expose a portion of circuit 525-a). In some embodiments, one or more vias 910 may support an interface between die 410-e and at least one of one or more other sets of semiconductor dies (e.g., memory dies, a stack of dies 240), and may be a TSV based on being formed at least through substrate 535. Additionally or alternatively, one or more vias 910 may provide an interface between die 410-e and at least one other die 410-e. For example, based on vias 910-a-3 penetrating substrate 535-a-1 and vias 910-a-4 penetrating substrate 535-a-2, the circuit 525-a-1 of die 410-e-1 and the circuit 525-a-2 of die 410-e-2 can be coupled (for example, electrically coupled, can be communicatively coupled).

[0085] A fifth set of operations may also include forming one or more vias 915 (e.g., TV, PDN TRV, bypass vias), which may include forming one or more third cavities to a third depth through at least one or more dielectric material 705. Each third cavity may be formed between a plurality of dies 410-e, alongside a plurality of dies 410-e, or otherwise bypassing a plurality of dies 410-e (e.g., along the x-direction, along the y-direction, or along both directions), and may be in contact with the carrier 505 (e.g., may be filled with conductive material in contact with the alignment mechanism 545-a, or otherwise in contact with the carrier 505, or may penetrate through to reach the carrier 505). The vias 915 may be formed through layers 905 (e.g., logic layers, layers containing logic chiplets). The via 915 may bypass die 410-e and provide an interface (for example, may be later coupled) between a set of one or more other semiconductor dies (e.g., die 240) located on top of layer 905 and the surface of one or more dielectric materials 705 on the opposite side of the set of one or more other semiconductor dies.

[0086] Forming conduction pathways 906, vias 910, and vias 915 may involve simultaneously or sequentially filling one or more first cavities, one or more second cavities, and one or more third cavities with one or more conductive materials (e.g., according to a simultaneous damascene process, a triple damascene process, or a backside triple damascene process). Thus, in some embodiments, conduction pathways 906, vias 910, and vias 915 may be referred to as, or included in, a backside triple damascene RDL. Forming a semiconductor unit 920 may be based on filling a plurality of conduction pathways 906, one or more vias 910, and, in some embodiments, one or more vias 915, with one or more conductive materials (e.g., a single conductive material, a conductive liner material, and a conductive filler material). For example, based on the formation of conduction paths 906, each of the multiple dies 410-e can be electrically coupled (e.g., connected) to at least one other die 410-e via RDL (e.g., via an RDL that may contain multiple conduction paths 906) (e.g., die 410-e-1 can be electrically coupled to die 410-e-2). That is, electrically connecting the dies 410-e can be based on forming an RDL containing multiple conduction paths 906 on the dies 410-e. Forming a semiconductor unit 920 can be based on coupling each of the multiple dies 410-e to at least one other die 410-e. The semiconductor unit 920 may be an example of an implementation of the function of die 205, die 405, logic die, or some other die.

[0087] Figure 10 shows a portion of the semiconductor system 500 after one or more sets of manufacturing operations have been performed. For example, the sixth set of operations may include forming a layer 1005 (e.g., at least a portion of the RDL), which may include one or more dielectric materials 1010 and one or more conductive pads 1015 (e.g., bonding pads) on top of the die 410-e. In some embodiments, the layer 1005 may also include conductive paths between the conductive pads 1015 (e.g., signal paths of the RDL along various directions in the xy plane, though not shown), providing electrical coupling between vias 910, vias 915, or combinations thereof. In some embodiments, each conductive pad 1015 may couple one or more other semiconductor dies (e.g., die 240) stacked on top of layer 1005 with PDNs (e.g., via carrier 505, via 915, and PDN TRV), via 910 of die 410-e, RDLs on die 410-e (e.g., conduction path 906), or any combination thereof (e.g., may enable such coupling). A sixth set of manufacturing operations may also include forming one or more pads 1020 (e.g., redundant pads, dummy pads, conductive pads) that can be used for purposes other than the electrical coupling of components (e.g., as alignment mechanisms). In some embodiments, at least some of the conductive pads 1015 may implement the function of contacts 222. In some embodiments, forming the conductive pads 1015 and 1020 together with the corresponding vias (e.g., vias penetrating layer 1005 to bond with layer 905) and signal paths in layer 1005 may be based on simultaneously filling the cavity with one or more conductive materials (e.g., according to a simultaneous damascene process, a double damascene process, or a back-side double damascene process). Thus, in some embodiments, the conductive pads 1015, 1020, and the corresponding signal paths and vias in layer 1005 may be referred to as a back-side double damascene RDL, or comprised of a back-side double damascene RDL, which may correspond to a back-side double damascene process RDL formed on top of a triple damascene process RDL associated with a fifth set of operations (e.g., a set of operations for the device of a heterogeneous die 410-e).

[0088] Figure 11 shows a portion of the semiconductor system 500 after one or more seventh sets of manufacturing operations have been performed. For example, the seventh set of operations may include forming layers 1105 (e.g., including dies 240, memory dies, array dies) on top of carriers 505, layers 905, and layers 1005 (e.g., lamination, assembly, bonding). Components of the semiconductor system 500 may include various layers and materials, such as bonding layer 1115, bonding layer 1120, one or more dielectric materials 1130 (e.g., silicon oxide), substrate 1135 (e.g., silicon substrate), and one or more conductive materials 1140 (e.g., copper, aluminum, or any other material).

[0089] In some embodiments, forming layer 1105 may involve bonding (e.g., bonding) one or more sets of dies 1145-a (e.g., a stack) onto at least one of the dies 410-e (e.g., with at least one of the dies 410-e) (e.g., via one or more RDLs, via layer 1005), where each die in the set of dies 1145-a may include circuits 1125-a, such as memory circuits (e.g., multiple memory arrays, memory array 250), interface circuits (e.g., interface block 245, or components of interface block 245), or other circuits (e.g., non-volatile storage 270, sensor 275, or other circuits associated with other circuits). In some embodiments, a die 1145 or a stack of dies 1145 may be bonded separately to at least one of the dies 410-e as their respective sets. In some other embodiments, multiple dies 1145 (e.g., multiple dies 1145 in a layer of dies 1145) or a stack of dies 1145 may be in a continuous state (e.g., as part of a wafer or other semiconductor component, as part of a stack of a wafer or other semiconductor component) or may be mechanically connected in a different way (e.g., along the x-direction, along the y-direction, though not shown), which may involve separation into later semiconductor units (e.g., singulation). In some other such embodiments, a die 1145 may be part of a reconstructed wafer or other reconstructed semiconductor component of a die 1145 (e.g., a good-quality die 1145), in which case such reconstruction may involve coupling a singulated die 1145 or a separate die 1145 in a different way with a carrier (e.g., similar to coupling a die 410 with a carrier 505, though not shown).Therefore, in some embodiments, the wafer of die 1145, or a reconstructed wafer of die 1145, may be bonded (e.g., bonded) to a semiconductor unit 920 that is at least partially formed from the bonded die 410 (for example, an RDL between the reconstructed wafer of die 1145 and the reconstructed wafer of die 410, where the RDL provides at least a portion of such bonding).

[0090] Circuit 1125-a may include FEOL circuits (e.g., transistor circuits, circuits formed at least partially from the doped portion of substrate 1135) and BEOL circuits (e.g., interconnection circuits). Each instance of circuit 1125-a may be operable via one or more interconnection regions 1150-a based on instances of circuit 525-a of die 410-e to which each set is bonded. In some embodiments, interconnection regions 1150-a may include components or circuits that couple circuit 1125 with other circuits 1125 of each die 1145-a (e.g., couple between circuit 1125-a-1 and circuit 1125-a-2), couple circuit 1125 with conduction pad 1110, or couple circuit 1125 with conduction pad 1112, or couple various combinations thereof (e.g., TSV, bonding pads, BEOL circuits).

[0091] In some embodiments, bonding one die 1145-a to another die 1145-a may include bonding one or more conductive pads 1110-a to one or more conductive pads 1112-a. For example, among many examples, conductive pad 1110-a may be an embodiment of contact 247 or contact 256, and conductive pad 1112-a may be an embodiment of contact 257 or contact 260. In some embodiments, conductive pad 1112-a of the first die 1145-a (e.g., conductive pad 1112-a-1) may be bonded (e.g., fused) with conductive pad 1110-a of the second die 1145-a (e.g., conductive pad 1110-a-3), which includes using an embodiment of hybrid bonding (e.g., wafer-to-wafer or die-to-die front-to-back hybrid bonding). In some embodiments, such bonding may involve bonding of each dielectric portion (e.g., surface) of the die 1145-a, such as the fusion of dielectric material 242. In some embodiments, material 1160 (e.g., additional silicon, additional substrate material) may be formed or placed on top of the semiconductor system 500 and bonded to the die 1145-a at the top of the stack of die 1145-a, which includes using an embodiment of fusion bonding (e.g., wafer-to-wafer front-to-back fusion bonding).

[0092] In some embodiments, bonding one or more sets of dies 1145-a to die 410-e may be based on one or more conductive pads 1110-a in each set of dies 1145-a and one or more conductive pads 1015-a in die 410-e. For example, by a hybrid bonding embodiment (e.g., stack-to-wafer front-to-back hybrid bonding), a set of dies 1145-a may be bonded to die 410-e. An interconnection region 1150-a may be coupled with conductive pads 1110-a to provide a communication interface between die 410-e and die 1145-a. In some embodiments, the interconnection region 1150-a may implement the functions of buses 255, 246, 251, 301, 302, 303, 304, or a combination thereof. For example, one or more conductive pads 1110-a (e.g., conductive pad 1110-a-2) may be bonded by vias 910 (e.g., TSV), one or more conductive paths 906 (e.g., RDL), or both, which can penetrate the substrate 535-a of the die 410-e to which each set of dies 1145-a is bonded. The vias 910 and conductive paths 906 may provide interfaces between each set of dies 1145-a and the die 410-e. In some embodiments, one or more conductive pads 1110-a (e.g., conductive pad 1110-a-1) may be bonded with vias 915 (e.g., PDN TRV), which may provide interfaces that bypass the die 410-e and penetrate layer 905. In some embodiments, bonding one or more sets of dies 1145-a to die 410-e may be based on the fusion between the respective conductive portions and the fusion between the respective dielectric portions (e.g., surface-to-wafer bonding, front-to-back bonding, hybrid bonding of both dielectric and conductive materials). In some embodiments, at least some, but not all, of the dies 1145-a may be able to satisfy evaluations (e.g., operational evaluations) (e.g., can be verified to satisfy them) before bonding one or more sets of dies 1145-a to die 410-e.

[0093] Figure 12 shows a portion of the semiconductor system 500 after one or more eighth sets of manufacturing operations have been performed. For example, the eighth set of operations may include forming one or more contacts 1205 (e.g., electrical contacts, solder balls, microbumps, controller collapse chip connect (C4) bumps) to one or more depths (e.g., along the z-direction) relative to the carrier 505. Forming the contacts 1205 may include forming cavities through at least a portion of the carrier 505. In some embodiments, forming one or more contacts 1205-a (e.g., with respect to each of the die 410-e) may be based on forming cavities through at least a portion of the carrier and at least a portion of the die 410-e, and forming one or more conductive materials in each of the cavities. Forming the contacts 1205 may involve forming at least several contacts 1205 (e.g., contacts 1205-a-2 and 1205-a-3) on the surface of the semiconductor system 500 (e.g., on the surface of the carrier 505 opposite to the multiple dies 410-e) and coupling them to the circuit 525 of the die 410-e. In some embodiments, one or more contacts 1205 (e.g., contacts 1205-a-1 and 1205-a-4) may be formed on the surface of the semiconductor system 500 and coupled to at least one set of one or more dies 1145-a, which may bypass the die 410-e. For example, vias 915 may provide an interface between a set of dies 1145-a and the surface of a semiconductor unit opposite to each set of dies 1145-a (e.g., the surface of layer 905) via the contacts 1205. In some embodiments, the semiconductor system 500 may include a combination of one or more first contacts 1205 (e.g., contact 1205-a-1) that can be coupled to one or more vias 915 (e.g., PDN TRV) and one or more second contacts 1205 (e.g., contact 1205-a-2) that can be coupled to one or more dies 410-e (e.g., pads of logic chiplets), which may have different depths along the z-direction.Based on the formation of one or more contacts 1205, the semiconductor system 500 may be able to be coupled in a communicative manner with other components (e.g., a GPU or other peripheral components).

[0094] After the eighth set of manufacturing operations, the semiconductor system 500 may be ready for packaging at any time, which may include separating (e.g., dicing) multiple semiconductor units 920 on the same carrier 505 from one another. According to the techniques described with reference to Figures 5 to 12, the semiconductor system 500 may include multiple dies 410-e (e.g., chiplets, logic chiplets, logic dies, semiconductor dies, die portions) which are electrically coupled via conduction paths 906 (e.g., included in RDL) to form one or more semiconductor units 920 (e.g., semiconductor units 920 associated with the function of a logic die, die 205, or die 405). The semiconductor system 500 may further include one or more sets of dies 1145-a (e.g., a stack of dies 240, semiconductor dies, array dies, DRAM dies, and memory dies), which may be bonded to each die 410-e (e.g., die 410-e of each semiconductor unit 920) via one or more bonding pads 1015-a (e.g., within layer 1005) and one or more vias 910 (e.g., TSVs). For example, layer 905 (e.g., a lower die in a stack) may be associated with one or more units 280, and layer 1105 may be associated with one or more dies 240. One or more sets of dies 1145-a may also be bonded to one or more vias 915 (e.g., PDN TRVs), which may provide an interface to the set of dies 1145-a (e.g., a power supply interface) on the surface of the semiconductor system 500 (e.g., via contacts 1205-a).

[0095] By utilizing one or more techniques described herein, components of the semiconductor system 500 (e.g., HBM devices, 3D stacked memoryIncreased manufacturing yield of wafers associated with the device can be supported. For example, the technique herein enables the manufacturing and evaluation of relatively small semiconductor dies (e.g., die 410) that can be separated separately, and enables the reconstruction of a relatively large semiconductor unit (e.g., a semiconductor unit implementing the functions of die 205 or die 405) using multiple relatively small dies (e.g., using die 410 that satisfy evaluation). Furthermore, the technique described herein may enable direct power supply to one or more stacked memory dies (e.g., die 1145-a, die 240) with low resistance, based on the fact that one or more vias 915 can bypass die 410-e to support more efficient use of die area. Thus, the manufacturing of the semiconductor system 500 may be accompanied by increased yield, and the semiconductor system 500 may operate with improved efficiency. Although some of the techniques described herein are explained in the context of memory systems, the techniques described herein may also be implemented in other semiconductor systems that implement heterogeneous semiconductor components (e.g., dies associated with different functions, including different logic functions, different storage functions, or processing functions, or any combination thereof), including heterogeneous semiconductor components interconnected within layers, between layers, or in any combination thereof.

[0096] Figure 13 shows a flowchart illustrating Method 1300, which supports semiconductor die coupling techniques in stacked memory architectures, according to embodiments disclosed herein. The operation of Method 1300 may be carried out by a manufacturing system, or one or more controllers associated with a manufacturing system. In some embodiments, one or more controllers may execute a set of instructions for controlling one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using dedicated hardware.

[0097] In 1305, the method may include bonding a plurality of first semiconductor dies to a carrier, each of the first semiconductor dies comprising its own portion of the circuit of a semiconductor unit.

[0098] In 1310, the method may include forming a semiconductor unit based at least partially on bonding a plurality of first semiconductor dies to a carrier, and then electrically connecting each of the plurality of first semiconductor dies to at least one of the other first semiconductor dies.

[0099] In 1315, the method may include bonding one or more sets of second semiconductor dies to at least one of a plurality of first semiconductor dies, each of which second semiconductor dies in its set includes a memory array, the memory array being operable at least partially on its set of circuits of the semiconductor units of the first semiconductor die to which its set is bonded.

[0100] In some embodiments, the apparatus described herein (e.g., a manufacturing system) may perform methods such as method 1300. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., a non-temporary computer-readable medium storing instructions that can be executed by one or more controllers to control one or more functional elements of a manufacturing system), or any combination thereof, for performing the following embodiments of the disclosure.

[0101] Embodiment 1: Bonding a plurality of first semiconductor dies (e.g., die 410) to a carrier (e.g., carrier 505), wherein each of the first semiconductor dies includes its own portion of the circuit (e.g., circuit 525) of a semiconductor unit (e.g., semiconductor unit 920), and the bonding is performed. After bonding the plurality of first semiconductor dies to the carrier, the semiconductor unit is formed by at least partially electrically connecting each of the plurality of first semiconductor dies to at least one of the other first semiconductor dies. Bonding one or more sets of second semiconductor dies (e.g., die 240, die 1145) to at least one of the plurality of first semiconductor dies, wherein each of the sets of second semiconductor dies includes a memory array (e.g., at least one memory array 250 of circuit 1125), and the memory array is operable at least partially on the respective portion of the circuit of the semiconductor unit of the first semiconductor die to which the respective set is bonded. A method or apparatus including an action, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing a certain action.

[0102] Embodiment 2: The method or apparatus according to Embodiment 1, wherein, with respect to each of the first semiconductor dies, the respective portion of the circuit includes a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

[0103] Embodiment 3: The method or apparatus according to any one of Embodiments 1 to 2, wherein each first portion of the circuit of the first semiconductor die of the semiconductor unit is associated with a first logic function, and each second portion of the circuit of another first semiconductor die of the semiconductor unit is associated with a second logic function different from the first logic function.

[0104] Embodiment 4: The method or apparatus according to any one of Embodiments 1 to 3, wherein each of a first set of one or more second semiconductor dies and each of a second set of one or more second semiconductor dies are contained in a reconstructed wafer of the second semiconductor dies bonded to the semiconductor unit.

[0105] Embodiment 5: The method or apparatus of any embodiment 1 to 4, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing the forming, wherein the one or more dielectric materials separate each substrate (e.g., substrate 535) of the first semiconductor dies, the dielectric materials separating each substrate (e.g., substrate 535) of the first semiconductor dies.

[0106] Embodiment 6: Forming a plurality of first cavities through one or more dielectric materials to a first depth, wherein each of the first cavities is in contact with at least two of the first semiconductor dies, The method involves forming a plurality of second cavities through one or more dielectric materials to a second depth, wherein each of the second cavities penetrates at least a portion of each of the first semiconductor dies of the first semiconductor die. Forming a plurality of third cavities to a third depth through one or more dielectric materials, wherein each of the third cavities is located between the plurality of first semiconductor dies and is in contact with the carriers, The method involves simultaneously (for example, sequentially) forming one or more conductive materials within the plurality of first cavities, the plurality of second cavities, and the plurality of third cavities. The method or apparatus of embodiment 5, further comprising actions, mechanisms, circuits, logic, means, or instructions for performing, or any combination thereof.

[0107] Embodiment 7: The method or apparatus of Embodiment 6, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for performing the forming, wherein the one or more conduction pads, the one or more conduction paths, and the one or more vias are formed in one or more second dielectric materials (e.g., layers 1005) adjacent to one or more conductor materials (e.g., conduction paths 906), wherein the one or more conduction pads, the one or more conduction paths, and the one or more vias are formed, at least in part on the simultaneous formation of one or more second conductor materials in cavities associated with the one or more conduction pads, the one or more conduction paths, and the one or more vias.

[0108] Embodiment 8: The method or apparatus of any embodiment 1 to 7, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for removing a portion of the dielectric material on the plurality of first semiconductor dies after forming the dielectric material along at least the carrier.

[0109] Embodiment 9: The method or apparatus of any embodiment 1 to 8, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing the formation, wherein each of the one or more vias is coupled to one set of the one or more sets of second semiconductor dies, wherein the one or more vias are coupled to one set of the one or more sets of second semiconductor dies.

[0110] Embodiment 10: The method or apparatus according to Embodiment 9, wherein at least one of the one or more vias provides an interface (e.g., is part of an interface that supports an interface) between each set of the one or more second semiconductor dies and the surface of the semiconductor unit opposite to each set of the one or more second semiconductor dies.

[0111] Embodiment 11: The method or apparatus of any one of Embodiments 9 to 10, further comprising an operation, mechanism, circuit, logic, means, or instruction for forming one or more electrical contacts in each of the one or more vias, at least partially based on forming a cavity through at least a portion of the carrier and forming one or more conductive materials within the cavity.

[0112] Embodiment 12: The method or apparatus of any of Embodiments 1 to 11, wherein electrically connecting each of the plurality of first semiconductor dies is at least partially based on forming a plurality of conduction signal paths (e.g., conduction path 906) on the first semiconductor dies of the semiconductor unit.

[0113] Embodiment 13: The method or apparatus of Embodiment 12, further comprising operations, mechanisms, circuits, logic, means, or instructions, or any combination thereof, for verifying that each first semiconductor die of the plurality of first semiconductor dies and each set of the one or more second semiconductor dies satisfy operational evaluations before bonding each set of the one or more second semiconductor dies to at least one of the plurality of first semiconductor dies.

[0114] Embodiment 14: The method or apparatus of any of Embodiments 1 to 13, wherein bonding each set of the one or more second semiconductor dies to at least one of the plurality of first semiconductor dies is at least partially based on forming one or more vias (e.g., vias 910) through the substrate of the first semiconductor die to which each set is bonded.

[0115] Embodiment 15: The method or apparatus according to Embodiment 14, wherein each via provides an interface between each set of the one or more second semiconductor dies and the at least one first semiconductor die, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both of these interfaces.

[0116] Embodiment 16: The method or apparatus of any embodiment 1 to 15, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing the formation, wherein each of the plurality of conduction pads is formed on the plurality of first semiconductor dies, wherein each of the plurality of conduction pads is coupled via the carrier to the PDN, the TSV of the plurality of first semiconductor dies, the RDL on the plurality of first semiconductor dies, or any combination thereof.

[0117] Embodiment 17: The method or apparatus of any of Embodiments 1 to 16, wherein bonding each set of the one or more second semiconductor dies to at least one of the plurality of first semiconductor dies is at least partially based on fusion between the respective conductive portions and fusion between the respective dielectric portions.

[0118] Embodiment 18: The method or apparatus of any embodiment 1 to 17, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for forming one or more electrical contacts on each of the first semiconductor dies, at least partially based on forming a cavity through at least a portion of the carrier and forming one or more conductive materials within the cavity.

[0119] Embodiment 19: The method or apparatus according to any one of Embodiments 1 to 18, wherein bonding the plurality of first semiconductor dies to the carrier comprises, with respect to at least one first semiconductor die, bonding the face of the at least one semiconductor die opposite to the substrate of the at least one semiconductor die to the carrier.

[0120] Embodiment 20: The method or apparatus of any embodiment 1 to 19, further comprising an operation, mechanism, circuit, logic, means, or instruction, or any combination thereof, for removing a portion of material from at least one of the first semiconductor dies after bonding the plurality of first semiconductor dies to the carrier.

[0121] Embodiment 21: The method or apparatus according to any one of Embodiments 1 to 20, wherein the plurality of first semiconductor dies at least partially overlap along the direction from the carrier.

[0122] Embodiment 22: The method or apparatus according to any of Embodiments 1 to 21, wherein bonding the plurality of first semiconductor dies to the carrier is at least partially based on one or more alignment mechanisms (e.g., alignment mechanism 545) of the carrier.

[0123] Embodiment 23: The method or apparatus according to any of Embodiments 1 to 22, wherein bonding the plurality of first semiconductor dies to the carrier provides a mechanical bond between the plurality of first semiconductor dies and the carrier without any associated electrical coupling.

[0124] Figure 14 shows a flowchart illustrating Method 1400, which supports semiconductor die coupling techniques in stacked memory architectures, according to embodiments disclosed herein. The operation of Method 1400 may be carried out by a manufacturing system, or one or more controllers associated with a manufacturing system. In some embodiments, one or more controllers may execute a set of instructions for controlling one or more functional elements of the manufacturing system to perform the described functions. Additionally or alternatively, one or more controllers may perform aspects of the described functions using dedicated hardware.

[0125] In 1405, the method may include bonding a plurality of first semiconductor dies to a carrier, each first semiconductor die comprising its own portion of the circuit of a semiconductor unit of a semiconductor system.

[0126] In 1410, the method may include coupling each of a plurality of first semiconductor dies with at least one other first semiconductor die via an RDL including a plurality of conducted signal paths, wherein the semiconductor unit is formed of the coupled first semiconductor dies.

[0127] In 1415, the method may include forming a dielectric portion of a semiconductor unit comprising one or more dielectric materials between a plurality of first semiconductor dies.

[0128] In 1420, the method may include forming a plurality of vias between a plurality of first semiconductor dies that penetrate the dielectric portion.

[0129] In 1425, the method may include bonding at least one set of one or more second semiconductor dies to a semiconductor unit, each second semiconductor die comprising a memory array, the memory array being operable by one of the bonded first semiconductor dies, and the bonding at least partially comprises fusing a plurality of first bonding pads of the first semiconductor die with a plurality of second bonding pads of the at least one set of second semiconductor dies, and bonding a plurality of third bonding pads coupled with a plurality of vias with a plurality of fourth bonding pads of the at least one set of second semiconductor dies.

[0130] In some embodiments, the apparatus described herein (e.g., a manufacturing system) may perform methods such as method 1400. The apparatus may include mechanisms, circuits, logic, means, or instructions (e.g., a non-temporary computer-readable medium storing instructions that can be executed by one or more controllers to control one or more functional elements of a manufacturing system), or any combination thereof, for performing the following embodiments of the disclosure.

[0131] Embodiment 24: Bonding a plurality of first semiconductor dies to a carrier, wherein each first semiconductor die includes its own portion of the circuit of the semiconductor unit of the semiconductor system, The coupling involves coupling each of the plurality of first semiconductor dies with at least one other first semiconductor die via an RDL including a plurality of conducted signal paths, wherein the semiconductor unit is formed of the coupled first semiconductor dies, To form a dielectric portion of the semiconductor unit containing one or more dielectric materials between the plurality of first semiconductor dies, A plurality of vias are formed between the plurality of first semiconductor dies, penetrating the dielectric portion. Bonding at least one set of one or more second semiconductor dies to the semiconductor unit, each second semiconductor die including a memory array, the memory array being operable by one of the bonded first semiconductor dies, wherein the bonding is at least partially based on fusing a plurality of first bonding pads of the first semiconductor die with a plurality of second bonding pads of the at least one set of second semiconductor dies, and bonding a plurality of third bonding pads coupled with the plurality of vias with a plurality of fourth bonding pads of the at least one set of second semiconductor dies. A method or apparatus including an action, mechanism, circuit, logic, means, or instruction, or any combination thereof, for performing a certain action.

[0132] It should be noted that the methods described herein describe possible embodiments, and that the operations and steps may be rearranged or otherwise modified, and that other embodiments are also possible. Furthermore, two or more parts of the methods may be combined.

[0133] The system is described. Below, an overview of the aspects of the system described herein is provided.

[0134] Embodiment 25: A carrier comprising one or more material levels, A plurality of first semiconductor dies bonded to the carrier, each first semiconductor die including its own substrate, each substrate being separated from the respective substrates of the other first semiconductor dies, each first semiconductor die including its own portion of the circuit of a semiconductor unit, each portion being electrically coupled to its respective portion of the circuit of the semiconductor unit of at least one other first semiconductor die, A set of at least one set of one or more second semiconductor dies, each set of one or more second semiconductor dies being electrically coupled to each of the plurality of first semiconductor dies, each second semiconductor die including one or more memory arrays, each of the memory arrays being operable at least partially on each of the first semiconductor dies to which the second semiconductor die is connected, A system that includes this.

[0135] Embodiment 26: The system according to Embodiment 25, wherein with respect to each of the first semiconductor dies, the respective portion of the circuit includes a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

[0136] Embodiment 27: The system according to any one of embodiments 25 to 26, further comprising a dielectric portion of one or more dielectric materials between each of the substrates of the plurality of first semiconductor dies.

[0137] Embodiment 28: The system according to Embodiment 27, further comprising one or more vias penetrating the dielectric portions between the plurality of first semiconductor dies, each of which is coupled to one set of the one or more sets of second semiconductor dies and bypasses the plurality of first semiconductor dies.

[0138] Embodiment 29: The system according to Embodiment 28, wherein at least one of the one or more vias provides an interface between one set of the one or more sets of second semiconductor dies and the surface of the semiconductor unit opposite to each of the one or more sets of second semiconductor dies.

[0139] Embodiment 30: A system according to any one of embodiments 25 to 29, further comprising an RDL including a plurality of conducted signal paths, wherein each first semiconductor die is electrically coupled to at least one other first semiconductor die via the RDL.

[0140] Embodiment 31: The system according to any one of embodiments 25 to 30, further comprising one or more vias formed through the substrate of at least one of the plurality of first semiconductor dies, each via providing an interface between at least one set of the set of one or more second semiconductor dies and each of the first semiconductor dies, an interface between the at least one first semiconductor die and at least one other first semiconductor die, or both of these interfaces.

[0141] Embodiment 32: The system according to any one of embodiments 25 to 31, further comprising a plurality of conductive pads on a plurality of first semiconductor dies, each of the plurality of conductive pads coupling each set of the one or more second semiconductor dies to a PDN, a TSV of the plurality of first semiconductor dies, an RDL on the plurality of first semiconductor dies, or any combination thereof, via the carriers.

[0142] Embodiment 33: One or more first electrical contacts present on the surface of the system and coupled to at least one of the plurality of first semiconductor dies, One or more second electrical contacts are present on the surface of the system and are coupled to at least one set of the one or more second semiconductor dies, and bypass the plurality of first semiconductor dies. The system according to any one of embodiments 25 to 32, further including the system described above.

[0143] The system is described. Below, an overview of the aspects of the system described herein is provided.

[0144] Embodiment 34: Bonding a plurality of first semiconductor dies to a carrier, wherein each of the first semiconductor dies includes its own portion of the circuit of a semiconductor unit, After bonding the plurality of first semiconductor dies to the carrier, the semiconductor unit is formed by at least partially electrically connecting each of the plurality of first semiconductor dies to at least one of the other first semiconductor dies. Bonding one or more sets of second semiconductor dies to at least one of the plurality of first semiconductor dies, wherein each of the sets of second semiconductor dies includes a memory array, and the memory array is operable at least partially on the respective portion of the circuit of the semiconductor unit of the first semiconductor die to which the respective set is bonded. A system formed by the process of executing a certain action.

[0145] The system is described. Below, an overview of the aspects of the system described herein is provided.

[0146] Embodiment 35: A system comprising a plurality of first semiconductor dies, wherein the plurality of first semiconductor dies are electrically coupled to form a semiconductor unit of the system, and the system further comprises A dielectric material for separating each substrate associated with each of the plurality of first semiconductor dies, RDL including a plurality of conduction paths, wherein the plurality of conduction paths electrically connect each of the plurality of first semiconductor dies to at least one other first semiconductor die, A set of one or more second semiconductor dies, each of which includes a plurality of memory arrays, Each set of the second semiconductor die is bonded to one or more bonding pads that connect to each of the first semiconductor dies among the plurality of first semiconductor dies, Between the plurality of first semiconductor dies, a plurality of vias penetrating the dielectric material, each of the plurality of vias is coupled to at least one set of second semiconductor dies, The system including the above.

[0147] Embodiment 36: A first portion comprising one or more first conductive materials formed continuously along three depths with respect to the thickness of the system, A second portion located above the first portion, comprising one or more second conductive materials formed continuously along two depths with respect to the thickness of the system, The system according to embodiment 35, further including the following:

[0148] The information and signals described herein may be represented using any of a variety of different techniques and methods. For example, signaling data, instructions, commands, information, signals, bits, or symbols that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. In some drawings, signals may be shown as a single signal, but a signal may represent a bus of signals, and a bus may have a variety of bit widths.

[0149] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” can refer to relationships between components that support the flow of signals between them. Components are considered to be in a state of electronic communication (e.g., conducted contact, connected, coupled) if there is any electrical path (e.g., conducted path) between them that can support the flow of signals (e.g., charge, current, voltage) between them at any time. Conducted paths between components that are in a state of electronic communication (e.g., conducted contact, connected, coupled) can be open or closed at any time, based on the operation of the device containing the connected components. Conducted paths between connected components can be direct conduction paths between components, or they can be indirect conduction paths that may include intermediate components such as switches, transistors, or other components. In some embodiments, the flow of signals between connected components can be temporarily interrupted by using one or more intermediate components, such as switches or transistors.

[0150] The descriptions provided herein in relation to the accompanying drawings are illustrative and do not represent all embodiments that may be practiced or that fall within the claims. The embodiments for carrying out the invention include specific details to facilitate understanding of the techniques described. However, these techniques can be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid ambiguity of the concepts of the embodiments described.

[0151] In the attached diagram, similar components or mechanisms may have the same reference label. Similar components can be distinguished by adding one or more dashes and additional labels after the reference label. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of any additional reference labels.

[0152] The functions described herein may be implemented in hardware, software, firmware, or any combination thereof, executed by a processing system (e.g., one or more processors, one or more controllers, control circuits, processing circuits, logic circuits). When a function is implemented in software executed by a processing system, the function may be stored or transmitted as one or more instructions (e.g., code) on a computer-readable medium. Due to the nature of software, the functions described herein may be implemented using software, hardware, firmware, hardwiring, or any combination thereof, executed by a processing system. Mechanisms for implementing functions may be physically located in various locations, including distribution so that parts of the function are implemented in different physical locations.

[0153] The exemplary blocks and modules described herein may be implemented or run on one or more processors, such as DSPs, ASICs, FPGAs, discrete gate logic, discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, controller, microcontroller, state machine, or any other type of processor. The processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors used in conjunction with a DSP core, or any other such configuration).

[0154] Where used herein, including in the claims, “or” in a list of items (e.g., a list of items ending with a phrase such as “at least one of the following” or “one or more of the following”) indicates an inclusive list, for example, the list “at least one of A, B, or C” means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, where used herein, the phrase “based on” should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, where used herein, the phrase “based on” should be interpreted in the same way as the phrase “based at least partially on.”

[0155] As used herein, including in the claims, the article “a” preceding a noun is unrestricted and is understood to refer to “at least one” of those nouns, or “one or more” of those nouns. Thus, the terms “a,” “at least one,” “one or more,” and “at least one of one or more” may be interchangeable. For example, if a claim describes a “component” that performs one or more functions, each of the distinct functions may be performed by a single component or by any combination of multiple components. Thus, the term “a component” having a characteristic or performing a function may refer to “at least one of one or more components” having a particular characteristic or performing a particular function. When a component introduced with the article “a” is subsequently referred to using the terms “the” or “said,” it may refer to any or all of one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components," and a subsequent reference to "the component" in the claims may be understood to be equivalent to a reference to "at least one of the one or more components." Similarly, a component introduced as "one or more components" may be referred to later using the terms "the" or "said" to refer to any or all of the one or more components. For example, a subsequent reference to "the one or more components" in the claims may be understood to be equivalent to a reference to "at least one of the one or more components."

[0156] Computer-readable media include both non-temporary computer storage media and communication media, and these include any media that facilitate the transfer of computer programs from one location to another. Non-temporary storage media can be any available media that a computer can access. Examples, but not limited to, of non-temporary computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD)ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-temporary media that can be used to transport or store desired program code means in the form of instructions or data structures and that can be accessed by a computer or processor. Any connection is also appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, the terms "Disk" and "Disc" include CDs, laser discs, optical discs, digital multipurpose discs (DVDs), floppy disks, and Blu-ray discs. A "Disk" typically reproduces data magnetically, while a "Disc" reproduces data optically using a laser. Combinations of these also fall within the scope of computer-readable media.

[0157] The descriptions herein are provided to enable those skilled in the art to create or use this disclosure. Various modifications to this disclosure will be obvious to those skilled in the art, and the general principles defined herein can be applied to other modifications without departing from the scope of this disclosure. Thus, this disclosure should be recognized as having the broadest scope consistent with the principles and new features disclosed herein, and not limited to the examples and designs described herein.

Claims

1. Bonding a plurality of first semiconductor dies to a carrier, wherein each of the first semiconductor dies comprises its respective portion of the circuit of a semiconductor unit, After bonding the plurality of first semiconductor dies to the carrier, the semiconductor unit is formed at least partially by electrically connecting each of the plurality of first semiconductor dies to at least one of the other first semiconductor dies. Bonding one or more sets of second semiconductor dies to at least one of the plurality of first semiconductor dies, wherein each of the sets of second semiconductor dies comprises a memory array, and the memory array is operable at least partially based on the respective portion of the circuit of the semiconductor unit of the first semiconductor die to which the respective set is bonded. Methods that include...

2. The method according to claim 1, wherein with respect to each of the first semiconductor dies, the respective portion of the circuit comprises a memory interface circuit, a memory controller circuit, a host controller circuit, a host processor circuit, or any combination thereof.

3. The method according to claim 1, wherein each first portion of the circuit of the first semiconductor die of the semiconductor unit is associated with a first logic function, and each second portion of the circuit of another first semiconductor die of the semiconductor unit is associated with a second logic function different from the first logic function.

4. The method according to claim 1, wherein each of a first set of one or more second semiconductor dies and each of a second set of one or more second semiconductor dies are included in a reconstructed wafer of the second semiconductor dies bonded to the semiconductor unit.

5. The method according to claim 1, further comprising forming one or more dielectric materials between the plurality of first semiconductor dies, at least along the carriers, wherein the one or more dielectric materials separate the respective substrates of the first semiconductor dies.

6. The method involves forming a plurality of first cavities through one or more dielectric materials to a first depth, wherein each of the first cavities is in contact with at least two of the first semiconductor dies. The method involves forming a plurality of second cavities through one or more dielectric materials to a second depth, wherein each of the second cavities penetrates at least a portion of each of the first semiconductor dies of the first semiconductor die. The process involves forming a plurality of third cavities through one or more dielectric materials to a third depth, wherein each of the third cavities is located between the plurality of first semiconductor dies and is in contact with the carriers. To simultaneously form one or more conductive materials in the plurality of first cavities, the plurality of second cavities, and the plurality of third cavities, The method according to claim 5, further comprising:

7. The method according to claim 6, wherein one or more conduction pads, one or more conduction paths, and one or more vias are formed in one or more second dielectric materials adjacent to one or more conductor materials, wherein the one or more conduction pads, one or more conduction paths, and one or more vias are formed at least in part on the basis of simultaneously forming one or more second conductor materials in cavities associated with the one or more conduction pads, one or more conduction paths, and one or more vias.

8. The method according to claim 1, further comprising forming one or more vias between a plurality of first semiconductor dies, through one or more dielectric materials, wherein each of the one or more vias is coupled to one set of the one or more sets of second semiconductor dies.

9. The method according to claim 8, wherein at least one of the one or more vias provides an interface between each set of the one or more second semiconductor dies and the surface of the semiconductor unit opposite to each set of the one or more second semiconductor dies.

10. The method of claim 8, further comprising forming one or more electrical contacts in each of the one or more vias, at least partially based on forming a cavity through at least a portion of the carrier and forming one or more conductive materials within the cavity.

11. The method according to claim 1, wherein electrically connecting each of the plurality of first semiconductor dies is at least partially based on forming a plurality of conducted signal paths on the first semiconductor dies of the semiconductor unit.

12. The method according to claim 11, further comprising verifying that each first semiconductor die of the plurality of first semiconductor dies and each set of the one or more second semiconductor dies satisfy operational evaluations before bonding each set of the one or more second semiconductor dies to at least one of the plurality of first semiconductor dies.

13. The method according to claim 1, wherein bonding each set of the one or more second semiconductor dies to at least one of the plurality of first semiconductor dies is at least partially based on each set penetrating the substrate of the bonded first semiconductor die to form one or more vias.

14. The method according to claim 1, further comprising forming one or more electrical contacts on each of the first semiconductor dies, at least partially based on forming a cavity through at least a portion of the carriers and forming one or more conductive materials within the cavity.

15. The method according to claim 1, wherein bonding the plurality of first semiconductor dies to the carrier includes, with respect to at least one first semiconductor die, bonding the surface of the at least one semiconductor die opposite to the substrate of the at least one semiconductor die to the carrier.

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