Semiconductor equipment

Abstract

To provide a semiconductor device that can mitigate an electric field applied to a gate insulation film and can reduce ON resistance.SOLUTION: A p-type low concentration region 61 faces a bottom face of a trench 37 and extends in a lengthwise direction (first direction X) of the trench 37. The p-type low concentration regions 61 which adjoin each other in a widthwise direction (second direction Y) of the trench 37 have predetermined parts coupled by p-type low concentration coupling parts dotted at an interval of 3 μm or less in the first direction X. The impurity concentration of the p-type low concentration region 61 and the p-type low concentration coupling part is 3×1017 / cm3 or more and 9×1017 / cm3 or less. The depth d1 from the bottom face of the trench 37 to an undersurface of the p-type low concentration region 61 is 0.7 μm or more and 1.1 μm or less. A p+-type high concentration region 64 is provided between the bottom face of the trench 37 and the p-type low concentration region 61. The impurity concentration of the p+-type high concentration region 64 is twice or more the impurity concentration of the p-type low concentration region 61.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a semiconductor device. [Background technology]

[0002] Traditionally, there have been several types of power semiconductor devices used to control high voltages and large currents, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are used depending on the application.

[0003] For example, bipolar transistors and IGBTs have a higher current density than MOSFETs, allowing for higher currents, but they cannot be switched at high speeds. Specifically, bipolar transistors are limited to switching frequencies of a few kHz, and IGBTs are limited to switching frequencies of a few tens of kHz. On the other hand, MOSFETs have a lower current density than bipolar transistors and IGBTs, making it difficult to operate them at high currents, but they can perform high-speed switching operations up to a few MHz.

[0004] Furthermore, unlike IGBTs, MOSFETs have a p-type base region and n-type base region inside the semiconductor substrate (semiconductor chip). - A MOSFET incorporates a parasitic diode (body diode) formed at the pn junction (main junction) with the drift region. The MOSFET can use this internally embedded parasitic diode as a freewheeling diode to protect itself. Therefore, the MOSFET does not require an additional external freewheeling diode for protection, making it attractive from an economic standpoint.

[0005] Although silicon (Si) is used as a component material for power semiconductor devices, there is a strong market demand for power semiconductor devices that combine high current and high speed capabilities. As a result, efforts have been focused on improving IGBTs and MOSFETs, and development has progressed to the point where they are almost at the material's limits. For this reason, alternative semiconductor materials to silicon are being considered from the perspective of power semiconductor devices, and silicon carbide (SiC) is attracting attention as a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed, and high-temperature characteristics.

[0006] Silicon carbide is a chemically very stable semiconductor material with a wide bandgap of 3 eV, making it extremely stable as a semiconductor even at high temperatures. Furthermore, because silicon carbide has a maximum electric field strength that is more than an order of magnitude greater than that of silicon, it is expected to be a semiconductor material that can sufficiently reduce on-resistance. These characteristics of silicon carbide are not unique to silicon carbide, but are also shared by all semiconductors with a wider bandgap than silicon (hereinafter referred to as wide-bandgap semiconductors).

[0007] Furthermore, in MOSFETs, as current increases, a trench gate structure, in which the channel is formed perpendicular to the front surface of the semiconductor chip along the sidewall of the trench, is more cost-effective than a planar gate structure, in which the channel (inversion layer) is formed along the front surface of the semiconductor chip. This is because the trench gate structure can increase the density of unit cells (constituent units of the element) per unit area, thereby increasing the current density per unit area compared to the planar gate structure.

[0008] As the current density per unit area increases, the rate of temperature rise corresponding to the occupied volume of the unit cell also increases. Therefore, a double-sided cooling structure is necessary to improve discharge efficiency and stabilize reliability. A double-sided cooling structure is a cooling structure in which rod-shaped terminal pins are joined to the aluminum (Al) electrode film on the front surface of the semiconductor substrate in a position almost perpendicular to it, and the drain pad on the back surface of the semiconductor substrate is joined to the cooling fins via a metal base plate of an insulating substrate. This allows heat generated in the semiconductor substrate to be dissipated from both main surfaces of the semiconductor substrate.

[0009] The structure of a conventional semiconductor device will be described. Figures 17-20 show the cross-sectional structure at the cutting lines AA1-AA1', AA2-AA2', BB1-BB1', and BB2-BB2' in Figure 21, respectively. Figure 21 is a plan view showing the layout of a part of a conventional semiconductor device as seen from the front side of the semiconductor substrate. Figure 21 shows the first and second pages. + The high-concentration regions 261 and 262 are indicated by thick dashed outlines and hatching, p + The high-concentration type connecting section 263 is shown by a solid line outline and hatching.

[0010] The conventional semiconductor device 230 shown in Figures 17-21 is a vertical MOSFET with a general trench gate structure on the front side of a semiconductor substrate (semiconductor chip) 210 made of silicon carbide. + n - The silicon carbide layers 212 and 213, which form the p-type drift region 232 and the p-type base region 234, are grown epitaxially in sequence. The main surface of the semiconductor substrate 210 on the side of the p-type silicon carbide layer 213 is considered the front surface, and n + The main surface on the mold starting substrate 211 side is designated as the back surface.

[0011] The trench gate structure has a p-type base region 234, n + Type source area 235, p ++It is composed of a type contact region 236, a trench 237, a gate insulating film 238, and a gate electrode 239. A plurality of unit cells (functional units of the device) of the MOSFET are arranged adjacent to each other, and the trenches 237 of each unit cell are arranged in a stripe shape extending in a first direction X parallel to the front surface of the semiconductor substrate 210. A p-type base region 234, n + type source region 235 and p ++ type contact region 236 is selectively provided between adjacent trenches 237.

[0012] Inside the semiconductor substrate 210, at a depth position closer to the n + type drain region 231 than the bottom surface of the trench 237, first and second p + type high-concentration regions 261, 262 for relaxing the electric field applied to the bottom surface of the trench 237 are provided. The first and second p + type high-concentration regions 261, 262 are arranged in a stripe shape extending linearly in the longitudinal direction (first direction X) of the trench 237. The first p + type high-concentration region 261 is provided away from the p-type base region 234 and faces the bottom surface of the trench 237 in the depth direction Z.

[0013] The second p + type high-concentration region 262 is provided between adjacent trenches 237, away from the first p + type high-concentration region 261 and the trench 237. The second p + type high-concentration region 262 is in contact with the p-type base region 234 and reaches approximately the same depth as the first p + type high-concentration region 261 on the side of the n + type drain region 231. The adjacent first and second p + type high-concentration regions 261, 262 are connected to each other at a predetermined location by a p + type high-concentration connection portion 263 having the same impurity concentration as these first and second p + type high-concentration regions 261, 262.

[0014] The adjacent first and second p + type high-concentration regions 261, 262 of +The portion where the n-type high-concentration connecting portion 263 is formed passes through a channel (n-type inversion layer) formed along the side wall of the trench 237 when the MOSFET is turned on. + Type drain region 231 to n + It does not become a path for current flowing toward the source region 235. + The high-concentration type connecting section 263 consists of adjacent 1st and 2p + Between the high-density regions 261 and 262, the stripes extend in a stripe-like manner in a second direction Y that is parallel to the front surface of the semiconductor substrate 210 and perpendicular to the first direction X.

[0015] 1st, 2p + Type high concentration regions 261,262 and p + The high-concentration connecting section 263 forms a grid-like planar shape (Figure 21). + Lower surface of the high-concentration connecting part 263 (n + The end on the drain region 231 side is the 1st, 2nd p + It is located at the same depth as the lower surface of the high-concentration region 261,262. + The thickness of the type high-concentration connecting section 263 is the first p + The thickness is the same as that of the high-concentration region 261. The metal silicide film 241, barrier metal 246, and Al electrode film 247 are sequentially stacked on the front surface of the semiconductor substrate 210 and function as a source electrode.

[0016] A double-sided cooling structure is formed by a wiring structure on the Al electrode film 247 and cooling fins (not shown) bonded to the drain electrode 252 on the back surface of the semiconductor substrate 210 via a metal base plate of an insulating substrate (not shown). Reference numerals 233, 240, and 240a represent the n-type current diffusion region, interlayer insulating film, and contact hole, respectively. Reference numerals 242 to 245 represent metal films constituting the barrier metal 246. Reference numerals 248 and 249 represent the plating film and terminal pins constituting the wiring structure on the Al electrode film 247, respectively. Reference numerals 250 and 251 represent protective films.

[0017] As a conventional trench gate vertical MOSFET, the p facing the bottom of the trench + High-concentration regions of type and p between adjacent trenches +A high-concentration region of the type, and n greater than the bottom surface of the trench. + An apparatus has been proposed in which the components are arranged to form a grid-like planar shape at a depth close to the drain region (see, for example, Patent Document 1 below). In Patent Document 1 below, p + Type high concentration region and n - The holes (positive charge) generated during avalanche yielding at the pn junction with the type drift region can be efficiently relocated to the source electrode, improving the reliability of the gate insulating film.

[0018] As a conventional trench gate vertical MOSFET, a device has been proposed in which the p-type trench bottom protection layer surrounding the bottom of the trench has a two-layer structure: a high-concentration protection layer facing the bottom of the trench and a low-concentration protection layer forming at least a part of the bottom surface of the trench bottom protection layer (see, for example, Patent Document 2 below). In Patent Document 2 below, the avalanche withstand capability is improved by mitigating the electric field applied to the pn junction between the trench bottom protection layer and the drift region using the low-concentration protection layer, which has a relatively low impurity concentration in the trench bottom protection layer.

[0019] As a conventional trench gate vertical MOSFET, the electric field applied to the gate insulating film at the bottom of the trench is mitigated by p + An apparatus has been proposed that includes a high-concentration region as the active region and a field-limiting ring (FLR) in the edge-terminal region surrounding the active region (see, for example, Patent Document 3 below). Patent Document 3 below describes a p that relaxes the electric field applied to the gate insulating film at the bottom of the trench. + It is disclosed that a high-concentration region and an FLR (Fiber Reinforced Reinforcement) in the edge termination region can be formed simultaneously. [Prior art documents] [Patent Documents]

[0020] [Patent Document 1] International Publication No. 2017 / 064949 [Patent Document 2] Patent No. 6266166 [Patent Document 3] Japanese Patent Publication No. 2016-225455 [Overview of the project] [Problems that the invention aims to solve]

[0021] In the conventional semiconductor device 230 described above (see Figures 17-21), the 1st and 2nd p + The high-density regions 261 and 262 relax the electric field applied to the gate insulating film 238 at the bottom of the trench 237. However, the more the cell structure of the unit cell (trench gate structure) is refined, the more the adjacent 1st and 2p regions + The spacing between the high-density regions 261 and 262 becomes narrower. As a result, the adjacent 1st and 2p regions of the semiconductor substrate 210 become narrower. + The resistance value of the JFET (Junction FET) resistor, which is the internal resistance between the high-concentration regions 261 and 262, increases, and the on-resistance RonA increases.

[0022] The purpose of this invention is to provide a semiconductor device that can mitigate the electric field applied to the gate insulating film and reduce on-resistance, in order to solve the problems of the prior art described above. [Means for solving the problem]

[0023] To solve the above-mentioned problems and achieve the objectives of the present invention, the semiconductor device according to this invention has the following features: A first semiconductor region of a first conductivity type is provided inside a semiconductor substrate made of a semiconductor having a wider bandgap than silicon. A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region. A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region. A trench penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region. The trench extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate. A gate electrode is provided inside the trench via a gate insulating film.

[0024] The first electrode is electrically connected to the second semiconductor region and the third semiconductor region. The second electrode is provided on the second main surface of the semiconductor substrate. A first low-concentration region of the second conductivity type is selectively provided inside the first semiconductor region. The first low-concentration region faces the bottom surface of the trench in the depth direction. The first connecting portion of the second conductivity type connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction. The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion constitute a grid-like planar shape.

[0025] Furthermore, in the semiconductor device according to this invention, the depth from the trench to the end of the first low-concentration region on the second electrode side is 0.7 μm or more and 1.1 μm or less.

[0026] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, it further comprises a first high-concentration region of a second conductivity type having a higher impurity concentration than the second semiconductor region, which electrically connects the second semiconductor region and the first low-concentration region.

[0027] Furthermore, in the semiconductor device according to this invention, the impurity concentrations of the first low-concentration region and the first connecting portion are both 3 × 10⁻¹⁰. 17 / cm 3 The above 9 x 10 17 / cm 3 The following characteristics apply:

[0028] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the adjacent first connecting portions are scattered in the first direction at intervals of 3 μm or less.

[0029] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the width of the first connecting portion in the first direction is 0.5 μm or more and 1.0 μm or less.

[0030] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, a second high-concentration region of a second conductivity type is further provided between the bottom surface of the trench and the first low-concentration region, in contact with the first low-concentration region, and having a higher impurity concentration than the first low-concentration region and the second semiconductor region.

[0031] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the impurity concentration in the second high-concentration region is at least twice the impurity concentration in the first low-concentration region.

[0032] Furthermore, in the semiconductor device according to this invention, the second high-concentration region is in contact with the gate insulating film at the bottom surface of the trench. The depth from the bottom surface of the trench to the end of the first high-concentration region on the second electrode side is 0.1 μm or more and 0.15 μm or less.

[0033] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the first high-concentration region is provided inside the first semiconductor region, separated from the first low-concentration region and the trenches, between adjacent trenches, and extends in a stripe shape in the first direction.

[0034] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the first low-concentration region is electrically connected to the first high-concentration region via the first connecting portion.

[0035] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the first high-concentration region is provided along only one side wall of the trench and is scattered in the first direction.

[0036] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the spacing at which the first high-concentration regions are scattered in the first direction is wider than the spacing at which the first connecting portions are scattered in the first direction.

[0037] Furthermore, the semiconductor device according to this invention further comprises, in the above-described invention, a second low-concentration region of a second conductivity type, provided within the first semiconductor region between adjacent trenches, in contact with the second semiconductor region and the first connecting portion, and separated from the first low-concentration region and the trenches, and extending in a stripe shape in the first direction. The end of the second low-concentration region on the second electrode side is located at a shallow position, at a distance of 0.1 μm or more from the end of the first low-concentration region on the second electrode side toward the first electrode. The impurity concentration of the second low-concentration region is characterized by being 10 times or more higher than the impurity concentration of the first low-concentration region.

[0038] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the width of the first low-concentration region is wider than the width of the trench and is 1.0 μm or more.

[0039] Furthermore, in the semiconductor device according to this invention, the impurity concentration in the first low-concentration region is 1 × 10⁻⁶ in the invention described above. 16 / cm 3 The above 8 x 10 16 / cm 3 The following characteristics apply:

[0040] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the impurity concentration of the first connecting portion is 10 times or more higher than the impurity concentration of the first low-concentration region.

[0041] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the first connecting portion is in contact with the second semiconductor region and electrically connects the second semiconductor region and the first low-concentration region.

[0042] Furthermore, the semiconductor device according to this invention is characterized in that, in the invention described above, the adjacent first connecting portions are scattered in the first direction at intervals of 2 μm to 5 μm.

[0043] According to the invention described above, the width of the first low-concentration region facing the bottom surface of the trench can be narrowed. As a result, the resistance value of the JFET resistor, which is the internal resistance of the semiconductor substrate, can be lowered, or the unit cell can be reduced in size, thereby increasing the unit cell density. Furthermore, according to the invention described above, even if the impurity concentration in the first low-concentration region is low, the depletion layer that spreads from the main junction (pn junction) when off is less likely to spread into the first high-concentration region between the bottom surface of the trench and the first low-concentration region. In addition, the total second conductivity type impurity concentration per predetermined area near the bottom surface of the trench is increased by the first connecting portion, making it less likely for the first low-concentration region to be depleted. [Effects of the Invention]

[0044] The semiconductor device according to the present invention has the effect of mitigating the electric field applied to the gate insulating film and reducing on-resistance. [Brief explanation of the drawing]

[0045] [Figure 1] This is a plan view showing the layout of the semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A1-A1' in Figure 6. [Figure 3] Figure 6 is a cross-sectional view showing the cross-sectional structure along the cutting line A2-A2'. [Figure 4] This is a cross-sectional view showing the cross-sectional structure along the cutting line B1-B1' in Figure 6. [Figure 5] Figure 6 is a cross-sectional view showing the cross-sectional structure along the cutting line B2-B2'. [Figure 6] This is a plan view showing a magnified portion of the active region in Figure 1. [Figure 7] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 8] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 9] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 10] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 11] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 12] This is a cross-sectional view showing the semiconductor device according to Embodiment 1 in the process of being manufactured. [Figure 13] This is a cross-sectional view showing a part of the structure of a semiconductor device according to Embodiment 2. [Figure 14] This is a cross-sectional view showing the cross-sectional structure at the cutting line C-C' in Figure 1. [Figure 15] This is a characteristic diagram showing the voltage-electric field characteristics of Example 1. [Figure 16] This is a characteristic diagram showing the on-resistance characteristics of Example 1. [Figure 17] This is a cross-sectional view showing the cross-sectional structure along the cutting line AA1-AA1' in Figure 21. [Figure 18] This is a cross-sectional view showing the cross-sectional structure along the cutting line AA2-AA2' in Figure 21. [Figure 19] This is a cross-sectional view showing the cross-sectional structure along the cutting line BB1-BB1' in Figure 21. [Figure 20] This is a cross-sectional view showing the cross-sectional structure along the cutting line BB2-BB2' in Figure 21. [Figure 21] This is a plan view showing the layout of a part of a conventional semiconductor device as seen from the front side of the semiconductor substrate. [Figure 22] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 4. [Figure 23] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 4. [Figure 24] This is a plan view showing a magnified portion of the active region in Figure 1. [Figure 25] This is a plan view showing an enlarged portion of another example of the active region in Figure 1. [Figure 26] This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 5. [Figure 27]This is a cross-sectional view showing the structure of a semiconductor device according to Embodiment 5. [Figure 28] This is a plan view showing a magnified portion of the active region in Figure 1. [Figure 29] This is a plan view showing an enlarged portion of another example of the active region in Figure 1. [Figure 30] This is a characteristic diagram showing the simulation results of the electric field strength of the gate insulating film in Example 2. [Figure 31] This is a characteristic diagram showing the simulation results of the electric field strength of the gate insulating film in Example 2. [Figure 32] This is a characteristic diagram showing the simulation results of the electric field strength of the gate insulating film in Example 2. [Modes for carrying out the invention]

[0046] Preferred embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0047] (Embodiment 1) The structure of the semiconductor device according to Embodiment 1 will now be described. Figure 1 is a plan view showing the layout of the semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figures 2 to 5 are cross-sectional views showing the cross-sectional structure at the cutting lines A1-A1', A2-A2', B1-B1', and B2-B2' in Figure 6, respectively. Figure 6 is a plan view showing an enlarged portion of the active region in Figure 1. Figure 6 shows the layout of the p-type low-concentration region (first low-concentration region) 61, the p-type low-concentration region 65, and the p-type low-concentration connecting portion 63 near the bottom surface of the trench 37.

[0048] The semiconductor device 30 according to Embodiment 1 shown in Figures 1 to 6 is a vertical MOSFET equipped with a trench gate structure (device structure) in the active region 1 of a semiconductor substrate (semiconductor chip) 10 made of silicon carbide (SiC). The active region 1 is the region through which the main current (drift current) flows when the MOSFET (semiconductor device 30) is turned on. Multiple unit cells (constituent units of the device) of the same structure of the MOSFET are arranged adjacent to each other in the active region 1. The active region 1 has, for example, a roughly rectangular planar shape and is located approximately in the center of the semiconductor substrate 10 (center of the chip).

[0049] The active region 1 is the area inside (towards the center of the chip) the side wall (side of the interlayer insulating film 40) outside (towards the chip edge) of the outermost contact hole 40b (see Figure 14 described later). The intermediate region 3 between the active region 1 and the edge termination region 2 is adjacent to the active region 1 and surrounds it. The boundary between the intermediate region 3 and the edge termination region 2 is the boundary between the first and third surfaces 10a and 10c (see Figure 14) of the front surface of the semiconductor substrate 10, described later. The edge termination region 2 is the area between the active region 1 and the edge (chip edge) of the semiconductor substrate 10.

[0050] The edge termination region 2 surrounds the active region 1 via the intermediate region 3 and has the function of mitigating the electric field on the front side of the semiconductor substrate 10 and maintaining the breakdown voltage. Breakdown structures such as a field limiting ring (FLR) structure and a junction termination extension (JTE) structure are arranged in the edge termination region 2. Breakdown voltage is the limit voltage at which the source-drain voltage does not increase further even if the source-drain current increases during avalanche breakdown at the main junction (pn junction) of the active region 1.

[0051] In the active region 1, a trench gate structure is provided on the front side of the semiconductor substrate 10. The trench gate structure consists of a p-type base region (second semiconductor region) 34, n + Type source region (third semiconductor region) 35, p ++It consists of a type contact region 36, a trench 37, a gate insulating film 38, and a gate electrode 39. Outside the outermost trench 37 (the part of the outer p-type base region 34a described later: see Figure 14), n + The configuration does not have a type source area 35. Multiple trench gate structures of multiple unit cells (functional units of elements) of the semiconductor device 30 are arranged adjacent to each other.

[0052] The semiconductor substrate 10 is made of n + n - The semiconductor substrate 10 is formed by sequentially epitaxially growing the respective epitaxial layers 12 and 13, which will become the p-type drift region (first semiconductor region) 32 and the p-type base region 34. The main surface of the semiconductor substrate 10 on the side of the p-type epitaxial layer 13 is considered the front surface, and n + The main surface on the mold starting substrate 11 side is considered the back surface. + The starting substrate 11 is n + This is the type drain region 31. - The type drift region 32 is formed by the p-type base region 34 and n + It is provided between the drain region 31 and the drain region 31.

[0053] n - The drift region 32 is n - The type epitaxial layer 12 has an active region 1 which includes an n-type current diffusion region 33, a p-type low-concentration region (low-concentration region) 61, a p-type low-concentration region 65, a p-type low-concentration connecting portion (first connecting portion) 63, and p + Type high-concentration regions (second and first high-concentration regions) 62, 64, and the outer perimeter p of the edge termination region 2 and intermediate region 3, which will be described later. + Type region 62a, outer p-type low-concentration region 65a, FLR23 and n + This is the portion excluding the channel stopper region 24 (see Figure 14). - The type drift region 32 extends from the active region 1 to the tip edge and is exposed to the edge of the semiconductor substrate 10 (the side surface of the semiconductor substrate 10) (see Figure 14).

[0054] Trench 37 penetrates the p-type epitaxial layer 13 from the front surface of the semiconductor substrate 10 in the depth direction Z, and n -The trenches 37 of each unit cell extend in a stripe-like manner in a first direction X parallel to the front surface of the semiconductor substrate 10, for example, and reach the intermediate region 3. Inside the trenches 37, a gate electrode 39 is provided via a gate insulating film 38. Between adjacent trenches 37, there are p-type base regions 34 and n + Type source region 35 and p ++ Each type of contact region 36 is selectively provided.

[0055] The p-type base region 34 is the n of the p-type epitaxial layer 13. + Type source region 35 and p ++ This is the portion excluding the type contact region 36. The p-type base region 34 is in contact with the gate insulating film 38 at the side wall of the trench 37. The p-type base region 34 extends linearly in the longitudinal direction (first direction X) of the trench 37. + Type source region 35 and p ++ The p-type contact region 36 is selectively provided between the front surface of the semiconductor substrate 10 and the p-type base region 34, in contact with the p-type base region 34, and is exposed to the front surface of the semiconductor substrate 10.

[0056] Exposure on the front surface of the semiconductor substrate 10 means n + Type source region 35 and p ++ The contact region 36 is in contact with the NiSi film 41, which will be described later, through the contact hole 40a, which will be described later. + The mold source region 35 is in contact with the gate insulating film 38 at the side wall of the trench 37. + The type source region 35 consists of a portion extending in the first direction X along the side wall of the trench 37 and a portion adjacent to each other in the first direction X. ++ It has a portion sandwiched between the type contact regions 36, and p ++ It has a ladder-like planar shape that surrounds the contact area 36.

[0057] p ++ The contact area 36 is n + It is located further away from the trench 37 than the type source region 35. ++The p-type contact region 36 penetrates the p-type base region 34 and is arranged to contact the lower surface (the end on the n + -type drain region 31 side) of the p-type base region 34. The lower surface of the p ++ -type contact region 36 does not necessarily contact the lower surface of the p-type base region 34. The p ++ -type contact regions 36 are scattered in the first direction X. The p ++ -type contact regions 36 may not be provided. In this case, instead of the p ++ -type contact regions 36, the p-type base region 34 reaches the front surface of the semiconductor substrate 10 and is exposed. Between the p-type base region 34 and the n + -type drain region 31 (the n + -type starting substrate 11), an n + -type drift region 32 is provided in contact with the n - -type drain region 31.

[0058] Between the p-type base region 34 and the n - -type drift region 32, at a depth position closer to the n + -type drain region 31 than the bottom surface of the trench 37, an n-type current diffusion region 33, a p-type low-concentration region 61, a p-type low-concentration region 65, a p-type low-concentration connection portion 63, a p + -type high-concentration region 62, and a p + -type high-concentration region 64 are selectively provided respectively. The n-type current diffusion region 33 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. The upper surface (the end on the n + -type source region 35 side) of the n-type current diffusion region 33 contacts the p-type base region 34.

[0059] The n-type current diffusion region 33 contacts the p-type low-concentration region 61, the p-type low-concentration region 65, the p-type low-concentration connection portion 63, the p + -type high-concentration region 62, and the p + -type high-concentration region 64, and the gate insulating film 38 on the side wall of the trench 37, in a direction parallel to the front surface of the semiconductor substrate 10. Between the p-type low-concentration region 61 and the p-type low-concentration region 65 of the n-type current diffusion region 33, and between the p + -type high-concentration region 62 and the p+ A JFET resistance is formed between the n-type high-concentration region 64. The n-type current diffusion region 33 does not need to be provided. In this case, instead of the n-type current diffusion region 33, - The type drift region 32 reaches the p-type base region 34 and touches the p-type base region 34.

[0060] p-type low concentration region 61, p-type low concentration region 65, p-type low concentration connection portion 63, p + Type high concentration region 62 and p + The p-type high-concentration region 64 has the function of mitigating the electric field applied to the gate insulating film 38 at the bottom surface of the trench 37. p-type low-concentration region 65, p-type low-concentration connecting portion 63 and p + The p-type high-concentration region 62 has the function of mitigating the electric field applied to the gate insulating film 38 on the side wall of the trench 37. The p-type low-concentration region 61 (outline of the thick dashed line and hatched dot portion in Figure 6) and p + The high-concentration region 64 extends in the first direction X and is located on the outer periphery of the active region 1. + It is connected to the p-type region 62a and the outer p-type low-concentration region 65a. The p-type low-concentration region 65 (outline of the thick dashed line and hatched area of ​​the solid line in Figure 6) and p + The high-concentration region 62 extends in the first direction X and is located on the outer periphery of the active region 1, at the outer periphery p + It is connected to the type region 62a and the outer p-type low-concentration region 65a. The p-type low-concentration connecting portion 63 (the outline of the thick solid line and the hatched portion of the dots in Figure 6) is scattered in the first direction X.

[0061] The depth of the p-type low-concentration region 61 and the p-type low-concentration region 65 is n greater than the bottom surface of the trench 37. + The depth should be approximately the same as that of the n-type drain region 31. Approximately the same depth means the same depth within a range that includes tolerances due to process variations. For example, the p-type low concentration region 61 and the p-type low concentration region 65 should be at approximately the same depth as the n-type current diffusion region 33, or at a depth greater than the n-type current diffusion region 33. + It reaches a deep position on the drain region 31 side, n -It may be in contact with the n-type drift region 32 (see Figures 2-5), or it may terminate inside the n-type current diffusion region 33 and be surrounded by the n-type current diffusion region 33 (not shown).

[0062] The p-type low-concentration region 61 is provided separately from the p-type base region 34 and faces the bottom surface of the trench 37 in the depth direction Z. The bottom surface of the p-type low-concentration region 61 is from the bottom surface of the trench 37 (n + The depth (distance) d1 to the end on the drain region 31 side is, for example, about 0.7 μm to 1.1 μm, and from the bottom surface of the trench 237 in the conventional structure (see Figures 17-21) to the first p + The distance (depth) d201 (=4μm~5μm) to the bottom surface of the high-concentration region 261 of type p is deeper. The impurity concentration of the low-concentration region 61 of type p is, for example, 3 × 10⁻¹⁰ 17 / cm 3 The above 9 x 10 17 / cm 3 The following is the extent of the first p facing the bottom surface of the conventional trench 237. + The impurity concentration is lower than that of the high-concentration region 261.

[0063] Therefore, the p-type low-concentration region 61 is the first p-type of the conventional structure. + Compared to the high-concentration region 261 of the p-type, it is formed with a low dose of ion implantation and impurities are less likely to diffuse. For this reason, the width of the p-type low-concentration region 61 (width in the second direction Y) is less than that of the first p-type region of the conventional structure. + The width of the p-type high-concentration region 261 can be made narrower. This allows for a narrower cell pitch (the width between adjacent trenches 37) compared to the conventional structure, and increases the number of cells that can be placed in the active region 1. The width of the p-type low-concentration region 61 is, for example, wider than the width of the trench 37.

[0064] Adjacent p-type low-concentration regions 61 are connected at predetermined locations by p-type low-concentration connecting portions 63 having approximately the same impurity concentration as the p-type low-concentration region 61. Approximately the same impurity concentration means that the impurity concentration is the same within a range that includes tolerances due to process variations. The p-type low-concentration connecting portions 63 extend in a stripe shape between adjacent p-type low-concentration regions 61 in a second direction Y that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the first direction X. The p-type low-concentration regions 61 and the p-type low-concentration connecting portions 63 form a grid-like planar shape. If a p-type low-concentration region 65 is provided, the p-type low-concentration region 61 and the p-type low-concentration region 65 are connected at predetermined locations by the p-type low-concentration connecting portions 63, and the p-type low-concentration region 61, p-type low-concentration region 65, and p-type low-concentration connecting portions 63 form a grid-like planar shape.

[0065] The width (width in the first direction X) w1 of the p-type low-concentration connecting portion 63 is between the process limit (e.g., about 0.5 μm) and about 1.0 μm, and the adjacent first and second p-type connecting portions of the conventional structure are + p connects the high-concentration regions 261 and 262. + The width w201 of the p-type high-concentration connecting portion 263 is narrower than that of the p-type low-concentration connecting portion 63 adjacent to each other in the first direction X is, for example, about 3 μm or less, and the spacing (pitch) w2 between adjacent p-type low-concentration connecting portions 63 in the first direction X of the conventional structure is narrower than that of the p-type high-concentration connecting portion 263. + The spacing between the high-concentration connecting sections 263 is narrower than w202 (30 μm to 50 μm).

[0066] The thickness of the p-type low-concentration connecting portion 63 is, for example, the thickness of the p-type low-concentration region 61 and p + The total thickness is approximately the same as or less than the total thickness of the high-concentration region 64. The upper surface of the p-type low-concentration connecting portion 63 is p + n + The p-type drain region 31 is only required to be located deep within the p-type drain region 31, and may be located on the p-type base region 34 side of the bottom surface of the trench 37. For example, the upper surface of the p-type low-concentration connecting portion 63 may be at the same depth as the upper surface of the p-type low-concentration region 61. The lower surface of the p-type low-concentration connecting portion 63 is preferably located at approximately the same depth as the lower surface of the p-type low-concentration region 61, but it may be at a depth of n +It may be located at a shallow depth on the source region 35 side. Also, it may be located below the lower surface of the p-type low-concentration region 61. + It may be located on the drain region 31 side.

[0067] p-type low concentration region 65 and p + The high-concentration p-type regions 62 are located between adjacent trenches 37, with p-type low-concentration regions 61 and p + It is provided separately from the high-concentration region 64 and the trench 37. + The high-concentration region 62 has adjacent p-type low-concentration connecting portions 63 in the first direction X. + It extends in the first direction X so as to penetrate the end on the drain region 31 side. + n of the high concentration region 62 + The end on the drain region 31 side terminates inside the p-type low-concentration connecting portion 63. The p-type low-concentration region 65 is provided between adjacent p-type low-concentration connecting portions 63 in the first direction X, and is in contact with each of these adjacent p-type low-concentration connecting portions 63 in the first direction X. + The high-concentration region 62 is electrically connected to the p-type base region 34, thereby connecting the p-type low-concentration region 61, the p-type low-concentration region 65, the p-type low-concentration connecting portion 63, and p + The high-concentration region 64 is fixed at the potential of the source electrode.

[0068] Also, p + The high-concentration region 62 of type p on the upper surface ++ It is in contact with the type contact region 36 or the p-type base region 34 and extends linearly in the first direction X for a length approximately equal to the longitudinal length of the trench 37. "Approximately equal length" means that the length is the same within the range of tolerance due to process variations. + The high-concentration region 62 is arranged in a stripe pattern. + The p-type high-concentration region 62 is the portion that extends in the first direction X between the p-type base region 34 and the p-type low-concentration connecting portion 63 (the p-type high-concentration region described later). + (corresponding to type region 81: see Figure 9) and a portion extending in the first direction X so as to penetrate the adjacent p-type low-concentration connecting portion 63 in the first direction X (p described later) +It corresponds to type region 83 (see Figure 9) and is formed by connecting in the depth direction Z. Also, the p-type low concentration region 65 is formed on the upper surface p + It is provided so as to be in contact with the p-type high-concentration region 62. The lower surface of the p-type low-concentration region 65 is at approximately the same height as the lower surface of the p-type low-concentration region 61 and the p-type low-concentration connecting portion 63. The impurity concentration of the p-type low-concentration region 65 is, for example, 3 × 10⁻⁶. 17 / cm 3 The above 9 x 10 17 / cm 3 It is approximately as follows.

[0069] p + The high-concentration region 62 of type n + p + It reaches approximately the same depth as the high-concentration region 64. + The impurity concentration in the high-concentration region 62 of the p-type is higher than the impurity concentration in the low-concentration region 61 of the p-type and the base region 34 of the p-type. + The impurity concentration in the high-concentration region 62 is p + The impurity concentration in the high-concentration region 64 may be approximately the same as that of the type. + The width of the p-type high-concentration region 62 (width in the second direction Y) may be wider than the width of the p-type low-concentration region 61 (for example, the second p in the conventional structure). + The width may be approximately the same as the width of the high-concentration region 262 of the type, or less than or equal to the width of the low-concentration region 61 of the p-type.

[0070] p + The p-type high-concentration region 64 is provided between the p-type low-concentration region 61 and the bottom surface and bottom corner of the trench 37, in contact with the p-type low-concentration region 61. The bottom corner is the boundary between the side wall and the bottom surface of the trench 37. + By positioning the p-type high-concentration region 64 between the p-type low-concentration region 61 and the bottom surface of the trench 37, the electric field applied to the gate insulating film 38 at the bottom surface of the trench 37 can be mitigated when the MOSFET is off, even if the impurity concentration in the p-type low-concentration region 61 is low.

[0071] p +The impurity concentration in the p-type high-concentration region 64 is higher than the impurity concentrations in the p-type low-concentration region 61 and the p-type base region 34, and is, for example, about twice or more the impurity concentration in the p-type low-concentration region 61. + The high-concentration region 64 has adjacent p-type low-concentration connecting portions 63 in the first direction X. + It extends in the first direction X so as to penetrate through the end on the drain region 31 side, but it may also be provided so as to be in contact with the upper surface of the p-type low-concentration connecting portion 63. + The width of the high-concentration region 64 (width in the second direction Y) is wider than the width of the trench 37, p + The high-concentration region 64 is located opposite the bottom surface and bottom corner of the trench 37. + The width of the high-concentration region 64 of type p may be approximately the same as the width of the low-concentration region 61 of type p. Approximately the same width means that the width is the same within the range that includes tolerances due to process variations.

[0072] p + The high-concentration region 64 may be in contact with the gate insulating film 38 at the bottom surface (or bottom surface and bottom corner portion) of the trench 37 (Figure 2). + In the high-density region 64, due to the depth variation caused by etching to form the trenches 37, the trenches 37 are p in the depth direction Z. + It has a thickness t1 (for example, about 0.4 μm) that does not penetrate the high-concentration region 64. From the bottom surface of the trench 37, p + The distance to the lower surface of the high-concentration region 64 is, for example, between 0.1 μm and 0.15 μm, due to variations in the depth caused by etching of the trench 37.

[0073] The interlayer insulating film 40 is provided over almost the entire surface of the front surface of the semiconductor substrate 10 and covers all gate electrodes 39. Contact holes 40a that penetrate the interlayer insulating film 40 in the depth direction Z are n + Type source region 35 and p ++ The contact region 36 is exposed. The nickel silicide (NixSiy, where x and y are integers; hereafter referred to collectively as NiSi) film 41 makes ohmic contact with the semiconductor substrate 10 at the contact hole 40a of the interlayer insulating film 40, n +Type source region 35 and p ++ It is electrically connected to the type contact area 36.

[0074] p ++ If a type contact area 36 is not provided, p ++ Instead of the type contact region 36, the p-type base region 34 is exposed to the contact hole 40a of the interlayer insulating film 40 and electrically connected to the NiSi film 41. A barrier metal 46 is provided along the surfaces of the interlayer insulating film 40 and the NiSi film 41 in the active region 1. The barrier metal 46 has the function of preventing mutual reactions between each metal film of the barrier metal 46 or between opposing regions across the barrier metal 46.

[0075] The barrier metal 46 may have a laminated structure in which, for example, a first titanium nitride (TiN) film 42, a first titanium (Ti) film 43, a second TiN film 44, and a second Ti film 45 are stacked in order. The first TiN film 42 covers the entire surface of the interlayer insulating film 40 in the active region 1. The first Ti film 43 is provided on the entire surface of the first TiN film 42 and the NiSi film 41. The second TiN film 44 is provided on the entire surface of the first Ti film 43. The second Ti film 45 is provided on the entire surface of the second TiN film 44.

[0076] An aluminum (Al) electrode film 47 is provided across the entire surface of the second Ti film 45. The Al electrode film 47 is provided via a barrier metal 46 and a NiSi film 41. + Type source region 35 and p ++ It is electrically connected to the type contact region 36. The Al electrode film 47 may be, for example, an Al film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film with a thickness of about 5 μm. The Al electrode film 47, barrier metal 46, and NiSi film 41 function as a source electrode (first electrode).

[0077] One end of the terminal pin 49 is bonded to the Al electrode film 47 via a plating film 48 and a solder layer (not shown). The other end of the terminal pin 49 is bonded to a metal bar (not shown) positioned opposite the front surface of the semiconductor substrate 10. The other end of the terminal pin 49 is exposed to the outside of the case (not shown) on which the semiconductor substrate 10 is mounted and is electrically connected to an external device (not shown). The terminal pin 49 is soldered to the plating film 48 while standing approximately perpendicular to the front surface of the semiconductor substrate 10.

[0078] The terminal pin 49 is a round rod-shaped (cylindrical) wiring member having a predetermined diameter corresponding to the current capability of the MOSFET, and is connected to the external ground potential (lowest potential). The terminal pin 49 is an external connection terminal that extracts the potential of the Al electrode film 47 to the outside. The first and second protective films 50 and 51 are heat-resistant organic polymer material films, such as polyimide. The first protective film 50 covers the portion of the surface of the Al electrode film 47 other than the plating film 48. The first protective film 50 is a passivation film that protects the front surface of the semiconductor substrate 10.

[0079] The portion of the Al electrode film 47 exposed to the opening of the first protective film 50 becomes the source pad. The second protective film 51 covers the boundary between the plating film 48 and the first protective film 50. The drain electrode (second electrode) 52 is on the back surface (n) of the semiconductor substrate 10. + The entire back surface of the starting substrate 11 is in ohmic contact, + Type drain region 31(n + It is electrically connected to the starting substrate 11). A drain pad (electrode pad: not shown) is provided on the drain electrode 52 in a laminated structure in which, for example, a Ti film, a nickel (Ni) film, and a gold (Au) film are stacked in order.

[0080] By bonding terminal pins 49 to the Al electrode film 47 on the front surface of the semiconductor substrate 10 and bonding the drain pad on the back surface to the metal base plate of the insulating substrate, the semiconductor substrate 10 has a double-sided cooling structure with cooling structures on both main surfaces. Heat generated in the semiconductor substrate 10 is dissipated from the fin portion of the cooling fins via the metal base plate bonded to the drain pad on the back surface of the semiconductor substrate 10, and also from the metal bar to which the terminal pins 49 on the front surface of the semiconductor substrate 10 are bonded.

[0081] The operation of the semiconductor device 30 according to Embodiment 1 will now be described. When a positive voltage (forward voltage) is applied to the drain electrode 52 with respect to the source electrode (Al electrode film 47), and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 39, a channel (n-type inversion layer) is formed in the portion of the p-type base region 34 along the trench 37. As a result, n + From the drain region 31 through the channel n + A current (drift current) flows towards the source region 35, and the MOSFET turns on.

[0082] The impurity concentration in the p-type low-concentration region 61 facing the bottom surface of trench 37 is the same as the first p-type region facing the bottom surface of trench 237 in the conventional structure (see Figures 17-21). + Impurity concentration in the high-concentration region 261 (e.g., 5.0 × 10) 18 / cm 3 Lower than the degree. The first p of the conventional structure. + Compared to the first p-type high-concentration region 261, the p-type low-concentration region 61 formed by low-dose ion implantation has a narrower extension in the second direction Y by 0.15 μm on each side. Therefore, the width of the p-type low-concentration region 61 is less than that of the first p-type in the conventional structure. + Compared to the high-concentration region 261, it is 0.3 μm narrower in total.

[0083] Between the adjacent p-type low-concentration regions 61 and 65, the portion where the p-type low-concentration connecting portion 63 is formed is n when the MOSFET is turned on. + From the drain region 31 through the channel n +This does not create a path for current flowing toward the p-type source region 35. As the width of the p-type low concentration region 61 is narrowed, the width between adjacent p-type low concentration regions 61 and p-type low concentration regions 65 is widened, which allows the resistance value of the JFET resistance, an internal resistance formed between them, to be lowered, thereby reducing the on-resistance.

[0084] Alternatively, if the width between adjacent p-type low-concentration regions 61 and p-type low-concentration regions 65 is maintained, the unit cell size can be reduced by the amount by which the width of the p-type low-concentration region 61 is narrowed, and the unit cell density of the active region 1 can be increased while maintaining the area (surface area) of the active region 1. Therefore, the on-resistance can be reduced by increasing the unit cell density of the active region 1 while maintaining the resistance value of the JFET resistor formed between adjacent p-type low-concentration regions 61 and p-type low-concentration regions 65.

[0085] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 39, the p-type low concentration region 61, the p-type low concentration region 65, the p-type low concentration connecting portion 63, and p + type high concentration region 62, p + Type high concentration region 64 and p-type base region 34, and n-type current diffusion region 33 and n - The pn junction (main junction) is reverse-biased between the pn drift region 32 and the pn junction, preventing current flow and keeping the MOSFET in the off state. Furthermore, the pn junction is reverse-biased by the p-type low concentration region 61, p-type low concentration region 65, p-type low concentration connecting portion 63 and p + A depletion layer extends across the high-concentration region 62.

[0086] This depletion layer is between the bottom of trench 37 and the p-type low-concentration region 61. +The impurities are less likely to spread into the high-concentration p-type region 64. Therefore, even if the impurity concentration in the low-concentration p-type region 61 is low, the electric field applied to the gate insulating film 38 at the bottom of the trench 37 can be relaxed. Furthermore, by narrowing the spacing w2 between the p-type low-concentration connecting portions 63 that connect adjacent p-type low-concentration regions 61 to, for example, 3 μm or less, the total amount of p-type impurities per predetermined area near the bottom of the trench 37 becomes higher in a narrow range of approximately 3 μm or less in the first direction X, making it less likely for the p-type low-concentration region 61 to be depleted, and thus further relaxing the electric field applied to the gate insulating film 38 at the bottom of the trench 37.

[0087] Furthermore, when the MOSFET is off, a negative voltage is applied to the drain electrode 52 relative to the source electrode, thereby creating a p-type low-concentration region 61, a p-type low-concentration region 65, a p-type low-concentration connecting portion 63, and p + type high concentration region 62, p + Type high concentration region 64 and p-type base region 34, and n-type current diffusion region 33 and n - A forward current can be passed through the drift region 32 and the parasitic diode formed by the pn junction. For example, if the MOSFET is an inverter device, a parasitic diode built into the semiconductor substrate 10 can be used as a freewheeling diode to protect the MOSFET itself.

[0088] Next, a method for manufacturing the semiconductor device 30 according to Embodiment 1 will be described. Figures 7 to 12 are cross-sectional views showing the semiconductor device according to Embodiment 1 in the process of manufacturing. Figures 7 to 12 show the state of the cross-sectional structure at the cutting line A1-A1' in Figure 6 (the cross-sectional structure corresponding to Figure 2) in the process of manufacturing. The state of the cross-sectional structure at the cutting lines A2-A2', B1-B1', and B2-B2' in Figure 6 in the process of manufacturing is omitted from the illustration, but please refer to the corresponding Figures 3 to 5.

[0089] First, as shown in Figure 7, n made of silicon carbide + Prepare a starting substrate (starting wafer) 11. Next, n + On the front surface of the mold starting substrate 11, n +n-type impurities such as nitrogen (N) are doped at a lower impurity concentration than the n-type starting substrate 11. - The type epitaxial layer 12a(12) is epitaxially grown. - The thickness t11 of the type epitaxial layer 12a is, for example, about 30 μm when the withstand voltage is 3300 V class, and for example, about 10 μm when the withstand voltage is 1200 V class.

[0090] Next, as shown in Figure 8, photolithography and ion implantation of p-type impurities such as Al were performed in the active region 1. - A p-type low-concentration region 61, a p-type low-concentration region 65, and a p-type low-concentration connecting portion 63 (see Figure 3) are selectively formed on the surface region of the type epitaxial layer 12a. Next, by photolithography and ion implantation of p-type impurities such as Al, n-type impurities are formed in the active region 1. - In the surface region of the type epitaxial layer 12a, p + p, which is part of the high-concentration region 62 + A type region 81 is selectively formed.

[0091] Next, by photolithography and ion implantation of p-type impurities such as Al, p is implanted into the surface region of the low-concentration p-type region 61. + A high-concentration region 64 of type n is formed. Next, by photolithography and ion implantation of n-type impurities such as nitrogen, n - An n-type region 82 is formed on the surface region of the n-type epitaxial layer 12a, which becomes part of the n-type current diffusion region 33. - p-type low-concentration region 61, p-type low-concentration region 65, p-type low-concentration connecting portion 63, p + type high concentration region 64, p + The part excluding the type region 81 and the n-type region 82 is n - This results in a drift region of 32.

[0092] p-type low concentration region 61, p-type low concentration region 65, p-type low concentration connection portion 63, p + type high concentration region 64, p + The formation order of the type region 81 and the n-type region 82 is interchangeable. For example, p +Type high concentration region 64 and p + After simultaneously forming the type region 81, p + Type high concentration region 64 and p + The portion of the ion implantation mask used to form the p-type region 81 corresponding to the formation region of the p-type low-concentration connecting portion 63 is removed and opened. By using this ion implantation mask to form the p-type low-concentration region 61, the p-type low-concentration region 65, and the p-type low-concentration connecting portion 63, p + The high-concentration region 64 and the low-concentration region 61 of the p-type can be formed in the same position in a self-aligned manner, and p + The p-type region 81 and the p-type low-concentration region 65 can be formed in the same position in a self-aligned manner.

[0093] In the process up to this point, the p-type low-concentration regions 61 and p-type low-concentration regions 65 are alternately arranged in the second direction Y, and adjacent p-type low-concentration regions 61 and p-type low-concentration regions 65 are connected by the p-type low-concentration connecting portion 63. On the surface area of ​​the p-type low-concentration region 61, a p-type low-concentration region with the same width as the p-type low-concentration region 61 is formed. + A p-type high-concentration region 64 is formed. On the surface region of the p-type low-concentration region 65, a p-type low-concentration region 65 with the same width as the p-type low-concentration region 65 is formed. + A type region 81 is formed. - When viewed from the surface side of the type epitaxial layer 12a, the p-type low-concentration region 61, the p-type low-concentration region 65, and the p-type low-concentration connecting portion 63 are arranged in a grid pattern surrounding the n-type region 82 which is arranged in a matrix pattern. Then, the p-type low-concentration region 61 and the p-type low-concentration region 65 are respectively placed on top of the p-type low-concentration region 61 and the p-type low-concentration region 65. + Type high concentration region 64 and p + The mold region 81 forms a stripe-like pattern extending in the first direction X.

[0094] The distance between adjacent p-type low-concentration regions 61 and 65 is, for example, about 0.5 μm to 1.5 μm. As described above, the p-type low-concentration region 61 is formed to a depth d1 (see Figure 2) of, for example, about 0.7 μm to 1.1 μm from the bottom surface of the trench 37 formed in a later step. As described above, the impurity concentration of the p-type low-concentration region 61 is, for example, 3 × 10⁻⁶. 17 / cm3 The above 9 x 10 17 / cm 3 The following is the extent to which the spacing w2 between adjacent p-type low-concentration connecting portions 63 in the first direction X should be, for example, 3 μm or less.

[0095] Here, the p-type low-concentration connecting portion 63 is formed simultaneously with the p-type low-concentration region 61 and the p-type low-concentration region 65. However, the p-type low-concentration connecting portion 63 only needs to be formed with approximately the same impurity concentration as the p-type low-concentration region 61 and the p-type low-concentration region 65, and may be formed at a different timing than the p-type low-concentration region 61 and the p-type low-concentration region 65. The n-type region 82 is formed to a depth d1 (see Figure 2) of approximately 0.7 μm to 1.1 μm from the bottom surface of the trench 37 formed in a later step. The impurity concentration of the n-type region 82 is, for example, 3 × 10⁻¹⁶. 17 / cm 3 The above 9 x 10 17 / cm 3 It is approximately as follows.

[0096] Next, as shown in Figure 9, n - An n-type impurity, such as nitrogen, is further doped onto the n-type epitaxial layer 12a. - The type epitaxial layer 12b(12) is epitaxially grown to a thickness t12 of, for example, 0.5 μm, n - The type epitaxial layer 12 (12a, 12b) is made to a predetermined thickness. - The impurity concentration of the type epitaxial layer 12 is, for example, 3 × 10⁻⁶. 15 / cm 3 To that extent. Next, by photolithography and ion implantation of p-type impurities such as Al, n - In the type epitaxial layer 12b, p + p, which is part of the high-concentration region 62 + A type region 83 is formed.

[0097] Next, by photolithography and ion implantation of n-type impurities such as nitrogen, - An n-type region 84 is formed in the type epitaxial layer 12b, which becomes part of the n-type current diffusion region 33. +Type regions 81 and 83 are connected to each other, p + A high-concentration n-type region 62 is formed. Adjacent n-type regions 82 and 84 in the depth direction Z are connected to form an n-type current diffusion region 33. + The conditions such as the impurity concentration in the type region 83 and the n-type region 84 are, for example, p + This is similar to type region 81 and n-type region 82. + The formation order of the type region 83 and the n-type region 84 may be reversed.

[0098] Next, as shown in Figure 10, n - A p-type epitaxial layer 13 doped with p-type impurities, such as aluminum, is epitaxially grown on a p-type epitaxial layer 12. The thickness t13 and impurity concentration of the p-type epitaxial layer 13 are, for example, about 1.3 μm and 4 × 10⁻¹⁶, respectively. 17 / cm 3 To that extent. Up to this point, n + A semiconductor substrate (semiconductor wafer) 10 is completed by sequentially stacking epitaxial layers 12 and 13 on a mold starting substrate 11.

[0099] Next, photolithography and ion implantation of n-type impurities such as phosphorus (P) are performed on the surface region of the p-type epitaxial layer 13. + A p-type source region 35 is selectively formed. Next, by photolithography and ion implantation of p-type impurities such as aluminum, p-type impurities are implanted into the surface region of the p-type epitaxial layer 13. ++ A type contact region 36 is selectively formed. ++ The type contact region 36 has a p-shaped lower surface. + It may be formed in contact with the p-type high-concentration region 62. The portion of the p-type epitaxial layer 13 that remains p-type without ion implantation becomes the p-type base region 34. + Type source region 35 and p ++ The formation order of the type contact region 36 is interchangeable.

[0100] The diffusion regions formed by ion implantation may be formed by multi-stage ion implantation, in which a predetermined dose is implanted in multiple stages under different conditions. Next, a heat treatment (hereinafter referred to as activation annealing) is performed to activate the impurities implanted in the epitaxial layers 12 and 13. Activation annealing may be performed all at once after all diffusion regions have been formed, or it may be performed each time a diffusion region is formed by ion implantation. The temperature and time of activation annealing may be, for example, about 1700°C and about 2 minutes, respectively.

[0101] This activated annealing allows all diffusion regions formed by ion implantation (n-type current diffusion region 33, p-type low concentration region 61, p-type low concentration region 65, p-type low concentration connecting region 63, p + type high concentration region 62, p + type high concentration region 64, n + Type source region 35 and p ++ In the contact region 36), impurities are activated, and impurity diffusion occurs according to Gauss's law, corresponding to the respective impurity concentrations and diffusion coefficients.

[0102] Next, as shown in Figure 11, photolithography and, for example, dry etching are used to remove material from the front surface of the semiconductor substrate 10 in the depth direction Z. + The p-type source region 35 and the p-type base region 34 penetrate through the p-type source region 35 and in the depth direction Z. + A trench 37 is formed at a position opposite the high-concentration region 64. The trench 37 is p + It may terminate at a position shallower than the high-concentration region 64, or p + The high concentration region 64 may also be reached.

[0103] Next, as shown in Figure 12, along the front surface of the semiconductor substrate 10 and the inner wall (side wall and bottom surface) of the trench 37, n +A gate insulating film 38 is formed in contact with the p-type source region 35, the p-type base region 34, and the n-type current diffusion region 33. The gate insulating film 38 may be, for example, a thermal oxide film formed by thermal oxidation of the semiconductor surface at a temperature of about 1000°C in an oxygen (O2) atmosphere, or it may be a deposited film by high-temperature oxidation (HTO).

[0104] Next, a polysilicon (poly-Si) layer, for example, a phosphorus (P)-doped layer, is deposited (formed) on the front surface of the semiconductor substrate 10 so as to be embedded inside the trench 37. Then, this polysilicon layer is selectively removed, leaving only the portion that will become the gate electrode 39 inside the trench 37.

[0105] Next, an interlayer insulating film 40, such as BPSG (Boro Phospho Silicate Glass) or PSG, is formed on the entire front surface of the semiconductor substrate 10 to cover the gate electrode 39, with a thickness of, for example, 1 μm. Then, a contact hole 40a is formed in the depth direction Z by photolithography and etching, penetrating the interlayer insulating film 40 and the gate insulating film 38. In this contact hole 40a, n + Type source region 35 and p ++ The mold contact area 36 is exposed. Next, the interlayer insulating film 40 is planarized (reflow) by heat treatment.

[0106] Next, a first TiN film 42 is formed in the active region 1, covering only the interlayer insulating film 40. Then, by a general method, a NiSi film 41 is formed inside the contact hole 40a of the interlayer insulating film 40, making ohmic contact with the front surface of the semiconductor substrate 10. In addition, a NiSi film is formed as a drain electrode 52, making ohmic contact with the back surface of the semiconductor substrate 10. The NiSi film is formed by reacting a nickel film with the semiconductor substrate 10, for example, by heat treatment at a temperature of 970°C.

[0107] Next, by sputtering, a first Ti film 43, a second TiN film 44, and a second Ti film 45 are sequentially deposited to cover the NiSi film 41 and the first TiN film 42, forming a barrier metal 46 that covers almost the entire surface of the active region 1. Next, an Al electrode film 47 is deposited on the second Ti film 45. Simultaneously with the Al electrode film 47, a gate pad (not shown) is formed on the interlayer insulating film 40, separate from the Al electrode film 47. Next, a drain pad (not shown) is formed on the surface of the drain electrode 52 by sequentially depositing, for example, a Ti film, a Ni film, and a gold (Au) film.

[0108] Next, a first protective film 50 made of an organic polymer material such as polyimide is formed on the entire front surface of the semiconductor substrate 10, and the Al electrode film 47 and gate pad are covered with the first protective film 50. Next, the first protective film 50 is selectively removed to expose the Al electrode film 47 (source pad) and gate pad in different openings, respectively. Next, after general pre-plating treatment, a plating film 48 is formed in each opening of the first protective film 50 by general plating treatment. Next, the plating film 48 is dried by heat treatment (bake).

[0109] Next, a second protective film 51 made of an organic polymer material such as polyimide is formed to cover the boundary between the plating film 48 and the first protective film 50. Next, the strength of the first and second protective films 50 and 51 is improved by heat treatment (curing). Then, terminal pins 49 are bonded to the plating film 48 by solder layers. A wiring structure is also formed on the gate pad by bonding terminal pins in the same way as on the Al electrode film 47. After that, the semiconductor wafer (semiconductor substrate 10) is diced (cut) to separate it into individual chips, thereby completing the MOSFETs shown in Figures 1 to 6.

[0110] As explained above, according to Embodiment 1, the impurity concentration of the p-type low-concentration region facing the bottom surface of the trench is low, so that the p-type low-concentration region can be formed with a low dose of ion implantation, and the width of the p-type low-concentration region can be narrowed. By the amount that the width of the p-type low-concentration region is narrowed, the resistance value of the JFET resistor, which is the internal resistance of the semiconductor substrate, can be lowered, and thus the on-resistance can be reduced. Alternatively, by the amount that the width of the p-type low-concentration region is narrowed, the unit cell can be reduced, and the unit cell density can be increased. Therefore, while maintaining the resistance value of the JFET resistor, the unit cell density of the active region can be increased, and the on-resistance can be reduced.

[0111] Furthermore, according to Embodiment 1, the depletion layer extending from the main junction (pn junction) of the active region when off is between the bottom surface of the trench and the p-type low-concentration region. + It is difficult for the p-type impurities to spread into the high-concentration region. Therefore, even if the impurity concentration in the low-concentration p-type region is low, the electric field applied to the gate insulating film at the bottom of the trench can be relaxed. Furthermore, according to Embodiment 1, by narrowing the distance between the p-type low-concentration connecting portions that connect adjacent p-type low-concentration regions to about 3 μm or less, the total p-type impurity concentration per predetermined area near the bottom of the trench becomes high in a narrow range of about 3 μm or less in the first direction, and the p-type low-concentration region is less likely to be depleted. Therefore, the electric field applied to the gate insulating film at the bottom of the trench can be further relaxed.

[0112] Furthermore, according to Embodiment 1, the manufacturing method of a conventional semiconductor device (see Figures 17-21) can be applied. Specifically, the p-type low-concentration region and the p-type low-concentration connecting portion of Embodiment 1 are the first p-type of a conventional semiconductor device. + Type high concentration region and p + The impurity concentration of the high-concentration coupling section and p + It can be easily formed by simply changing the pitch of the high-concentration p-type connecting portion. Furthermore, according to Embodiment 1, by optimizing the impurity concentration of the p-type low-concentration region and the p-type low-concentration connecting portion, and the pitch of the p-type low-concentration connecting portion, the electric field applied to the gate insulating film at the bottom of the trench is mitigated. This makes semiconductor device design easier.

[0113] (Embodiment 2) The structure of the semiconductor device according to Embodiment 2 will now be described. Figure 13 is a cross-sectional view showing a part of the structure of the semiconductor device according to Embodiment 2. The layout of the semiconductor device 90 according to Embodiment 2, as viewed from the front side of the semiconductor substrate 10, is the same as in Figure 1. In the semiconductor device 90 according to Embodiment 2, p + Instead of the high-concentration region 62 (see Figure 2), p + The p-type high-concentration connecting portion 91 electrically connects the p-type low-concentration region 61 and the p-type low-concentration connecting portion 63 to the p-type base region 34. The semiconductor device 90 according to Embodiment 2 is shown in Figures 3 and 6. + The structure has the following configurations: one in which the p-type high-concentration region 62 (shown only in Figure 3) and the p-type low-concentration region 65 are removed and the cell pitch is narrowed; the structure shown in Figure 4; and the structure shown in Figure 13. Figure 13 corresponds to the cross-sectional structure at the cutting line A1-A1' when the p-type low-concentration region 65 is removed and the cell pitch is narrowed from Figure 6. Specifically, the semiconductor device 90 according to Embodiment 2 differs from the semiconductor device 30 according to Embodiment 1 (see Figure 2) in the following two points.

[0114] The first difference is that there is no p-type region (corresponding to reference numerals 62 and 65 in Figure 2) between adjacent trenches 37 to mitigate the electric field applied to the gate insulating film 38 at the bottom of the trenches 37 (see Figure 13). Therefore, p ++ The p-type contact region 36 does not need to reach the bottom surface of the p-type base region 34 (not shown). As described above, the p-type low-concentration region 61 facing the trench 37 is formed by low-dose ion implantation, making it difficult for impurities to diffuse, thus allowing the cell pitch to be narrowed. When the cell pitch is sufficiently narrowed, the p-type low-concentration region 61, the p-type low-concentration connecting portion 63 and p + In the high-concentration region 64 only, the electric field applied to the gate insulating film 38 at the bottom of the trench 37 is sufficiently relaxed. Also, between adjacent trenches 37, p + By eliminating the high-concentration region, the cell pitch can be further narrowed.

[0115] The second difference is, p + Type high concentration region 64 is p + The p-type base region 34 is connected at a predetermined location by a type high-concentration connecting portion (first high-concentration region) 91 (see Figure 13). + The p-type high-concentration connecting section 91 connects the p-type low-concentration region 61 and the p + The high-concentration region 64 is fixed at the potential of the source electrode. + The high-concentration type connecting portion 91 is arranged at points in the first direction X, in contact with the gate insulating film 38 on one side wall of the trench 37 (not shown). + The high-concentration type connecting section 91 is located along one side wall of the trench 37, p + It extends from the high-concentration region 64 of the type to the p-type base region 34, + The high-concentration region 64 and the p-type base region 34 are connected. The other side wall of the trench 37 is p + A high-concentration type connecting section 91 is not provided.

[0116] p + The portion where the p-type high-concentration connecting portion 91 is formed does not become a current path when the MOSFET is turned on, similar to the portion where the p-type low-concentration connecting portion 63 is formed. Only one side wall of the trench 37 is p + By providing the high-concentration connecting section 91, it is possible to suppress the reduction in channel area. + The p-type high-concentration connecting portion 91 may be positioned at a different location from the p-type low-concentration connecting portion 63 in the first direction X, or it may be positioned in contact with the p-type low-concentration connecting portion 63. Between adjacent trenches 37, + The spacing between the type high-concentration connecting portions 91 scattered in the first direction X may be wider than the spacing w2 between the p-type low-concentration connecting portions 63 scattered in the first direction X. + The high-concentration connecting section 91 is p + It may also be part of the high-concentration region 64. + The high-concentration type connecting portion 91 may be arranged in a stripe-like pattern extending in the first direction X along the side wall of the trench 37.

[0117] The method for manufacturing the semiconductor device 90 according to Embodiment 2 is the same as the method for manufacturing the semiconductor device 30 according to Embodiment 1, p + The process of forming the high-concentration region 62 and the low-concentration region 65 of the p-type is omitted, and n is formed by photolithography and ion implantation of p-type impurities such as Al. - p + A step of selectively forming the molded high-concentration connecting portion 91 can be added.

[0118] As explained above, according to Embodiment 2, by narrowing the cell pitch, p near the bottom surface of the trenches between adjacent trenches + The same effects as in Embodiment 1 can be obtained without providing a high-concentration region.

[0119] (Embodiment 3) As Embodiment 3, the structure of the edge termination region 2 and intermediate region 3 of the semiconductor device 30 according to Embodiment 1 will be described. Figure 14 is a cross-sectional view showing the cross-sectional structure at the cutting line C-C' in Figure 1. As shown in Figure 14, on the front surface of the semiconductor substrate 10, a step 53 is formed by etching away the portion of the edge termination region 2 of the p-type epitaxial layer 13. The front surface of the semiconductor substrate 10 is divided by the step 53, with the portion of the edge termination region 2 (hereinafter referred to as the second surface) 10b being more densely packed than the portion of the active region 1 and intermediate region 3 (hereinafter referred to as the first surface) 10a. + It is recessed on the drain region 31 side.

[0120] The second surface 10b of the front surface of the semiconductor substrate 10 is exposed by the formation of a step 53. - This is the exposed surface of the p-type epitaxial layer 12. When the step 53 is formed, the p-type epitaxial layer 13 is formed together with the lower n-type epitaxial layer 13. -The surface region of the type epitaxial layer 12 may be slightly removed. At the portion (hereinafter referred to as the third surface: mesa edge of the step 53) 10c connecting the first surface 10a and the second surface 10b of the front surface of the semiconductor substrate 10, the active region 1, the intermediate region 3, and the edge termination region 2 are element-separated. The third surface 10c of the front surface of the semiconductor substrate 10 is the side surface of the p-type epitaxial layer 13 exposed by the formation of the step 53.

[0121] In the intermediate region 3 and the edge termination region 2, the first to third surfaces 10a to 10c of the front surface of the semiconductor substrate 10 are covered with an insulating layer in which a field oxide film 71 and an interlayer insulating film 40 are laminated in this order. At the outer periphery of the active region 1, contact holes 40b are provided in a substantially rectangular shape surrounding the active region 1 in the field oxide film 71 and the interlayer insulating film 40. In the contact holes 40b, ++ the outer peripheral p ++ type contact region 36a is exposed, and a NiSi film 41 that makes an ohmic contact with the outer peripheral p

[0122] In the intermediate region 3, on the field oxide film 71, a gate polysilicon wiring layer 72 and a gate metal wiring layer 73 serving as a gate runner are laminated in this order outside the contact holes 40b. The gate polysilicon wiring layer 72 and the gate metal wiring layer 73 surround the active region 1 in a substantially rectangular shape. The gate polysilicon wiring layer 72 faces the end of the trench 37 in the depth direction Z and contacts the gate electrode 39 at the end of the trench 37. Through the gate polysilicon wiring layer 72 and the gate metal wiring layer 73, all the gate electrodes 39 are electrically connected to a gate pad (not shown).

[0123] In the intermediate region 3, a p-type base region 34 extends from the active region to reach the third surface 10c of the front surface of the semiconductor substrate 10. The p-type base region 34 is provided over the entire active region 1 and intermediate region 3. The outer peripheral portion (hereinafter referred to as the outer peripheral p-type base region) 34a of the p-type base region 34 surrounds the periphery of the active region 1 in a substantially rectangular shape. The outer peripheral p-type base region 34a is the portion of the p-type base region 34 that is outside the n + -type source region 35 in the first direction X (the longitudinal direction of the trench 37), and is also the portion outside the outermost trench 37 in the second direction Y (the lateral direction of the trench 37).

[0124] Over the entire area between the first surface 10a of the front surface of the semiconductor substrate 10 and the outer peripheral p-type base region 34a, a p ++ -type contact region 36 (hereinafter referred to as the outer peripheral p ++ -type contact region 36a) is provided in contact with the outer peripheral p-type base region 34a. FIG. 14 shows a case where the depth of the p ++ -type contact region 36 is shallower than the depth of the p-type base region 34. The outer peripheral p ++ -type contact region 36a is exposed on the first surface 10a of the front surface of the semiconductor substrate 10. Here, being exposed on the first surface 10a of the front surface of the semiconductor substrate 10 means that the outer peripheral p ++ -type contact region 36a contacts the NiSi film 41 through the outermost contact hole 40b of the interlayer insulating film 40. The outer peripheral p ++ -type contact region 36a surrounds the periphery of the active region 1 in a substantially rectangular shape.

[0125] The outer peripheral p ++ -type contact region 36a contacts the gate insulating film 38 on the outer sidewall of the outermost trench 37. The outer peripheral p ++ -type contact region 36a has a function of drawing out the holes accumulated in the edge termination region 2 during the switching of the MOSFET or the like to the source electrode through the outer peripheral p + -type region 62a and the outer peripheral p-type base region 34a when the MOSFET is turned off. The outer peripheral p ++ -type contact region 36a may not be provided. In this case, the outer peripheral p ++Instead of the type contact region 36a, the outer peripheral p-type base region 34a reaches and is exposed on the first surface 10a of the front surface of the semiconductor substrate 10.

[0126] Apart from the outermost trench 37 and adjacent to the outermost p-type base region 34a in the depth direction Z, there is a p-type low-concentration region (hereinafter referred to as the outermost p-type low-concentration region) 65a and p + Mold high concentration area (hereinafter referred to as outer periphery p + A mold region (62a) is provided. Outer circumference p + The p-type region 62a and the outer p-type low-concentration region 65a surround the active region 1 in a roughly rectangular shape. + Type region 62a is all p + The edges of the high-concentration region 64 and all p + The outer edge of the p-type high-concentration region 62 is in contact with the edge of the p-type low-concentration region 61 and the edge of the p-type low-concentration region 65. The outer edge of the p-type low-concentration region 65a is in contact with the edge of the p-type high-concentration region 62. + It is provided so as to be in contact with the lower surface of the mold region 62a. Outer circumference p + The mold region 62a may extend outward beyond the step 53 and be exposed to the second surface 10b of the front surface of the semiconductor substrate 10. Exposure to the second surface 10b of the front surface of the semiconductor substrate 10 means contact with the field oxide film 71 on the second surface 10b.

[0127] In the edge termination region 2, the surface region (n) of the second surface 10b of the front surface of the semiconductor substrate 10 - Multiple FLRs 23 of the same structure with a floating potential constituting the FLR structure 20 are provided apart from each other in the surface region of the epitaxial layer 12, and outside of them, away from the FLR structure 20, n + A channel stopper region 24 is provided. Multiple FLRs 23 are located on the outer periphery p + Outside the type region 62a and the outer peripheral p-type low concentration region 65a, the outer peripheral p + Type region 62a and outer p-type low-concentration region 65a and n + The intermediate region 3 is provided at a distance from the channel stopper region 24 and concentrically surrounds the active region 1.

[0128] The innermost FLR23 and the outermost p + Between type region 62a, between adjacent FLR23s, and between the outermost FLR23 and n + The distance between the channel stopper region 24 and the channel stopper region is n - This is the type drift region 32. FLR23 may consist of a p-type low-concentration region 61, a p-type low-concentration region 65, or a p-type low-concentration region 21 (hatched portion) formed simultaneously with the p-type low-concentration connecting portion 63. By forming FLR23 simultaneously with the p-type low-concentration region 61 of the active region 1, it is not necessary to perform the process for forming the FLR structure 20 separately, thus simplifying the manufacturing process.

[0129] FLR23 consists of a p-type low-concentration region 21 formed simultaneously with the p-type low-concentration region 61, the p-type low-concentration region 65, or the p-type low-concentration connecting portion 63, and p + Type high concentration region 62 or p + The high-concentration region 64 and the p formed simultaneously + The high-concentration region 22 may also be a two-layer structure. Whether the FLR23 is a one-layer or two-layer structure, the upper end of the FLR23 (the end on the second surface 10b side of the front surface of the semiconductor substrate 10) may be exposed to the second surface 10b of the front surface of the semiconductor substrate 10, or it may be at a depth position away from the second surface 10b of the front surface of the semiconductor substrate 10 (for example, n - It may be located at the same depth as the upper surface of the type epitaxial layer 12a.

[0130] n + The channel stopper region 24 is located outside the FLR structure 20, and is separated from the FLR structure 20. + The channel stopper region 24 is exposed on the second surface 10b of the front surface of the semiconductor substrate 10. + The channel stopper region 24 is exposed at the edge of the semiconductor substrate 10. + By providing a channel stopper region 24, n + Compared to the case where the channel stopper region 24 is not provided, n when the MOSFET is turned off -The depletion layer extending outward from the active region 1 within the drift region 32 can be suppressed. A channel stopper electrode (not shown) is not provided.

[0131] When the MOSFET is off, FLR23 and n - The high voltage applied to the edge termination region 2 is borne by the pn junction with the drift region 32. Specifically, when the MOSFET is off, the depletion layer that extends from the main junction (pn junction) of the active region 1 is FLR23 and n - The pn junction with the drift region 32 causes the edge termination region 2 to extend outward in the normal direction (towards the tip end). The amount by which the depletion layer extends outward in the edge termination region 2 ensures a predetermined withstand voltage based on the dielectric breakdown field strength of silicon carbide and the width of the depletion layer (the width in the direction from the active region 1 towards the tip end (the normal direction of the concentrically arranged FLR23)).

[0132] The method for manufacturing the semiconductor device 90 according to Embodiment 3 is the same as the method for manufacturing the semiconductor device 30 according to Embodiment 1 (see Figures 7-12), but further includes FLR23 and n in the edge termination region 2. + A p-type channel stopper region 24 is formed, and a gate polysilicon wiring layer 72 and a gate metal wiring layer 73 are formed in the intermediate region 3. The p-type low-concentration region 21 constituting the FLR23 is formed in the same way as the p-type low-concentration region 61 (see Figure 8), p-type low-concentration region 65 (see Figure 8), and p-type low-concentration connecting portion 63 (see Figure 3) of the active region 1. - It can be formed on the type epitaxial layer 12a.

[0133] The components of FLR23 + The high-concentration region 22 is the p of the active region 1. + Type high concentration region 64 and simultaneously n - Formed in the type epitaxial layer 12a, or in the p of the active region 1 + Type high concentration region 62 and simultaneously n - The layer can be formed on the type epitaxial layer 12b, or both. +The channel stopper region 24 is formed by the creation of a step 53, which exposes the n on the second surface 10b of the front surface of the semiconductor substrate 10 in the edge termination region 2. - The n of the active region 1 is present in the surface region of the type epitaxial layer 12. + The type source region 35 may be formed at the same time.

[0134] Perimeter p ++ Type contact area 36a, outer p-type base area 34a, outer p-type low concentration area 65a and outer p + Each of the type regions 62a is p of the active region 1. ++ Type-type contact area 36, ​​p-type base area 34, p-type low-concentration area 65 and p + It should be formed simultaneously with the high-concentration region 62. + Type source area 35, p ++ Type contact area 36 and outer circumference p ++ The type contact region 36a may be formed before the step 53 is formed. The third surface 10c of the front surface of the semiconductor substrate 10 may be obtuse (inclined) or approximately right (vertical) with respect to the first and second surfaces 10a and 10b, for example. The step 53 may be formed by etching to form the trench 37.

[0135] A portion of the polysilicon layer deposited to form the gate electrode 39 may be left as the gate polysilicon wiring layer 72. When the gate electrode 39 and the gate polysilicon wiring layer 72 are formed simultaneously, the field oxide film 71 is formed after the formation of the gate insulating film 38 and before the deposition of the polysilicon layer. Although not shown in Figure 14, the gate insulating film 38 may remain between the front surface of the semiconductor substrate 10 and the field oxide film 71. The contact holes in which the gate polysilicon wiring layer 72 is exposed may be formed simultaneously with the contact holes 40a and 40b. The gate metal wiring layer 73 may be formed simultaneously with the Al electrode film 47.

[0136] The edge termination region 2 and intermediate region 3 of Figure 14 may be applied to the semiconductor device 90 (Figure 13) according to Embodiment 2.

[0137] As described above, according to Embodiment 3, the process of forming a p-type low-concentration region and a p-type low-concentration connecting portion near the bottom surface of the trench and the process of forming an FLR in the edge terminal region can be performed simultaneously, thus simplifying the manufacturing process.

[0138] (Example 1) The breakdown voltage and on-resistance of the semiconductor device 30 according to Embodiment 1 were verified. Figure 15 is a characteristic diagram showing the voltage-electric field characteristics of Embodiment 1. In Figure 15, the horizontal axis is the voltage between the source and drain, and the vertical axis is the electric field applied to the gate insulating film 38. Figure 15 shows the simulation results of the breakdown voltage of the semiconductor device 30 according to Embodiment 1 described above (see Figures 2-6: hereinafter referred to as Embodiment 1) and a comparative example. The comparative example is p + This embodiment differs from Example 1 in that it does not have a high-concentration region 64 and the spacing w2 between adjacent p-type low-concentration connecting portions 63 in the first direction X is wider than 3 μm.

[0139] As shown in Figure 15, the results confirm that in the comparative example, when a forward voltage is applied between the source and drain, and a voltage below the gate threshold voltage is applied to the gate electrode 39, the electric field across the gate insulating film 38 at the bottom of the trench 37 increases when the main junction (pn junction) of the active region is reverse-biased. In the comparative example, the p-type low-concentration region 61 facing the bottom of the trench 37 has a low impurity concentration, which causes the p-type low-concentration region 61 to be completely depleted, resulting in a high electric field across the gate insulating film 38 at the bottom of the trench 37.

[0140] On the other hand, in Example 1, compared to the comparative example, the electric field applied to the gate insulating film 38 at the bottom of the trench 37 could be relaxed, and it was confirmed that voltage-electric field characteristics (not shown) similar to those of a conventional semiconductor device (see Figures 17-21; hereinafter referred to as the conventional example) could be obtained. In Example 1, the depletion layer that spreads when the main junction of the active region is reverse-biased is the p between the bottom of the trench 37 and the p-type low-concentration region 61. +Because it is difficult for the high-concentration region 64 to spread inside, the electric field applied to the gate insulating film 38 at the bottom of the trench 37 can be mitigated.

[0141] Furthermore, by narrowing the spacing w2 between adjacent p-type low-concentration connecting portions 63 in the first direction X to, for example, 3 μm or less, the total p-type impurity concentration per predetermined area near the bottom surface of the trench 37 increases, making it less likely for the p-type low-concentration region 61 to be depleted. As a result, the electric field applied to the gate insulating film 38 at the bottom surface of the trench 37 can be further reduced. Therefore, in Example 1, even if the impurity concentration in the p-type low-concentration region 61 is low, the electric field applied to the gate insulating film 38 at the bottom surface of the trench 37 can be mitigated.

[0142] Figure 16 is a characteristic diagram showing the on-resistance (RonA) characteristics of Example 1. Figure 16 also shows the simulation results of the on-resistance of Example 1 and the conventional example described above. From the results shown in Figure 16, it was confirmed that Example 1 can reduce the on-resistance compared to the conventional example. The p-type low-concentration region 61 of Example 1 corresponds to the first p-type region of the conventional example. + Compared to the high-concentration region 261 of the p-type, it is formed with a low dose of ion implantation and its spread in the second direction Y is narrower. As a result, the adjacent p-type low-concentration regions 61 and p + This is because the resistance value of the JFET resistor between the high-concentration region 62 and the high-concentration region can be reduced.

[0143] (Embodiment 4) The structure of the semiconductor device according to Embodiment 4 will now be described. Figures 22 and 23 are cross-sectional views showing the structure of the semiconductor device according to Embodiment 4. Figures 22 and 23 show the cross-sectional structure at the cutting lines C1-C1' and C2-C2' in Figure 24, respectively. The overall layout of the semiconductor device 100 according to Embodiment 4, as viewed from the front side of the semiconductor substrate 10, is the same as in Figure 1.

[0144] FIG. 24 is a plan view showing an enlarged part of the active region of FIG. 1. FIG. 25 is a plan view showing an enlarged part of another example of the active region of FIG. 1. FIGS. 24 and 25 show the layouts of a p-type low-concentration region 101 (thick broken-line contour and dot hatching), a p-type low-concentration region 102 (thick broken-line contour and slanted hatching), and a p-type low-concentration connection portion 103 (thick solid-line contour and dot hatching).

[0145] The semiconductor device 100 according to Embodiment 4 is different from the semiconductor device 30 (see FIGS. 2 to 6) according to Embodiment 1 in the following three points. The first difference is that, as a p-type region having a function of relaxing the electric field applied to the gate insulating film 38 on the inner wall of the trench 37, p-type high-concentration regions 62 and 64 (see FIG. 2) are not provided, and only a p-type low-concentration region (first low-concentration region) 101 and a p-type low-concentration region (second low-concentration region) 102 are provided. + The second difference is that the lower surface (the end on the n-type drain region 31 side) of the p-type low-concentration region 102 between adjacent trenches 37 is at a shallow position separated from the lower surface of the p-type low-concentration region 101 facing the bottom surface of the trench 37 by a distance d100 of, for example, about 0.1 μm or more toward the n-type source region 35 side. The third difference is that the impurity concentration of the p-type low-concentration region 102 is, for example, about 10 times or more higher than the impurity concentration of the p-type low-concentration region 101.

[0146] The configurations of the p-type low-concentration regions 101 and 102 other than the depth (thickness), depth position, and impurity concentration are the same as those of the p-type low-concentration regions 61 and 65 (see FIG. 2) in Embodiment 1. The adjacent p-type low-concentration regions 101 are partially connected by a p-type low-concentration connection portion 103. The configuration of the p-type low-concentration connection portion 103 other than the depth, depth position, and impurity concentration is the same as that of the p-type low-concentration connection portion 63 (see FIG. 3) in Embodiment 1. + The lower surface (the end on the n-type drain region 31 side) of the p-type low-concentration region 102 between adjacent trenches 37 is at a shallow position separated from the lower surface of the p-type low-concentration region 101 facing the bottom surface of the trench 37 by a distance d100 of, for example, about 0.1 μm or more toward the n-type source region 35 side. The third difference is that the impurity concentration of the p-type low-concentration region 102 is, for example, about 10 times or more higher than the impurity concentration of the p-type low-concentration region 101. + The third difference is that the impurity concentration of the p-type low-concentration region 102 is, for example, about 10 times or more higher than the impurity concentration of the p-type low-concentration region 101.

[0147] The configurations of the p-type low-concentration regions 101 and 102 other than the depth (thickness), depth position, and impurity concentration are the same as those of the p-type low-concentration regions 61 and 65 (see FIG. 2) in Embodiment 1. The adjacent p-type low-concentration regions 101 are partially connected by a p-type low-concentration connection portion 103. The configuration of the p-type low-concentration connection portion 103 other than the depth, depth position, and impurity concentration is the same as that of the p-type low-concentration connection portion 63 (see FIG. 3) in Embodiment 1.

[0148] Specifically, the p-type low-concentration region 101 has the function of mitigating the electric field applied to the gate insulating film 38 at the bottom surface of the trench 37. The p-type low-concentration region 101 is connected to the p-type base region 34 and n - The p-type low-concentration region 101 is provided between the p-type drift region 32 and the p-type base region 34, and faces the bottom surface of the trench 37 in the depth direction Z. The p-type low-concentration region 101 extends linearly in the first direction X for a length approximately the same as the longitudinal length of the trench 37.

[0149] The lower surface of the p-type low-concentration region 101 is n greater than the bottom surface of the trench 37. + It is located deep on the drain region 31 side. The depth (distance) d101 from the bottom surface of the trench 37 to the bottom surface of the p-type low-concentration region 101 is, for example, about 0.7 μm to 1.1 μm. The p-type low-concentration region 101 is at approximately the same depth as the n-type current diffusion region 104, or is at a greater depth than the n-type current diffusion region 104. + It reaches a deep position on the drain region 31 side, n - It may be in contact with the drift region 32.

[0150] The width of the p-type low-concentration region 101 (width in the second direction Y) is wider than the width of the trench 37. The p-type low-concentration region 101 faces the bottom surface and bottom corners of the trench 37. The p-type low-concentration region 101 may be in contact with the gate insulating film 38 at the bottom surface and bottom corners of the trench 37. The impurity concentration of the p-type low-concentration region 101 is, for example, 1 × 10⁻⁶ 16 / cm 3 The above 8 x 10 16 / cm 3 It is approximately as follows.

[0151] The p-type low-concentration region 102 has the function of mitigating the electric field applied to the gate insulating film 38 on the side wall of the trench 37. The p-type low-concentration region 102 is provided between adjacent trenches 37, separated from the p-type low-concentration region 101 and the trenches 37. The p-type low-concentration region 102 extends linearly in the first direction X, with a length approximately the same as the longitudinal length of the trench 37, so as to penetrate the p-type low-concentration connecting portion 103.

[0152] The p-type low-concentration region 102 is p on the upper surface++ It is in contact with the p-type contact region 36 or the p-type base region 34 and is electrically connected to the p-type base region 34. The lower surface of the p-type low-concentration region 102 is n lower than the bottom surface of the trench 37. + It is located deep on the side of the p-type drain region 31. Also, the lower surface of the p-type low-concentration region 102 is n from the lower surface of the p-type low-concentration region 101. + It is located at a shallow position, for example, at a distance d100 of 0.1 μm or more, on the type source region 35 side.

[0153] The impurity concentration in the p-type low-concentration region 102 is about 10 times higher than the impurity concentration in the p-type low-concentration region 101, for example, 1 × 10⁻⁶ 17 / cm 3 The above 1 x 10 18 / cm 3 The extent is as follows. By setting the depth position and impurity concentration of the lower surface of the p-type low-concentration region 102 in this way, when the MOSFET (semiconductor device 30) is turned off, the lower surface corner portion of the p-type low-concentration region 102 (the boundary between the lower surface and the side surface) becomes the electric field concentration point in the active region 1.

[0154] As in the conventional structure (see Figures 17-20), the first p facing the trench 237 + The high-concentration region 261 and the second p between adjacent trenches 237 + When the high-concentration region 262 and the lower surface are at the same depth, when the MOSFET (semiconductor device 230) is turned off, the first p facing the trench 237 + Avalanche breakdown is likely to occur at the lower corner of the high-concentration region 261. Therefore, the large current amplified by the avalanche breakdown has a significant adverse effect on the trench gate structure.

[0155] In contrast, in Embodiment 4, when the MOSFET is off, the electric field concentrates at the lower corner of the p-type low-concentration region 102, which is away from the trench 37, and the inventors have confirmed that avalanche breakdown is likely to occur at the lower corner of the p-type low-concentration region 102. This prevents avalanche breakdown from occurring at the lower corner of the p-type low-concentration region 101 facing the trench 37, thereby reducing the adverse effects on the trench gate structure caused by the large current amplified by avalanche breakdown.

[0156] The p-type low-concentration connecting portion 103 has the function of mitigating the electric field applied to the gate insulating film 38 on the side wall of the trench 37. The p-type low-concentration connecting portion 103 is provided between adjacent trenches 37, in contact with the p-type low-concentration regions 101 and 102, and connects them. The p-type low-concentration connecting portion 103 is formed, for example, by partially extending a part of the p-type low-concentration region 102 in the second direction Y. The entire upper surface of the p-type low-concentration connecting portion 103 is in contact with the p-type base region 34.

[0157] The p-type low-concentration connecting portions 103 are scattered in the first direction X. Each p-type low-concentration connecting portion 103 has, for example, a roughly rectangular planar shape that is long in the second direction Y and extends to the vicinity of the trench 37. It is sufficient that the p-type low-concentration connecting portion 103 extends to the vicinity of the trench 37 so as to be in contact with or overlapping with the p-type low-concentration region 101, and between the p-type low-concentration connecting portion 103 and the trench 37 is an n-type current diffusion region 104 (or n - A type drift region 32) may exist.

[0158] The n-type current diffusion region 104 between the p-type low-concentration junction 103 and the trench 37 serves as a path for the current (drift current) flowing through the channel when the MOSFET is turned on, thereby reducing the on-resistance. The width w101 of the p-type low-concentration junction 103 (width in the first direction X) is greater than or equal to the process limit (e.g., about 0.5 μm). The spacing w102 between adjacent p-type low-concentration junctions 103 in the first direction X is, for example, about 2 μm to 5 μm.

[0159] The lower surface of the p-type low-concentration connecting portion 103 is at approximately the same depth as the upper surface of the p-type low-concentration region 101, or is at a depth of n greater than the upper surface of the p-type low-concentration region 101. + It is sufficient that the p-type drain region 31 is located at a deep position. That is, the lower surface of the p-type low-concentration connecting portion 103 should be at a depth such that at least the end of the p-type low-concentration connecting portion 103 in the second direction Y is in contact with the p-type low-concentration region 101, and it may be at a different depth than the lower surface of the p-type low-concentration region 102.

[0160] The p-type low-concentration connecting portion 103 may be formed simultaneously with the p-type low-concentration region 102, and the lower surface of the p-type low-concentration connecting portion 103 may be positioned at approximately the same depth as the lower surface of the p-type low-concentration region 102. The shallower the depth of the p-type low-concentration connecting portion 103 (the distance from the lower surface of the p-type base region 34 to the lower surface of the p-type low-concentration connecting portion 103), the shorter the time required for the ion implantation process to form the p-type low-concentration connecting portion 103 can be.

[0161] The p-type low-concentration connecting portion 103 may be formed simultaneously with the p-type low-concentration region 102, so that the impurity concentration of the p-type low-concentration connecting portion 103 is approximately the same as the impurity concentration of the p-type low-concentration region 102. The impurity concentration of the p-type low-concentration connecting portion 103 is about 10 times or more higher than the impurity concentration of the p-type low-concentration region 101, for example, 1 × 10⁻⁶ 17 / cm 3 The above 1 x 10 18 / cm 3 The following levels are acceptable, and the impurity concentration may differ from that of the p-type low-concentration region 102.

[0162] The n-type current diffusion region 104 is a p-type low-concentration connecting portion 103 and n - These regions are provided in contact with the n-type drift region 32. The n-type current diffusion region 104 extends in the second direction Y to the p-type low concentration region 101 and is in contact with the p-type low concentration region 101. The n-type current diffusion region 104 extends between the p-type low concentration connecting portion 103, the p-type low concentration region 102 and the trench 37 to the p-type base region 34 and is in contact with the p-type base region 34 on its upper surface.

[0163] A JFET resistor is formed between the p-type low-concentration region 101 and the p-type low-concentration region 102 of the n-type current diffusion region 104. The lower surface of the p-type low-concentration region 102 is from the lower surface of the p-type low-concentration region 101. + By being located at a shallow position separated by the above distance d100 on the source region 35 side, the cell pitch can be shortened. Instead of providing the n-type current diffusion region 104, the n-type current diffusion region 104 is replaced with n - The type drift region 32 may reach the p-type base region 34.

[0164] n + Type source region 35 and p ++ The layout of the type contact area 36 can be changed as appropriate. For example, as in Embodiment 1, p is scattered in the first direction X. ++ The grid-like planar shape surrounding the contact area 36 is n + A type source region 35 may be placed (Figure 24), n + Type source region 35 and p ++ The type contact region 36 may also extend linearly in the first direction X (Figure 25).

[0165] The method for manufacturing the semiconductor device 100 according to Embodiment 4 is the same as the method for manufacturing the semiconductor device 30 according to Embodiment 1 (see Figures 7-12), but with p-type low-concentration regions 61, 65, p + Instead of the p-type high-concentration regions 62, 64, the p-type low-concentration connecting portion 63, and the n-type current diffusion region 33, a p-type low-concentration region 101, a p-type low-concentration region 102, a p-type low-concentration connecting portion 103, and an n-type current diffusion region 104 may be formed at a predetermined depth position.

[0166] The edge termination region 2 and intermediate region 3 shown in Figure 14 may be applied to the semiconductor device 100 according to Embodiment 4.

[0167] As explained above, according to Embodiment 4, the p-type low-concentration regions between adjacent trenches are defined such that the distance between the lower surfaces is n relative to the p-type low-concentration region facing the bottom surface of the trench. +The trench is made shallower, for example, by about 0.1 μm or more, on the source region side, and the impurity concentration is increased by more than 10 times. This creates a structure that is prone to avalanche breakdown at the lower corners of the p-type low-concentration regions between adjacent trenches when the MOSFET is off.

[0168] This structure reduces the adverse effects of the large current amplified by avalanche breakdown on the trench gate structure. For example, it can suppress the application of a high electric field to the gate insulating film due to the large current amplified by avalanche breakdown. By mitigating the electric field applied to the gate insulating film, optimization by shortening the cell pitch becomes possible, and on-resistance can be reduced.

[0169] Therefore, according to Embodiment 4, the electric field applied to the gate insulating film can be relaxed, and the on-resistance can be reduced by optimization through shortening the cell pitch. For this reason, the p-type low-concentration region between adjacent trenches and the p-type base region, and the p-type low-concentration region facing the bottom surface of the trench and the bottom surface of the trench, + The same effects as in Embodiments 1 and 2 can be obtained without providing a high-concentration region.

[0170] (Embodiment 5) The structure of the semiconductor device according to Embodiment 5 will now be described. Figures 26 and 27 are cross-sectional views showing the structure of the semiconductor device according to Embodiment 5. Figures 26 and 27 show the cross-sectional structure at the cutting lines D1-D1' and D2-D2' in Figure 28, respectively. The overall layout of the semiconductor device 110 according to Embodiment 5, as viewed from the front side of the semiconductor substrate 10, is the same as in Figure 1.

[0171] Figure 28 is a plan view showing an enlarged portion of the active region in Figure 1. Figure 29 is a plan view showing an enlarged portion of another example of the active region in Figure 1. Figures 28 and 29 show the layout of the p-type low-concentration region 101 (outline of the thick dashed line and hatched portion of the dots) and the p-type low-concentration connecting portion 103 (outline of the thick solid line and hatched portion of the dots).

[0172] The semiconductor device 110 according to Embodiment 5 differs from the semiconductor device 100 according to Embodiment 4 (see Figures 22-25) in the following two points. The first difference is that, as a p-type region having the function of mitigating the electric field applied to the gate insulating film 38 on the inner wall of the trench 37, a p-type low-concentration region (reference numeral 102 in Figures 22 and 23) is not provided between adjacent trenches 37, and only a p-type low-concentration region 101 and a p-type low-concentration connecting portion 103 are provided.

[0173] Between adjacent trenches 37, p-type base region 34 and p ++ Type contact area 36(p ++ If a type contact region 36 is not provided, only the p-type base region 34 is provided. (n + The only p-type region located on the drain region 31 side is the p-type low-concentration coupling portion 103. This widens the path for the current (drift current) that flows through the channel when the MOSFET is turned on.

[0174] By widening the current path, the cell pitch can be shortened (the state in which the cell pitch of the semiconductor device 110 according to Embodiment 5 is shortened is not shown), thereby reducing the on-resistance. While this allows for lower on-resistance, shortening the cell pitch also narrows the spacing between adjacent trenches 37, increasing the resistance of the JFET resistor and thus increasing the strength of the electric field applied to the gate insulating film 38 on the side walls of the trenches 37.

[0175] Therefore, the second difference is that the width (width in the second direction Y) w111 of the p-type low-concentration region 101 facing the trench 37 is made wider than the width w112 of the trench 37, and is about 1.0 μm or more. The inventors have confirmed that this widens the spacing of equipotential lines near the upper corner of the p-type low-concentration region 101 (boundary between the top surface and the side surface), and reduces the electric field applied to the gate insulating film 38 on the side wall of the trench 37 (see Figure 30 described later).

[0176] Furthermore, the inventors have confirmed that the wider the width w111 of the p-type low-concentration region 101, the closer the strength of the electric field applied to the gate insulating film 38 on the side wall of the trench 37 approaches a constant value, regardless of the breakdown voltage (see Figures 31 and 32 described later). For example, when the width w112 of the trench 37 is about 0.7 μm, the width w111 of the p-type low-concentration region 101 is about 1.0 μm. The width w111 of the p-type low-concentration region 101 increases or decreases in proportion to the increase or decrease in the width w112 of the trench 37.

[0177] The impurity concentration in the p-type low-concentration region 101 is the same as in Embodiment 4 (i.e., for example, 1 × 10⁻⁶). 16 / cm 3 The above 8 x 10 16 / cm 3 (Within the following range). In Embodiment 5, the impurity concentrations of the p-type low-concentration region 101 and the p-type low-concentration connecting portion 103 are within the range of the impurity concentration of the p-type low-concentration region 61 in Embodiment 1 (i.e., for example, 3 × 10). 17 / cm 3 The above 9 x 10 17 / cm 3 You may set it to the following range:

[0178] n + Type source region 35 and p ++ The layout of the type contact region 36 is similar to that of Embodiment 4, with p scattered in the first direction X. ++ The grid-like planar shape surrounding the contact area 36 is n + Alternatively, the layout may include a type source area 35 (Figure 28), n + Type source region 35 and p ++ The type contact region 36 may also be arranged in a linear manner in the first direction X (Figure 29).

[0179] The method for manufacturing the semiconductor device 110 according to Embodiment 5 is the same as the method for manufacturing the semiconductor device 100 according to Embodiment 4, but the step of forming a p-type low-concentration region 102 between adjacent trenches 37 can be omitted.

[0180] The edge termination region 2 and intermediate region 3 shown in Figure 14 may be applied to the semiconductor device 110 according to Embodiment 5.

[0181] As described above, according to Embodiment 5, by not providing p-type low-concentration regions between adjacent trenches, the on-resistance can be reduced by shortening the cell pitch. Furthermore, by widening the width of the p-type low-concentration region facing the trench, the electric field applied to the gate insulating film on the side wall of the trench can be mitigated. For this reason, the same effects as in Embodiment 4 can be obtained even without providing p-type low-concentration regions between adjacent trenches.

[0182] (Example 2) For the semiconductor device 110 according to Embodiment 5 described above (see Figures 26-29; hereinafter referred to as Embodiment 2), the relationship between the width w111 of the p-type low-concentration region 101 facing the trench 37, the strength of the electric field applied to the gate insulating film 38 on the side wall of the trench 37 when off, and the breakdown voltage was verified. Figures 30-32 are characteristic diagrams showing the simulation results of the electric field strength of the gate insulating film in Embodiment 2.

[0183] The horizontal axis of Figure 30 represents the width w111 [μm] of the p-type low-concentration region 101 (the p-type low-concentration region below the trench) facing the trench 37. The horizontal axis of Figures 31 and 32 represents the breakdown voltage [V] (the breakdown voltage applied to the gate insulating film 38 during avalanche breakdown). The vertical axis of Figures 30 to 32 represents the electric field strength (oxide film electric field strength [MV / cm]) applied to the gate insulating film 38 on the side wall of the trench 37.

[0184] Figure 30 shows the results of simulating the electric field strength applied to the gate insulating film 38 on the side wall of the trench 37 by changing the width w111 of the p-type low-concentration region 101 facing the trench 37 in various ways for Example 2. Figure 30 shows two samples of Example 2 with a forward voltage of 700V (voltage applied to the gate insulating film 38) applied between the source and drain, one with a gate voltage VG of 0V and the other with a gate voltage VG of -7V.

[0185] Furthermore, for the two samples of Example 2 (a sample with a gate voltage VG of -7V and a sample with a gate voltage VG of 0V), the width w111 of the p-type low-concentration region 101 facing the trench 37 and the breakdown voltage (breakdown voltage applied to the gate insulating film 38: up to approximately 1000V) were varied in various ways, and the results of simulating the electric field strength applied to the gate insulating film 38 on the side wall of the trench 37 are shown in Figures 31 and 32, respectively.

[0186] The results shown in Figures 30-32 confirm that increasing the width w111 of the p-type low-concentration region 101 reduces the intensity of the electric field applied to the gate insulating film 38 on the side wall of the trench 37 when the device is off in Example 2. Furthermore, it was confirmed that the relationship between the width w111 of the p-type low-concentration region 101 and the intensity of the electric field applied to the gate insulating film 38 on the side wall of the trench 37 when the device is off follows the same trend regardless of the gate voltage VG (≤ 0V) or breakdown voltage.

[0187] Specifically, regardless of the gate voltage VG or breakdown voltage, setting the width w111 of the p-type low-concentration region 101 to 1.0 μm or more tends to significantly reduce the electric field applied to the gate insulating film 38 on the side wall of the trench 37. However, since the on-resistance increases as the width w111 of the p-type low-concentration region 101 widens, it can be seen that the width w111 of the p-type low-concentration region 101 should be determined within the range of 1.0 μm to 1.4 μm in order to obtain a predetermined on-resistance. In other words, generalizing with the width w112 of the trench 37, the width w111 of the p-type low-concentration region 101 (=w111 / w112) relative to the width w112 of the trench 37 should be determined within the range of 1.4 times to 2 times.

[0188] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, in embodiments 1 and 2, the FLR is a p-type low-concentration region that relaxes the electric field applied to the gate insulating film at the bottom surface of the trench, a p-type low-concentration connecting portion and p + The high-concentration region may be formed at a different timing than the high-concentration region. In Embodiment 3, the front surface of the semiconductor substrate has an edge termination region n -It is sufficient that the type epitaxial layer is exposed, and a continuous flat surface may be provided from the active region to the tip edge without creating any steps. The present invention is also applicable when a wide-bandgap semiconductor other than silicon carbide is used instead of silicon carbide as the semiconductor material. Furthermore, the present invention also holds true when the conductivity type (n-type, p-type) is reversed. [Industrial applicability]

[0189] As described above, the semiconductor device according to the present invention is useful for power semiconductor devices that control high voltage and high current. [Explanation of symbols]

[0190] 1 active area 2 Edge Termination Region 3 Intermediate area 10 Semiconductor substrates 10a~10c The first to third sides of the front surface of the semiconductor substrate 11 n + Mold starting substrate 12,12a,12b n - Type epitaxial layer 13 p-type epitaxial layer 20 FLR structure 21. Low-concentration region of p-type FLR 22 FLR p + Type high concentration area 23 FLR 24 n + Type channel stopper region 30,90,100,110 Semiconductor equipment 31 n + Type drain region 32 n - Type drift region 33,104 n-type current diffusion region 34 p-type base region 34a Outer p-type base region 35 n + Type source area 36 p ++ Type Contact Area 36a outer circumference p ++Type Contact Area 37 Trench 38 Gate Insulator 39 Post Station 40 Interlayer insulating film 40a, 40b Contact holes in the interlayer insulating film 41 NiSi film 42 1st TiN film 43 1st Ti film 44 2nd TiN film 45 2nd Ti film 46 Barrier Metal 47 Al electrode film 48 Plating film 49 terminal pins 50 1st protective film 51 Second protective film 52 Drain electrode 53 Steps on the front surface of the semiconductor substrate 61,101 p-type low-concentration region opposite the bottom surface of the trench 62 p between adjacent trenches + Type high concentration area 62a outer circumference p + type area 63,103 p-type low concentration connection 64 The bottom surface of the trench opposite p + Type high concentration area 65,102 p-type low-concentration regions between adjacent trenches 65a Outer p-type low concentration region 71 Field Oxide Film 72 Gate polysilicon wiring layer 73 Gate metal wiring layer 81,83 p + type area 82,84 n-type region 91 p + Mold high concentration connection part d1 Depth from the bottom of the trench to the bottom of the p-type low-concentration region d100 Distance from the bottom surface of the p-type low-concentration region opposite the bottom surface of a trench to the bottom surface of the p-type low-concentration region between adjacent trenches d101 Depth from the bottom of the trench to the bottom of the p-type low-concentration region t1 p opposite the bottom surface of the trench + Thickness of the high-concentration region of the type t11, t12 n - Thickness of the epitaxial layer t13 Thickness of the p-type epitaxial layer w1, w101 Width of p-type low-concentration connecting section w2, w102 Spacing between adjacent p-type low-concentration connecting parts in the first direction. w111 Width of the p-type low-concentration region opposite the trench w112 trench width X First direction parallel to the front surface of the semiconductor substrate Y: A second direction parallel to the front surface of the semiconductor substrate and perpendicular to the first direction. Z-direction (depth)

Claims

1. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region, and extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the second semiconductor region and the third semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, A first low-concentration region of a second conductivity type is selectively provided within the first semiconductor region and faces the bottom surface of the trench in the depth direction, A first connecting portion of a second conductivity type that connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, Equipped with, The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion form a grid-like planar shape. A semiconductor device characterized in that the depth from the trench to the end of the first low-concentration region on the second electrode side is 0.7 μm or more and 1.1 μm or less.

2. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region, and extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the second semiconductor region and the third semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, A first low-concentration region of a second conductivity type is selectively provided within the first semiconductor region and faces the bottom surface of the trench in the depth direction, A first connecting portion of a second conductivity type that connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, Equipped with, The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion form a grid-like planar shape. The second semiconductor region and the first low-concentration region are electrically connected, and the first high-concentration region of a second conductivity type has a higher impurity concentration than the second semiconductor region, A semiconductor device characterized in that the impurity concentration in the first low-concentration region and the first connecting portion is both 3 × 10¹⁷ / cm³ or more and 9 × 10¹⁷ / cm³ or less.

3. A semiconductor substrate made of a semiconductor having a wider bandgap than silicon, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region, and extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the second semiconductor region and the third semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, A first low-concentration region of a second conductivity type is selectively provided within the first semiconductor region and faces the bottom surface of the trench in the depth direction, A first connecting portion of a second conductivity type that connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, Equipped with, The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion form a grid-like planar shape. The second semiconductor region and the first low-concentration region are electrically connected, and the first high-concentration region of a second conductivity type has a higher impurity concentration than the second semiconductor region, The semiconductor device is characterized in that the first high-concentration region is provided along only one side wall of the trench and is scattered in the first direction.

4. The semiconductor device according to claim 1, further comprising a first high-concentration region of a second conductivity type having a higher impurity concentration than the second semiconductor region, which electrically connects the second semiconductor region and the first low-concentration region.

5. The semiconductor device according to claim 3 or 4, characterized in that the impurity concentration of the first low-concentration region and the first connecting portion is both 3 × 10¹⁷ / cm³ or more and 9 × 10¹⁷ / cm³ or less.

6. The semiconductor device according to any one of claims 2 to 5, characterized in that the adjacent first connecting portions are scattered in the first direction at intervals of 3 μm or less.

7. The semiconductor device according to any one of claims 2 to 6, characterized in that the width of the first connecting portion in the first direction is 0.5 μm or more and 1.0 μm or less.

8. The semiconductor device according to any one of claims 2 to 7, further comprising a second high-concentration region of a second conductivity type with a higher impurity concentration than the first low-concentration region and the second semiconductor region, between the bottom surface of the trench and the first low-concentration region, in contact with the first low-concentration region.

9. The semiconductor device according to claim 8, characterized in that the impurity concentration in the second high-concentration region is twice or more the impurity concentration in the first low-concentration region.

10. The second high-concentration region is in contact with the gate insulating film at the bottom surface of the trench, The semiconductor device according to claim 8 or 9, characterized in that the depth from the bottom surface of the trench to the end of the second high-concentration region on the second electrode side is 0.1 μm or more and 0.15 μm or less.

11. The semiconductor device according to any one of claims 2 to 10, characterized in that the first high-concentration region is provided inside the first semiconductor region, away from the first low-concentration region and the trench, between adjacent trenches, and extends in a stripe shape in the first direction.

12. The semiconductor device according to claim 11, characterized in that the first low-concentration region is electrically connected to the first high-concentration region via the first connecting portion.

13. The semiconductor device according to claim 2, characterized in that the first high-concentration region is provided along only one side wall of the trench and is scattered in the first direction.

14. The semiconductor device according to claim 3 or 13, characterized in that the spacing between the first high-concentration regions in the first direction is wider than the spacing between the first connecting portions in the first direction.

15. The second low-concentration region of a second conductivity type is further provided within the first semiconductor region between adjacent trenches, in contact with the second semiconductor region and the first connecting portion, and separated from the first low-concentration region and the trench, and extending in a stripe shape in the first direction, The end of the second low-concentration region on the second electrode side is located at a shallow position, at a distance of 0.1 μm or more from the end of the first low-concentration region on the second electrode side toward the first electrode. The semiconductor device according to claim 1, characterized in that the impurity concentration in the second low-concentration region is 10 times or more higher than the impurity concentration in the first low-concentration region.

16. A semiconductor substrate made of a semiconductor having a wider bandgap than silicon, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region, and extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the second semiconductor region and the third semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, A first low-concentration region of a second conductivity type is selectively provided within the first semiconductor region and faces the bottom surface of the trench in the depth direction, A first connecting portion of a second conductivity type that connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, Equipped with, The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion form a grid-like planar shape. Between adjacent trenches, within the first semiconductor region, further comprising a second low-concentration region of a second conductivity type, which is in contact with the second semiconductor region and the first connecting portion, and is provided separately from the first low-concentration region and the trench, and extends in a stripe shape in the first direction, The end of the second low-concentration region on the second electrode side is located at a shallow position, at a distance of 0.1 μm or more from the end of the first low-concentration region on the second electrode side toward the first electrode. A semiconductor device characterized in that the impurity concentration in the second low-concentration region is 10 times or more higher than the impurity concentration in the first low-concentration region.

17. The semiconductor device according to claim 1, characterized in that the width of the first low-concentration region is wider than the width of the trench and is 1.0 μm or more.

18. The semiconductor device according to any one of claims 15 to 17, characterized in that the impurity concentration in the first low-concentration region is 1 × 10¹⁶ / cm³ or more and 8 × 10¹⁶ / cm³ or less.

19. The semiconductor device according to any one of claims 15 to 18, characterized in that the impurity concentration of the first connecting portion is 10 times or more higher than the impurity concentration of the first low-concentration region.

20. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region, and extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the second semiconductor region and the third semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, A first low-concentration region of a second conductivity type is selectively provided within the first semiconductor region and faces the bottom surface of the trench in the depth direction, A first connecting portion of a second conductivity type that connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, Equipped with, The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion form a grid-like planar shape. The width of the first low-concentration region is wider than the width of the trench and is 1.0 μm or more. A semiconductor device characterized in that the impurity concentration in the first low-concentration region is 1 × 10¹⁶ / cm³ or more and 8 × 10¹⁶ / cm³ or less.

21. A semiconductor substrate made of a semiconductor with a wider bandgap than silicon, A first semiconductor region of a first conductivity type provided inside the semiconductor substrate, A second semiconductor region of a second conductivity type is provided between the first main surface of the semiconductor substrate and the first semiconductor region, A third semiconductor region of a first conductivity type is selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region, A trench that penetrates the third semiconductor region and the second semiconductor region in the depth direction and reaches the first semiconductor region, and extends in a stripe shape in a first direction parallel to the first main surface of the semiconductor substrate, A gate electrode is provided inside the trench via a gate insulating film, A first electrode electrically connected to the second semiconductor region and the third semiconductor region, A second electrode provided on the second main surface of the semiconductor substrate, A first low-concentration region of a second conductivity type is selectively provided within the first semiconductor region and faces the bottom surface of the trench in the depth direction, A first connecting portion of a second conductivity type that connects adjacent first low-concentration regions in a second direction parallel to the first main surface of the semiconductor substrate and perpendicular to the first direction, Equipped with, The first low-concentration region and the first connecting portion are electrically connected to the second semiconductor region. The first low-concentration region extends linearly in the first direction, and the first low-concentration region and the first connecting portion form a grid-like planar shape. The width of the first low-concentration region is wider than the width of the trench and is 1.0 μm or more. A semiconductor device characterized in that the impurity concentration of the first connecting portion is 10 times or more higher than the impurity concentration of the first low-concentration region.

22. The semiconductor device according to any one of claims 15 to 21, characterized in that the first connecting portion is in contact with the second semiconductor region and electrically connects the second semiconductor region and the first low-concentration region.

23. The semiconductor device according to any one of claims 15 to 22, characterized in that the adjacent first connecting portions are scattered in the first direction at intervals of 2 μm to 5 μm.

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