Semiconductor device and method for manufacturing a semiconductor device

Abstract

To suppress rise in on-resistance while increasing coatability of a gate electrode.SOLUTION: A contact layer 13 has a partial region where a trench 20 is provided. The trench 20 has such a depth that it extends through a contact layer 13 and a channel layer 12, and reaches a drift layer 11. In a side face of the trench 20, regions 20a and 20b from which the drift layer 11 and the channel layer 12 are exposed are vertical to a principal face of a substrate 10. On the other hand, a region 20c from which the contact layer 13 is exposed in the side face of the trench 20 includes: a region 20c1 ranging from the surface of the channel layer 12 to a given level H, which is vertical to the principal face of the substrate 10; and a region 20c2 ranging from the level H to a top face of the trench 20 and inclined by an angle of θ to the principal face of the substrate 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a trench gate type semiconductor device made of a group III nitride semiconductor and a method for manufacturing the same. [Background technology]

[0002] In a trench-type vertical MISFET, n - - A drift layer made of GaN, a channel layer made of p-GaN, n + -A semiconductor layer is formed by sequentially stacking contact layers made of GaN. A trench reaching the depth of the drift layer is formed in this semiconductor layer. A gate insulating film is continuously formed on the bottom, sides, and top of the trench (the region of the semiconductor layer surface near the trench), and a gate electrode is further formed via the gate insulating film.

[0003] Here, it is not easy to cover the corners formed by the trench side and the contact layer surface with the gate electrode, and coating defects are likely to occur. If the gate electrode coating is defective, there is a concern that it may cause malfunction of the MISFET or an increase in resistance.

[0004] Therefore, as shown in Patent Document 1, it is conceivable to improve the coverage of the gate electrode by making the cross-section of the trench V-shaped. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2008-78604 [Patent Document 2] Japanese Patent Publication No. 2018-129558 [Overview of the project] [Problems that the invention aims to solve]

[0006] However, if the trench cross-section is V-shaped as in Patent Document 1, the channel length (the length of the side of the channel layer exposed on the trench side) becomes longer, which worsens the on-resistance.

[0007] Therefore, the object of the present invention is to improve the coverage of the gate electrode while suppressing the increase in on-resistance in a trench-type semiconductor device made of a group III nitride semiconductor. [Means for solving the problem]

[0008] The present invention relates to a trench gate type semiconductor element made of a group III nitride semiconductor, comprising: a substrate; a first layer made of an n-type group III nitride semiconductor provided on the substrate; a second layer made of a p-type group III nitride semiconductor provided on the first layer; a third layer made of an n-type group III nitride semiconductor provided on the second layer; and a trench provided in a part of the surface of the third layer, with a depth that penetrates the third layer and the second layer and reaches the first layer. A recess provided in a portion of the surface of the third layer, penetrating the third layer and reaching the second layer to a depth, a gate electrode covering the side of the trench and the surface of the third layer near the trench, electrodes provided on the bottom surface, side of the recess and the surface of the third layer near the recess, The trench side surface in which the second layer is exposed is perpendicular to the main surface of the substrate, and the trench side surface in which the third layer is exposed is such that the first region from the surface of the second layer to a predetermined height is perpendicular to the main surface of the substrate, and the second region from the predetermined height to the surface of the third layer is inclined with respect to the main surface of the substrate, and the inclination is such that the cross-sectional area of ​​the plane parallel to the bottom surface of the trench increases as you move from the bottom surface side of the trench to the top surface side. Furthermore, the corner formed by the side surface of the recess and the surface of the third layer is chamfered. This semiconductor device is characterized by the following features.

[0009] The present invention may further include an ion implantation region formed by implanting ions into a predetermined region of the surface of the second layer, and a p-type impurity region formed below the ion implantation region, at a predetermined depth from the surface of the first layer, and in a region the width of the second layer.

[0010] In the present invention, the inclination angle of the second region may be 15 to 75°.

[0011] In the present invention, the width in the direction parallel to the main surface of the substrate in the second region may be 0.1 to 0.3 μm.

[0012] The present invention is also a method for manufacturing a trench gate type semiconductor device made of a group III nitride semiconductor, including a first step of sequentially forming a first layer made of an n-type group III nitride semiconductor, a second layer made of a p-type group III nitride semiconductor, and a third layer made of an n-type group III nitride semiconductor on a substrate; a second step of forming a trench reaching the first layer through the third layer and the second layer in a partial region on the surface of the third layer, and forming the trench such that the side surface of the trench is perpendicular to the main surface of the substrate; and a third step of etching the side surface of the trench so that in the region where the third layer is exposed on the side surface of the trench, a first region from the surface of the second layer to a predetermined height is perpendicular to the main surface of the substrate, and a second region from the predetermined height to the surface of the third layer is inclined with respect to the main surface of the substrate, and the inclination is such that the cross-sectional area in a plane parallel to the bottom surface of the trench increases from the bottom side to the top side of the trench. A fourth step of forming a recess in a portion of the surface of the third layer to a depth that penetrates the third layer and reaches the second layer; a fifth step of etching so that the corners formed by the side surface of the recess and the surface of the third layer are chamfered; a sixth step of forming a gate electrode so as to cover the side surface of the trench and the area of ​​the third layer surface near the trench; and a seventh step of forming electrodes on the bottom surface, side surface of the recess and the area of ​​the third layer surface near the recess. A method for manufacturing a semiconductor device, characterized by having the above.

[0013] In the present invention, the third step may be a step of dry etching the entire upper surface of the wafer.

[0014] In the present invention, the first step includes a step of ion implanting a predetermined region on the surface of the second layer to form an ion implantation region after the formation of the second layer and before the formation of the third layer. Before the second step and before the third step, a heat treatment is performed to diffuse the p-type impurities in the second layer, and a fourth step of forming a p-type impurity region at a predetermined depth from the surface of the first layer and within the width region of the second layer below the ion implantation region. The third step may also serve to remove the thermal damage generated on the side surface of the trench by the fourth step.

Effect of the Invention

[0015] According to the present invention, it is possible to improve the coverage of the gate electrode while suppressing the increase in on-resistance. As a result, the stability of the device operation can be improved. [Brief explanation of the drawing]

[0016] [Figure 1] A diagram showing the configuration of the semiconductor device of the first embodiment. [Figure 2] A diagram showing a magnified view of a portion of trench 20. [Figure 3] A diagram showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 4] A diagram showing the manufacturing process of a semiconductor device according to the first embodiment. [Figure 5] A diagram showing the configuration of the semiconductor device of the second embodiment. [Figure 6] A magnified view of a portion of trench 220. [Figure 7] A magnified view of a portion of trench 220. [Figure 8] A diagram showing the manufacturing process of a semiconductor device according to the second embodiment. [Figure 9] A diagram showing the manufacturing process of a semiconductor device according to the second embodiment. [Modes for carrying out the invention]

[0017] Embodiments of the present invention will be described below with reference to the figures.

[0018] (First Embodiment) Figure 1 shows the configuration of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is a trench gate vertical FET, and as shown in Figure 1, it has a substrate 10, a drift layer 11, a channel layer 12, a contact layer 13, a gate insulating film 14, a gate electrode 15, a source electrode 16, a drain electrode 17, and a body electrode 18.

[0019] The substrate 10 is a Si-doped n-plane with the c-plane as the main surface. + -It consists of GaN. The Si concentration of substrate 10 is 1 × 10 18 / cm 3 The above is the case. The material of the substrate 10 may be other than GaN, and any material can be used as long as it can grow a group III nitride semiconductor and has conductivity. For example, Si, SiC, ZnO, etc. can be used.

[0020] The drift layer 11 is provided on the substrate 10. The drift layer 11 is composed of Si-doped n - -GaN. The thickness of the drift layer 11 is 8 to 15 μm. Also, the Si concentration of the drift layer 11 is 1×10 15 ~5×10 16 / cm 3 is.

[0021] The channel layer 12 is provided on the drift layer 11. The channel layer 12 is composed of Mg-doped p-GaN. The thickness of the channel layer 12 is 0.1 to 1 μm. Also, the Mg concentration of the channel layer 12 is 1×10 17 ~8×10 19 / cm 3 is.

[0022] The contact layer 13 is provided on the channel layer 12. The contact layer 13 is composed of Si-doped n + -GaN. The thickness of the contact layer 13 is 0.1 to 0.5 μm. Also, the Si concentration of the contact layer 13 is 1×10 18 ~1×10 19 / cm 3 is.

[0023] A trench 20 is provided in a partial region on the surface of the contact layer 13. The depth of the trench 20 is such that it penetrates the contact layer 13 and the channel layer 12 and reaches the drift layer 11. The drift layer 11 is exposed on the bottom surface of the trench 20. Also, on the side surface of the trench 20, the drift layer 11, the channel layer 12, and the contact layer 13 are exposed in order from the bottom surface side. Hereinafter, the region where the drift layer 11 is exposed on the side surface of the trench 20 is 20a, the region where the channel layer 12 is exposed is 20b, and the region where the contact layer 13 is exposed is 20c.

[0024] Figure 2 is an enlarged view of a portion of the trench 20. As shown in Figure 2, the regions 20a and 20b on the side surface of the trench 20, where the drift layer 11 and channel layer 12 are exposed, are perpendicular to the main surface of the substrate 10. On the other hand, the region 20c on the side surface of the trench 20, where the contact layer 13 is exposed, is perpendicular to the main surface of the substrate 10 in the region 20c1 from the surface of the channel layer 12 up to a certain height H, while the region 20c2 from height H to the top surface of the trench 20 (the surface of the contact layer 13 and the region near the trench 20) is inclined θ with respect to the main surface of the substrate 10. The inclination is such that the cross-sectional area of ​​the plane parallel to the bottom surface of the trench 20 increases as you move from the bottom side of the trench 20 towards the top side.

[0025] As described above, the trench 20 has a chamfered shape at the corners formed by the side and top surfaces of the trench 20. Therefore, the gate electrode 15 does not bend sharply at the corners formed by the side and top surfaces of the trench 20, but is bent gradually at a gentle angle. As a result, the coverage of the gate electrode 15 can be improved.

[0026] Furthermore, the channel length is determined by the length of the region 20b on the side of the trench 20 where the channel layer 12 is exposed. Since region 20b is perpendicular to the main surface of the substrate 10, there is no change in the channel length compared to the conventional structure (where all regions on the side of the trench 20 are perpendicular). Therefore, it is possible to improve the coverage of the gate electrode 15 while suppressing an increase in on-resistance.

[0027] Furthermore, because the corners formed by the side and top surfaces of the trench 20 are chamfered, the path of the current flowing across the surface of the contact layer 13 is shortened. As a result, the resistance of the element can be reduced.

[0028] Furthermore, the side regions 20b and 20c1 of the trench 20 do not need to be strictly perpendicular to the main surface of the substrate 10, but can be in the range of 80 to 90 degrees. Also, the side region 20a of the trench 20 may be perpendicular or inclined. For example, it may be between 45 and 90 degrees.

[0029] The inclination angle θ of region 20c2 on the side of the trench 20 can be any value as long as it is greater than 0° and less than the inclination angles of the other regions on the side (20a, 20b, 20c1), but it is preferably between 15 and 75°. This range can further improve the coverage of the gate electrode 15. The inclination angle θ may also change in steps or continuously.

[0030] Furthermore, the width W of region 20c2 (the width in the direction parallel to the main surface of the substrate 10, where H0 is the thickness of the contact layer 13, W = (H0 - H) / tanθ) is preferably 0.1 to 0.3 μm. By setting it within this range, the coverage of the gate electrode 15 can be further improved.

[0031] The height H can be any value as long as it is 0 or greater and less than or equal to the thickness of the contact layer 13, but it is preferable that the height H is set such that the inclination angle θ is 15 to 75° and the width W is 0.1 to 0.3 μm.

[0032] A recess 21 is provided in a portion of the contact layer 13 that is different from the area where the trench 20 is formed. The recess 21 is a groove that penetrates the contact layer 13 and reaches the channel layer 12. The side surface of the recess 21 may be perpendicular or inclined with respect to the main surface of the substrate 10.

[0033] The gate insulating film 14 is continuously provided across the bottom, sides, and top of the trench 20. The gate insulating film 14 is made of, for example, SiO2.

[0034] The gate electrode 15 is provided across the bottom, side, and top surfaces of the trench 20 via a gate insulating film 14. The gate electrode 15 is made of, for example, TiN. Here, the region 20c2 on the side of the trench 20 has a slope, which can improve the coverage of the gate electrode 15.

[0035] The body electrode 18 is continuously provided across the bottom, side, and top surfaces (the surface of the contact layer 13 and the region near the recess 21) of the recess 21. The body electrode 18 is made of, for example, Ni.

[0036] The source electrode 16 is provided on the contact layer 13 and the body electrode 18. The source electrode 16 is made of, for example, Pd / Al / Ti.

[0037] The drain electrode 17 is provided on the back surface of the substrate 10. The drain electrode 17 is made of, for example, Pd / Al / Ti.

[0038] As described above, in the semiconductor device of the first embodiment, the region on the side of the trench 20 where the contact layer 13 is exposed is sloped. Therefore, it is possible to improve the coverage of the gate electrode 15 while suppressing the increase in on-resistance. As a result, the stability of the device operation can be improved.

[0039] Next, the method for manufacturing the semiconductor device according to the first embodiment will be described.

[0040] First, a drift layer 11, a channel layer 12, and a contact layer 13 are sequentially formed on the substrate 10 by the MOCVD method (see Figure 3(a)).

[0041] Next, a predetermined area of ​​the contact layer 13 is dry-etched until it reaches the drift layer 11 to form a trench 20 (see Figure 3(b)). The etching conditions are set so that the side surface of the trench 20 is perpendicular to the main surface of the substrate 10.

[0042] Next, the entire top surface of the wafer is dry-etched. Since the convex parts of the top surface are etched preferentially, the corners formed by the side surface and the top surface of the trench 20 are etched preferentially. As a result, the corners are chamfered, and a sloped side surface is formed in region 20c2 of the side surface of the trench 20, while the other regions 20a, 20b, and 20c1 of the side surface remain vertical (see Figure 3(c)).

[0043] For etching, a chlorine-based gas such as Cl2, BCl3, or SiCl4 is used. Cl2 is particularly preferred because it can suppress the adhesion of impurities (such as B and Si) to the channel layer 12 exposed on the side surface of the trench 20.

[0044] Furthermore, this dry etching covers the entire top surface and does not require a mask, thus eliminating the need for mask formation margins. This allows for miniaturization of the device, which in turn reduces chip resistance.

[0045] Wet etching may be used instead of dry etching. However, in the case of wet etching, it is necessary to cover the areas that are not to be etched with a mask. An aqueous solution such as TMAH can be used as the wet etching solution. In addition, with wet etching using TMAH, specific surface orientations (c-plane or m-plane) can be exposed on the side surface of the trench 20 due to anisotropy, thereby reducing on-resistance. Furthermore, since the etching rate becomes very slow once a specific surface orientation is exposed, it functions as an etching stopper and offers excellent shape reproducibility.

[0046] Next, a predetermined area of ​​the contact layer 13 is dry-etched until it reaches the channel layer 12 to form a recess 21 (see Figure 3(d)). Alternatively, dry etching of the entire upper surface of the wafer may be performed after the formation of the trench 20 and recess 21. In this case, the corners of the recess 21 can also be chamfered, which can improve the coverage of the body electrode 18 and source electrode 16.

[0047] Next, the gate insulating film 14 is formed continuously across the bottom, sides, and top of the trench 20 by the ALD method (see Figure 4(a)).

[0048] Next, gate electrodes 15 are formed on the bottom, side, and top surfaces of the trench 20 via the gate insulating film 14 by vapor deposition or sputtering (see Figure 4(b)). Here, region 20c2 of the side surface of the trench 20 is inclined, and the corners formed by the side surface and top surface of the trench 20 are chamfered. As a result, the curvature of the gate electrodes 15 is gentle at these corners, making it easier to form the gate electrodes 15 along the corners and improving the coverage of the gate electrodes 15.

[0049] Next, a body electrode 18 is formed continuously on the bottom, side, and top surfaces of the recess 21, and a source electrode 16 is formed on the contact layer 13 and the body electrode 18. Then, a drain electrode is formed on the back surface of the substrate 10. The body electrode 18, source electrode 16, and drain electrode 17 are deposited by vapor deposition or sputtering and patterned by lift-off. The semiconductor device of the first embodiment is manufactured by the above method.

[0050] (Second Embodiment) Figure 5 shows the configuration of the semiconductor device of the second embodiment. As shown in Figure 5, the semiconductor device of the second embodiment is a vertical FET with a trench gate structure made of a group III nitride semiconductor, and as shown in Figure 1, it is composed of a substrate 210, a first n layer (drift layer) 211, a first p layer (channel layer) 212, a p-type impurity region 213, a second n layer (contact layer) 214, an ion implantation region 215, a gate insulating film 216, a gate electrode 217, a drain electrode 218, and a source electrode 219.

[0051] The substrate 210 is made of Si-doped n-GaN with the c-plane as the main surface. The material of the substrate 210 is not limited to GaN; any conductive material capable of growing Group III nitride semiconductor crystals can be used.

[0052] On the substrate 210, a first n-layer 211 made of Si-doped n-GaN, a first p-layer 212 made of Mg-doped p-GaN, and a second n-layer 214 made of Si-doped n-GaN are stacked in that order. The impurity concentrations of each layer are, for example, as follows: The Si concentration of the first n-layer 211 is 1 × 10⁻⁶. 15 ~2.5×10 16 / cm 3 The Mg concentration in the first p layer 212 is 1 × 10⁻⁶ 17 ~2×10 19 / cm 3 The Si concentration in the second n layer 214 is 1 × 10⁻⁶ 18 ~1 × 10 19 / cm 3 Furthermore, the thickness of each layer is, for example, 10 μm for the first n layer 211, 1 μm for the first p layer 212, and 0.2 μm for the second n layer 214.

[0053] A trench 220 is provided in a predetermined area on the surface of the second n layer 214. Figure 6 is an enlarged view of a part of the trench 220. The trench 220 is a groove that penetrates the second n layer 214 and the first p layer 212 and reaches the first n layer 211. The first n layer 211 is exposed at the bottom of the trench 220, and on the side surface, in order from the bottom side, the first n layer 211, the p-type impurity region 213, the first p layer 212, and the second n layer 214 are exposed. Hereinafter, the area on the side surface of the trench 220 in which the first n layer 211 is exposed will be referred to as 220a, the area in which the p-type impurity region 213 is exposed as 220b, the area in which the first p layer 212 is exposed as 220c, and the area in which the second n layer 214 is exposed as 220d.

[0054] The planar pattern of the trench 220 is, for example, honeycomb-like, and the first p layer 212 and the second n layer 214 are partitioned into a regular hexagonal planar pattern. The width of the trench 220 is, for example, 1.6 to 5 μm. The depth of the trench 220 can be any depth as long as the first n layer 211 is exposed, but it is preferably 0.1 to 0.5 μm from the surface of the second n layer 214. This is to ensure that the first n layer 211 is reliably exposed.

[0055] As shown in Figure 6, of the side surfaces of the trench 220, the regions 220a, 220b, and 220c where the first n layer 211, the p-type impurity region 213, and the first p layer 212 are exposed are perpendicular to the main surface of the substrate 210. On the other hand, of the side surfaces of the trench 220, the region 220d where the second n layer 214 is exposed is such that the region 220d1 from the surface of the first p layer 212 up to a certain height H is perpendicular to the main surface of the substrate 210, while the region 220d2 from height H to the top surface of the trench 220 (the surface of the second n layer 214 and the region near the trench 220) is inclined at an angle θ with respect to the main surface of the substrate 210. The inclination is such that the cross-sectional area of ​​the plane parallel to the bottom surface of the trench 220 increases as you move from the bottom side of the trench 220 towards the top side.

[0056] As described above, the shape of the trench 220 is such that the corners formed by the side and top surfaces of the trench 220 are chamfered. Therefore, the gate electrode 217 does not bend sharply at the corners formed by the side and top surfaces of the trench 220, but is bent gradually at a gentle angle. As a result, the coverage of the gate electrode 217 can be improved.

[0057] Furthermore, the channel length is determined by the length of the side of the trench 220 where the first p-layer 212 is exposed (region 220c). Since region 220c is perpendicular to the main surface of the substrate 210, the channel length remains unchanged compared to the conventional structure (where all regions of the trench 220 are perpendicular). Therefore, it is possible to improve the coverage of the gate electrode 217 while suppressing an increase in on-resistance.

[0058] Furthermore, because the corners formed by the side and top surfaces of the trench 220 are chamfered, the current path flowing across the surface of the second n layer 214 is shortened. As a result, the resistance of the element can be reduced.

[0059] Furthermore, the side regions 220c and 220d1 of the trench 220 do not need to be strictly perpendicular to the main surface of the substrate 210, but can be in the range of 80 to 90 degrees. Also, the side regions 220a and 220b of the trench 220 may be perpendicular or inclined, for example, they may be in the range of 45 to 90 degrees.

[0060] The inclination angle θ of region 220d2 on the side of trench 220 can be any value as long as it is greater than 0° and less than the inclination angles of the other regions on the side (220a, 220b, 220c, 220d1), but it is preferably between 15 and 75°. This range can further improve the coverage of the gate electrode 217. The inclination angle θ may also change in steps or continuously.

[0061] Furthermore, the width W of region 220d2 (where H0 is the thickness of the second n layer 214, (H0-H) / tanθ) is preferably 0.1 to 0.3 μm. This range can further improve the coverage of the gate electrode 217.

[0062] The height H can be any value as long as it is 0 or greater and less than or equal to the thickness H0 of the second n layer 214, but it is preferable that the height H is set such that the tilt angle θ is 15 to 75° and the width W is 0.1 to 0.3 μm.

[0063] An ion implantation region 215 is located near the surface of the first p layer 212. The ion implantation region 215 is a p-type region in which Mg ions are implanted on the surface of the first p layer 212, and is a region for forming a p-type impurity region 213. The side surface of the ion implantation region 215 is located inward from the side surface of the first p layer 212, and is positioned so as not to be exposed to the side surface of the trench 220. The side surface of the trench 220 is the device operating region, and if the ion implantation region 215, which is a region damaged by ion implantation, is exposed to the side surface of the trench 220, it may adversely affect the operation of the device.

[0064] The p-type impurity region 213 is located below the ion implantation region 215 and near the surface of the first n-layer 211. The p-type impurity region 213 is formed by the diffusion of Mg in the first p-layer 212 and the ion implantation region 215. This p-type impurity region 213 can alleviate the electric field concentrated at the corner 220e formed by the bottom and side of the trench 220. The Mg concentration in the p-type impurity region 213 is, for example, 1 × 10⁻⁶. 17 ~2×1018 / cm 3 Therefore, the deeper the region, the lower the Mg concentration. The bottom surface of the p-type impurity region 213 is a curved surface that is convex toward the substrate 210. Also, the width of the p-type impurity region 213 is approximately the same as the first p-layer 212 partitioned by the trench 220.

[0065] The thickness of the p-type impurity region 213 can be arbitrary, but it is preferable to set it as follows: It is preferable to set the thickness so that the corner 220e formed by the side and bottom surfaces of the trench 220 is not covered by the p-type impurity region 213 (see Figure 7). By making the corner 220e of the trench 220 in contact with the first n layer 211, a channel can be easily formed at that corner 220e, and the increase in resistance can be suppressed. Alternatively, the thickness may be such that the corner 220e of the trench 220 is in contact with the p-type impurity region 213. By making the corner 220e covered by the p-type impurity region 213, the electric field concentration at the corner 220e of the trench 220 can be further reduced, and further improvements in breakdown voltage and reliability can be achieved. In addition, it is preferable that the bottom surface 213a of the central part (thickest part) of the p-type impurity region 213 be lower (towards the substrate 210) than the bottom surface of the trench 220. This can further reduce the electric field concentration at the corner 220e of the trench 220.

[0066] The gate insulating film 216 is provided in a film-like manner along the bottom, side, and top surfaces of the trench 220. Here, the top surface of the trench 220 refers to the region of the second n layer 214 surface near the trench 220. The gate insulating film 216 is made of, for example, SiO2.

[0067] The gate electrode 217 is provided in a film-like manner along the bottom, side, and top surfaces of the trench 220 via a gate insulating film 216. The gate electrode 217 is made of, for example, Al. Here, the region 220d2 on the side of the trench 220 has a slope, which can improve the coverage of the gate electrode 217.

[0068] The drain electrode 218 is provided on the back surface of the substrate 210. The drain electrode 218 is made of, for example, Ti / Al.

[0069] A groove (recess) 221 is provided on the surface of the second n layer 214, in the central part when viewed from above, with a depth that penetrates the second n layer 214 and the ion implantation region 215 and reaches the first p layer 212. The first p layer 212 is exposed at the bottom of the recess 221.

[0070] The source electrode 219 is provided continuously on the surface of the second n layer 214, the side surface and bottom surface of the recess 221. The source electrode 219 is made of, for example, Ti / Al. The source electrode 219 is in contact with the undamaged first p layer 212, rather than the p-type impurity region 213 which is damaged by ion implantation. Therefore, the contact resistance of the source electrode 219 can be reduced. In addition, as in the first embodiment, body electrodes may be provided continuously on the bottom surface, side surface and top surface of the recess 221.

[0071] In the semiconductor device of the second embodiment, the p-type impurity region 213 is provided only in the intended region, enabling the device structure to be realized as designed. Furthermore, in the semiconductor device of the second embodiment, the n-type region on the surface of the first p-layer 212 is formed by epitaxial growth rather than ion implantation to create the second n-layer 214, making it easier to control the Si concentration and enabling higher concentrations. In addition, since the second n-layer 214 is not damaged by ion implantation, there is no concern about performance degradation such as increased resistance. Therefore, low resistance is possible.

[0072] Furthermore, in the semiconductor device of the second embodiment, the region on the side of the trench 220 where the second n layer 214 is exposed is inclined. Therefore, similar to the first embodiment, it is possible to improve the coverage of the gate electrode 15 while suppressing an increase in on-resistance.

[0073] Next, the method for manufacturing the semiconductor device according to the second embodiment will be described with reference to the figure.

[0074] First, a first n-GaN layer 211 and a first p-GaN layer 212 are sequentially laminated on a substrate 210 made of n-GaN using the MOCVD method (see Figure 8(a)). Then, a heat treatment is performed to activate the Mg in the first p-layer 212 and convert it to the p-type.

[0075] Next, a through-film (not shown) made of AlN is formed on the first p layer 212 by MOCVD, and Mg is ion-implanted on the surface of the first p layer 212 to form an ion-implanted region 215. The ion-implanted region is positioned inside the region of the first p layer 212 that is scheduled to be partitioned in subsequent processes. A photoresist or the like can be used as a mask to form in the region that is not ion-implanted. The through-film is used to control the amount of ions implanted into the first p layer 212. Ion implantation is performed, for example, at 500°C, an acceleration voltage of 230 keV, and a dose of 2.3 × 10⁻⁶. 14 / cm 2 This is done. After ion implantation, the through-membrane and mask are removed (see Figure 8(b)).

[0076] The ions to be implanted may be any p-type impurity other than Mg; for example, Be may be implanted. Furthermore, ion implantation may be performed in multiple steps, allowing for better control of the ion distribution in the depth direction. Additionally, ion implantation may be performed from a direction perpendicular to the surface of the first p-layer 212 while rotating the substrate 210. This narrows the width of the concentration distribution of the implanted ions in the depth direction, allowing for precise ion implantation at the target location.

[0077] Next, a second n-layer 214 made of n-GaN is formed on the first p-layer 212 and the ion-implanted region 215 by MOCVD (see Figure 8(c)).

[0078] Next, a predetermined region on the surface of the second n layer 214 is dry-etched until it reaches the first n layer 211 to form a trench 220 (see Figure 8(d)). This trench 220 partitions the first p layer 212 into predetermined regions, removing the first p layer 212 in the regions where the p-type impurity region 213 is not to be formed. Furthermore, the ion implantation region 215 was patterned to be inside the region of the first p layer 212 that was to be partitioned, so the ion implantation region 215 is inside the partitioned first p layer 212. Therefore, the ion implantation region 215 is not exposed on the side of the trench 220.

[0079] Next, a heat treatment is performed. The heat treatment atmosphere can be any inert gas atmosphere, such as a nitrogen atmosphere. The heat treatment temperature is 1000 to 1100°C, and the heat treatment time is 5 to 120 minutes. This heat treatment diffuses the Mg contained in the first p layer 212 and the ion implantation region 215 to the region on the surface side of the first n layer 211 and below the ion implantation region 215. This forms a p-type impurity region 213 below the ion implantation region 215 and to a predetermined depth from the surface of the first n layer 211 (see Figure 8(e)).

[0080] Here, since the trench 220 is formed before heat treatment, Mg does not diffuse laterally beyond this trench 220. Therefore, the width of the p-type impurity region 213 is approximately the same as the width of the first p-layer 212 demarcated by the trench 220.

[0081] The diffusion of Mg toward the substrate 210 decreases closer to the side of the trench 220 and increases further away from the side. As a result, the bottom surface of the p-type impurity region 213 becomes a curved surface that is convex toward the substrate 210.

[0082] The thickness of the p-type impurity region 213 can be controlled by ion implantation conditions, heat treatment conditions, the thickness of the first p-layer 212, the Mg concentration, etc. For example, in ion implantation conditions, the thickness of the p-type impurity region 213 can be increased by increasing the dose. In heat treatment conditions, the thickness of the p-type impurity region 213 can be increased by increasing the heat treatment time.

[0083] It is preferable to control the thickness of the p-type impurity region 213 so that the corner 220e formed by the side and bottom surfaces of the trench 220 is not covered by the p-type impurity region 213. By making the corner 220e of the trench 220 in contact with the first n layer 211, channels can be easily formed at the corner 220e, and the increase in resistance can be suppressed.

[0084] Alternatively, it is preferable that the corner 220e of the trench 220 be in contact with the p-type impurity region 213. By covering the corner 220e with the p-type impurity region 213, electric field concentration at the corner 220e of the trench 220 can be further reduced, thereby improving breakdown voltage and reliability.

[0085] Furthermore, it is preferable to control the thickness of the p-type impurity region 213 so that the thickest part of the p-type impurity region 213 is on the substrate 210 side of the bottom surface of the trench 220. This can further mitigate electric field concentration at the corners 220e of the trench 220.

[0086] Next, dry etching is performed on the entire upper surface of the wafer. In this dry etching process, the convex portions of the upper surface are preferentially etched, so the corners formed by the side surface and the upper surface of the trench 220 are preferentially etched. As a result, the corners are chamfered, and a sloped side surface is formed in region 220d2 of the side surface of the trench 220, while the other regions 220a, 220b, 220c, and 220d1 of the side surface remain vertical (see Figure 9(a)).

[0087] Furthermore, this dry etching removes thermal damage to the sides of the trench 220 caused by the heat treatment in the previous step. Conventionally, a protective film was formed before the heat treatment to suppress thermal damage, but in the second embodiment, this is not necessary, and the manufacturing process can be further simplified.

[0088] For etching, chlorine-based gases such as Cl2, BCl3, and SiCl4 are used. Cl2 is particularly preferred because it can suppress the adhesion of impurities (B and Si) to the first p layer 212.

[0089] Furthermore, this dry etching covers the entire top surface and does not require a mask, thus eliminating the need for mask formation margins. This allows for miniaturization of the device, which in turn reduces chip resistance.

[0090] Wet etching may be used instead of dry etching. However, in the case of wet etching, it is necessary to cover the areas that are not to be etched with a mask. An aqueous solution such as TMAH can be used as the wet etching solution. Furthermore, in the case of wet etching with TMAH, a specific surface orientation (m-plane) can be exposed on the side surface of the trench 220 due to anisotropy, thereby reducing on-resistance. In addition, since the etching rate becomes very slow once the specific surface orientation is exposed, it functions as an etching stopper and offers excellent shape reproducibility.

[0091] Next, a predetermined area on the surface of the second n layer 214 is dry-etched until it reaches the first p layer 212 to form a recess 221 (see Figure 9(b)). After forming the trench 220 and recess 221, dry etching of the entire upper surface of the wafer may be performed. In this case, the corners of the recess 221 can also be chamfered, which can improve the coverage of the source electrode 219.

[0092] Next, the gate insulating film 216 is formed in a film-like manner along the bottom, sides, and top of the trench 220 by the ALD method (see Figure 9(c)).

[0093] Next, a source electrode 219 is formed continuously on the second n layer 214, the side surface of the recess 221, and the bottom surface of the recess 221 by vapor deposition or sputtering. Then, a gate electrode 217 is formed on the bottom, side surface, and top surface of the trench 220 via a gate insulating film 216 by vapor deposition. Next, a drain electrode 218 is formed on the back surface of the substrate 210 by vapor deposition. The semiconductor device of the second embodiment is then fabricated.

[0094] As described above, according to the semiconductor device manufacturing method of the second embodiment, after ion implantation and before heat treatment, a trench 220 to a depth reaching the first n layer 211 is formed, and the first p layer 212 in the region where the p-type impurity region 213 is not to be formed is removed. Therefore, the Mg in the first p layer 212 and the ion implantation region 215 cannot diffuse laterally beyond the trench 220. As a result, the p-type impurity region 213 can be formed in the intended region, and the device structure as designed can be realized.

[0095] Furthermore, in the second embodiment, heat treatment damage can be removed, and the trench 220 can be etched so that region 220d2 on the side surface is inclined. As a result, the manufacturing process can be simplified, and, similar to the first embodiment, the coverage of the gate electrode 15 can be improved while suppressing the increase in on-resistance.

[0096] (modified version) The first and second embodiments were trench-gate type vertical MISFETs, but the present invention can be applied to any semiconductor device as long as it is a trench-gate type. For example, it can be applied to IGBTs. Furthermore, it can be applied not only to vertical devices but also to horizontal devices. [Industrial applicability]

[0097] This invention can be used in power devices and the like. [Explanation of Symbols]

[0098] 10: Circuit board 11: Drift layer 12: Channel Layer 13: Contact Layer 14: Gate Insulator 15: Gate Shutdown 16: Source electrode 17: Drain electrode 18: Body electrode 20: Trench 21: Recess

Claims

1. A trench gate type semiconductor device made of a group III nitride semiconductor, circuit board and A first layer made of an n-type group III nitride semiconductor is provided on the substrate, A second layer made of a p-type group III nitride semiconductor is provided on the first layer, A third layer made of an n-type group III nitride semiconductor is provided on the second layer, A trench is provided in a portion of the surface of the third layer, and penetrates the third layer and the second layer to a depth that reaches the first layer, A recess is provided in a portion of the surface of the third layer, and penetrates the third layer to a depth that reaches the second layer, A gate electrode covering the side surface of the trench and the third layer surface, which covers a region near the trench, The bottom surface, side surface, and third layer surface of the recess, and electrodes provided in the region near the recess, It has, The region of the trench side surface in which the second layer is exposed is perpendicular to the main surface of the substrate. In the trench side surface region where the third layer is exposed, the first region from the surface of the second layer to a predetermined height is perpendicular to the main surface of the substrate, and the second region from the predetermined height to the surface of the third layer is inclined with respect to the main surface of the substrate, and the inclination is such that the cross-sectional area of ​​the plane parallel to the bottom surface of the trench increases as you move from the bottom surface side of the trench to the top surface side. The corner formed by the side surface of the recess and the surface of the third layer is chamfered. A semiconductor device characterized by the following features.

2. An ion implantation region formed by implanting p-type impurity ions into a predetermined region of the surface of the second layer, A p-type impurity region formed below the ion implantation region, at a predetermined depth from the surface of the first layer and within the width of the second layer, The semiconductor element according to claim 1, further comprising the above.

3. The semiconductor element according to claim 1 or 2, characterized in that the inclination angle of the second region is 15 to 75°.

4. The semiconductor element according to claim 1 or 2, characterized in that the width of the second region in the direction parallel to the main surface of the substrate is 0.1 to 0.3 μm.

5. A method for manufacturing a trench gate type semiconductor device made of a group III nitride semiconductor, A first step involves sequentially forming a first layer made of an n-type group III nitride semiconductor, a second layer made of a p-type group III nitride semiconductor, and a third layer made of an n-type group III nitride semiconductor on a substrate. A second step involves forming a trench in a portion of the surface of the third layer, with a depth that penetrates the third layer and the second layer and reaches the first layer, such that the side surface of the trench is perpendicular to the main surface of the substrate. A third step involves etching the trench side so that, in the region of the trench side where the third layer is exposed, the first region from the surface of the second layer to a predetermined height is perpendicular to the main surface of the substrate, and the second region from the predetermined height to the surface of the third layer is inclined with respect to the main surface of the substrate, and the inclination is such that the cross-sectional area of ​​the plane parallel to the bottom surface of the trench increases as you move from the bottom surface side of the trench to the top surface side. A fourth step involves forming a recess in a portion of the surface of the third layer, with a depth that penetrates the third layer and reaches the second layer. A fifth step involves etching the corner formed by the side surface of the recess and the surface of the third layer so that it is chamfered, A sixth step is to form a gate electrode so as to cover the side surface of the trench and the third layer surface in the vicinity of the trench, A seventh step involves forming electrodes on the bottom surface, side surface, and third layer surface in a region near the recess of the recess. A method for manufacturing a semiconductor device, characterized by having the following features.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that the third step is a step of dry etching the entire upper surface of the wafer.

7. The first step includes a step of ion implanting p-type impurities into a predetermined region on the surface of the second layer after the formation of the second layer and before the formation of the third layer to form an ion implantation region, The process includes an eighth step, after the second step but before the third step, in which heat treatment is performed to diffuse p-type impurities in the second layer, thereby forming a p-type impurity region in the ion implantation region, at a predetermined depth from the surface of the first layer, and within the width of the second layer. The third step also serves to remove the thermal damage that occurred on the trench side surface as a result of the eighth step. A method for manufacturing a semiconductor device according to claim 5 or 6, characterized by the above.

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