Semiconductor equipment

Abstract

To stabilize an operation.SOLUTION: A semiconductor device includes a substrate, a metal layer provided under the substrate, a plurality of source electrodes provided on the substrate, one or a plurality of first via wires overlapping, in plan view, one of first source electrodes among the plurality of source electrodes being the closest to an end of the source electrodes arranged in a direction where the source electrodes are arranged, penetrating the substrate, and electrically connecting the metal layer and the first source electrode, and one or a plurality of second via wires overlapping, in plan view, one of second source electrodes among the source electrodes being the second closest to the end of the source electrodes, penetrating the substrate, and electrically connecting the metal layer and the second source electrode. A first inductance between one of the first source electrodes and the metal layer through one or a plurality of first via wires is larger than a second inductance between one of the second source electrodes and the metal layer through one or a plurality of second via wires.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] In a multi-finger type field effect transistor (FET) having a plurality of source electrodes, a plurality of gate electrodes, and a plurality of drain electrodes, it is known to connect via holes to the source electrodes (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The source inductance may be different between the source electrode closest to the edge among the plurality of source electrodes and the other source electrodes. As a result, the high-frequency operation may become unstable.

[0005] This disclosure has been made in view of the above problems, and an object thereof is to stabilize the operation.

Means for Solving the Problems

[0006] One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a metal layer provided beneath the substrate; a plurality of source electrodes provided on the substrate; one or more first vias that overlap in a plan view with one of the first source electrodes closest to the edge of the plurality of source electrodes arranged in the direction in which the plurality of source electrodes are arranged, penetrate the substrate, and electrically connect the metal layer and the first source electrode; and one or more second vias that overlap in a plan view with one of the second source electrodes second closest to the edge of the plurality of source electrodes, penetrate the substrate, and electrically connect the metal layer and the second source electrode, wherein the first inductance through the one or more first vias between one of the first source electrodes and the metal layer is greater than the second inductance through the one or more second vias between one of the second source electrodes and the metal layer. [Effects of the Invention]

[0007] According to this disclosure, the operation can be stabilized. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a plan view of the semiconductor device according to Example 1. [Figure 2] Figure 2 is a cross-sectional view of AA in Figure 1. [Figure 3] Figure 3 is a plan view of the semiconductor device according to Comparative Example 1. [Figure 4] Figure 4 is a plan view showing the virtual structure 1. [Figure 5] Figure 5 is a circuit diagram showing the equivalent circuit of virtual structure 1. [Figure 6] Figure 6 is a plan view showing the virtual structure 2. [Figure 7] Figure 7 is a circuit diagram showing the equivalent circuit of virtual structure 2. [Figure 8] Figure 8 is a plan view showing the virtual structure 3. [Figure 9] Figure 9 is a plan view of the semiconductor device according to Example 2. [Figure 10] Figure 10 is a plan view of the semiconductor device according to Example 3. [Figure 11] Figure 11 is a plan view of the device according to Example 4. [Figure 12] Figure 12 is a plan view of the semiconductor device according to Example 5. [Figure 13] Figure 13 is a plan view of the semiconductor device according to Example 6. [Figure 14] Figure 14 is a plan view of the semiconductor device according to Example 7. [Modes for carrying out the invention]

[0009] [Details of the embodiments of this disclosure] First, the contents of the embodiments of this disclosure will be listed and explained. (1) One embodiment of the present disclosure is a semiconductor device comprising: a substrate; a metal layer provided beneath the substrate; a plurality of source electrodes provided on the substrate; one or more first vias that overlap in a plan view with one of the first source electrodes closest to the end of the plurality of source electrodes arranged in the direction in which the plurality of source electrodes are arranged, penetrate the substrate, and electrically connect the metal layer and the first source electrode; and one or more second vias that overlap in a plan view with one of the second source electrodes second closest to the end of the plurality of source electrodes, penetrate the substrate, and electrically connect the metal layer and the second source electrode, wherein the first inductance through the one or more first vias between one of the first source electrodes and the metal layer is greater than the second inductance through the one or more second vias between one of the second source electrodes and the metal layer. This allows for stable operation. (2) In (1) above, the one or more first via connections are multiple first via connections, the one or more second via connections are multiple second via connections, and the spacing between adjacent first via connections may be smaller than the spacing between adjacent second via connections. (3) In (2) above, the number of the plurality of first vias is less than or equal to the number of the plurality of second vias, and the area in a plan view in which each of the plurality of first vias contacts the first source electrode is less than or equal to the area in a plan view in which each of the plurality of second vias contacts the second source electrode. (4) In (1) above, the number of the one or more first via connections may be less than the number of the one or more second via connections. (5) In the above (4), if the one or more first vias are a plurality of first vias and the one or more second vias are a plurality of second vias, the spacing between adjacent first vias is less than or equal to the spacing between adjacent second vias, and the area in a plan view where each of the one or more first vias contacts the first source electrode is less than or equal to the area in a plan view where each of the one or more second vias contacts the second source electrode. (6) In (1) above, the area in a plan view in which each of the one or more first vias contacts the first source electrode may be smaller than the area in a plan view in which each of the one or more second vias contacts the second source electrode. (7) In the above (6), The number of the one or more first via connections is less than or equal to the number of the one or more second via connections. If the one or more first vias are multiple first vias and the one or more second vias are multiple second vias, then the spacing between adjacent first vias is less than or equal to the spacing between adjacent second vias. a That's fine. (8) In any of (1) to (7) above, one of the plurality of source electrodes, the third source electrode closest to the end, overlaps in a plan view with the substrate and penetrates the metal layer and the 3 The device comprises one or more third via connections electrically connecting to a source electrode, wherein the third inductance through the one or more third via connections between one of the third source electrodes and the metal layer may be less than the second inductance. (9) In any of (1) to (8) above, when the one or more first via wirings are one first via wiring, the first inductance is the self-inductance of the one first via wiring, and when the one or more first via wirings are a plurality of first via wirings, the first inductance is the sum of the inductance obtained by synthesizing the self-inductances of each of the plurality of first via wirings and the mutual inductance between the plurality of first via wirings. When the one or more second via wirings are one second via wiring, the second inductance is the self-inductance of the one second via wiring, and when the one or more second via wirings are a plurality of second via wirings, the second inductance may be the sum of the inductance obtained by synthesizing the self-inductances of each of the plurality of second via wirings and the mutual inductance between the plurality of second via wirings. (10) In any of (1) to (9) above, a plurality of gate electrodes provided on the substrate and a plurality of drain electrodes provided on the substrate are provided, and each of the plurality of gate electrodes may be sandwiched between the plurality of source electrodes and the plurality of drain electrodes.

[0010] A specific example of a semiconductor device according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is shown by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0011] [Example 1] FIG. 1 is a plan view of a semiconductor device according to Example 1. FIG. 2 is a cross-sectional view taken along line A-A of FIG. 1. The normal direction of the upper surface of the substrate 10 is the Z direction, the arrangement direction of the source electrodes 12a to 12c, the gate electrode 14, and the drain electrode 16 is the X direction, and the extending direction is the Y direction. In the plan view such as FIG. 1, the source electrodes 12a to 12c, the drain electrode 16, and the drain bus bar 26 are shown by cross-hatching.

[0012] As shown in Figures 1 and 2, in the semiconductor device 100 of Embodiment 1, the substrate 10 comprises a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. An active region 11 is provided on the substrate 10. Regions other than the active region 11 are inactive regions in which the semiconductor layer 10b has been deactivated by ion implantation or the like. That is, the active region 11 is the region in the substrate 10 in which the semiconductor layer 10b is activated, and the inactive region is the region in which the semiconductor layer 10b has been deactivated. The FET 35 is provided in the active region 11.

[0013] Multiple source electrodes 12a to 12c (source fingers), a gate electrode 14 (gate finger), and a drain electrode 16 (drain finger) are provided on the active region 11. Source electrode 12a (first source electrode) is closest to the end of the multiple source electrodes 12a to 12c in the X direction (the direction in which the source electrodes 12a to 12c are arranged). Source electrode 12b (second source electrode) is second closest to the end of the multiple source electrodes 12a to 12c in the X direction. Source electrode 12c (third source electrode) is third closest to the end of the multiple source electrodes 12a to 12c in the X direction.

[0014] In the X direction, the drain electrode 16 and the source electrodes 12a to 12c are arranged alternately, one at a time. The gate electrode 14 is provided between one of the multiple source electrodes 12a to 12c and one of the multiple drain electrodes 16. As a result, the source electrodes 12a to 12c and the drain electrode 16 sandwiching the gate electrode 14 form a single unit FET 35a to 35c. Each of the unit FETs 35a to 35c is connected to the source electrode 12a 12c It has the following characteristics. Unit FETs 35a to 35c are arranged in the X direction. The number of unit FETs 35a to 35c should be four or more.

[0015] A gate busbar 24 and a drain busbar 26 are provided extending in the X direction on an inactive region on the upper surface of the substrate 10. The -Y ends in the Y direction of multiple gate electrodes 14 are connected to the gate busbar 24. The +Y ends in the Y direction of multiple drain electrodes 16 are connected to the drain busbar 26.

[0016] Via holes 22a to 22c, which penetrate the substrate 10, are connected to source electrodes 12a to 12c, respectively. A metal layer 28 is provided on the lower surface of the substrate 10. A reference potential, such as ground potential, is supplied to the metal layer 28. Via wirings 28a (first via wiring), 28b (second via wiring), and 28c (third via wiring) are provided on the side and top surfaces of the via holes 22a, 22b, and 22c, respectively. That is, via wirings 28a to 28c are provided on the substrate below source electrodes 12a to 12c, and overlap with source electrodes 12a to 12c in a plan view. Via wirings 28a to 28c penetrate the substrate 10 and electrically connect and short-circuit the metal layer 28 and source electrodes 12a to 12c, respectively. Via wirings 28a to 28c are made of the same metal layer as metal layer 28 and are formed simultaneously. A cavity is provided within the via wiring 28a to 28c within the via holes 22a to 22c. The cavity is filled with a gas such as air. A conductor may be embedded in the cavity within the via wiring 28a to 28c.

[0017] Within a single source electrode 12a to 12c, via connections 28a to 28c are arranged in the Y direction. The planar shape of via connections 28a to 28c is, for example, a rounded rectangle. The long axis direction of via connections 28a to 28c is the Y direction, and the short axis directionThis is in the X direction. The planar shape of via wiring 28a to 28c may be a rounded rectangle, or it may be a roughly elliptical, roughly circular, or oblong shape. The planar area of ​​via wiring 28a to 28c (the area in the region that contacts source electrodes 12a to 12c) is approximately the same for all of them. The region in which via wiring 28a to 28c connects to source electrodes 12a to 12c is contained within source electrodes 12a to 12c. That is, via wiring 28a to 28c is not provided outside of source electrodes 12a to 12c on the upper surface of substrate 10.

[0018] If the semiconductor device 100 is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a diamond substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes, for example, a nitride semiconductor layer such as a GaN layer, an AlGaN layer, and / or an InGaN layer. If the semiconductor device 100 is a GaN HEMT (Gallium Nitride High Electron Mobility Transistor), the semiconductor layer 10b includes a GaN electron transport layer and an AlGaN barrier layer provided on the GaN electron transport layer. If the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes, for example, an arsenide semiconductor layer such as a GaAs layer, an AlGaAs layer, and / or an InGaAs layer.

[0019] From source electrode 12a 12c The drain electrode 16 is, for example, a metal film such as an adhesion film (e.g., a titanium film) provided on the substrate 10 and an aluminum film provided on the adhesion film. A wiring layer such as a gold layer may be provided on the aluminum film. The gate electrode 14 is, for example, a metal film such as an adhesion film (e.g., a nickel film) provided on the substrate 10 and a gold film provided on the adhesion film. The metal layer 28 and via wirings 28a to 28c are, for example, gold layers.

[0020] The widths Vx in the X direction of via connections 28a to 28c are approximately the same, for example, 20 μm. The widths Va, Vb, and Vc in the Y direction of via connections 28a to 28c are approximately the same, for example, 50 μm. The spacing Db in the Y direction of via connections 28b and the spacing Dc in the Y direction of via connections 28c are approximately the same, for example, 50 μm. The spacing Da in the Y direction of via connections 28a is smaller than the spacings Db and Dc, for example, 20 μm. The spacing Dab in the X direction between via connections 28a and 28b, and the spacing Dbc in the X direction between via connections 28b and 28c are, for example, 100 μm. The thickness T1 of the substrate 10 is, for example, 100 μm, and the thickness T2 of via connections 28a, 28b, and 28c is, for example, 5 μm.

[0021] [Comparative Example 1] Figure 3 is a plan view of the semiconductor device according to Comparative Example 1. As shown in Figure 3, in the semiconductor device 110 of Comparative Example 1, the spacing Da of the via wiring 28a is approximately the same as the spacings Db and Dc. The other configurations are the same as in Example 1 and will not be described.

[0022] [Virtual Structure 1] The problem of Comparative Example 1 will be explained using a hypothetical structure. Note that the following discussion using the hypothetical structure assumes that the Y-direction width of source electrodes 12a to 12c is sufficiently smaller than the wavelength of the high-frequency signal. If the Y-direction width of source electrodes 12a to 12c is approximately the wavelength of the high-frequency signal, then source electrodes 12a to 12c will be represented as distributed parameters, making a lumped-parameter representation difficult. For example, when semiconductor device 100 is used as a power amplifier for wireless communication, the operating bandwidth is in the range of 0.5 GHz to 10 GHz. If the frequency of the high-frequency signal (e.g., the center frequency of the amplifier's operating bandwidth) is 10 GHz or less, the above condition is satisfied if the Y-direction width of source electrodes 12a to 12c is several hundred μm or less.

[0023] Figure 4 is a plan view showing the virtual structure 1. As shown in Figure 4, the source electrode 12a is connected to ground via a via wiring 28a provided in the via hole 22a. The via wiring 28a has a self-inductance of 2 × L1. Since the two via wirings 28a are magnetically coupled, a mutual inductance M1 is generated.

[0024] Figure 5 is a circuit diagram showing the equivalent circuit of virtual structure 1. As shown in Figure 5, the line between ports P1 and P2 (corresponding to source electrode 12a) is connected to ground Gnd via the resistance Rv, self-inductance L1, and mutual inductance M1 of via wiring 28a. The self-inductance L1 is the sum of the two self-inductances 2 × L1 of via wiring 28a connected in parallel, resulting in a total inductance L1.

[0025] [Virtual Structure 2] Figure 6 is a plan view showing the virtual structure 2. As shown in Figure 6, source electrodes 12a and 12b are connected to ground via via wirings 28a and 28b provided in via holes 22a and 22b, respectively. Via wirings 28a and 28b have a self-inductance of 2 × L1. Similar to via wiring 28a, the two via wirings 28b are magnetically coupled to each other, resulting in a mutual inductance M1. Furthermore, via wirings 28a and 28b are magnetically coupled. This results in a mutual inductance M2.

[0026] Figure 7 is a circuit diagram showing the equivalent circuit of virtual structure 2. As shown in Figure 7, the line of port P1 (corresponding to source electrode 12a) is connected to node N1 via resistor Rv, self-inductance L1, and mutual inductance M1. The line of port P2 (corresponding to source electrode 12b) is connected to node N1 via resistor Rv, self-inductance L1, and mutual inductance M1. Node N1 is connected to ground via mutual inductance M2.

[0027] Thus, in virtual structure 2, the source inductance is larger than in virtual structure 1 by the amount of mutual inductance M2. The inductances were simulated using electromagnetic field analysis. In the simulation, the width Vx of via wiring 28a to 28c was set to 20 μm, the widths Va, Vb and Vc were set to 50 μm, the spacing Da, Db and Dc between via wirings 28a to 28c were set to 50 μm, and the spacing Dab between via wiring 28a and 28b was set to 50 μm. of The substrate 10 was a SiC substrate with a thickness T1 of 100 μm, and the via wirings 28a, 28b, and 28c had a thickness T2 of 5 μm. At this time, L1 = 15 pH, M1 = 5 pH, and M2 = 5 pH.

[0028] [Virtual Structure 3] Figure 8 is a plan view showing the virtual structure 3. As shown in Figure 8, source electrodes 12a to 12c are arranged in the same way as in Figure 3. The mutual inductance between adjacent source electrodes and via wiring is denoted as M2, and the mutual inductance between adjacent electrodes and via wiring is denoted as M3. The mutual inductance M3 is smaller than the mutual inductance M2.

[0029] The mutual inductances contributing to the source inductance Lsa of source electrode 12a are the mutual inductance M2 between source electrode 12a and the via wiring 28b of the adjacent source electrode 12b, and the mutual inductance M3 between source electrode 12c and the via wiring 28c of the two adjacent source electrode 12c. The mutual inductances contributing to the source inductance Lsb of source electrode 12b are the mutual inductance M2 between source electrode 12a and the via wiring 28a of the adjacent source electrode 12a, the mutual inductance M2 between source electrode 12c and the via wiring 28c of the adjacent source electrode 12c, and the mutual inductance M3 between source electrode 12b and the via wiring 28b of the two adjacent source electrode 12b. to The mutual inductance is M3. The mutual inductances contributing to the source inductance Lsc of the source electrode 12c are the two mutual inductances M2 between the two source electrodes 12b and the via wiring 28b, and the two mutual inductances M3 between the two source electrodes 12a and the via wiring 28a.

[0030] Thus, the mutual inductance contributing to the source inductance Lsa of the source electrode 12a is one mutual inductance M2 and one mutual inductance M3. The mutual inductance contributing to the source inductance Lsb of the source electrode 12b is two mutual inductances M2 and one mutual inductance M3. The mutual inductance contributing to the source inductance Lsc of the source electrode 12c is two mutual inductances M2 and two mutual inductances M3. These mutual inductances are connected in series with the ground. Simplifying and describing the above inductance relationships, Lsa = L1 + M1 + M2 + M3 Lsb = L1 + M1 + 2×M2 + M3 Lsc = L1 + M1 + 2×M2 + 2×M3 That is. The magnitude relationship of the source inductances is Lsa < Lsb < Lsc. Since the mutual inductance M3 is smaller than M2, Lsb - Lsa > Lsc - Lsb.

[0031] As described above, in Comparative Example 1, the source inductances Lsa of the unit FET 35a, the source inductance Lsb of the unit FET 35b, and the source inductance Lsc of the unit FET 35c are different. Therefore, when the semiconductor device 110 is used as an amplifier and a high-frequency signal is input to the gate electrode 14, the operations of the unit FETs 35a to 35c become non-uniform. As a result, the gain of the amplifier decreases.

[0032] According to Example 1, the interval Da between the via wirings 28a is smaller than the intervals Db and Dc. As a result, the mutual inductance M1a between the via wirings 28a becomes larger than the mutual inductance M1 between the via wirings 28b and the mutual inductance M1 between the via wirings 28c. That is Lsa = L1 + M1a + M2 + M3 On the other hand, [[ID= (21)]] Lsb = L1 + M1 + 2×M2 + M3 Therefore, by setting M1a-M1 to approximately M2, Lsa and Lsb can be made almost the same. Thus, the difference between Lsa and Lsb in Example 1 can be made smaller than the difference between Lsa and Lsb in Comparative Example 1. On the other hand, the difference between Lsb and Lsc in Comparative Example 1 is not very large. Thus, the operation of unit FETs 35a to 35c can be made uniform.

[0033] [Example 2] Figure 9 is a plan view of the semiconductor device according to Embodiment 2. As shown in Figure 9, in the semiconductor device 101 of Embodiment 2, the spacing Da in the Y direction of via wiring 28a is smaller than the spacing Db in the Y direction of via wiring 28b, and the spacing Db is smaller than the spacing Dc in the Y direction of via wiring 28c. The widths Va, Vb, and Vc in the Y direction of via wirings 28a to 28c are the same. The other configurations are the same as in Embodiment 1 and will not be described.

[0034] The relationship between the inductances in Example 2 can be simplified as follows: Lsa = L1 + M1a + M2 + M3 Lsb = L1 + M1b + 2 × M2 + M3 Lsc = L1 + M1c + 2 × M2 + 2 × M3 Here, Da <Db<Dcであるため、M1a> M1b > M1c. Set M1a-M1b to approximately M2 and M1b-M1c to approximately M3. This allows the difference between Lsa and Lsb, and the difference between Lsb and Lsc, to be smaller in Example 2 compared to Comparative Example 1. Therefore, the operation of unit FETs 35a to 35c can be made more uniform.

[0035] [Example 3] Figure 10 is a plan view of the semiconductor device according to Embodiment 3. As shown in Figure 10, in the semiconductor device 102 of Embodiment 3, two via connections 28a are connected to one source electrode 12a. Three via connections 28b are connected to one source electrode 12b. Three via connections 28c are connected to one source electrode 12c. The spacings Da, Db, and Dc are approximately the same, and the widths Va, Vb, and Vc are approximately the same. The other configurations are the same as in Embodiment 1 and will not be described.

[0036] The relationships between the inductances in Example 3 can be simplified as follows: Lsa = L1a + M1 + M2 + M3 Lsb = L1b + M1 + 2 × M2 + M3 Lsc = L1c + M1 + 2 × M2 + 2 × M3 Therefore, there are two via connections 28a connected to one source electrode 12a, three via connections 28b connected to one source electrode 12b, and three via connections 28c connected to one source electrode 12c. Thus, L1b = L1c ≈ 2 × L1a / 3. Therefore, L1a > L1b = L1c. As a result, the difference between Lsa and Lsb can be made smaller in Example 3 compared to Comparative Example 1. Thus, the operation of unit FETs 35a to 35c can be made uniform.

[0037] [Example 4] Figure 11 is a plan view of the semiconductor device according to Embodiment 4. As shown in Figure 11, in the semiconductor device 103 of Embodiment 4, two via connections 28a are connected to one source electrode 12a. Three via connections 28b are connected to one source electrode 12b. Four via connections 28c are connected to one source electrode 12c. The spacings Da, Db, and Dc are approximately the same, and the widths Va, Vb, and Vc are approximately the same. The other configurations are the same as in Embodiment 1 and will not be described.

[0038] The relationships between the inductances in Example 4 can be simplified as follows: Lsa = L1a + M1 + M2 + M3 Lsb = L1b + M1 + 2 × M2 + M3 Lsc = L1c + M1 + 2 × M2 + 2 × M3 Therefore, from the number of via connections 28a, 28b, and 28c, L1b ≈ 2 × L1a / 3. L1c ≈ L1a / 2. Therefore, L1a > L1b > L1c. As a result, in Example 4, the difference between Lsa and Lsb and the difference between Lsb and Lsc can be reduced compared to Comparative Example 1. Therefore, the operation of unit FETs 35a to 35c can be made uniform.

[0039] [Example 5] Figure 12 is a plan view of the semiconductor device according to Embodiment 5. As shown in Figure 12, in the semiconductor device 104 of Embodiment 5, two via connections 28a are connected to one source electrode 12a. Three via connections 28b are connected to one source electrode 12b. Three via connections 28c are connected to one source electrode 12c. The spacing Da is smaller than Db and Dc. The widths Va, Vb, and Vc are approximately the same as those of Embodiment 1 and are therefore omitted from the description.

[0040] The relationships between the inductances in Example 5 can be described in a simplified manner: Lsa = L1a + M1a + M2 + M3 Lsb = L1b + M1b + 2 × M2 + M3 Lsc = L1c + M1c + 2 × M2 + 2 × M3 Therefore, the number of via connections 28a is less than the number of via connections 28b and 28c. Thus, L1a > L1b ≈ L1c.<Db=Dcであるため、M1a> M1b ≈ M1c. As a result, in Example 5, the difference between Lsa and Lsb can be reduced compared to Comparative Example 1. Therefore, the operation of unit FETs 35a to 35c can be made uniform.

[0041] [Example 6] Figure 13 is a plan view of the semiconductor device according to Embodiment 6. As shown in Figure 13, in the semiconductor device 105 of Embodiment 6, the width Va of via wiring 28a in the Y direction is smaller than the width Vb of via wiring 28b in the Y direction, and the width Vb is smaller than the width Vc of via wiring 28c in the Y direction. The other configurations are the same as in Embodiment 1 and will not be described.

[0042] The relationships between the inductances in Example 6 can be described in a simplified manner as follows: Lsa = L1a + M1 + M2 + M3 Lsb = L1b + M1 + 2 × M2 + M3 Lsc = L1c + M1 + 2 × M2 + 2 × M3 That is. <Vb<Vcのため、L1a> L1b > L1c. As a result, in Example 6, the difference between Lsa and Lsb, and the difference between Lsb and Lsc can be reduced compared to Comparative Example 1. Therefore, the operation of unit FETs 35a to 35c can be made uniform.

[0043] [Example 7] Figure 14 is a plan view of the semiconductor device according to Embodiment 7. As shown in Figure 14, in the semiconductor device 106 of Embodiment 7, one via wiring 28a is connected to one source electrode 12a. Two via wirings 28b are connected to one source electrode 12b. Three via wirings 28c are connected to one source electrode 12c. The width Va of the via wiring 28a in the Y direction is smaller than the width Vb of the via wiring 28b in the Y direction, and the width Vb is smaller than the width Vc of the via wiring 28c in the Y direction. The spacing Db of the via wiring 28b in the Y direction is smaller than the spacing Dc of the via wiring 28c in the Y direction. The other configurations are the same as in Embodiment 1 and will not be described.

[0044] The relationships between the inductances in Example 7 can be described in a simplified manner as follows: Lsa = L1a + M2 + M3 Lsb = L1b + M1b + 2 × M2 + M3 Lsc = L1c + M1c + 2 × M2 + 2 × M3 Therefore, M1 is not included in Lsa because there is only one via wiring 28a connected to one source electrode 12a. Db<Dcのため、M1b> It is M1c. <Vb<Vcのため、L1a> L1b > L1c. As a result, in Example 7, the difference between Lsa and Lsb, and the difference between Lsb and Lsc can be reduced compared to Comparative Example 1. Therefore, the operation of unit FETs 35a to 35c can be made uniform.

[0045] [Summary of Examples 1 to 7] In Examples 1 to 7, the first inductance through one or more via connections 28a between one of the source electrodes 12a and the metal layer 28 is greater than the second inductance through one or more via connections 28b between one of the source electrodes 12b and the metal layer 28. This makes the difference between the source inductance Lsa of source electrode 12a and the source inductance Lsb of source electrode 12b smaller than in Comparative Example 1. Therefore, the operation of unit FETs 35a to 35c can be made uniform. The gain of semiconductor devices 100 to 106 can be improved.

[0046] As in Examples 2, 4, 5, and 7, the third inductance through one or more via connections 28c between one of the source electrodes 12c and the metal layer 28 is smaller than the second inductance through one or more via connections 28b between one of the source electrodes 12b and the metal layer 28. This makes the difference between the source inductance Lsb of source electrode 12b and the source inductance Lsc of source electrode 12c smaller than in Comparative Example 1. Thus, the operation of unit FETs 35a to 35c can be made uniform, and the gain of the semiconductor device can be further improved.

[0047] The first inductance is, for example, 1.05 times or more and 1.1 times or more than the second inductance. Also, the first inductance is, for example, 2 times or less than the second inductance. The difference between source inductances Lsa and Lsb in Examples 1 to 7 is smaller than the difference between source inductances Lsa and Lsb in Comparative Example 1, where the number of via wirings 28a and 28b are the same and Va=Vb and Da=Db. As a result, the operation of unit FETs 35a to 35c can be made more uniform than in Comparative Example 1.

[0048] The second inductance is, for example, 1.01 times or more the third inductance and 1.05 times or more. Also, the second inductance is, for example, 1.5 times or less the third inductance. Compared to the difference between source inductances Lsb and Lsc in Comparative Example 1, the source inductances in Examples 2, 4, 5 and 7 Lsb and Lsc The difference is small. This makes it possible to make the operation of unit FETs 35a to 35c more uniform than in Comparative Example 1.

[0049] When one via wiring 28a is connected to one source electrode 12a, the first inductance is the self-inductance of the single via wiring 28a. When multiple via wirings 28a are connected to one source electrode 12a, the first inductance is the inductance resulting from the sum of the self-inductances of each via wiring 28a (L1) and the mutual inductance M1 between the multiple via wirings 28a.

[0050] When one via wiring 28b is connected to one source electrode 12b, the second inductance is the self-inductance of the single via wiring 28b. When multiple via wirings 28b are connected to one source electrode 12b, the second inductance is the inductance resulting from the sum of the self-inductances of each via wiring 28b (L1) and the mutual inductance M1 between the multiple via wirings 28b.

[0051] When one via wiring 28c is connected to one source electrode 12c, the third inductance is the self-inductance of the via wiring 28c. When multiple via wirings 28c are connected to one source electrode 12c, the third inductance is the inductance resulting from the sum of the self-inductances of each via wiring 28c (L1) and the mutual inductance M1 between the multiple via wirings 28c.

[0052] These methods allow the difference in mutual inductance M2 between source inductance Lsa and Lsb to be compensated using self-inductance L1 and mutual inductance M1.

[0053] As in Examples 1, 2, and 5, the spacing Da between adjacent vias 28a is made smaller than the spacing Db between adjacent vias 28b. This makes the mutual inductance M1 at source inductance Lsa larger than the mutual inductance M1 at source inductance Lsb. Thus, the difference between source inductances Lsa and Lsb can be reduced.

[0054] In this case, the first number of via connections 28a connected to one source electrode 12a is made equal to or less than the second number of via connections 28b connected to one source electrode 12b. The first area in a plan view where each via connection 28a contacts the source electrode 12a is made equal to or less than the second area in a plan view where each via connection 28b contacts the source electrode 12b. This makes the sum of the self-inductance L1 and mutual inductance M1 in source inductance Lsa greater than the sum of the self-inductance L1 and mutual inductance M1 in source inductance Lsb.

[0055] For example, the spacing Da is 0.95 times or less of the spacing Db and 0.9 times or less. Also, for example, spacing Da is 0.1 times or more of the spacing Db. When the difference between source inductance Lsb and Lsc is reduced, spacing Db is smaller than spacing Dc and 0.99 times or less of the spacing Dc and 0.98 times or less. Also, for example, spacing Db is 0.1 times or more of the spacing Dc. When there are three or more via connections 28a (28b or 28c) connected to one source electrode 12a (12b or 12c), there are multiple spacings between adjacent via connections 28a (28b or 28c). If the values ​​of the multiple spacings are different from each other, spacing Da (Db or Dc) is the average of the values ​​of the multiple spacings.

[0056] As in Examples 3, 4, 5, and 7, the number of via connections 28a is reduced to less than the number of via connections 28b. This makes the self-inductance L1 at source inductance Lsa greater than the self-inductance L1 at source inductance Lsb. Thus, the difference between source inductance Lsa and Lsb can be reduced.

[0057] In this configuration, the spacing Da between adjacent vias 28a is made equal to or smaller than the spacing Db between adjacent vias 28b. The first area in a plan view where each via 28a contacts the source electrode 12a is made equal to or smaller than the second area in a plan view where each via 28b contacts the source electrode 12b. This makes the sum of the self-inductance L1 and mutual inductance M1 in the source inductance Lsa greater than the sum of the self-inductance L1 and mutual inductance M1 in the source inductance Lsb.

[0058] For example, to reduce the difference between source inductances Lsb and Lsc, the number of via connections 28b is reduced to less than the number of via connections 28c.

[0059] As in Examples 6 and 7, the first area in a plan view where each via wiring 28a contacts the source electrode 12a is made smaller than the second area in a plan view where each via wiring 28b contacts the source electrode 12b. This makes the sum of the self-inductance L1 and mutual inductance M1 at source inductance Lsa larger than the sum of the self-inductance L1 and mutual inductance M1 at source inductance Lsb.

[0060] In this configuration, the spacing Da between multiple vias 28a is set to be the same as or smaller than the spacing Db between vias 28b. The first number of vias 28a connected to one source electrode 12a is set to be the same as or smaller than the second number of vias 28b connected to one source electrode 12b. This makes the sum of the self-inductance L1 and mutual inductance M1 in source inductance Lsa greater than the sum of the self-inductance L1 and mutual inductance M1 in source inductance Lsb.

[0061] For example, the first area is 0.95 times or less of the second area and 0.9 times or less. Also, the first area is, for example, 0.1 times or more of the second area. When the difference between source inductances Lsb and Lsc is reduced, the second area is smaller than the third area in a plan view where the via wiring 28c contacts the source electrode 12c, 0.99 times or less of the third area and 0.95 times or less. Also, the second area is, for example, 0.1 times or more of the third area. When there are multiple via wirings 28a (28b or 28c) connected to one source electrode 12a (12b or 12c), and the areas of the multiple via wirings 28a (28b or 28c) are different from each other, the first area (second area or third area) is the average of the areas of the multiple via wirings 28a (28b or 28c).

[0062] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims, not in the sense described above, and all modifications within the meaning and scope equivalent to the claims are intended. [Explanation of Symbols]

[0063] 10, 10a substrate 10b Semiconductor layer 11 Active area 12a, 12b, 12c source electrodes 14 Guard gate 16 Drain electrode 22a, 22b, 22c via holes 24 Gate Bus Bar 26 Drain Busbar 28 Metal layer Via wiring for 28a, 28b, and 28c 35a, 35b, 35c Unit FET 100, 101, 102, 103, 104, 105, 106, 110 Semiconductor

Claims

1. circuit board and A metal layer provided beneath the substrate, Multiple source electrodes provided on the substrate, One or more first via connections, which overlap in a plan view with one of the first source electrodes closest to the end of the arranged multiple source electrodes in the direction in which the multiple source electrodes are arranged, penetrate the substrate, and electrically connect the metal layer and the first source electrode, One or more second via connections overlap in a plan view with one of the second source electrodes, which is the second closest to the end among the plurality of source electrodes, penetrate the substrate, and electrically connect the metal layer and the second source electrode. Equipped with, A semiconductor device in which the first inductance through the one or more first via connections between one of the first source electrodes and the metal layer is greater than the second inductance through the one or more second via connections between one of the second source electrodes and the metal layer.

2. The one or more first via connections are multiple first via connections, The one or more second via connections are a plurality of second via connections, The semiconductor device according to claim 1, wherein the spacing between adjacent first vias is smaller than the spacing between adjacent second vias.

3. The number of the plurality of first via connections is less than or equal to the number of the plurality of second via connections. The semiconductor device according to claim 2, wherein the area in a plan view where each of the plurality of first via connections contacts the first source electrode is less than or equal to the area in a plan view where each of the plurality of second via connections contacts the second source electrode.

4. The semiconductor device according to claim 1, wherein the number of the one or more first via connections is less than the number of the one or more second via connections.

5. If the one or more first via connections are multiple first via connections, and the one or more second via connections are multiple second via connections, then the spacing between adjacent first via connections is less than or equal to the spacing between adjacent second via connections. The semiconductor device according to claim 4, wherein the area in a plan view in which each of the one or more first vias contacts the first source electrode is less than or equal to the area in a plan view in which each of the one or more second vias contacts the second source electrode.

6. The semiconductor device according to claim 1, wherein the area in a plan view where each of the one or more first vias contacts the first source electrode is smaller than the area in a plan view where each of the one or more second vias contacts the second source electrode.

7. The number of the one or more first via connections is less than or equal to the number of the one or more second via connections, The semiconductor device according to claim 6, wherein, in the case where the one or more first vias are a plurality of first vias and the one or more second vias are a plurality of second vias, the spacing between adjacent first vias is less than or equal to the spacing between adjacent second vias.

8. The system includes one or more third via connections that overlap in a plan view with one of the third source electrodes, which is the third closest to the end of the plurality of source electrodes, penetrate the substrate, and electrically connect the metal layer and the third source electrode, The semiconductor device according to any one of claims 1 to 7, wherein the third inductance via the one or more third via connections between one of the third source electrodes and the metal layer is smaller than the second inductance.

9. If the one or more first via connections are a single first via connection, the first inductance is the self-inductance of the single first via connection. When the one or more first via connections are multiple first via connections, the first inductance is the sum of the combined inductance of the self-inductances of each of the multiple first via connections and the mutual inductance between the multiple first via connections. If the one or more second via connections are a single second via connection, the second inductance is the self-inductance of the single second via connection. The semiconductor device according to any one of claims 1 to 7, wherein, in the case where the one or more second vias are multiple second vias, the second inductance is the sum of the inductance obtained by combining the self-inductances of each of the multiple second vias and the mutual inductance between the multiple second vias.

10. A plurality of gate electrodes provided on the substrate, Multiple drain electrodes provided on the substrate, Equipped with, The semiconductor device according to any one of claims 1 to 7, wherein each of the plurality of gate electrodes is sandwiched between the plurality of source electrodes and the plurality of drain electrodes.

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