Computing apparatus and method thereof

Abstract

To provide a method and device for designing an appropriate computation scheme that performs transformation efficiently in a butterfly process.SOLUTION: A computing device 200 which performs a butterfly process upon a sequence of 2N pieces of input data includes a first buffer, a second buffer, a fetch unit, an arithmetic unit, and a control unit. The control unit causes the fetch unit to read 2h pieces of input data from a memory as a first group of input data to the first buffer, causes the arithmetic unit to perform h stages of the butterfly process upon the first group of input data to generate a first group of updated data, causes, when the first group of update data is generated, the fetch unit to read another 2h pieces of input data from the memory as a second group of input data to the second buffer, and causes the fetch unit to write the first group of updated data to the memory.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims the benefit of the prior U.S. Provisional Application No. 63 / 554,140, ​​filed on 15 February 2024, which is incorporated in its entirety by reference.

[0002] This disclosure relates to a computing device, and more specifically to a computing device that performs number theory transformations (NTT) or fast Fourier transforms (FFT). [Background technology]

[0003] The Discrete Fourier Transform (DFT) is widely used in signal processing and image processing because it can analyze the frequency components of a signal. The Fast Fourier Transform (FFT) is a widely used algorithm for calculating the Deep Fourier Transform (DFT) and is known for its efficiency and speed. The Fast Fourier Transform (FFT) reduces the computational complexity of the DFT to O(n 2 The time complexity is reduced from ) to O(n log n), where n is the number of input data points. This makes it particularly useful for real-time signal processing and other applications where speed is critical.

[0004] On the other hand, number theory transformations (NTTs) are variations of the FFT specifically designed for operations on finite fields. NTT is used in lattice cryptography, which is important for post-quantum cryptography and homomorphic cryptography schemes.

[0005] To facilitate FFT and NTT calculations, a butterfly processing scheme is proposed. Butterfly processing involves combining and reordering input data in a specific way to efficiently compute transformations. However, butterfly processing typically requires two input data points and two update data points per calculation, making memory bandwidth a significant challenge in hardware implementation. Therefore, how to design an appropriate computational scheme to execute the conversion more efficiently becomes an issue to be solved.

Summary of the Invention

[0006] One aspect of the present disclosure provides a computing device. The computing device is configured to perform butterfly processing on a sequence of 2 N (N is a positive integer) input data. The computing device includes a first buffer, a second buffer, a fetch unit, an arithmetic unit, and a control unit. The fetch unit is coupled to a memory, the first buffer, and the second buffer. The arithmetic unit is coupled to the first buffer and the second buffer and is configured to perform arithmetic operations required for the butterfly processing. The control unit causes the fetch unit to read 2 N of the 2 h (h is greater than or equal to 2 and less than N) input data as a first input data group stored in the first buffer from the memory. The control unit further causes the arithmetic unit to perform h-stage butterfly processing on the first input data group to generate a first updated data group stored in the first buffer. When generating the first updated data group, the control unit causes the fetch unit to read another 2 N of the 2 h input data as a second input data group from the memory, and when the first updated data group is generated, causes the fetch unit to read another 2 N of the 2 h input data as a second input data group stored in the second buffer from the memory. The control unit is further configured to cause the fetch unit to write the first update data group to the memory.

[0007] Another aspect of the present disclosure provides a method of operating a computing device to perform butterfly processing on a sequence of 2 N (where N is a positive integer) input data. The computing device includes a first buffer, a second buffer, a fetch unit, and an arithmetic unit. The method includes the steps of: reading, by the fetch unit, 2 N of the 2 h (where h is greater than or equal to 2 and less than N) input data from the memory as a first input data group to the first buffer; performing, by the arithmetic unit, h-stage butterfly processing on the first input data group to generate a first update data group to the first buffer; when the first update data group is generated, reading, by the fetch unit, another 2 N of the 2 h input data from the memory as a second input data group to the second buffer; and writing, by the fetch unit, the first update data group to the memory.

Brief Description of the Drawings

[0008] The present disclosure can be more fully understood by reference to the detailed description and the claims in connection with the drawings, in which like reference numerals refer to like elements throughout the drawings.

[0009] [Figure 1] Shows a scheme of butterfly processing of NTT according to the Cooley-Tukey algorithm. [Figure 2] Shows a computing system according to a comparative embodiment of the present disclosure. [Figure 3] Shows a computing system according to an embodiment of the present disclosure. [Figure 4]A flowchart shows a method for operating the computing device shown in Figure 3 to perform a butterfly process according to one embodiment of the present disclosure. [Figure 5] Figure 3 shows the data path control structure in the NTT butterfly processing computer according to one embodiment of this disclosure. [Figure 6] This shows the butterfly processing scheme for an INTT that follows the Gentleman-Sande algorithm. [Figure 7] Figure 3 shows the data path control structure in the computing device for butterfly processing of an INTT according to one embodiment of this disclosure. [Modes for carrying out the invention]

[0010] To facilitate the computation of complex Fourier transforms, Cooley and Tukey proposed a well-known algorithm for re-representing larger discrete Fourier transforms (DFTs) into several smaller DFTs. For example, a composite DFT of size N can be re-represented by N1 DFTs of size N2 (where N, N1, and N2 are positive integers, and N = N1·N2), and such re-representation can be performed recursively, thus reducing the complexity of the DFT.

[0011] Butterfly processing schemes have been developed to perform Fast Fourier Transforms (FFTs) or Number Theory Transforms (NTTs) in hardware, based on Cooley-Tukey's algorithm. Figure 1 shows the scheme of NTT's butterfly processing, which follows Cooley-Tukey's algorithm. In Figure 1, the butterfly process is 2 N It is used to transform an input polynomial of order -1 (in this embodiment, N is equal to 4), and the 16 coefficients of the input polynomial are X[0] to X

[15] of the input data for the butterfly process. In such cases, the butterfly process shown in Figure 1 can derive the transformed data X'[0]~X'

[15] as coefficients of the transformed polynomial, according to the input data X[0]~X

[15] and predetermined rotation factors φ[1]~φ

[15] .

[0012] The butterfly processing scheme shown in Figure 1 includes N stages (i.e., four stages: ST1, ST2, ST3, and ST4). In the first stage ST1, input data X[0] and input data X[8] are searched, and a remainder multiplication is performed on input data X[8] and a predetermined rotation factor φ[1] by a predetermined coefficient q. In such cases, the intermediate data X1[0] of the first stage ST1 can be derived by adding the input data X[0] and the result of the modulo multiplication, and the intermediate data X1[8] of the first stage ST1 can be derived by subtracting the result of the modulo multiplication from the input data X[0]. In other words, the intermediate data X1[0] and X1[8] can be expressed as equations (1) and (2) shown below.

[0013] X1[0]=X[0]+X[8]·φ[1]mod q (1) X1[8]=X[0]-X[8]·φ[1]mod q (2)

[0014] Similarly, other intermediate data for the first stage ST1 can be derived using the same calculation operation. For example, a remainder multiplication can be performed on the input data X[9] and a predetermined rotation factor φ[1] by a predetermined coefficient q, and the intermediate data X1[1] of the first stage ST1 can be derived by adding the results of the remainder multiplication performed on the input data X[1] and the input data X[9]. Furthermore, the intermediate data X1[9] of the first stage ST1 can be derived by subtracting the result of the modulo multiplication performed on the input data X[9] from the input data X[1].

[0015] The arithmetic operations used to derive the intermediate data in the first stage ST1 are further applied to other stages to derive intermediate or final transformed data. For example, in the second stage ST2, intermediate data X1[0] and intermediate data X1[4] can be searched, and a remainder multiplication can be performed on the intermediate data X1[4] and a predetermined rotation factor φ[2] by a predetermined coefficient q. In such cases, the intermediate data X2[0] of the second stage ST2 can be derived by adding the results of the modulo multiplication performed on the intermediate data X1[0] and the intermediate data X1[4], and the intermediate data X2[4] of the second stage ST2 can be derived by subtracting the result of the modulo multiplication performed on the intermediate data X1[4] from the intermediate data X1[0].

[0016] Figure 2 shows a calculation system 10 according to one comparative embodiment of the present disclosure. The calculation system 10 can perform the butterfly process shown in Figure 1. The computing system 10 includes a computing device 100 and a memory 12. In this embodiment, the computing device 100 can complete one stage of calculation for two input data per cycle. For example, the computing device 100 can derive intermediate data X1[0] and X1[8] based on input data X[0] and X[8] in one cycle, and derive intermediate data X1[1] and X1[9] based on input data X[1] and X[9] in another cycle.

[0017] In such a case, in order to maximize the utilization of the computing device 100, the computing device 100 needs to read two data from memory 12 and write two data back to memory 12 in each cycle, meaning that memory 12 needs to support two read operations and two write operations per cycle (assuming that each word in memory 12 has the capacity to store only one input data). However, most memory only supports two accesses in a single cycle (e.g., two read operations and two write operations, or one read operation and one write operation), and additional design work and circuit space are required to make the memory support four accesses in a single cycle (e.g., 4-port memory). As a result, using 4-port memory significantly increases costs and causes considerable power consumption due to high-frequency access operations.

[0018] Figure 3 shows a computing system 20 according to one embodiment of the present disclosure. The computing system 20 includes a memory 22 and a computing device 200. Compared to computing device 100, computing device 200 can reduce the required memory bandwidth while maintaining efficient use of the arithmetic units within computing device 200, thereby simplifying hardware requirements and reducing power consumption.

[0019] The computing device 200 includes a first buffer 210, a second buffer 220, a fetch unit 230, an arithmetic unit 240, and a control unit 250. The fetch unit 230 may be coupled to the memory 22, the first buffer 210, and the second buffer 220. The fetch unit 230 can read data from memory 22 and write data to memory 22. The first buffer 210 and the second buffer 220 can behave as ping-pong buffers, sequentially receiving data read from memory 22 by the fetch unit 230 and sending data to the fetch unit 230 to sequentially write the data to memory 22. The arithmetic unit 240 is coupled to the first buffer 210 and the second buffer 220, and can perform the calculation operations necessary for butterfly processing based on the data stored in the first buffer 210 and the second buffer 220, and can return the calculation results by storing them in the first buffer 210 and the second buffer 220. The control unit 250 can control the data flow between the fetch unit 230, the first buffer 210, the second buffer 220, and the arithmetic unit 240 to perform butterfly processing. Each part of the computing device 200 can be implemented using digital electronic circuits, firmware, software, and / or a combination thereof. Furthermore, memory 22 may be static random-access memory (SRAM), but this disclosure is not limited thereto.

[0020] In this embodiment, the computing device 200 performs FFT or NTT's 2 N Butterfly processing can be performed on a sequence of input data (where N is a positive integer). In such a case, the first buffer 210 and the second buffer 220 each have 2 N 2 of the input data h It can have a capacity to store (h is 2 or more and less than N) input data items. Therefore, the computing device 200 fetches from memory 22 to the fetch unit 230. h The system can sequentially read individual input data and store them in the first buffer 210 or the like. Then, the arithmetic unit 240 reads the corresponding input data according to the calculation order determined by the butterfly process, and stores the 2 in the first buffer 210. h Based on the input data, it is possible to perform calculations for h stages of butterfly processing.

[0021] Furthermore, while the arithmetic unit 240 performs calculations on the input data stored in the first buffer 210, the computing device 200 fetches another 2 from memory 22 to the fetch unit 230. h The system can read individual input data and store it in the second buffer 220. In other words, by alternately using the first buffer 210 and the second buffer 220 to buffer input data for calculations of multiple stages of butterfly processing, the computing device 200 can achieve appropriate data scheduling that reduces the bandwidth required for memory 22 while maintaining a high hardware utilization rate of the arithmetic unit 240.

[0022] In some embodiments, the arithmetic unit 240 can complete a one-stage butterfly processing calculation for two input data within one cycle. Therefore, the arithmetic unit 240 is 2 h To perform h-stage butterfly processing on individual data points, h·2 h-1 It requires a cycle. In such cases, the fetch unit 230 keeps the arithmetic unit 240 busy, h·2 h-1 Within the cycle, 2 h Read the data, 2 h Write individual data (i.e., to read, h·2) h-2 It requires a cycle to write, h·2 h-2 It requires a cycle. In other words, the fetch unit 230 is 2 N at least

number

number

[0023] Figure 4 shows a flowchart of method M1 for operating the computing device 200 to perform butterfly processing according to one embodiment of the present disclosure. Method M1 includes steps S110 to S117.

[0024] In this embodiment, the calculation system 20 can perform the butterfly process shown in Figure 1 (where N is equal to 4 and h is equal to 2) according to method M1. In such cases, the first buffer 210 and the second buffer 220 are each 2 2 (That is, it can have a capacity to store 4) input data, in which case the total 2 4 (That is, butterfly processing is performed on 16) input data points. For example, the first buffer 210 may include four registers R[0], R[1], R[2], and R[3], each for storing input data, as shown in Figure 3. Similarly, the second buffer 220 may include four registers R'[0], R'[1], R'[2], and R'[3], each for storing input data.

[0025] Table 1 shows a portion of the data scheduling for the NTT computer 200 that performs the butterfly processing shown in Figure 1.

[0026] [Table 1(1)] [Table 1(2)]

[0027] Referring to Figures 1, 4 and Table 1, in step S110, the control unit 250 fetches four input data from memory to the fetch unit 230 as the first input data group, and then fetches two of them (i.e., h·2). h-2 ) It can be read within a continuous cycle. The control unit 250 can write the first input data group to the first buffer 210. In this embodiment, where h is equal to 2, the first input data group is 2 N The first input data out of the number of input data, 2N (2) N-1 (1)th input data, 2 N (2) N-2 +1)th input data, and 2 N (2) N-1 +2 N-2 The (+1)th input data may be included. For example, in Table 1, the fetch unit 230 retrieves X[0] of the input data (i.e., the first input data out of the 16 input data X[0] to X

[15] ) and X[8] of the input data (i.e., the second input data out of the 16 input data X[0] to X

[15] ). N-1 The (1)th input data can be read from memory 22 within the first cycle #1, and furthermore, the input data X[4] (i.e., (2) of the 16 input data X[0] to X

[15] N-2 (1)th input data) and X

[12] of the input data (i.e., (2) of the 16 input data X[0] to X

[15] N-1 +2 N-2 The (+1)th input data can be read from memory 22 within the second cycle #2. In this embodiment, the memory 22 can deliver read data in the next cycle after a read request is received in the first cycle #1, thereby enabling the fetch unit 230 to store the input data X[0] and X[8] in registers R[0] and R[2], respectively, in the second cycle #2, and further, to store the input data X[4] and X

[12] in registers R[1] and R[3], respectively, in the third cycle #3.

[0028] In step S111, once at least a portion of the first input data group is stored in the first buffer 210, the control unit 250 can cause the arithmetic unit 240 to perform a two-stage (i.e., h-stage) butterfly process on the first input data group stored in the first buffer 210 to generate the first updated data group (i.e., the intermediate data X2[0], X2[8], X2[4], and X2

[12] ). The control unit 250 can write the first update data set to the first buffer 210. In some embodiments, the arithmetic unit 240 can complete the calculations required for one stage of butterfly processing on two input data within one cycle. For example, as shown in Table 1, the arithmetic unit 240 may derive intermediate data X1[0] and X1[8] in the third cycle #3 based on the input data X[0] and X[8] stored in registers R[0] and R[2], and derive intermediate data X1[4] and X1

[12] in the fourth cycle #4 based on the input data X[4] and X

[12] stored in registers R[1] and R[3].

[0029] In response to this, the intermediate data X1[0], X1[8], X1[4], and X1

[12] of the butterfly processing of the first stage ST1 are stored in the first buffer 210 in an in-place manner. In other words, the intermediate data X1[0] can be stored in register R[0], which originally stores the corresponding input data X[0], and the intermediate data X1[4] can be stored in register R[1], which originally stores the corresponding input data X[4].

[0030] Next, the arithmetic unit 240 may derive intermediate data X2[0] and X2[4] in the fifth cycle #5 based on intermediate data X1[0] and X1[4] stored in registers R[0] and R[1], and may derive intermediate data X2[8] and X2

[12] in the sixth cycle #6 based on intermediate data X1[8] and X1

[12] stored in registers R[2] and R[3]. The control unit 250 can then store the first update data group (i.e., X2[0], X2[4], X2[8], and X2

[12] , which are intermediate data from the butterfly processing of the second stage ST2) in the first buffer 210. In this embodiment, the intermediate data X2[0] and X2[4] are stored in registers R[0] and R[1] of the first buffer 210 within the fifth cycle #5, and the intermediate data X2[8] and X2

[12] are stored in registers R[2] and R[3] of the first buffer 210 within the sixth cycle #6.

[0031] In step S112, if the arithmetic unit 240 generates the first update data group, the control unit 250 can cause the fetch unit 230 to read the input data X[1], X[9], X[5], and X

[13] as the second input data group from the memory 22 during the fifth cycle #5 and the sixth cycle #6. Furthermore, the control unit 250 can store the second input data group in the second buffer 220. In this embodiment, the input data X[1] and X[9] retrieved in the fifth cycle #5 are stored in the registers R'[0] and R'[2] of the second buffer 220, respectively, in the sixth cycle #6, and the input data X[5] and X

[13] retrieved in the sixth cycle #6 are stored in the registers R'[1] and R'[3] of the second buffer 220, respectively, in the seventh cycle #7.

[0032] In other words, when the arithmetic unit 240 performs the butterfly processing calculations of the second stage ST2 on the intermediate data X1[0], X1[4], X1[8], and X1

[12] , the fetch unit 230 can read the input data from memory 22 for subsequent calculations. Next, the first buffer 210 needs to store the intermediate data X2[0], X2[4], X2[8], and X2

[12] of the butterfly processing of the second stage ST2, which are derived by the arithmetic unit 240. Therefore, the input data X[1], X[9], X[5], and X

[13] fetched by the fetch unit 230 are stored in the second buffer 220, thereby avoiding data contention in the first buffer 210.

[0033] In step S113, once at least a portion of the second input data group is stored in the second buffer 220, the control unit 250 can cause the arithmetic unit 240 to perform a two-stage butterfly process on the second input data group (i.e., the input data X[1], X[9], X[5], X

[13] ) to generate the second update data group. The control unit 250 can store the second update data set in the second buffer 220. Specifically, as shown in Table 1, the arithmetic unit 240 may derive the intermediate data X1[1] and X1[9] of the butterfly processing of the first stage ST1 in the seventh cycle #7 based on the input data X[1] and X[9] stored in registers R'[0] and R'[2], and derive the intermediate data X1[5] and X1

[13] of the butterfly processing of the first stage ST1 in the eighth cycle #8 based on the input data X[5] and X

[13] stored in registers R'[1] and R'[3]. In this embodiment, the intermediate data X1[1], X1[5], X1[9], and X1

[13] are stored in registers R'[0], R'[1], R'[2], and R'[3] respectively in an in-place manner.

[0034] Next, the arithmetic unit 240 may derive the intermediate data X2[1] and X2[5] of the butterfly processing of the second stage ST2 based on the intermediate data X1[1] and X1[5] stored in registers R'[0] and R'[1] within the 9th cycle #9, and may derive the intermediate data X2[9] and X2

[13] of the butterfly processing of the second stage ST2 based on the intermediate data X1[9] and X1

[13] stored in registers R'[2] and R'[3] within the 10th cycle #10. The control unit 250 can then store the second update data group (i.e., the intermediate data X2[1], X2[5], X2[9], and X2

[13] of the butterfly processing of the second stage ST2) in the second buffer 220. In this embodiment, the intermediate data X2[1] and X2[5] are stored in registers R'[0] and R'[1] of the second buffer 220 within the 9th cycle #9, and the intermediate data X2[9] and X2

[13] are stored in registers R'[2] and R'[3] of the second buffer 220 within the 10th cycle #10.

[0035] In step S114, when step S113 is executed and the arithmetic unit 240 generates the second update data group (i.e., X2[1], X2[5], X2[9] and X2

[13] , which are intermediate data for the butterfly processing of the second stage ST2), the control unit 250 sends the first update data group to the memory 22 in two (i.e., h·2) in the fetch unit 230. h-2 ) It is possible to write within a continuous cycle. For example, the fetch unit 230 may write intermediate data X2[0] and X2[8] to replace the input data X[0] and X[8] in memory 22 within the 7th cycle #7, and write intermediate data X2[4] and X2

[12] to replace the input data X[4] and X

[12] in memory 22 within the 8th cycle #8.

[0036] Furthermore, in step S115, if step S113 is executed within the 9th cycle #9 and the 10th cycle #10, and the arithmetic unit 240 generates the second update data group (i.e., the intermediate data X2[1], X2[5], X2[9], and X2

[13] of the butterfly processing of the second stage ST2), the control unit 250 can cause the fetch unit 230 to read the input data X[2], X

[10] , X[6], and X

[14] from memory 22 as the third input data group. The control unit 250 can store the third input data group in the first buffer 210 for subsequent calculations.

[0037] In step S116, once at least a portion of the third input data group is stored in the first buffer 210, the control unit 250 can cause the arithmetic unit 240 to perform a two-stage butterfly process on the third input data group (i.e., the input data X[2], X

[10] , X[6], X

[14] ) to generate the third update data group. Furthermore, in step S117, if step S116 is executed and the arithmetic unit 240 generates the third update data group, the control unit 250 instructs the fetch unit 230 to store the second update data group in memory 22 as two (i.e., h·2) h-2 ) It is possible to write within a continuous cycle. For example, the fetch unit 230 may write intermediate data X2[1] and X2[9] to replace the input data X[1] and X[9] in memory 22 within the 11th cycle #11, and write intermediate data X2[5] and X2

[13] to replace the input data X[5] and X

[13] in memory 22 within the 12th cycle #12.

[0038] By repeating steps S110 to S117, the computing device 200 can update the input data X[0] to X

[15] with the intermediate data X2[0] to X2

[15] of the second stage ST2 butterfly process, and further update the intermediate data X2[0] to X2

[15] of the second stage ST2 butterfly process with the converted data X'[0] to X'

[15] , thereby completing the butterfly process.

[0039] In the calculation system 20 and method M1, a first buffer 210 and a second buffer 220 are used to process multiple input data (for example, 2 h Because the input data (1) is stored alternately, the data scheduling for butterfly processing can be optimized so that the fetch unit 230 and the arithmetic unit 240 can be properly pipelined, thereby reducing the memory bandwidth required for memory 22 while maintaining the hardware utilization rate of the computing device 200.

[0040] Furthermore, since the data flow of the butterfly process is predetermined and the arithmetic operations of the butterfly process at all stages are basically the same, a general data access scheme can be derived for the registers R[0]~R[3] of the first buffer 210 and the registers R'[0]~R'[3] of the second buffer 220. Figure 5 shows the structure of data path control in NTT's computing device 200 for butterfly processing according to one embodiment of the present disclosure. In other words, the structure shown in Figure 5 can operate according to method M1 in Figure 4 to realize the NTT butterfly processing scheme shown in Figure 1. As shown in Figure 5, the computing device 200 further includes a plurality of multiplexers (MUX) M1 to M14. MUX M1~M14 can be controlled by control unit 250 (control unit 250, control lines coupled between MUX M1~M14, and control unit 250 not shown in Figure 5 for brevity).

[0041] In this embodiment, the arithmetic unit 240 includes an adder 242, a subtractor 244, and a remainder multiplier 246. The adder 242 has a first input terminal connected to the first input terminal IN1 of the arithmetic unit 240, a second input terminal, and an output terminal connected to the first output terminal OUT1 of the arithmetic unit 240. The subtractor 244 has a first input terminal connected to the first input terminal IN1 of the arithmetic unit 240, a second input terminal, and an output terminal connected to the second output terminal OUT2 of the arithmetic unit 240. The remainder multiplier 246 has a first input terminal connected to the second input terminal IN2 of the arithmetic unit 240, a second input terminal configured to receive the corresponding rotation factor (i.e., one of the rotation factors φ[1] to φ

[15] ), and output terminals connected to the second input terminal of the adder 242 and the second input terminal of the subtractor 244. In some embodiments, the adder 242 and the subtractor 244 may each be implemented by adders that support signed addition, but the disclosure is not limited thereto.

[0042] MUX M1 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the first output terminal OUT1 of the arithmetic unit 240, and an output terminal connected to register R[0]. MUX M2 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the first output terminal OUT1 of the arithmetic unit 240, a third input terminal connected to the second output terminal OUT2 of the arithmetic unit 240, and an output terminal connected to register R[1]. The MUX M3 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the first output terminal OUT1 of the arithmetic unit 240, a third input terminal connected to the second output terminal OUT2 of the arithmetic unit 240, and an output terminal connected to register R[2]. The MUX M4 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the second output terminal OUT2 of the arithmetic unit 240, and an output terminal connected to register R[3].

[0043] The MUX M5 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the first output terminal OUT1 of the arithmetic unit 240, and an output terminal connected to register R'[0]. The MUX M6 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the first output terminal OUT1 of the arithmetic unit 240, a third input terminal connected to the second output terminal OUT2 of the arithmetic unit 240, and an output terminal connected to register R'[1]. The MUX M7 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the first output terminal OUT1 of the arithmetic unit 240, a third input terminal connected to the second output terminal OUT2 of the arithmetic unit 240, and an output terminal connected to register R'[2]. The MUX M8 has a first input terminal connected to the fetch unit 230, a second input terminal connected to the second output terminal OUT2 of the arithmetic unit 240, and an output terminal connected to register R'[3].

[0044] The MUX M9 has a first input terminal connected to register R[1], a second input terminal connected to register R[2], a third input terminal connected to register R[3], and an output terminal. The MUX M10 has a first input terminal connected to register R'[1], a second input terminal connected to register R'[2], a third input terminal connected to register R'[3], and an output terminal. MUX M11 has a first input terminal connected to the output terminal of MUX M9, a second input terminal connected to the output terminal of MUX M10, and an output terminal connected to the second input terminal IN2 of the arithmetic unit 240.

[0045] The MUX M12 has a first input terminal connected to register R[0], a second input terminal connected to register R[1], a third input terminal connected to register R[2], and an output terminal. The MUX M13 has a first input terminal connected to register R'[0], a second input terminal connected to register R'[1], a third input terminal connected to register R'[2], and an output terminal. MUX M14 has a first input terminal connected to the output terminal of MUX M12, a second input terminal connected to the output terminal of MUX M13, and an output terminal connected to the first input terminal IN1 of the arithmetic unit 240.

[0046] As a result, by controlling the multiplexers M1 to M14, the control unit 250 can control the data flow of the computing device 200, thereby allowing the arithmetic unit 240 to receive the corresponding data, perform calculations, and store the calculation results in the corresponding registers, thereby completing the calculations for each stage of the butterfly process.

[0047] In some embodiments, the computing device 200 may further include data path control units 232 and 234 for controlling the data flow between the fetch unit 230 and registers R[0] to R[3], and between the fetch unit 230 and registers R'[0] to R'[3]. In some embodiments, each of the data path control units 232 and 234 may include a multiplexer, a demultiplexer, or a combination thereof, meaning that the data path control units 232 and 234 can be implemented using digital electronic circuits.

[0048] In this embodiment, the computing system 20 is used to execute NTT, but the disclosure is not limited thereto. In some embodiments, the calculation system 20 may be used to perform the FFT simply by changing the input data and rotation factors.

[0049] Furthermore, in some embodiments, the calculation system 20 may be used to perform inverse NTT (INTT) and inverse FFT (IFFT). Figure 6 shows the butterfly processing scheme for INTT following the Gentleman-Sande algorithm. In Figure 6, the butterfly process of INTT is 2 N (In this embodiment, N is equal to 4) The Y[0] to Y

[15] of the input data are divided into 2 N Convert the individual data points into Y'[0]~Y'

[15] . The INTT butterfly process shown in Figure 6 is the reverse version of the NTT butterfly process shown in Figure 1, with the rotation factors φ'[1] to φ'

[15] reversed.

[0050] For example, the intermediate data Y1[0] of the first stage ST1 of the butterfly process in Figure 6 can be derived by adding the input data Y[0] and the input data Y[1], and the intermediate data Y1[1] of the first stage ST1 of the butterfly process in Figure 6 can be derived by subtracting the input data Y[1] from the input data Y[0] and performing a remainder multiplication by a predetermined coefficient q on the result of the subtraction and the corresponding rotation factor φ'[1]. In other words, the intermediate data Y1[0] and Y1[1] can be expressed as equations (3) and (4) shown below.

[0051] Y1[0]=Y[0]+Y1 (3) Y1[1]=(Y[0]-Y[1])·φ'[1]mod q (4)

[0052] In this embodiment, the computing device 200' shown in Figure 7 differs from the computing device 200 in that it replaces the arithmetic unit 240 with an arithmetic unit 240' for calculating equations (3) and (4), and may be used to perform the butterfly processing of INTT shown in Figure 6. For example, the computing device 200' fetches data from memory 22 to the fetch unit 230. h The system can sequentially read individual input data and store them in the first buffer 210 or the like. Then, the arithmetic unit 240' reads the corresponding input data according to the calculation order determined by the butterfly processing of INTT, and stores the 2 in the first buffer 210. h Based on the input data, it is possible to perform calculations for the h-stage butterfly process of INTT.

[0053] Furthermore, the computing device 200' fetches another 2 from memory 22 to the fetch unit 230 while the arithmetic unit 240' performs calculations on the input data stored in the first buffer 210. h The system can read individual input data and store it in the second buffer 220. In other words, when performing the butterfly processing of INTT, the computing device 200' can alternately buffer the input data using the first buffer 210 and the second buffer 220 so that the fetch unit 230 and the arithmetic unit 240' can be properly pipelined, thereby maintaining a high hardware utilization rate of the arithmetic unit 240' while reducing the memory bandwidth required for memory 22. In this embodiment, the calculation system 20 may be used to perform an INTT, but the disclosure is not limited thereto. In some embodiments, the calculation system 20 may be used to perform IFFT simply by changing the input data and rotation factors.

[0054] Table 2 shows a portion of the data scheduling for the computing device 200' that performs the butterfly processing of the INTT shown in Figure 6.

[0055] [Table 2(1)] [Table 2(2)]

[0056] Referring to Figure 6 and Table 2, the control unit 250 fetches four input data from memory 22 to the fetch unit 230, and then fetches two of these data (i.e., h·2). h-2 ) It can be read within a continuous cycle. In this embodiment, where h is equal to 2, for example, the input data read in the first cycle #1 and the second cycle #2 is 2 N The first input data out of the number of input data (for example, data Y[0]), 2 N The second input data out of the individual input data (for example, data Y[1]), 2 N The third input data out of the individual input data (for example, data Y[2]), and 2 N It may include the fourth input data (for example, data Y[3]) among the individual input data.

[0057] Since the data flow of the INTT butterfly process is predetermined and the arithmetic operations of the butterfly process at all stages are basically the same, a general data access scheme can be derived for the registers R[0]~R[3] of the first buffer 210 and the registers R'[0]~R'[3] of the second buffer 220. Figure 7 shows the structure of data path control in a computing device 200' for butterfly processing of an INTT according to one embodiment of the present disclosure. In other words, the structure shown in Figure 7 can operate according to method M1 in Figure 4 to realize the INTT butterfly processing scheme shown in Figure 6.

[0058] As shown in Figure 7, the mux M1~M14 used in the data path control structure for NTT's butterfly processing in Figure 5 may also be used in INTT's butterfly processing in Figure 7. Comparing the structure shown in Figure 5 with the structure shown in Figure 7, the difference lies in the fact that the arithmetic unit 240' is reconfigured according to the arithmetic operations required for the butterfly processing of INTT. Specifically, the first input terminal IN1 of the arithmetic unit 240' is connected to the first input terminal of the adder 242 and the first input terminal of the subtractor 244; the second input terminal IN2 of the arithmetic unit 240' is connected to the second input terminal of the adder 242 and the second input terminal of the subtractor 244; the first output terminal OUT1 of the arithmetic unit 240' is connected to the output terminal of the adder 242; and the second output terminal OUT2 of the arithmetic unit 240' is connected to the output terminal of the modulo multiplier 246. Furthermore, the output terminal of the subtractor 244 is connected to the first input terminal of the remainder multiplier 246. The second input terminal of the remainder multiplier 246 is configured to receive the corresponding rotation factor (i.e., one of the rotation factors Φ'[1] to Φ'

[15] ). In some embodiments, the arithmetic unit 240' may include a multiplexer (not shown in Figures 5 and 7) for reconfiguring the data flow, thereby allowing the arithmetic unit 240' to have the configuration shown in Figure 5 when performing NTT or FFT, and to have the configuration shown in Figure 7 when performing INTT or IFFT.

[0059] By appropriately controlling the multiplexers M1 to M14 with the control unit 250, the computing device 200' can perform the butterfly processing of INTT and alternately store multiple input data using the first buffer 210 and the second buffer 220, thereby optimizing the data scheduling of the butterfly processing and enabling the fetch unit 230 and the arithmetic unit 240' to be properly pipelined. As a result, the memory bandwidth required for memory 22 can be reduced, and the hardware utilization rate of computing device 200' can be maintained.

[0060] In summary, the computing device, computing system, and method for operating the computing device provided in embodiments of this disclosure use two buffers to process multiple input data (e.g., 2 h By storing the input data (individual data points) alternately, the data scheduling for butterfly processing can be optimized, and the operation of the fetch unit and arithmetic unit can be properly pipelined. As a result, the memory bandwidth required for memory can be reduced, and the hardware utilization rate of the computing device can be maintained.

Claims

1. 2 Ｎ A computing device configured to perform butterfly processing on a sequence of input data (where N is a positive integer), First buffer and, The second buffer, A memory, a fetch unit coupled to the first buffer and the second buffer, A calculation unit coupled to the first buffer and the second buffer and configured to perform calculation operations necessary for the butterfly process, A control unit, including, the control unit The fetch unit, Ｎ Two of the input data ｈ (where h is 2 or more and less than N) input data are read from the memory as a first input data group to be stored in the first buffer. The calculation unit is instructed to perform the h-stage butterfly processing on the first input data group to generate the first update data group to be stored in the first buffer. When the first update data set is generated, the fetch unit receives the second set of data. Ｎ Two other input data items ｈ The individual input data are read from the memory as a second group of input data stored in the second buffer. A computing device configured to cause the fetch unit to write the first update data set to the memory.

2. The control unit further, The computing device according to claim 1, wherein when at least a portion of the second input data group is stored in the second buffer, the computing unit is configured to perform the h-stage butterfly processing on the second input data group to generate a second update data group to be stored in the second buffer.

3. The computing device according to claim 2, wherein when the second update data set is generated, the control unit is configured to cause the fetch unit to write the second update data set to the memory.

4. The control unit further, When the second set of updated data is generated, the fetch unit receives the second set of data. Ｎ Two of the input data ｈ The computing device according to claim 2, configured to read individual input data from the memory as a group of third input data stored in the first buffer.

5. The computing apparatus according to claim 1, wherein when at least a portion of the first input data group is stored in the first buffer, the control unit causes the arithmetic unit to perform the h-stage butterfly processing on the first input data group.

6. The computing apparatus according to claim 1, wherein the intermediate data generated in the first stage of the h-stage butterfly processing for the first input data group is stored in the first buffer in an in-place manner.

7. The computing device according to claim 1, wherein the computing unit is configured to complete the calculations required for one stage of the butterfly processing for two input data within one cycle.

8. The aforementioned butterfly processing is for Fast Fourier Transform (FFT) or Number Theory Transform (NTT), and the calculation unit is, An adder having a first input terminal connected to the first input terminal of the calculation unit, a second input terminal, and an output terminal connected to the first output terminal of the calculation unit, A subtractor having a first input terminal connected to the first input terminal of the calculation unit, a second input terminal, and an output terminal connected to the second output terminal of the calculation unit, The calculation device according to claim 1, comprising a remainder multiplier having a first input terminal coupled to the second input terminal of the calculation unit, a second input terminal configured to receive a corresponding rotation factor, and an output terminal coupled to the second input terminal of the adder and the second input terminal of the subtractor.

9. A first multiplexer (MUX) having a first input terminal connected to the fetch unit, a second input terminal connected to the first output terminal of the arithmetic unit, and an output terminal connected to the first register of the first buffer, A second MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the first output terminal of the arithmetic unit, a third input terminal connected to the second output terminal of the arithmetic unit, and an output terminal connected to the second register of the first buffer, A third MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the first output terminal of the arithmetic unit, a third input terminal connected to the second output terminal of the arithmetic unit, and an output terminal connected to the third register of the first buffer, A fourth MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the second output terminal of the arithmetic unit, and an output terminal connected to the fourth register of the first buffer, A fifth MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the first output terminal of the arithmetic unit, and an output terminal connected to the first register of the second buffer, A sixth MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the first output terminal of the arithmetic unit, a third input terminal connected to the second output terminal of the arithmetic unit, and an output terminal connected to the second register of the second buffer, A seventh MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the first output terminal of the arithmetic unit, a third input terminal connected to the second output terminal of the arithmetic unit, and an output terminal connected to the third register of the second buffer, The computing apparatus according to claim 7, further comprising an eighth MUX having a first input terminal connected to the fetch unit, a second input terminal connected to the second output terminal of the arithmetic unit, and an output terminal connected to the fourth register of the second buffer.

10. A ninth MUX having a first input terminal connected to the second register of the first buffer, a second input terminal connected to the third register of the first buffer, a third input terminal connected to the fourth register of the first buffer, and an output terminal, A 10th MUX having a first input terminal connected to the second register of the second buffer, a second input terminal connected to the third register of the second buffer, a third input terminal connected to the fourth register of the second buffer, and an output terminal, The computing apparatus according to claim 8, further comprising an eleventh MUX having a first input terminal connected to the output terminal of the ninth MUX, a second input terminal connected to the output terminal of the tenth MUX, and an output terminal connected to the second input terminal of the arithmetic unit.

11. A 12th MUX having a first input terminal connected to the first register of the first buffer, a second input terminal connected to the second register of the first buffer, a third input terminal connected to the third register of the first buffer, and an output terminal, A 13th MUX having a first input terminal connected to the first register of the second buffer, a second input terminal connected to the second register of the second buffer, a third input terminal connected to the third register of the second buffer, and an output terminal, The computing apparatus according to claim 8, further comprising a 14th MUX having a first input terminal connected to the output terminal of the 12th MUX, a second input terminal connected to the output terminal of the 13th MUX, and an output terminal connected to the first input terminal of the arithmetic unit.

12. 2 Ｎ A method for operating a computing device including a first buffer, a second buffer, a fetch unit and an arithmetic unit, to perform butterfly processing on a sequence of input data (where N is a positive integer), The fetch unit reads, as a first input data group to the first buffer, 2 Ｎ of the two ｈ (h is 2 or more and less than N) input data from the memory, in a step of reading the input data as a first input data group to the first buffer. The calculation unit performs the h-stage butterfly processing on the first input data group to generate the first update data group for the first buffer, When the first update data set is generated, the fetch unit will then process the second set. Ｎ Two other input data items ｈ The steps include reading the individual input data from the memory as a second set of input data to the second buffer, A method comprising the step of writing the first update data set to the memory using the fetch unit.

13. The method according to claim 12, further comprising the step of, when at least a portion of the second input data group is stored in the second buffer, the arithmetic unit performs h stages of the butterfly processing on the second input data group to generate a second update data group for the second buffer.

14. The method according to claim 13, wherein the step of writing the first update data group to the memory using the fetch unit is performed when the second update data group is generated.

15. When the second set of updated data is generated, the fetch unit will perform the second Ｎ Two of the input data ｈ The method according to claim 13, further comprising the step of reading the individual input data from the memory as a third input data group to the first buffer.

16. The method according to claim 12, wherein the arithmetic unit performs the h-stage butterfly processing on the first input data group to generate the first update data group for the first buffer, the step of which is performed when at least a portion of the first input data group is stored in the first buffer.

17. The method according to claim 12, further comprising the step of storing in place the intermediate data generated in the first stage of the h-stage butterfly processing for the first input data group using the first buffer.

18. h is equal to 2, the butterfly process is for NTT or FFT, and the first input data group is the 2 Ｎ The first input data among the individual input data, the second Ｎ (2) Ｎ－２ +1) The second input data, the 2 Ｎ (2) Ｎ－１ +1) The input data, and the 2 Ｎ (2) Ｎ－１ +2 Ｎ－２ The method according to claim 12, comprising the (+1)th input data.

19. h is equal to 2, the butterfly operation is for INTT or IFFT, and the first input data group is the 2 Ｎ The first input data among the input data, and the second Ｎ The second input data out of the individual input data, and the two Ｎ The third input data out of the individual input data, and the 2 Ｎ The method according to claim 12, comprising the fourth input data among the individual input data.

20. The calculation unit performs h stages of the butterfly processing on the first input data group to generate the first update data group for the first buffer. The method according to claim 12, further comprising the step of having the calculation unit complete the calculations required for one stage of the butterfly processing for two input data within one cycle.

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