Semiconductor devices and semiconductor memory devices

Abstract

To provide a semiconductor device whose characteristics can be improved.SOLUTION: A semiconductor device according to an embodiment includes a semiconductor layer containing silicon (Si), a first insulating layer provided in a first direction of the semiconductor layer, a second insulating layer surrounded by the semiconductor layer in a first cross section perpendicular to the first direction and containing silicon (Si) and oxygen (O), a third insulating layer surrounded by the second insulating layer in the first cross section and containing a metal element and oxygen (O), and a conductive layer surrounded by the first insulating layer in a second cross section perpendicular to the first direction, provided in the first direction of the third insulating layer, and spaced apart from the semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor memory device.

Background Art

[0002] A three-dimensional NAND flash memory in which memory cells are three-dimensionally arranged realizes high integration and low cost. In a three-dimensional NAND flash memory, for example, memory holes penetrating a stacked body are formed in a stacked body in which a plurality of insulating layers and a plurality of gate electrode layers are alternately stacked. By forming a charge storage layer and a semiconductor layer in the memory holes, a memory string in which a plurality of memory cells are connected in series is formed. Data is stored in the memory cell by controlling the amount of charge held in the charge storage layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device capable of improving characteristics.

Means for Solving the Problems

[0005] The semiconductor device according to the embodiment includes a semiconductor layer containing silicon (Si), a first insulating layer provided in a first direction of the semiconductor layer, and a second insulating layer that is surrounded by the semiconductor layer in a first cross section perpendicular to the first direction and contains silicon (Si) and oxygen (O), and a third insulating layer that is surrounded by the second insulating layer in the first cross section and contains a metal element and oxygen (O). A fourth insulating layer is provided between the second insulating layer and the third insulating layer, and comprises silicon (Si), oxygen (O), and nitrogen (N).The device comprises a conductive layer surrounded by the first insulating layer in a second cross-section perpendicular to the first direction, provided in the first direction of the third insulating layer, and spaced apart from the semiconductor layer. [Brief explanation of the drawing]

[0006] [Figure 1] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 5] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 6] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 7] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 8] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 9] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 10] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 11] An explanatory diagram of the manufacturing method of the semiconductor device according to the first embodiment. [Figure 12] Schematic cross-sectional view of a comparative semiconductor device. [Figure 13] A diagram illustrating the operation and effects of the method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] A schematic cross-sectional view of a semiconductor device, a modified example of the first embodiment. [Figure 15] A diagram illustrating the operation and effects of a method for manufacturing a semiconductor device, a modified example of the first embodiment. [Figure 16] Circuit diagram of the main part of the semiconductor memory device according to the second embodiment. [Figure 17] A schematic cross-sectional view of the main part of the semiconductor memory device according to the second embodiment. [Figure 18]Schematic cross-sectional view of a memory cell array of a semiconductor memory device according to a second embodiment. [Figure 19] Schematic cross-sectional view of a semiconductor memory device according to a second embodiment. [Figure 20] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 21] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 22] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 23] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 24] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 25] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 26] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 27] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 28] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 29] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 30] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 31] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 32] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 33] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 34] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 35] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 36] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 37] Explanatory drawing of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 38] An explanatory diagram of the method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 39] An explanatory diagram of the method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 40] An explanatory diagram of the method for manufacturing a semiconductor memory device according to the second embodiment. [Figure 41] A schematic cross-sectional view of a memory cell array of a semiconductor memory device, a modified example of the second embodiment. [Modes for carrying out the invention]

[0007] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described may be omitted from the description as appropriate.

[0008] Furthermore, for convenience, the terms "on," "above," "under," and "below" may be used in this specification. "On," "above," "under," and "below" are terms that indicate, for example, relative positional relationships within a drawing. The terms "on," "above," "under," and "below" do not necessarily define positional relationships with respect to gravity.

[0009] Qualitative and quantitative analysis of the chemical composition of components constituting semiconductor devices or semiconductor memory devices described herein can be performed, for example, by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX). Furthermore, a transmission electron microscope (TEM) can be used, for example, to measure the thickness of components constituting semiconductor devices or semiconductor memory devices, the distance between components, etc.

[0010] (First embodiment) The semiconductor device of the first embodiment comprises a semiconductor layer containing silicon (Si), a first insulating layer provided in a first direction of the semiconductor layer, a second insulating layer surrounded by the semiconductor layer in a first cross-section perpendicular to the first direction and containing silicon (Si) and oxygen (O), a third insulating layer surrounded by the second insulating layer in a first cross-section and containing a metal element and oxygen (O), and a conductive layer surrounded by the first insulating layer in a second cross-section perpendicular to the first direction, provided in a first direction of the third insulating layer and spaced apart from the semiconductor layer.

[0011] Figures 1, 2, and 3 are schematic cross-sectional views of a semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment includes an insulating structure 100. The insulating structure 100 is a structure that electrically isolates the conductive layer and the semiconductor layer. The insulating structure 100 is a structure that maintains the insulating properties between the conductive layer and the semiconductor layer.

[0012] Figure 2 shows the AA' section of Figure 1. The AA' section is a section perpendicular to the first direction. The AA' section is an example of the first section.

[0013] Figure 3 shows the BB' section of Figure 1. The BB' section is a section perpendicular to the first direction. The BB' section is an example of the second section.

[0014] The insulating structure 100 includes a semiconductor layer 10, a first insulating layer 12, a second insulating layer 14, a third insulating layer 16, and a conductive layer 18.

[0015] The first direction is perpendicular to the surface of the semiconductor layer 10. The second direction is perpendicular to the first direction.

[0016] The semiconductor layer 10 contains silicon (Si). For example, the semiconductor layer 10 is mainly composed of silicon (Si). When we say that the semiconductor layer 10 is mainly composed of silicon (Si), it means that among the elements contained in the semiconductor layer 10, there are no elements with a higher content than silicon (Si). The semiconductor layer 10 is, for example, a single-crystal silicon layer or a polycrystalline silicon layer.

[0017] The semiconductor layer 10 is not limited to a single-crystal silicon layer or a polycrystalline silicon layer. The semiconductor layer 10 may be, for example, a silicon germanide layer or a silicon carbide layer.

[0018] The first insulating layer 12 is provided in a first direction of the semiconductor layer 10. The first insulating layer 12 is provided, for example, on top of the semiconductor layer 10. The first insulating layer 12 is in contact with the semiconductor layer 10, for example.

[0019] The first insulating layer 12 includes, for example, an oxide. The first insulating layer 12 includes, for example, silicon (Si) and oxygen (O). The first insulating layer 12 includes, for example, silicon oxide. The first insulating layer 12 is, for example, silicon oxide.

[0020] The first insulating layer 12 includes, for example, a nitride. The first insulating layer 12 includes, for example, silicon (Si) and nitrogen (N). The first insulating layer 12 includes, for example, silicon nitride. The first insulating layer 12 is, for example, silicon nitride.

[0021] The first insulating layer 12 includes, for example, an oxynitride. The first insulating layer 12 includes, for example, silicon (Si), oxygen (O), and nitrogen (N). The first insulating layer 12 includes, for example, silicon oxynitride. The first insulating layer 12 is, for example, silicon oxynitride.

[0022] The second insulating layer 14 is surrounded by the semiconductor layer 10 in a first cross-section perpendicular to the first direction. For example, as shown in Figure 2, the second insulating layer 14 is surrounded by the semiconductor layer 10 in the AA' cross-section. The second insulating layer 14 is in contact with the semiconductor layer 10, for example.

[0023] The second insulating layer 14 contains silicon (Si) and oxygen (O). For example, the second insulating layer 14 is mainly composed of silicon (Si) and oxygen (O). The statement that the second insulating layer 14 is mainly composed of silicon (Si) and oxygen (O) means that among the elements contained in the second insulating layer 14, there are no elements that are present in a higher proportion than silicon (Si) and oxygen (O).

[0024] The second insulating layer 14 includes, for example, silicon oxide.

[0025] The third insulating layer 16 is surrounded by the second insulating layer 14 in a first cross-section perpendicular to the first direction. For example, as shown in Figure 2, the third insulating layer 16 is surrounded by the second insulating layer 14 in the AA' cross-section. The third insulating layer 16 is spaced apart from, for example, the semiconductor layer 10.

[0026] The third insulating layer 16 is provided in the first direction of the conductive layer 18. The third insulating layer 16 is provided below the conductive layer 18. The third insulating layer 16 is provided directly below the conductive layer 18.

[0027] The third insulating layer 16 contains a metallic element and oxygen (O). The metallic element contained in the third insulating layer 16 is, for example, at least one metallic element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), yttrium (Y), titanium (Ti), nickel (Ni), zinc (Zn), indium (In), tin (Sn), gallium (Ga), and tungsten (W).

[0028] The third insulating layer 16 mainly consists of, for example, the above-mentioned metal element and oxygen (O). The statement that the third insulating layer 16 mainly consists of the above-mentioned metal element and oxygen (O) means that among the elements contained in the third insulating layer 16, there are no elements present in a higher proportion than the above-mentioned metal element and oxygen (O).

[0029] The third insulating layer 16 includes, for example, a metal oxide.

[0030] The third insulating layer 16 includes, for example, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, titanium oxide, nickel oxide, zinc oxide, indium oxide, tin oxide, gallium oxide, or tungsten oxide.

[0031] The chemical composition of the third insulating layer 16 is, for example, different from that of the second insulating layer 14. The dielectric constant of the third insulating layer 16 is, for example, higher than that of the second insulating layer 14.

[0032] The width of the third insulating layer 16 in the second direction is, for example, 2 nm to 10 nm. The width of the second insulating layer 14 in the second direction is, for example, 3 to 20 times the width of the third insulating layer 16 in the second direction.

[0033] The conductive layer 18 is surrounded by the first insulating layer 12 in a second cross-section perpendicular to the first direction. For example, as shown in Figure 3, the conductive layer 18 is surrounded by the first insulating layer 12 in the BB' cross-section. The conductive layer 18 is in contact with the first insulating layer 12, for example.

[0034] The conductive layer 18 is provided in a first direction of the third insulating layer 16. The conductive layer 18 is in contact with, for example, the third insulating layer 16. The conductive layer 18 is in contact with, for example, the second insulating layer 14.

[0035] The width of the conductive layer 18 in the second direction is smaller than, for example, the width of the second insulating layer 14 in the second direction.

[0036] The conductive layer 18 is, for example, a metal, a metallic compound, or a semiconductor. The conductive layer 18 includes, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), or titanium (Ti). The conductive layer 18 includes, for example, polycrystalline silicon.

[0037] Next, an example of a method for manufacturing the semiconductor device according to the first embodiment will be described.

[0038] Figures 4, 5, 6, 7, 8, 9, 10, and 11 are explanatory diagrams of the manufacturing method of the first embodiment of the device. Figures 4 to 11 are cross-sectional views corresponding to Figure 1. Figures 4 to 11 show an example of the manufacturing method of the insulating structure 100 of the first embodiment.

[0039] The following explanation will use the example where the semiconductor layer 10 is single-crystal silicon, the first insulating layer 12 is silicon oxide, the second insulating layer 14 is silicon oxide, the third insulating layer 16 is aluminum oxide, and the conductive layer 18 is tungsten (W).

[0040] First, a first silicon oxide film 21 is formed on the single-crystal silicon layer 20 (Figure 4). The first silicon oxide film 21 is formed, for example, by chemical vapor deposition (CVD).

[0041] Next, a patterned resist film 22 is formed on the first silicon oxide film 21 (Figure 5). The resist film 22 is formed by photolithography.

[0042] Next, an opening 23 is formed using the resist film 22 as a mask (Figure 6). The opening 23 penetrates the first silicon oxide film 21 and forms a recess 24 in the single-crystal silicon layer 20. The opening 23 is formed, for example, by reactive ion etching (RIE).

[0043] Next, the resist film 22 is removed (Figure 7). The resist film 22 is removed, for example, by ashing.

[0044] Next, an aluminum oxide film 25 is formed inside the opening 23 (Figure 8). The aluminum oxide film 25 is formed, for example, by atomic layer deposition (ALD) method. The thickness of the aluminum oxide film is, for example, 1 nm to 5 nm.

[0045] Next, a second silicon oxide film 26 is formed between the single-crystal silicon layer 20 and the aluminum oxide film 25 using radical oxidation (Figure 9). The second silicon oxide film 26 is formed by the oxidation of the single-crystal silicon layer 20 by radical oxidation.

[0046] Radical oxidation is carried out in an atmosphere containing oxygen radicals or hydroxyl radicals. For example, radical oxidation is carried out in an atmosphere of plasma-generated oxygen, hydrogen, and argon gases. For example, radical oxidation is carried out in an atmosphere of plasma-generated water vapor.

[0047] The methods for generating oxygen radicals and hydroxyl radicals used in radical oxidation are not particularly limited. Oxygen radicals and hydroxyl radicals can be generated, for example, using inductively coupled plasma, microwave plasma, electron cyclotron resonance, helicon wave, or thermal filament methods.

[0048] The temperature for radical oxidation is, for example, between 300°C and 900°C. The pressure for radical oxidation is, for example, between 50 Pa and 3000 Pa.

[0049] Next, the aluminum oxide film 25 inside the opening 23 and on the surface of the first silicon oxide film 21 is removed (Figure 10). The aluminum oxide film 25 is removed, for example, by a wet etching method.

[0050] Next, the inside of the opening 23 is filled with a tungsten film 27 (Figure 11). The tungsten film 27 is formed, for example, by the CVD method.

[0051] By the above manufacturing method, the insulating structure 100 shown in Figures 1, 2, and 3 is formed.

[0052] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0053] Figure 12 is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device includes an insulating structure 900. The insulating structure 900 is a structure that electrically separates the conductive layer and the semiconductor layer.

[0054] The comparative example insulation structure 900 includes a semiconductor layer 10, a first insulation layer 12, a second insulation layer 14, and a conductive layer 18. The comparative example insulation structure 900 differs from the insulation structure 100 of the first embodiment in that it does not include a third insulation layer 16.

[0055] The insulating structure 900 is a structure for maintaining electrical insulation between the conductive layer 18 and the semiconductor layer 10. By providing a second insulating layer 14 between the conductive layer 18 and the semiconductor layer 10, electrical insulation between the conductive layer 18 and the semiconductor layer 10 is maintained.

[0056] However, for example, if the distance between the conductive layer 18 and the semiconductor layer 10 becomes shorter, the electric field strength between the conductive layer 18 and the semiconductor layer 10 increases. For example, as shown in Figure 12, the electric field strength E increases at the point where the distance between the conductive layer 18 and the semiconductor layer 10 is minimized. As the electric field strength E increases, leakage current flows more easily between the conductive layer 18 and the semiconductor layer 10, and the electrical insulation between the conductive layer 18 and the semiconductor layer 10 decreases.

[0057] In the first embodiment of the insulating structure 100, a third insulating layer 16 having a higher dielectric constant than the second insulating layer 14 is provided below the conductive layer 18. By providing the third insulating layer 16 with a higher dielectric constant, the electric field lines between the conductive layer 18 and the semiconductor layer 10 are distributed, and the electric field strength between the conductive layer 18 and the semiconductor layer 10 is reduced. For example, the electric field strength E at the point where the distance between the conductive layer 18 and the semiconductor layer 10 is minimized is reduced. As a result of the reduced electric field strength E, leakage current between the conductive layer 18 and the semiconductor layer 10 is suppressed, and the electrical insulation between the conductive layer 18 and the semiconductor layer 10 is improved. Therefore, the characteristics of the semiconductor device equipped with the insulating structure 100 are improved.

[0058] The second insulating layer 14 constituting the insulating structure 100 is formed by radical oxidation after forming a metal oxide film, such as an aluminum oxide film, on the semiconductor layer, as described above. Through the inventors' research, it has become clear that by combining a metal oxide film and radical oxidation, the semiconductor layer can be oxidized thickly at a lower temperature compared to, for example, thermal oxidation.

[0059] Figure 13 is an explanatory diagram of the operation and effects of the semiconductor device manufacturing method according to the first embodiment. Figure 13 is a diagram showing the thickness of the oxide film formed by oxidizing the semiconductor layer by radical oxidation.

[0060] Figure 13 compares the oxide film thickness when a metal oxide film is formed on a semiconductor layer and when no metal oxide film is formed. Figure 13 shows the case where the semiconductor layer is a single-crystal silicon layer and the metal oxide film is an aluminum oxide film. Figure 13 shows the case where the aluminum oxide film thickness is 3 nm and the radical oxidation temperature is 700°C.

[0061] As is clear from Figure 13, when an aluminum oxide film is formed on a semiconductor layer and radical oxidation is performed, the oxide film thickness is more than seven times greater than when no aluminum oxide film is formed. In other words, it can be seen that a significant acceleration of oxidation occurs when an aluminum oxide film is formed on a semiconductor layer and radical oxidation is performed.

[0062] The mechanism by which rapid oxidation occurs, as shown in Figure 13, is not entirely clear. However, it is thought that the presence of a film in which metal elements and oxygen (O) coexist on a silicon-containing semiconductor layer lowers the activation energy for oxide film formation, leading to rapid oxidation. It is also thought that oxygen-deficient regions in the metal oxide are filled by oxygen radicals and hydroxyl radicals, and then oxygen radicals that subsequently penetrate the metal oxide release oxygen from the metal oxide, resulting in rapid oxidation.

[0063] The insulating structure 100 of the first embodiment, which includes a third insulating layer 16, is easy to form at low temperatures. Therefore, for example, even if an element with low heat resistance is formed in the semiconductor device before the insulating structure 100 is formed, the degradation of the characteristics of that element due to heat treatment can be suppressed.

[0064] (modified version) Figure 14 is a schematic cross-sectional view of a modified semiconductor device of the first embodiment. The modified semiconductor device of the first embodiment includes an insulating structure 101. The insulating structure 101 is a structure that electrically separates the conductive layer and the semiconductor layer. The modified semiconductor device of the first embodiment differs from the semiconductor device of the first embodiment in that it further includes a fourth insulating layer containing silicon (Si), oxygen (O), and nitrogen (N) between the second insulating layer and the third insulating layer.

[0065] In the insulating structure 101, a fourth insulating layer 28 is provided between the second insulating layer 14 and the third insulating layer 16. The fourth insulating layer 28 is in contact with, for example, the second insulating layer 14 and the third insulating layer 16.

[0066] The fourth insulating layer 28 contains silicon (Si), oxygen (O), and nitrogen (N). For example, the fourth insulating layer 28 is mainly composed of silicon (Si), oxygen (O), and nitrogen (N). The statement that the fourth insulating layer 28 is mainly composed of silicon (Si) and oxygen (O) means that among the elements contained in the fourth insulating layer 28, there are no elements that are present in a higher proportion than silicon (Si), oxygen (O), and nitrogen (N).

[0067] The fourth insulating layer 28 includes, for example, silicon oxynitride.

[0068] The comparative example insulation structure 101 can be manufactured, for example, by forming a silicon oxynitride film in the opening 23 before forming the aluminum oxide film 25 in the manufacturing method of the insulation structure 100 of the first embodiment described above.

[0069] Figure 15 is an explanatory diagram illustrating the operation and effects of a modified semiconductor device manufacturing method according to the first embodiment. Figure 15 is a diagram showing the thickness of the oxide film formed by oxidizing the semiconductor layer by radical oxidation.

[0070] Figure 15 compares the oxide film thickness when a film containing silicon (Si), oxygen (O), and nitrogen (N) and a metal oxide film are formed on a semiconductor layer, when only a metal oxide film is formed, and when neither a film containing silicon (Si), oxygen (O), and nitrogen (N) nor a metal oxide film is formed. Figure 15 shows the case where the semiconductor layer is a single-crystal silicon layer, the film containing silicon (Si), oxygen (O), and nitrogen (N) is a silicon oxynitride film, and the metal oxide film is an aluminum oxide film. Figure 15 shows the case where the silicon oxynitride film thickness is 8 nm, the aluminum oxide film thickness is 3 nm, and the radical oxidation temperature is 700°C.

[0071] As is clear from Figure 15, when a silicon oxynitride film and an aluminum oxide film are formed on a semiconductor layer and radical oxidation is performed, the oxide film thickness is more than 26 times greater than when no silicon oxynitride film or aluminum oxide film is formed. Furthermore, when a silicon oxynitride film and an aluminum oxide film are formed on a semiconductor layer and radical oxidation is performed, the oxide film thickness is more than 3 times greater than when only an aluminum oxide film is formed and radical oxidation is performed. This shows that a significantly increased rate of oxidation occurs when a silicon oxynitride film and an aluminum oxide film are formed on a semiconductor layer and radical oxidation is performed.

[0072] The insulating structure 101 of the modified embodiment, which includes a fourth insulating layer 28, can be easily formed at low temperatures and in a short time. Therefore, for example, even if an element with low heat resistance is formed on the semiconductor device before the insulating structure 101 is formed, the degradation of the characteristics of that element due to heat treatment can be further suppressed.

[0073] As described above, according to the first embodiment and its modifications, the insulating properties between the conductive layer and the semiconductor layer are improved, and the characteristics of the semiconductor device are improved.

[0074] (Second embodiment) The semiconductor memory device of the second embodiment includes: a first semiconductor layer containing silicon (Si); a first insulating layer provided in a first direction of the first semiconductor layer; a second insulating layer surrounded by the first semiconductor layer in a first cross-section perpendicular to the first direction and containing silicon (Si) and oxygen (O); a third insulating layer surrounded by the second insulating layer in a first cross-section and containing a metallic element and oxygen (O); a conductive layer extending in a first direction, surrounded by the first insulating layer in a second cross-section perpendicular to the first direction, provided in a first direction of the third insulating layer and spaced apart from the first semiconductor layer; a first gate electrode layer provided in a first direction of the first semiconductor layer and electrically connected to the conductive layer; a second semiconductor layer extending in a first direction; and a charge storage layer provided between the first gate electrode layer and the second semiconductor layer.

[0075] The semiconductor memory device of the second embodiment is a three-dimensional NAND flash memory. The memory cells of the semiconductor memory device of the second embodiment are so-called Metal-Oxide-Nitride-Oxide-Semiconductor (MONOS) type memory cells.

[0076] Figure 16 is a circuit diagram of the main components of a semiconductor memory device according to a second embodiment. Figure 16 is a circuit diagram including a memory cell array and contact electrodes of a three-dimensional NAND flash memory.

[0077] The main components of the 3D NAND flash memory of the second embodiment, as shown in Figure 16, include a first word line WL1, a second word line WL2, a third word line WL3, a common source line CSL, a source selection gate line SGS, multiple drain selection gate lines SGD, multiple bit lines BL, multiple memory strings MS, a first contact electrode CC1, a second contact electrode CC2, and a third contact electrode CC3.

[0078] Hereinafter, the first word line WL1, the second word line WL2, and the third word line WL3 may be referred to individually or collectively as word line WL. Similarly, the first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 may be referred to individually or collectively as contact electrode CC.

[0079] Multiple word lines WL are arranged in the z direction, spaced apart from each other. Multiple word lines WL are arranged stacked in the z direction. Multiple memory strings MS extend in the z direction. Multiple bit lines BL extend, for example, in the x direction.

[0080] Hereafter, we define the x-direction as the third direction, the y-direction as the second direction, and the z-direction as the first direction. The x, y, and z directions intersect with each other and are, for example, perpendicular to each other.

[0081] As shown in Figure 16, a memory string MS comprises a source selection transistor SST connected in series between a common source line CSL and a bit line BL, multiple memory cells, and a drain selection transistor SDT. One memory string MS is selected by selecting one bit line BL and one drain selection gate line SGD, and one memory cell is selected by selecting one word line WL. The word line WL is the gate electrode of a memory cell transistor MT that constitutes a memory cell. A contact electrode CC is provided to apply a gate voltage to the word line WL.

[0082] Note that while Figure 16 illustrates the case where one memory string MS contains three memory cells, the number of memory cells in one memory string MS is not limited to three.

[0083] Figure 17 is a schematic cross-sectional view of the main part of a semiconductor memory device according to the second embodiment. Figure 17 is a cross-sectional view including the memory cell array and contact electrodes of a three-dimensional NAND flash memory. Figure 17 is a cross-sectional view corresponding to the circuit diagram of Figure 16.

[0084] The 3D NAND flash memory of the second embodiment includes a first semiconductor layer 11, a first insulating layer 12, a second insulating layer 14, a third insulating layer 16, a second semiconductor layer 30, a gate insulating layer 31, a separation insulating layer 40, a connecting electrode 42, a wiring layer 46, a first memory string MS1, a second memory string MS2, a third memory string MS3, a first word line WL1, a second word line WL2, a third word line WL3, a plurality of bit lines BL, a first contact electrode CC1, a second contact electrode CC2, and a third contact electrode CC3. Note that the common source line CSL, source selection gate line SGS, and drain selection gate line SGD are not shown in Figure 17.

[0085] The second word line WL2 is an example of the first gate electrode layer. The first word line WL1 is an example of the second gate electrode layer. The second contact electrode CC2 is an example of a conductive layer.

[0086] The three-dimensional NAND flash memory of the second embodiment has a structure similar to the insulating structure 100 of the first embodiment in order to electrically isolate the contact electrode CC and the semiconductor layer 10. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0087] The first semiconductor layer 11 contains silicon (Si). The first semiconductor layer 11 is, for example, mainly composed of silicon (Si). The first semiconductor layer 11 is, for example, a single-crystal silicon layer or a polycrystalline silicon layer.

[0088] The first semiconductor layer 11 is not limited to a single-crystal silicon layer or a polycrystalline silicon layer. The first semiconductor layer 11 may be, for example, a silicon germanide layer or a silicon carbide layer.

[0089] The first memory string MS1, the second memory string MS2, and the third memory string MS3 each comprise a second semiconductor layer 30 and a gate insulating layer 31. The first memory string MS1, the second memory string MS2, and the third memory string MS3 are each electrically connected to the bit line BL by connecting electrodes 42.

[0090] The first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 extend in the z direction. The first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 are conductors.

[0091] The first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 are, for example, metals, metal compounds, or semiconductors. The first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 include, for example, tungsten (W), molybdenum (Mo), ruthenium (Ru), or titanium (Ti). The first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 are, for example, polycrystalline silicon.

[0092] The first contact electrode CC1 is electrically connected to the third word line WL3. The first contact electrode CC1 is in contact with the third word line WL3.

[0093] The first contact electrode CC1 is electrically isolated from the second word line WL2. The first contact electrode CC1 is spaced apart from the second word line WL2. An isolation insulating layer 40 is provided between the first contact electrode CC1 and the second word line WL2.

[0094] The first contact electrode CC1 is electrically isolated from the first word line WL1. The first contact electrode CC1 is spaced apart from the first word line WL1. An isolation insulating layer 40 is provided between the first contact electrode CC1 and the first word line WL1.

[0095] The second contact electrode CC2 is electrically connected to the second word line WL2. The second contact electrode CC2 is in contact with the second word line WL2.

[0096] The second contact electrode CC2 is electrically isolated from the first word line WL1. The second contact electrode CC2 is spaced apart from the first word line WL1. An isolation insulating layer 40 is provided between the second contact electrode CC2 and the first word line WL1.

[0097] The third contact electrode CC3 is electrically connected to the first word line WL1. The third contact electrode CC3 is in contact with the first word line WL1.

[0098] The isolation insulating layer 40 is, for example, an oxide. The isolation insulating layer 40 is, for example, silicon oxide.

[0099] The first contact electrode CC1, the second contact electrode CC2, and the third contact electrode CC3 are each electrically connected to the wiring layer 46. A gate voltage that controls the memory cell transistor MT is applied to the wiring layer 46.

[0100] Figures 18(a) and 18(b) are schematic cross-sectional views of a memory cell array of a semiconductor memory device according to a second embodiment. Figures 18(a) and 18(b) show cross-sections of multiple memory cells in the memory cell array of Figure 17, for example, in the first memory string MS1 enclosed by the dotted line.

[0101] Figure 18(a) is a yz cross-sectional view of the first memory string MS1. Figure 18(a) is the QQ' cross-section of Figure 18(b). Figure 18(b) is an xy cross-sectional view of the first memory string MS1. Figure 18(b) is the PP' cross-section of Figure 18(a). In Figure 18(a), the area enclosed by the dotted line is a single memory cell.

[0102] The word lines WL and the first insulating layer 12 are stacked alternately in the z direction. The word lines WL and the first insulating layer 12 are provided in the z direction of the first semiconductor layer 11. The word lines WL are spaced apart from the first semiconductor layer 11 in the z direction. The first insulating layer 12 electrically isolates the word lines WL from each other.

[0103] The second semiconductor layer 30 extends in the z-direction. The second semiconductor layer 30 extends in a direction perpendicular to the surface of the first semiconductor layer 11. The second semiconductor layer 30 penetrates the word line WL and the first insulating layer 12. The second semiconductor layer 30 is in contact with, for example, the first semiconductor layer 11.

[0104] The second semiconductor layer 30 is surrounded by word lines WL. The second semiconductor layer 30 is, for example, cylindrical. The second semiconductor layer 30 functions as the channel of the memory cell transistor MT.

[0105] The second semiconductor layer 30 is, for example, a polycrystalline semiconductor. The second semiconductor layer 30 is, for example, polycrystalline silicon.

[0106] The gate insulating layer 31 is provided between the word line WL and the second semiconductor layer 30. The gate insulating layer 31 is provided between the first word line WL1 and the second semiconductor layer 30. The gate insulating layer 31 is provided between the second word line WL2 and the second semiconductor layer 30. The gate insulating layer 31 is provided between the third word line WL3 and the second semiconductor layer 30.

[0107] The gate insulating layer 31 includes a tunnel insulating layer 32, a charge storage layer 33, and a block insulating layer 34.

[0108] The tunnel insulating layer 32 is provided between the second semiconductor layer 30 and the word line WL. The tunnel insulating layer 32 has the function of allowing charge to pass through in accordance with the voltage applied between the word line WL and the semiconductor layer 10. The tunnel insulating layer 32 includes, for example, an oxide, a nitride, or an oxynitride. The tunnel insulating layer 32 has, for example, a laminated structure of silicon oxide and silicon nitride.

[0109] The charge storage layer 33 is provided between the tunnel insulating layer 32 and the word line WL. The charge storage layer 33 is provided between the tunnel insulating layer 32 and the block insulating layer 34.

[0110] The charge storage layer 33 has the function of trapping and storing electric charge. This charge is, for example, electrons. The threshold voltage of the memory cell transistor MT changes depending on the amount of charge stored in the charge storage layer 33. By utilizing this change in threshold voltage, a single memory cell can store data.

[0111] The charge storage layer 33 includes, for example, a nitride. The charge storage layer 33 includes, for example, silicon nitride.

[0112] The block insulating layer 34 is provided between the charge storage layer 33 and the word line WL. The block insulating layer 34 has the function of blocking the current flowing between the charge storage layer 33 and the word line WL.

[0113] The block insulating layer 34 includes, for example, an oxide, an oxynitride, or a nitride. The block insulating layer 34 includes, for example, aluminum oxide or silicon oxide.

[0114] Figures 19(a), 19(b), 19(c), and 19(d) are schematic cross-sectional views of a semiconductor memory device according to a second embodiment. Figure 19(a) is the AA' cross-section of Figure 17. Figure 19(b) is the BB' cross-section of Figure 17. Figure 19(c) is the CC' cross-section of Figure 17. Figure 19(d) is the DD' cross-section of Figure 17.

[0115] The first insulating layer 12 is provided in a first direction of the first semiconductor layer 11. The first insulating layer 12 is provided, for example, on top of the first semiconductor layer 11. The first insulating layer 12 is in contact with the first semiconductor layer 11, for example.

[0116] The first insulating layer 12 includes, for example, an oxide. The first insulating layer 12 includes, for example, silicon (Si) and oxygen (O). The first insulating layer 12 includes, for example, silicon oxide. The first insulating layer 12 is, for example, silicon oxide.

[0117] The first insulating layer 12 includes, for example, a nitride. The first insulating layer 12 includes, for example, silicon (Si) and nitrogen (N). The first insulating layer 12 includes, for example, silicon nitride. The first insulating layer 12 is, for example, silicon nitride.

[0118] The first insulating layer 12 includes, for example, an oxynitride. The first insulating layer 12 includes, for example, silicon (Si), oxygen (O), and nitrogen (N). The first insulating layer 12 includes, for example, silicon oxynitride. The first insulating layer 12 is, for example, silicon oxynitride.

[0119] The second insulating layer 14 is surrounded by the first semiconductor layer 11 in a first cross-section perpendicular to the first direction. For example, as shown in Figure 19(a), the second insulating layer 14 is surrounded by the first semiconductor layer 11 in the AA' cross-section. The second insulating layer 14 is in contact with the first semiconductor layer 11, for example.

[0120] The second insulating layer 14 contains silicon (Si) and oxygen (O). For example, the second insulating layer 14 is mainly composed of silicon (Si) and oxygen (O). The statement that the second insulating layer 14 is mainly composed of silicon (Si) and oxygen (O) means that among the elements contained in the second insulating layer 14, there are no elements that are present in a higher proportion than silicon (Si) and oxygen (O).

[0121] The second insulating layer 14 includes, for example, silicon oxide.

[0122] The third insulating layer 16 is surrounded by the second insulating layer 14 in a first cross-section perpendicular to the first direction. For example, as shown in Figure 19(a), the third insulating layer 16 is surrounded by the second insulating layer 14 in the AA' cross-section. The third insulating layer 16 is spaced apart from, for example, the first semiconductor layer 11.

[0123] The third insulating layer 16 is provided in the first direction of the contact electrode CC. The third insulating layer 16 is provided below the contact electrode CC. The third insulating layer 16 is provided directly below the contact electrode CC.

[0124] The third insulating layer 16 contains a metallic element and oxygen (O). The metallic element contained in the third insulating layer 16 is, for example, at least one metallic element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), yttrium (Y), titanium (Ti), nickel (Ni), zinc (Zn), indium (In), tin (Sn), gallium (Ga), and tungsten (W).

[0125] The third insulating layer 16 mainly consists of, for example, the above-mentioned metal element and oxygen (O). The statement that the third insulating layer 16 mainly consists of the above-mentioned metal element and oxygen (O) means that among the elements contained in the third insulating layer 16, there are no elements present in a higher proportion than the above-mentioned metal element and oxygen (O).

[0126] The third insulating layer 16 includes, for example, a metal oxide.

[0127] The third insulating layer 16 includes, for example, aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, titanium oxide, nickel oxide, zinc oxide, indium oxide, tin oxide, gallium oxide, or tungsten oxide.

[0128] The chemical composition of the third insulating layer 16 is, for example, different from that of the second insulating layer 14. The dielectric constant of the third insulating layer 16 is, for example, higher than that of the second insulating layer 14.

[0129] The width of the third insulating layer 16 in the second direction is, for example, 2 nm to 10 nm. The width of the second insulating layer 14 in the second direction is, for example, 3 to 20 times the width of the third insulating layer 16 in the second direction.

[0130] The contact electrode CC is surrounded by the first insulating layer 12 in a second cross-section perpendicular to the first direction. For example, as shown in Figure 19(b), the contact electrode CC is surrounded by the first insulating layer 12 in a cross-section BB'. The contact electrode CC is in contact with the first insulating layer 12, for example.

[0131] The contact electrode CC is provided in a first direction of the third insulating layer 16. The contact electrode CC is in contact with, for example, the third insulating layer 16. The contact electrode CC is in contact with, for example, the second insulating layer 14.

[0132] The width of the contact electrode CC in the second direction is smaller than, for example, the width of the second insulating layer 14 in the second direction.

[0133] The second contact electrode CC2 is surrounded by the second word line WL2 in a third cross section perpendicular to the first direction. For example, as shown in Figure 19(c), the second contact electrode CC2 is surrounded by the second word line WL2 in the CC' cross section. The second contact electrode CC2 is in contact with the second word line WL2.

[0134] The second contact electrode CC2 is surrounded by the first word line WL1 in a fourth cross section perpendicular to the first direction. For example, as shown in Figure 19(d), the second contact electrode CC2 is surrounded by the first word line WL1 in the DD' cross section.

[0135] The second contact electrode CC2 is spaced apart from the first word line WL1. The second contact electrode CC2 is surrounded by a separation insulating layer 40. The separation insulating layer 40 is provided between the second contact electrode CC2 and the first word line WL1.

[0136] Next, an example of a method for manufacturing a semiconductor memory device according to the second embodiment will be described.

[0137] Figures 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, and 40 are explanatory diagrams of a method for manufacturing a semiconductor memory device according to a second embodiment. Figures 20 to 40 are cross-sectional views corresponding to Figure 17.

[0138] The following explanation will use the case where the first semiconductor layer 11 is single-crystal silicon, the first insulating layer 12 is silicon oxide, the second insulating layer 14 is silicon oxide, the third insulating layer 16 is aluminum oxide, and the contact electrode CC is tungsten (W) as an example.

[0139] First, a first silicon oxide film 51 and a first silicon nitride film 52 are alternately formed on a single-crystal silicon layer 50 (Figure 20). The first silicon oxide film 51 and the first silicon nitride film 52 are formed, for example, by a CVD method.

[0140] Next, a stepped structure is formed on the first silicon oxide film 51 and the first silicon nitride film 52 (Figure 21). The stepped structure can be formed, for example, by repeatedly etching the first silicon oxide film 51 or the first silicon nitride film 52 and isotropically removing the resist film after patterning the resist film.

[0141] Next, a sidewall insulating film 53 is formed on the sides of the first silicon oxide film 51 and the first silicon nitride film 52 (Figure 22). The sidewall insulating film 53 can be formed, for example, by deposition by CVD and RIE. The sidewall insulating film 53 is, for example, silicon oxide.

[0142] Next, a silicon nitride film is selectively formed on the surface of the exposed first silicon nitride film 52 (Figure 23). The silicon nitride film is formed, for example, by the CVD method.

[0143] Next, a silicon oxide film is formed on the first silicon nitride film 52 to form a silicon oxide layer 55 including the first silicon oxide film 51 (Figure 24). The silicon oxide layer 55 ultimately becomes the first insulating layer 12. The silicon oxide film is formed, for example, by the CVD method.

[0144] Next, a first opening 56 is formed that penetrates the silicon oxide layer 55 and the first silicon nitride film 52 (Figure 25). The first opening 56 is formed, for example, by photolithography and RIE.

[0145] Next, a first insulating film 57 and a polycrystalline silicon film 58 are formed in the first opening 56 (Figure 26). The first insulating film 57 ultimately becomes the gate insulating layer 31. The polycrystalline silicon film 58 ultimately becomes the second semiconductor layer 30. The first insulating film 57 and the polycrystalline silicon film 58 are formed, for example, by the CVD method.

[0146] Next, a silicon oxide film is formed on the first insulating film 57 and the polycrystalline silicon film 58 (Figure 27). The formed silicon oxide film becomes part of the silicon oxide layer 55. The silicon oxide film is formed, for example, by the CVD method.

[0147] Next, a second opening 60 is formed (Figure 28). The second opening 60 penetrates the silicon oxide layer 55 and the first silicon nitride film 52. The second opening 60 forms a recess 61 in the single-crystal silicon layer 50. The second opening 60 is formed, for example, by the RIE method. A hard mask is applied as an etching mask, for example.

[0148] Next, the first silicon nitride film 52 exposed on the inner surface of the second opening 60 is recessed (Figure 29). The first silicon nitride film 52 is recessed, for example, by isotropic dry etching.

[0149] Next, a second silicon oxide film 62 is formed in the second opening 60 (Figure 30). The second silicon oxide film 62 is formed, for example, by a CVD method.

[0150] Next, a portion of the second silicon oxide film 62 inside the second opening 60 is removed (Figure 31). The second silicon oxide film 62 is removed, for example, by a wet etching method.

[0151] Next, an aluminum oxide film 63 is formed in the second opening 60 (Figure 32). The aluminum oxide film 63 is formed, for example, by the ALD method. The thickness of the aluminum oxide film 63 is, for example, 1 nm to 5 nm. A portion of the aluminum oxide film 63 ultimately becomes the third insulating layer 16.

[0152] Next, a third silicon oxide film 64 is formed between the single-crystal silicon layer 50 and the aluminum oxide film 63 using radical oxidation (Figure 33). The third silicon oxide film 64 is formed by the oxidation of the single-crystal silicon layer 50 by radical oxidation. The third silicon oxide film 64 ultimately becomes the second insulating layer 14.

[0153] Radical oxidation is carried out in an atmosphere containing oxygen radicals or hydroxyl radicals. For example, radical oxidation is carried out in an atmosphere of plasma-generated oxygen, hydrogen, and argon gases. For example, radical oxidation is carried out in an atmosphere of plasma-generated water vapor.

[0154] The methods for generating oxygen radicals and hydroxyl radicals used in radical oxidation are not particularly limited. Oxygen radicals and hydroxyl radicals can be generated, for example, using inductively coupled plasma, microwave plasma, electron cyclotron resonance, helicon wave, or thermal filament methods.

[0155] The temperature for radical oxidation is, for example, between 300°C and 900°C. The pressure for radical oxidation is, for example, between 50 Pa and 3000 Pa.

[0156] Next, the second opening 60 is filled with an amorphous silicon film 65 (Figure 34). The amorphous silicon film 65 is formed, for example, by the CVD method.

[0157] Next, the first silicon nitride film 52 is removed (Figure 35). The first silicon nitride film 52 is selectively removed from the silicon oxide layer 55 and the second silicon oxide film 62. The first silicon nitride film 52 is removed, for example, by a wet etching method in which a wet etching solution is supplied from an opening (not shown). A void 66 is formed in the area where the first silicon nitride film 52 has been removed.

[0158] Next, a first tungsten film 68 is formed in the void 66 (Figure 36). The first tungsten film 68 is formed using the CVD method. The first tungsten film 68 ultimately becomes a word line WL.

[0159] Next, the amorphous silicon film 65 formed in the second opening 60 is removed (Figure 37). The amorphous silicon film 65 is removed, for example, by a wet etching method.

[0160] Next, the aluminum oxide film 63 formed in the second opening 60 is removed (Figure 38). The aluminum oxide film 63 is removed, for example, by a wet etching method.

[0161] Next, a portion of the second silicon oxide film 62 formed inside the second opening 60 is removed (Figure 39). The portion of the second silicon oxide film 62 is removed, for example, by a wet etching method.

[0162] Next, the inside of the second opening 60 is filled with a second tungsten film 69 (Figure 40). The second tungsten film 69 is formed, for example, by CVD.

[0163] Subsequently, the connecting electrode 42, the wiring layer 46, and the bit line BL are formed using known process techniques.

[0164] By the manufacturing method described above, the 3D NAND flash memory of the second embodiment shown in Figure 17 is manufactured.

[0165] Next, the operation and effects of the semiconductor memory device of the second embodiment will be described.

[0166] In the semiconductor memory device of the second embodiment, a third insulating layer 16 with a dielectric constant higher than that of the second insulating layer 14 is provided below the contact electrode CC. By providing the third insulating layer 16 with a high dielectric constant, the electric field lines between the contact electrode CC and the first semiconductor layer 11 are distributed, and the electric field strength between the contact electrode CC and the first semiconductor layer 11 is reduced. Therefore, the leakage current between the contact electrode CC and the first semiconductor layer 11 is suppressed, and the electrical insulation between the contact electrode CC and the first semiconductor layer 11 is improved. Thus, the characteristics of the semiconductor memory device are improved.

[0167] Furthermore, the second insulating layer 14 is formed by radical oxidation after forming a metal oxide film, such as an aluminum oxide film, on the semiconductor layer, as described above. Through the inventors' studies, it has become clear that by combining a metal oxide film and radical oxidation, the semiconductor layer can be oxidized thickly at a lower temperature compared to, for example, thermal oxidation.

[0168] In the semiconductor memory device of the second embodiment, which includes a third insulating layer 16, a second insulating layer 14 that electrically isolates the contact electrode CC from the first semiconductor layer 11 can be formed at a low temperature. Therefore, for example, degradation of characteristics due to heat treatment of the memory cell formed before the formation of the second insulating layer 14 can be suppressed.

[0169] (modified version) Figures 41(a) and 41(b) are schematic cross-sectional views of a memory cell array of a semiconductor memory device of a modified example of the second embodiment. Figure 41(a) is a yz cross-sectional view of the first memory string MS1. Figure 41(a) is a QQ' cross-section of Figure 41(b). Figure 41(b) is an xy cross-sectional view of the first memory string MS1. Figure 41(b) is a PP' cross-section of Figure 41(a). In Figure 41(a), the area enclosed by the dotted line is a single memory cell. Figures 41(a) and 41(b) correspond to Figures 18(a) and 18(b) of the second embodiment.

[0170] The semiconductor memory device of the second embodiment differs from the semiconductor memory device of the second embodiment in that it includes a core insulating layer 35.

[0171] The core insulating layer 35 extends in the z direction. The core insulating layer 35 is surrounded by the second semiconductor layer 30. The core insulating layer 35 contains, for example, an oxide. The core insulating layer 35 contains, for example, silicon oxide.

[0172] As described above, according to the second embodiment and its modifications, the insulating properties between the conductive layer and the semiconductor layer are improved, making it possible to improve the characteristics of the semiconductor memory device.

[0173] In addition, in the semiconductor memory device of the second embodiment, it is also possible to provide a fourth insulating layer 28 containing silicon (Si), oxygen (O), and nitrogen (N) between the second insulating layer 14 and the third insulating layer 16, as in the modified example of the first embodiment.

[0174] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0175] 10 Semiconductor Layers 11 First semiconductor layer 12 First insulating layer 14. Second insulating layer 16. Third insulating layer 18. Conductive layer 28. The fourth insulating layer 30 Second semiconductor layer 33 Charge storage layer CC2 Second contact electrode (conductive layer) WL1 First ward line (second gate electrode layer) WL2 Second ward line (first gate electrode layer)

Claims

1. A semiconductor layer containing silicon (Si), A first insulating layer provided in the first direction of the semiconductor layer, In a first cross-section perpendicular to the first direction, a second insulating layer is surrounded by the semiconductor layer and contains silicon (Si) and oxygen (O), In the first cross-section, a third insulating layer is surrounded by the second insulating layer and contains a metal element and oxygen (O), A fourth insulating layer is provided between the second insulating layer and the third insulating layer, and comprises silicon (Si), oxygen (O), and nitrogen (N). A conductive layer is provided in a second cross-section perpendicular to the first direction, surrounded by the first insulating layer, in the first direction of the third insulating layer, and spaced apart from the semiconductor layer. A semiconductor device equipped with a semiconductor device.

2. The semiconductor device according to claim 1, wherein the conductive layer is in contact with the third insulating layer.

3. The semiconductor device according to claim 1, wherein the first insulating layer is in contact with the semiconductor layer.

4. The semiconductor device according to claim 1, wherein the third insulating layer is spaced apart from the semiconductor layer.

5. The semiconductor device according to claim 1, wherein the dielectric constant of the third insulating layer is higher than that of the second insulating layer.

6. The semiconductor device according to claim 1, wherein the conductive layer is in contact with the second insulating layer.

7. The semiconductor device according to claim 1, wherein the aforementioned metal element is at least one metal element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), yttrium (Y), titanium (Ti), nickel (Ni), zinc (Zn), indium (In), tin (Sn), gallium (Ga), and tungsten (W).

8. A first semiconductor layer containing silicon (Si), A first insulating layer provided in a first direction of the first semiconductor layer, A second insulating layer, comprising silicon (Si) and oxygen (O), is surrounded by the first semiconductor layer in a first cross-section perpendicular to the first direction. In the first cross-section, a third insulating layer is surrounded by the second insulating layer and contains a metal element and oxygen (O), A fourth insulating layer is provided between the second insulating layer and the third insulating layer, and comprises silicon (Si), oxygen (O), and nitrogen (N). A conductive layer extending in the first direction, surrounded by the first insulating layer in a second cross-section perpendicular to the first direction, provided in the first direction of the third insulating layer, and spaced apart from the first semiconductor layer, A first gate electrode layer is provided in the first direction of the first semiconductor layer and is electrically connected to the conductive layer, A second semiconductor layer extending in the first direction, A charge storage layer is provided between the first gate electrode layer and the second semiconductor layer, A semiconductor memory device equipped with the following features.

9. The semiconductor memory device according to claim 8, wherein the conductive layer is in contact with the first gate electrode layer.

10. The first semiconductor layer is provided in the first direction, and the first gate electrode layer is provided in the first direction, and further comprises a second gate electrode layer that is electrically separated from the conductive layer, The semiconductor memory device according to claim 8, wherein the charge storage layer is provided between the second gate electrode layer and the second semiconductor layer.

11. The semiconductor memory device according to claim 10, wherein the conductive layer is spaced apart from the second gate electrode layer.

12. In a third cross-section perpendicular to the first direction, the conductive layer is surrounded by the first gate electrode layer. The semiconductor memory device according to claim 10, wherein in a fourth cross section perpendicular to the first direction, the conductive layer is surrounded by the second gate electrode layer.

13. The semiconductor memory device according to claim 8, wherein the conductive layer is in contact with the third insulating layer.

14. The semiconductor memory device according to claim 8, wherein the first insulating layer is in contact with the first semiconductor layer.

15. The semiconductor memory device according to claim 8, wherein the third insulating layer is spaced apart from the first semiconductor layer.

16. The semiconductor memory device according to claim 8, wherein the dielectric constant of the third insulating layer is higher than that of the second insulating layer.

17. The semiconductor memory device according to claim 8, wherein the conductive layer is in contact with the second insulating layer.

18. The semiconductor memory device according to claim 8, wherein the aforementioned metal element is at least one metal element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), yttrium (Y), titanium (Ti), nickel (Ni), zinc (Zn), indium (In), tin (Sn), gallium (Ga), and tungsten (W).

19. A semiconductor layer containing silicon (Si), A first insulating layer provided in the first direction of the semiconductor layer, In a first cross-section perpendicular to the first direction, a second insulating layer is surrounded by the semiconductor layer and contains silicon (Si) and oxygen (O), In the first cross-section, a third insulating layer is surrounded by the second insulating layer and contains a metal element and oxygen (O), A conductive layer is provided in a second cross-section perpendicular to the first direction, surrounded by the first insulating layer, in the first direction of the third insulating layer, and spaced apart from the semiconductor layer. Equipped with, The conductive layer is in contact with the second insulating layer and the third insulating layer, and the second insulating layer is in contact with the semiconductor layer. The conductive layer, in a cross-section parallel to the first direction and including the third insulating layer, has a first portion in contact with the second insulating layer, a second portion in contact with the second insulating layer, and a third portion in contact with the third insulating layer, wherein the third portion is provided between the first portion and the second portion.

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