Semiconductor equipment

Abstract

To provide a semiconductor device capable of suppressing degradation of operating characteristics.SOLUTION: A semiconductor device according to an embodiment includes: a semiconductor layer having a first face and a second face facing the first face; a first semiconductor region of a first conductive type provided in the semiconductor layer, in contact with the second face, and including a first portion having a first minimum width, a second portion having a second minimum width smaller than the first minimum width, and a third portion connecting the first portion and the second portion to each other and having a third minimum width smaller than the second minimum width; a plurality of second semiconductor regions of a second conductive type in contact with the second face and provided so as to be separated from each other in the first semiconductor region; a third semiconductor region of the second conductive type provided between the first semiconductor region and the first face; a fourth semiconductor region of the first conductive type provided between the third semiconductor region and the first face; a fifth semiconductor region of the second conductive type provided between the fourth semiconductor region and the first face; a gate electrode facing the fourth semiconductor region; a gate insulating film; a first electrode in contact with the first face; and a second electrode in contact with the second face.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices. [Background technology]

[0002] An example of a semiconductor device is an Insulated Gate Bipolar Transistor (IGBT). In an IGBT, for example, a p-type collector region, an n-type drift region, and a p-type base region are provided on the collector electrode. A gate electrode is provided in a trench that penetrates the p-type base region and reaches the n-type drift region, with a gate insulating film in between. Furthermore, an n-type emitter region, connected to the emitter electrode, is provided in a region adjacent to the trench on the surface of the p-type base region.

[0003] In recent years, reverse-conducting IGBTs (RC-IGBTs), which integrate IGBTs and freewheeling diodes on the same semiconductor chip, have been widely developed and commercialized. RC-IGBTs are used, for example, as switching elements in inverter circuits. The freewheeling diode has the function of allowing current to flow in the opposite direction to the IGBT's on-current. Integrating IGBTs and freewheeling diodes on the same semiconductor chip offers many advantages, such as reducing chip size by sharing termination regions and distributing heat-generating areas.

[0004] In RC-IGBTs, the addition of a diode may degrade the operating characteristics of the IGBT. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Patent No. 6884114 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] The problem that this invention aims to solve is to provide a semiconductor device that suppresses the deterioration of its operating characteristics. [Means for solving the problem]

[0007] The semiconductor device of the embodiment includes a semiconductor layer having a first surface and a second surface facing the first surface, and a first minimum width provided within the semiconductor layer, in contact with the second surface. multiple A first part, a plurality of second parts having a second minimum width smaller than the first minimum width, and multiple Part 1 One of the first parts inside A first semiconductor region of a first conductivity type, which includes a plurality of third parts that connect one of the plurality of second parts, or two of the plurality of second parts, and have a third minimum width smaller than the second minimum width, and provided in the semiconductor layer, in contact with the second surface, multiple The semiconductor comprises: a plurality of second semiconductor regions of a second conductivity type provided spaced apart from each other within the first semiconductor region other than the first portion, the plurality of second portions, and the plurality of third portions; a third semiconductor region of a second conductivity type provided within the semiconductor layer between the first semiconductor region and the first surface and between the plurality of second semiconductor regions and the first surface; a fourth semiconductor region of a first conductivity type provided within the semiconductor layer and between the third semiconductor region and the first surface; a fifth semiconductor region of a second conductivity type provided within the semiconductor layer and between the fourth semiconductor region and the first surface; a gate electrode facing the fourth semiconductor region; a gate insulating film provided between the fourth semiconductor region and the gate electrode; a first electrode in contact with the first surface; and a second electrode in contact with the second surface, wherein the minimum width of the third is greater than the distance between two second semiconductor regions in the nearest position among the plurality of second semiconductor regions, and one of the plurality of third portions is the multiple Part 1 One of the first parts insideconnects to one of the plurality of second parts, and another one of the plurality of third parts connects to two of the plurality of second parts, and the one third part and the another third part intersect The two nearest first parts among the plurality of first parts are connected to any one of the plurality of second parts by the third part. .

Brief Description of the Drawings

[0008] [Figure 1] Schematic plan view of the semiconductor device of the first embodiment. [Figure 2] Schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 3] Schematic plan view of the semiconductor device of the first embodiment. [Figure 4] Schematic plan view of the semiconductor device of the first embodiment. [Figure 5] Schematic plan view of the semiconductor device of the first embodiment. [Figure 6] Schematic cross-sectional view of a part of the semiconductor device of the first embodiment. [Figure 7] Schematic plan view of the semiconductor device of the comparative example. [Figure 8] Explanation diagram of the operation and effect of the semiconductor device of the first embodiment. [Figure 9] Schematic plan view of the semiconductor device of the second embodiment. [Figure 10] Schematic plan view of the semiconductor device of the third embodiment.

Modes for Carrying Out the Invention

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same or similar members are denoted by the same reference numerals, and the description of the members once described will be omitted as appropriate.

[0010] In this specification, n + type, n-type, n - type notation, when there is, n + type, n-type, n - type means that the n-type impurity concentration is decreasing in the order of n-type, n-type, n + type, p-type, p- If there is a notation for the shape, p + shape, p shape, p - This means that the concentration of p-type impurities decreases in the order of their shapes.

[0011] In this specification, the n-type impurity concentration refers to the effective n-type impurity concentration after compensation, not the actual n-type impurity concentration. Similarly, the p-type impurity concentration refers to the effective p-type impurity concentration after compensation, not the actual p-type impurity concentration. For example, if the actual n-type impurity concentration is greater than the actual p-type impurity concentration, the n-type impurity concentration is calculated by subtracting the p-type impurity concentration from the actual n-type impurity concentration. The same applies to the p-type impurity concentration.

[0012] In this specification, the distribution and absolute value of impurity concentrations in semiconductor regions can be measured, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM). Additionally, the distribution and absolute value of impurity concentrations can be measured, for example, using spreading resistance analysis (SRA). SCM and SRA provide the relative magnitudes and absolute values ​​of carrier concentrations in the semiconductor regions. By assuming an activation rate for impurities, the relative magnitudes, distribution, and absolute values ​​of impurity concentrations between two semiconductor regions can be determined from the measurement results of SCM and SRA.

[0013] (First Embodiment) The semiconductor device of the first embodiment includes a semiconductor layer having a first surface and a second surface facing the first surface; a first semiconductor region of a first conductivity type provided within the semiconductor layer, in contact with the second surface, and including a first portion having a first minimum width, a second portion having a second minimum width smaller than the first minimum width, and a third portion connecting the first portion and the second portion and having a third minimum width smaller than the second minimum width; and a plurality of second semiconductor regions of a second conductivity type provided within the semiconductor layer, in contact with the second surface, and spaced apart from each other within the first semiconductor region other than the first portion, the second portion, and the third portion. The semiconductor device comprises: a third semiconductor region of a second conductivity type provided within a semiconductor layer and between a first semiconductor region and a first surface, and between a second semiconductor region and a first surface; a fourth semiconductor region of a first conductivity type provided within a semiconductor layer and between a third semiconductor region and a first surface; a fifth semiconductor region of a second conductivity type provided within a semiconductor layer and between a fourth semiconductor region and a first surface; a gate electrode facing the fourth semiconductor region; a gate insulating film provided between the fourth semiconductor region and the gate electrode; a first electrode in contact with the first surface; and a second electrode in contact with the second surface.

[0014] The semiconductor device of the first embodiment is an RC-IGBT100 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip. The RC-IGBT100 has a trench-gate type IGBT with a gate electrode located in a trench formed in the semiconductor layer. The following explanation will be given using the case where the first conductivity type is p-type and the second conductivity type is n-type as an example.

[0015] Figure 1 is a schematic plan view of a semiconductor device according to the first embodiment. Figure 1 shows the electrode and wiring patterns on the first side of the RC-IGBT100.

[0016] Figure 2 is a schematic cross-sectional view of a part of the semiconductor device of the first embodiment. Figure 2 is the AA' cross-section of Figure 1.

[0017] Figure 3 is a schematic plan view of a semiconductor device according to the first embodiment. Figure 3 shows the pattern of the semiconductor region in the semiconductor layer on the second face side of the RC-IGBT100.

[0018] FIG. 4 is a schematic plan view of the semiconductor device according to the first embodiment. FIG. 4 is an explanatory diagram of the pattern of the semiconductor regions in the semiconductor layer on the side of the second surface of the RC-IGBT 100. FIG. 4 is a diagram corresponding to FIG. 3.

[0019] FIG. 5 is a schematic plan view of the semiconductor device according to the first embodiment. FIG. 5 shows the pattern of the semiconductor regions in the semiconductor layer on the side of the first surface of the RC-IGBT 100.

[0020] FIG. 6 is a schematic cross-sectional view of a part of the semiconductor device according to the first embodiment. FIG. 6 is a cross-section taken along the line BB' of FIG. 5.

[0021] The RC-IGBT 100 according to the first embodiment includes a semiconductor layer 10, an upper electrode 12 (first electrode), a lower electrode 14 (second electrode), a gate electrode pad 16, a gate wiring 18, a gate electrode 20, and a gate insulating film 22.

[0022] In the semiconductor layer 10, there are a trench 28, a p + -type collector region 30 (first semiconductor region), an n + -type cathode region 32 (second semiconductor region), an n-type buffer region 34, an n - -type drift region 36 (third semiconductor region), a p-type base region 38 (fourth semiconductor region), an n + -type emitter region 40 (fifth semiconductor region), a p-type first guard ring region 42 (sixth semiconductor region), a p-type second guard ring region 44 (eighth semiconductor region), a p-type third guard ring region 46, and an n + -type peripheral cathode region 48 (seventh semiconductor region) are provided.

[0023] p + -type collector region 30 includes a first portion 30a, a second portion 30b, and a third portion 30c.

[0024] The semiconductor layer 10 has a first surface F1 and a second surface F2 facing the first surface F1. The semiconductor layer 10 is, for example, single-crystal silicon. The thickness of the semiconductor layer 10 is, for example, 40 μm or more and 700 μm or less.

[0025] In this specification, a direction parallel to the first surface F1 is referred to as the first direction. A direction parallel to the first surface F1 and perpendicular to the first direction is referred to as the second direction. In this specification, "depth" is defined as the distance in the direction toward the second surface F2 with respect to the first surface F1.

[0026] The upper electrode 12 is provided on the side of the first surface F1 of the semiconductor layer 10. The upper electrode 12 is an example of the first electrode. At least a portion of the upper electrode 12 is in contact with the first surface F1 of the semiconductor layer 10.

[0027] The upper electrode 12 functions as the emitter electrode of the transistor when the RC-IGBT100 operates as a transistor. Furthermore, the upper electrode 12 functions as the anode electrode of the diode when the RC-IGBT100 operates as a diode.

[0028] The upper electrode 12 is in contact with the base region 38. The upper electrode 12 is in contact with the emitter region 40. The upper electrode 12 is in contact with the first guard ring region 42. The upper electrode 12 is electrically connected to the base region 38, the emitter region 40, and the first guard ring region 42.

[0029] The upper electrode 12 is made of, for example, metal.

[0030] The lower electrode 14 is provided on the side of the second surface F2 of the semiconductor layer 10. The lower electrode 14 is an example of a second electrode. At least a portion of the lower electrode 14 is in contact with the second surface F2 of the semiconductor layer 10.

[0031] The lower electrode 14 functions as the collector electrode of the transistor when the RC-IGBT100 operates as a transistor. Furthermore, the lower electrode 14 functions as the cathode electrode of the diode when the RC-IGBT100 operates as a diode.

[0032] The lower electrode 14 is in contact with the collector region 30. The lower electrode 14 is in contact with the cathode region 32. The lower electrode 14 is in contact with the peripheral cathode region 48. The lower electrode 14 is electrically connected to the collector region 30, the cathode region 32, and the peripheral cathode region 48.

[0033] The lower electrode 14 is, for example, made of metal.

[0034] The gate electrode pad 16 is provided on the side of the first surface F1 of the semiconductor layer 10. The gate electrode pad 16 is made of, for example, metal.

[0035] The gate wiring 18 is provided on the side of the first surface F1 of the semiconductor layer 10. The gate wiring 18 is connected to the gate electrode pad 16. The gate wiring 18 is electrically connected to the gate electrode 20. The gate electrode pad 16 is made of, for example, metal.

[0036] The collector area 30 is p + This is a semiconductor region of a certain shape. The collector region 30 is an example of a first semiconductor region.

[0037] The collector region 30 is in contact with the second surface F2. The collector region 30 is in contact with the lower electrode 14. The collector region 30 is electrically connected to the lower electrode 14. The collector region 30 serves as a hole source when the RC-IGBT 100 operates as a transistor.

[0038] The collector region 30 includes a first portion 30a, a second portion 30b, and a third portion 30c, as shown in Figures 3 and 4. In Figure 4, solid auxiliary lines are used to clarify the boundaries of the first portion 30a, the second portion 30b, and the third portion 30c.

[0039] The first portion 30a is in contact with the second surface F2. Multiple first portions 30a are provided, for example. The first portion 30a is, for example, square. The first portion 30a has a first minimum width (w1 in Figure 4) on the second surface F2.

[0040] The second portion 30b is in contact with the second surface F2. Multiple second portions 30b are provided, for example. The second portion 30b is, for example, square. The second portion 30b has a second minimum width (w2 in Figure 4) on the second surface F2.

[0041] The third portion 30c is in contact with the second surface F2. The third portion 30c connects the first portion 30a and the second portion 30b. The third portion 30c connects, for example, two second portions 30b. For example, all first portions 30a and all second portions 30b are connected by the third portion 30c.

[0042] The third portion 30c is, for example, a line shape. The third portion 30c is oblique to the first and second directions, for example, as shown in Figures 3 and 4. For example, as shown in Figures 3 and 4, multiple third portions 30c that are oblique to each other intersect to form a grid shape. The third portion 30c has a third minimum width (w3 in Figure 4) on the second surface F2.

[0043] The minimum width of a figure having a given shape is defined as the diameter of its largest inscribed circle. If the figure is a square, the minimum width is equal to the length of one side of the square. If the figure is a rectangle, the minimum width is equal to the length of the shorter side of the rectangle.

[0044] The second minimum width w2 is smaller than the first minimum width w1. For example, the second minimum width w2 is between 50% and 80% of the first minimum width w1.

[0045] The third minimum width w3 is smaller than the second minimum width w2. For example, the third minimum width w3 is between 20% and 60% of the second minimum width w2.

[0046] The area of ​​the first portion 30a is, for example, larger than the area of ​​the second portion 30b.

[0047] The first portion 30a, the second portion 30b, and the third portion 30c of the collector region 30 have the function of suppressing snapback in the current-voltage characteristics when the RC-IGBT 100 operates as a transistor.

[0048] Multiple cathode regions 32 are n + This is a semiconductor region of a certain shape. The cathode region 32 is an example of a second semiconductor region.

[0049] The cathode region 32 is in contact with the second surface F2. The cathode region 32 is in contact with the lower electrode 14. The cathode region 32 is electrically connected to the lower electrode 14. The cathode region 32 serves as an electron source when the RC-IGBT100 operates as a diode.

[0050] As shown in Figures 3 and 4, the cathode regions 32 are provided in the collector region 30 on the second surface, spaced apart from each other. The cathode regions 32 are provided in the collector region 30 on the second surface, excluding the first portion 30a, the second portion 30b, and the third portion 30c.

[0051] The cathode region 32 is, for example, a square. The cathode region 32 has a fourth minimum width (w4 in Figure 4) on the second surface F2. Multiple cathode regions 32 are arranged in a dot pattern, for example, as shown in Figures 3 and 4.

[0052] The third minimum width w3 of the third portion 30c is, for example, greater than the distance (d in Figure 4) between two nearest cathode regions 32 among the multiple cathode regions 32. The third minimum width w3 is, for example, 1.2 times or more the distance d between two nearest cathode regions 32 among the multiple cathode regions 32.

[0053] For example, the fourth minimum width w4 of the cathode region 32 is smaller than the third minimum width w3 of the third portion 30c. For example, the fourth minimum width w4 of the cathode region 32 is 80% or less of the third minimum width w3 of the third portion 30c.

[0054] The buffer region 34 is an n-type semiconductor region. The buffer region 34 is provided between the collector region 30 and the first surface F1. The buffer region 34 is provided between the cathode region 32 and the first surface F1.

[0055] The buffer region 34 has the function of suppressing the extension of the depletion layer extending to the drift region 36, for example, when the RC-IGBT 100 is in the off state.

[0056] The concentration of n-type impurities in buffer region 34 is lower than the concentration of n-type impurities in cathode region 32.

[0057] The drift region 36 is n - This is a semiconductor region of a certain shape. The drift region 36 is an example of a third semiconductor region. The drift region 36 is provided between the buffer region 34 and the first surface F1.

[0058] The drift region 36 is the on-current path when the RC-IGBT100 operates as a transistor and when the RC-IGBT100 operates as a diode. The drift region 36 also has the function of depleting when the RC-IGBT100 is in the off state, thereby maintaining the breakdown voltage of the RC-IGBT100.

[0059] The n-type impurity concentration in the drift region 36 is lower than the n-type impurity concentration in the buffer region 34.

[0060] The base region 38 is a p-type semiconductor region. The base region 38 is an example of a fourth semiconductor region. The base region 38 is provided between the drift region 36 and the first surface F1.

[0061] The base region 38 is in contact with the upper electrode 12. The base region 38 is electrically connected to the upper electrode 12.

[0062] In the region of the base region 38 facing the gate electrode 20, an n-type inversion layer is formed when the RC-IGBT 100 operates as a transistor. The base region 38 functions as the channel region of the transistor. In addition, the base region 38 functions as a hole source when the RC-IGBT 100 operates as a diode.

[0063] The emitter region 40 is n + This is a semiconductor region of a certain shape. The emitter region 40 is an example of a fifth semiconductor region. The emitter region 40 is located between the base region 38 and the first surface F1.

[0064] The emitter region 40 is in contact with the gate insulating film 22.

[0065] The emitter region 40 is in contact with the upper electrode 12. The emitter region 40 is electrically connected to the upper electrode 12. The emitter region 40 serves as an electron source when the RC-IGBT 100 operates as a transistor.

[0066] The first guard ring region 42 is a p-type semiconductor region. The first guard ring region 42 is an example of a sixth semiconductor region. The first guard ring region 42 is provided between the drift region 36 and the first surface F1.

[0067] As shown in Figure 5, the first guard ring region 42 surrounds the base region 38 on the first surface F1. The first guard ring region 42 is in contact with the base region 38. Note that the emitter region 40 is not shown in Figure 5.

[0068] The first guard ring region 42 is in contact with the upper electrode 12. The first guard ring region 42 is electrically connected to the upper electrode 12.

[0069] The p-type impurity concentration in the first guard ring region 42 is higher than the p-type impurity concentration in the base region 38. For example, the p-type impurity concentration in the first guard ring region 42 is more than twice the p-type impurity concentration in the base region 38.

[0070] The depth of the first guard ring region 42 relative to the first surface F1 is, for example, deeper than the depth of the base region 38 relative to the first surface F1. The depth of the first guard ring region 42 relative to the first surface F1 is, for example, 1.2 times or more the depth of the base region 38 relative to the first surface F1.

[0071] The first guard ring region 42 has the function of improving the voltage withstand capability of the RC-IGBT100. In addition, the first guard ring region 42 functions as a hole source when the RC-IGBT100 is operating as a diode.

[0072] The second guard ring region 44 is a p-type semiconductor region. The second guard ring region 44 is an example of an eighth semiconductor region. The second guard ring region 44 is provided between the drift region 36 and the first surface F1.

[0073] As shown in Figure 5, the second guard ring region 44 surrounds the first guard ring region 42 on the first surface F1. A drift region 36 is provided between the second guard ring region 44 and the first guard ring region 42 on the first surface F1.

[0074] The second guard ring region 44 is separated from the upper electrode 12. The second guard ring region 44 is electrically isolated from the upper electrode 12.

[0075] The p-type impurity concentration in the second guard ring region 44 is higher than the p-type impurity concentration in the base region 38. For example, the p-type impurity concentration in the second guard ring region 44 is more than twice the p-type impurity concentration in the base region 38.

[0076] The depth of the second guard ring region 44 relative to the first surface F1 is, for example, deeper than the depth of the base region 38 relative to the first surface F1. The depth of the second guard ring region 44 relative to the first surface F1 is, for example, 1.2 times or more the depth of the base region 38 relative to the first surface F1.

[0077] The second guard ring region 44 has the function of improving the pressure resistance of the RC-IGBT100.

[0078] The third guard ring region 46 is a p-type semiconductor region. The third guard ring region 46 is provided between the drift region 36 and the first surface F1.

[0079] As shown in Figure 5, the third guard ring region 46 surrounds the second guard ring region 44 on the first surface F1. A drift region 36 is provided between the third guard ring region 46 and the second guard ring region 44 on the first surface F1.

[0080] The third guard ring region 46 is separated from the upper electrode 12. The third guard ring region 46 is electrically isolated from the upper electrode 12.

[0081] The p-type impurity concentration in the third guard ring region 46 is higher than the p-type impurity concentration in the base region 38. For example, the p-type impurity concentration in the third guard ring region 46 is more than twice the p-type impurity concentration in the base region 38.

[0082] The depth of the third guard ring region 46 relative to the first surface F1 is, for example, deeper than the depth of the base region 38 relative to the first surface F1. The depth of the third guard ring region 46 relative to the first surface F1 is, for example, 1.2 times or more the depth of the base region 38 relative to the first surface F1.

[0083] The third guard ring region 46 has the function of improving the pressure resistance of the RC-IGBT100.

[0084] The peripheral cathode region 48 is n + This is a semiconductor region of a certain shape. The peripheral cathode region 48 is an example of a seventh semiconductor region.

[0085] As shown in Figure 3, the peripheral cathode region 48 surrounds the collector region 30 on the second surface F2. The peripheral cathode region 48 is in contact with the collector region 30.

[0086] As shown in Figure 6, the peripheral cathode region 48 is provided in the direction from the first surface F1 to the second surface F2 relative to the first guard ring region 42. The peripheral cathode region 48 is also provided, for example, in the direction from the first surface F1 to the second surface F2 relative to the second guard ring region 44. Furthermore, the peripheral cathode region 48 is also provided, for example, in the direction from the first surface F1 to the second surface F2 relative to the third guard ring region 46.

[0087] In other words, the peripheral cathode region 48 is provided, for example, directly below the first guard ring region 42, the second guard ring region 44, and the third guard ring region 46.

[0088] The peripheral cathode region 48 is in contact with the second surface F2. The peripheral cathode region 48 is in contact with the lower electrode 14. The peripheral cathode region 48 is electrically connected to the lower electrode 14.

[0089] The n-type impurity concentration in the peripheral cathode region 48 is, for example, equal to the n-type impurity concentration in the cathode region 32.

[0090] The width of the peripheral cathode region 48 in the first direction is, for example, greater than the width of the first guard ring region in the first direction. Also, the width of the peripheral cathode region 48 in the second direction is, for example, greater than the width of the first guard ring region in the second direction.

[0091] The peripheral cathode region 48 serves as an electron source when the RC-IGBT100 operates as a diode.

[0092] Next, we will explain how the RC-IGBT100 works.

[0093] When the RC-IGBT100 operates as a transistor, a positive voltage is applied to the lower electrode 14 relative to the upper electrode 12. Then, a voltage exceeding the threshold voltage is applied to the gate electrode 20. When a voltage exceeding the threshold voltage is applied to the gate electrode 20, an n-type inversion layer is formed in the region of the base region 38 opposite to the gate electrode 20. In other words, a channel is formed in the region of the base region 38 opposite to the gate electrode 20.

[0094] When an n-type inversion layer is formed in the region of the base region 38 opposite the gate electrode 20, electrons are injected from the upper electrode 12 through the emitter region 40 and the channel into the drift region 36. In addition, holes are injected from the lower electrode 14 through the collector region 30 into the drift region 36.

[0095] An ON current flows from the lower electrode 14 to the upper electrode 12, turning the transistor of the RC-IGBT100 ON. Subsequently, when a voltage lower than the threshold voltage is applied to the gate electrode 20, the channel disappears, and the transistor of the RC-IGBT100 OFF.

[0096] When the RC-IGBT100 operates as a diode, a positive voltage is applied to the upper electrode 12 relative to the lower electrode 14. A voltage lower than the threshold voltage is applied to the gate electrode 20.

[0097] Holes are injected into the drift region 36 from the upper electrode 12 through the base region 38. Electrons are also injected into the drift region 36 from the lower electrode 14 through the cathode region 32.

[0098] An ON current flows from the upper electrode 12 to the lower electrode 14, turning the diode of the RC-IGBT100 ON. Subsequently, when the voltage at the lower electrode 14 becomes greater than or equal to the voltage at the upper electrode 12, the diode of the RC-IGBT100 turns OFF.

[0099] Next, the operation and effects of the semiconductor device according to the first embodiment will be described.

[0100] Figure 7 is a schematic plan view of a comparative example semiconductor device. Figure 7 shows the pattern of the semiconductor region in the semiconductor layer on the second face side of the comparative example RC-IGBT900. Figure 7 corresponds to Figure 3 of the first embodiment.

[0101] The comparative example RC-IGBT900 is p + The collector region 30 of the first embodiment differs from the RC-IGBT100 in that it does not include the second portion 30b and the third portion 30c. Furthermore, the comparative example RC-IGBT900 has n + This differs from the RC-IGBT100 of the first embodiment in that it does not include the peripheral cathode region 48 of the shape.

[0102] Figure 8 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 8 is a diagram showing the current-voltage characteristics of the comparative examples RC-IGBT900 and RC-IGBT100 when they are operating as transistors.

[0103] Figure 8 shows the current-voltage characteristics when a voltage exceeding the threshold voltage is applied to the gate electrode 20, and a positive voltage is applied to the lower electrode 14 (collector electrode) relative to the upper electrode 12 (emitter electrode). Hereinafter, the voltage applied to the lower electrode 14 (collector electrode) will be referred to as the collector voltage (VCE), and the current flowing from the lower electrode 14 (collector electrode) to the upper electrode 12 (emitter electrode) will be referred to as the collector current (ICE).

[0104] As shown in Figure 8, the comparative example RC-IGBT900 exhibits significant snapback in its current-voltage characteristics.

[0105] For example, consider the case where multiple RC-IGBT900s are connected in parallel. If snapback occurs in the current-voltage characteristics of the RC-IGBT900, the current flowing through the multiple RC-IGBT900s connected in parallel will become unbalanced. For example, an excessive current may flow through one RC-IGBT900, potentially leading to its destruction. Therefore, it is desirable to suppress the occurrence of snapback in the current-voltage characteristics of the RC-IGBT.

[0106] The snapback observed in the current-voltage characteristics of the comparative example RC-IGBT900 is thought to be due to the discontinuous change in the amount of holes injected from the collector region 30 to the drift region 36 as the voltage increases.

[0107] Hole injection from the collector region 30 to the buffer region 34 and the drift region 36 originates from the wider portion of the collector region 30. + At the junction surface of the collector region 30 and buffer region 34, which is far from the cathode region 32, the influence of potential leakage due to the current flowing from the cathode region 32 is reduced due to the distance from the cathode region 32.

[0108] Therefore, the voltage difference between the collector region 30 and the buffer region 34 tends to become larger. Consequently, hole injection is more likely to occur at low collector voltages in the wider portion of the collector region 30.

[0109] In the comparative example RC-IGBT900, the wide first portion 30a is provided, which makes it easier for hole injection from the collector region 30 to the drift region 36 in the low-voltage region where the collector voltage is less than 1V. Therefore, in the comparative example RC-IGBT900, the occurrence of snapback in the low-voltage region where the collector voltage is less than 1V is suppressed.

[0110] On the other hand, as shown in Figure 8, in the comparative example RC-IGBT900, snapback is significantly observed in the region where the collector voltage is 1V or higher. This is thought to be because, in the collector region 30, which is far from the first portion 30a, the voltage difference between the collector region 30 and the buffer region 34 does not tend to become large, and hole injection from the collector region 30 to the drift region 36 is suppressed.

[0111] As shown in Figure 8, in the RC-IGBT100 of the first embodiment, snapback is suppressed in the collector voltage range of 1V or higher. This is thought to be due to the following reasons.

[0112] First, in the RC-IGBT100 of the first embodiment, a wider second portion 30b is provided in addition to the first portion 30a. The provision of the second portion 30b makes it easier for hole injection to occur in the second portion 30b. Therefore, the continuity of the hole injection amount from the collector region 30 to the drift region 36 with respect to the voltage increase is improved. Thus, the occurrence of snapback in the collector voltage region of 1V or more is suppressed.

[0113] Furthermore, in the RC-IGBT100 of the first embodiment, a third portion 30c is provided that connects the first portion 30a and the second portion 30b. In the low-voltage region where the collector voltage is less than 1V, hole injection occurs in the first portion 30a as described above. Subsequently, the hole injection generated in the first portion 30a propagates through the third portion 30c, making it easier for hole injection to occur in the second portion 30b. Therefore, the continuity of the hole injection amount from the collector region 30 to the drift region 36 with respect to the voltage increase is further improved. Thus, the occurrence of snapback in the region where the collector voltage is 1V or higher is further suppressed.

[0114] The third minimum width w3 of the third part 30c is multiple n +It is preferable that the distance d between the two nearest cathode regions 32 in the cathode region 32 of the shape is greater than the distance d between the two nearest cathode regions 32. Satisfying the above condition makes it easier for hole injection generated in the first portion 30a to propagate in the third portion 30c, and promotes hole injection in the second portion 30b. Therefore, the occurrence of snapback is further suppressed.

[0115] The third minimum width w3 of the third part 30c is multiple n + It is more preferable that the distance d between two cathode regions 32 located at the nearest neighbor position within the cathode region 32 of the shape be 1.2 times or more, even more preferable that it be 1.5 times or more, and most preferable that it be 2 times or more.

[0116] The second minimum width w2 of the second portion 30b is preferably 50% to 80% of the first minimum width w1 of the first portion 30a. When the second minimum width w2 is larger than the lower limit, hole injection in the second portion 30b becomes more likely, and the occurrence of snapback is further suppressed. Also, when the second minimum width w2 is smaller than the upper limit, the area ratio of the cathode region 32 on the second surface F2 increases, and the on current during diode operation increases.

[0117] The third minimum width w3 of the third portion 30c is preferably 20% to 60% of the second minimum width w2 of the second portion 30b. When the third minimum width w3 is larger than the lower limit, the propagation of hole injection generated in the first portion 30a to the third portion 30c becomes easier, and hole injection in the second portion 30b is promoted. Therefore, the occurrence of snapback is further suppressed. Also, when the third minimum width w3 is smaller than the upper limit, the area ratio of the cathode region 32 on the second surface F2 increases, and the on current during diode operation increases.

[0118] It is preferable that the fourth minimum width w4 of the cathode region 32 is smaller than the third minimum width w3 of the third portion 30c. Satisfying the above conditions increases the area ratio of the collector region 30 on the second surface F2, and increases the on-current during transistor operation.

[0119] In the first embodiment, the RC-IGBT100 is provided with a second portion 30b and a third portion 30c in the collector region 30 compared to the comparative example RC-IGBT900, in order to suppress snapback in the current-voltage characteristics. As a result, the area ratio of the cathode region 32 on the second surface F2 is reduced in the RC-IGBT100 of the first embodiment compared to the comparative example RC-IGBT900, which may reduce the on-current during diode operation.

[0120] The RC-IGBT100 of the first embodiment has a p-shaped first guard ring region 42 and n + By providing a peripheral cathode region 48, the on-current during diode operation is increased. As shown in Figure 6, the peripheral cathode region 48 is located directly below the first guard ring region 42. The first guard ring region 42 is electrically connected to the upper electrode 12.

[0121] Therefore, when the RC-IGBT100 operates as a diode, an on-current flows from the first guard ring region 42 through the drift region 36 to the peripheral cathode region 48. Consequently, the on-current increases during diode operation.

[0122] The p-type impurity concentration in the first guard ring region 42 is preferably higher than the p-type impurity concentration in the base region 38. A higher hole content in the first guard ring region 42 increases the hole injection efficiency from the first guard ring region 42 to the drift region 36 when the RC-IGBT 100 operates as a diode. Therefore, the on-current during diode operation increases further.

[0123] The p-type impurity concentration in the first guard ring region 42 is preferably twice or more than the p-type impurity concentration in the base region 38, and more preferably five times or more.

[0124] The depth of the first guard ring region 42 is preferably greater than the depth of the base region 38. A greater depth of the first guard ring region 42 and an increase in the amount of holes within the first guard ring region 42 increase the efficiency of hole injection from the first guard ring region 42 to the drift region 36 when the RC-IGBT 100 operates as a diode. Consequently, the on-current during diode operation increases further.

[0125] The depth of the first guard ring region 42 is preferably 1.2 times or more the depth of the base region 38, more preferably 1.5 times or more, and even more preferably 2 times or more.

[0126] The peripheral cathode region 48 is preferably located directly below the second guard ring region 44 and the third guard ring region 46. When the RC-IGBT 100 operates as a diode, it becomes possible to allow current to flow diagonally from the first guard ring region 42 to the peripheral cathode region 48 directly below the second guard ring region 44 and the third guard ring region 46. Therefore, the on-current during diode operation is further increased.

[0127] As described above, according to the first embodiment, it is possible to suppress the occurrence of snapback and suppress the deterioration of the operating characteristics of the RC-IGBT.

[0128] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the shape of the second semiconductor region is striped. Some descriptions that overlap with the first embodiment will be omitted below.

[0129] The semiconductor device of the second embodiment is an RC-IGBT200 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0130] Figure 9 is a schematic plan view of a semiconductor device according to the second embodiment. Figure 9 shows the pattern of the semiconductor region in the semiconductor layer on the second face side of the RC-IGBT200. Figure 9 corresponds to Figure 3 of the first embodiment.

[0131] n of RC-IGBT200 in the second embodiment + The cathode region 32 has a striped shape, as shown in Figure 9. The cathode region 32 extends, for example, in a first direction.

[0132] As described above, according to the second embodiment, similar to the first embodiment, it is possible to suppress the occurrence of snapback and suppress the deterioration of the operating characteristics of the RC-IGBT.

[0133] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that the third portion of the first semiconductor region extends parallel to the first or second direction. Hereafter, some descriptions that overlap with the first embodiment will be omitted.

[0134] The semiconductor device of the third embodiment is an RC-IGBT300 in which an IGBT and a freewheeling diode are formed on the same semiconductor chip.

[0135] Figure 10 is a schematic plan view of a semiconductor device according to the third embodiment. Figure 10 shows the pattern of the semiconductor region in the semiconductor layer on the second face side of the RC-IGBT300. Figure 10 corresponds to Figure 3 of the first embodiment.

[0136] In the third embodiment, the third portion 30c of the collector region 30 of the RC-IGBT300 extends parallel to the first or second direction.

[0137] As described above, according to the third embodiment, similar to the first embodiment, it is possible to suppress the occurrence of snapback and suppress the deterioration of the operating characteristics of the RC-IGBT.

[0138] In the first to third embodiments, the case where the semiconductor layer is single-crystal silicon was described as an example, but the semiconductor layer is not limited to single-crystal silicon. For example, it may be other single-crystal semiconductors such as single-crystal silicon carbide.

[0139] In the first to third embodiments, the case of a stripe shape in which trenches are arranged in parallel was described as an example, but the present invention can also be applied to a mesh shape trench in which trenches intersect, or to a dot shape trench.

[0140] In the first to third embodiments, the case of a trench-gate type IGBT in which the gate electrode is provided in a trench was described as an example, but the present invention can also be applied to the case of a planar-gate type IGBT in which the gate electrode is provided on the surface of a semiconductor layer.

[0141] In the first to third embodiments, the collector region 30 was described as including a first portion 30a, a second portion 30b, and a third portion 30c. However, it is also possible to configure the collector region 30 to further include a fourth portion whose minimum width is midway between the first minimum width w1 of the first portion 30a and the second minimum width w2 of the second portion 30b.

[0142] In the first to third embodiments, the first portion 30a and the second portion 30b of the collector area 30 were described as squares, but the shapes of the first portion 30a and the second portion 30b are not limited to squares; for example, they may be rectangular or circular. Furthermore, the arrangement patterns of the first portion 30a and the second portion 30b are not limited to the arrangement patterns of the first to third embodiments.

[0143] In the first to third embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type was described as an example, but it is also possible to have the first conductivity type be n-type and the second conductivity type be p-type.

[0144] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of symbols]

[0145] 10 Semiconductor layer 12 Upper electrode (first electrode) 14. Lower electrode (second electrode) 20 gates 22 Gate insulating film 30. Collector region (first semiconductor region) 30a Part 1 30b Second part 30c Third part 32. Cathode region (second semiconductor region) 36. Drift region (third semiconductor region) 38. Base region (fourth semiconductor region) 40. Emitter region (5th semiconductor region) 42. First guard ring region (sixth semiconductor region) 44. Second guard ring region (eighth semiconductor region) 48 Peripheral cathode region (7th semiconductor region) 100 RC-IGBT (Semiconductor Device) 200 RC-IGBT (Semiconductor Device) 300 RC-IGBT (Semiconductor Device) F1 First Side F2 Second side w1 First minimum width w2 Second minimum width w3 Third minimum width w4 The fourth minimum width

Claims

1. A semiconductor layer having a first surface and a second surface facing the first surface, A first semiconductor region of a first conductivity type provided within the semiconductor layer, in contact with the second surface, comprising: a plurality of first portions having a first minimum width; a plurality of second portions having a second minimum width smaller than the first minimum width; and a plurality of third portions connecting one of the plurality of first portions and one of the plurality of second portions, or two of the plurality of second portions, and having a third minimum width smaller than the second minimum width; A plurality of second semiconductor regions of a second conductivity type are provided within the semiconductor layer, in contact with the second surface, and spaced apart from each other within the first semiconductor region other than the plurality of first portions, the plurality of second portions, and the plurality of third portions, A third semiconductor region of a second conductivity type is provided within the semiconductor layer, between the first semiconductor region and the first surface and between the plurality of second semiconductor regions and the first surface, A fourth semiconductor region of a first conductivity type is provided within the semiconductor layer and is located between the third semiconductor region and the first surface, A fifth semiconductor region of a second conductivity type is provided within the semiconductor layer and is located between the fourth semiconductor region and the first surface, The gate electrode facing the semiconductor region of the fourth, A gate insulating film is provided between the fourth semiconductor region and the gate electrode, A first electrode in contact with the first surface, The second electrode in contact with the second surface, Equipped with, The third minimum width is greater than the distance between two second semiconductor regions that are in the nearest neighbor position among the plurality of second semiconductor regions. One of the plurality of third parts connects one of the plurality of first parts and one of the plurality of second parts, another of the plurality of third parts connects two of the plurality of second parts, and the one of the plurality of third parts and the other of the plurality of third parts intersect. A semiconductor device in which two first parts located in the nearest position among the plurality of first parts are connected to any one of the plurality of second parts by the third part.

2. The semiconductor device according to claim 1, wherein the second minimum width is 50% or more and 80% or less of the first minimum width.

3. The semiconductor device according to claim 1, wherein the third minimum width is 20% or more and 60% or less of the second minimum width.

4. The semiconductor device according to claim 1, wherein the second semiconductor region has a fourth minimum width, and the fourth minimum width is smaller than the third minimum width.

5. The semiconductor device according to claim 1, wherein the first electrode is electrically connected to the fourth semiconductor region and the fifth semiconductor region.

6. A sixth semiconductor region of a first conductivity type is provided within the semiconductor layer, between the first semiconductor region and the first surface, and surrounding the fourth semiconductor region on the first surface. A seventh semiconductor region of a second conductivity type is provided within the semiconductor layer, is in contact with the second surface, surrounds the first semiconductor region on the second surface, and is provided in a direction from the first surface toward the second surface relative to the sixth semiconductor region, The semiconductor device according to claim 1, further comprising the above.

7. The semiconductor device according to claim 6, wherein the first electrode is electrically connected to the sixth semiconductor region.

8. The semiconductor device according to claim 6, wherein the concentration of the first conductivity type impurity in the sixth semiconductor region is higher than the concentration of the first conductivity type impurity in the fourth semiconductor region.

9. The semiconductor device according to claim 6, wherein the depth of the sixth semiconductor region with respect to the first surface is deeper than the depth of the fourth semiconductor region with respect to the first surface.

10. The semiconductor layer further comprises an eighth semiconductor region of a first conductivity type, which is provided within the semiconductor layer, surrounds the sixth semiconductor region on the first surface, has the third semiconductor region between it and the sixth semiconductor region, and is electrically separated from the first electrode. The semiconductor device according to claim 7, wherein the seventh semiconductor region is provided with respect to the eighth semiconductor region in a direction from the first surface toward the second surface.

11. The semiconductor device according to claim 1, wherein the plurality of second semiconductor regions are arranged in a first direction or a second direction perpendicular to the first direction, and the plurality of third portions are oblique to the first direction and the second direction.

12. The semiconductor device according to claim 1, wherein two of the plurality of third parts intersect at their respective intermediate positions.

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