Systems, devices, and methods for scheduling metadata requests

Abstract

To provide a device and a method for scheduling a metadata request.SOLUTION: A device includes a memory and a scheduler. The scheduler is coupled to the memory and a memory controller. The memory stores a plurality of metadata requests. Each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels. The scheduler performs scheduling of transmission of a first metadata request among the plurality of metadata requests to the memory controller at least partly based on a first bandwidth portion of a metadata request bandwidth allocated to a first metadata priority level associated with the first metadata request and transmission of the metadata request to the memory controller. The first bandwidth portion of the metadata bandwidth is allocated to transmission of the metadata request associated with the first metadata priority level.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] Embodiments relate to data communication in a computer system.

Background Art

[0002] Computing platforms typically include multiple threads or cores. Data transactions generated by different cores often have different priority levels. Examples of data transactions include read data transactions and write data transactions. All data transactions are associated with metadata. Metadata typically includes auxiliary and / or secondary information about user code or data associated with the data transaction. An example of metadata includes security metadata including, but not limited to, memory safety tags, access permissions, memory encryption information, and integrity information. Metadata is often stored in an isolated portion of memory hosted by a memory controller.

Brief Description of the Drawings

[0003] [Figure 1] A block diagram representation of one embodiment of a system including a memory traffic scheduler.

[0004] [Figure 2] A block diagram representation of one embodiment of a memory traffic scheduler.

[0005] [Figure 3] A flowchart diagram of one embodiment of a method for sending a data transaction from a core to a memory traffic scheduler.

[0006] [Figure 4] A flowchart diagram of one embodiment of a method for placing a memory access request in a memory access request queue.

[0007] [Figure 5] This is a flowchart illustrating one embodiment of a method for scheduling the transmission of memory access requests to a memory controller.

[0008] [Figure 6] This is a diagram illustrating an example of one embodiment of a memory transaction scheduling queue that includes weighted metadata requests.

[0009] [Figure 7] This is a diagram illustrating an example of one embodiment of a memory transaction scheduling queue that includes weighted metadata requests.

[0010] [Figure 8] This is a flowchart illustrating one embodiment of a method for managing the transmission of data transactions from the core to the memory traffic scheduler.

[0011] [Figure 9] This is a flowchart illustrating one embodiment of a method for dynamically adjusting the allocation of metadata bandwidth for sending high-priority and low-priority metadata requests.

[0012] [Figure 10] This is a flowchart illustrating one embodiment of a method for managing the transmission of data transactions from the core to the memory traffic scheduler.

[0013] [Figure 11] This is a flowchart illustrating one embodiment of a method for scheduling metadata requests to a memory controller.

[0014] [Figure 12A] This block diagram shows a more specific example of an in-order core architecture. [Figure 12B] This block diagram shows a more specific example of an in-order core architecture.

[0015] [Figure 13] A block diagram of a processor that may have multiple cores, may have an integrated memory controller, and may have integrated graphics, according to an embodiment of the present invention.

[0016] [Figure 14] A block diagram of a first more specific and exemplary system according to an embodiment.

[0017] [Figure 15] A block diagram of a SoC according to an embodiment.

[0018] [Figure 16] A block diagram contrasting the use of a software instruction converter for converting binary instructions in a source instruction set to binary instructions in a target instruction set, according to an embodiment.

Best Mode for Carrying Out the Invention

[0019] When a certain core among multiple cores in a computing platform generates a data transaction, such as a read data transaction or a write data transaction, the data transaction can be associated with metadata. Metadata typically includes auxiliary and / or secondary information regarding user code or data associated with the data transaction. The metadata is stored in a memory hosted by a memory controller.

[0020] A computing platform may include a metadata cache associated with the memory controller and shared by the cores. The metadata cache is typically located near the memory controller and stores a subset of the metadata stored in memory. When user code and / or data access triggers access to metadata associated with a data transaction, the metadata is fetched from memory, and the fetched metadata is stored in the metadata cache. The metadata stored in the metadata cache is available to serve future requests for that metadata.

[0021] The memory traffic scheduler manages the scheduling of memory access requests to the memory controller. The memory controller retrieves data from memory according to these memory access requests. Memory access requests include read data transactions, write data transactions, and metadata requests.

[0022] Different data transactions are associated with different data transaction priority levels or quality of service (QoS) classes. Metadata associated with a data transaction inherits the data transaction priority level as its metadata priority level. When a data transaction is received from the core, the memory traffic scheduler checks whether the metadata associated with the data transaction exists in the metadata cache. If the metadata does not exist in the metadata cache, the memory traffic scheduler generates a metadata request to send to the memory controller to retrieve the metadata from memory. Based on the QoS class associated with the parent data transaction, the memory traffic scheduler determines whether the metadata request is a high-priority metadata request or a low-priority metadata request.

[0023] The memory traffic scheduler schedules the transmission of memory access requests to the memory controller by partitioning the memory bandwidth, also known as the memory access bandwidth, among different classes of memory traffic based on these priorities. The first portion of the memory access bandwidth is allocated to the transmission of read data transactions, the second portion is allocated to the transmission of write data transactions, and the third portion is allocated to the transmission of metadata requests. The portion of the memory access bandwidth allocated to the transmission of metadata requests is further divided into high-priority metadata bandwidth and low-priority metadata bandwidth. The high-priority metadata bandwidth is allocated to the transmission of high-priority metadata requests, and the low-priority metadata bandwidth is allocated to the transmission of low-priority metadata requests. The low-priority metadata bandwidth is less than the high-priority metadata bandwidth.

[0024] The memory traffic scheduler schedules the transmission of high-priority metadata requests based on the high-priority metadata bandwidth and the order in which the high-priority metadata requests arrive at the memory traffic scheduler, and schedules the transmission of low-priority metadata requests based on the low-priority metadata bandwidth and the order in which the low-priority metadata requests arrive at the memory traffic scheduler.

[0025] Referring to Figure 1, a block diagram representation of one embodiment of system 100 including a memory traffic scheduler 106 is shown. System 100 may be, for example, at least part of a server computer, desktop computer, or laptop computer. System 100 includes at least one core 102, a data cache 104, a memory traffic scheduler 106, a metadata cache 108, a memory controller 110, and memory 112. System 100 may include additional components that facilitate the operation of system 100. One configuration of system 100 is shown, but alternative embodiments may include alternative configurations of the system including the memory traffic scheduler 106.

[0026] Among other functions that can be performed by core 102, each core 102 is configured to generate data transactions. Examples of data transactions include read data transactions and write data transactions. In one embodiment, each core 102 is configured to generate data transactions that include data transaction priority tags. The data transaction priority tags associated with a data transaction define the data transaction priority level for that data transaction. In one embodiment, the data transaction priority levels include high data transaction priority levels and low data transaction priority levels. In an alternative embodiment, the data transaction priority levels may include additional data transaction priority levels.

[0027] In one embodiment, each of the cores 102 is configured to generate data transactions having a specific data transaction priority level. The core identifier of each core 102 is associated with a specific data transaction priority level. In one embodiment, the system 100 may include two cores 102, where the first of the two cores 102 is configured to generate data transactions having a high data transaction priority level, and the second of the two cores 102 is configured to generate data transactions having a low data transaction priority level. The core identifier of the first core 102 is associated with data transactions having a high data transaction priority level, and the second core identifier of the second core 102 is associated with data transactions having a low data transaction priority level. Although one embodiment including two cores 102 and two data transaction priority levels has been described, alternative embodiments may include two or more cores and two or more data transaction priority levels.

[0028] One or more cores 102 are communicatively coupled to a data cache 104. The data cache 104 stores a subset of the data stored in memory 112. When a core 102 generates a read data transaction, the data is fetched from memory 112. The fetched data is stored in the data cache 104 and is available for future requests for the data in future read data transactions generated by one of the cores 102.

[0029] The memory traffic scheduler 106 is communicatively coupled to one or more cores 102. In one embodiment, the memory traffic scheduler 106 is communicatively coupled to one or more cores 102 via a data cache 104. The memory traffic scheduler 106 is communicatively coupled to a memory controller 110 and a metadata cache 108. The memory controller 110 is communicatively coupled to a memory 112. The memory 112 is hosted by the memory controller 110.

[0030] In one embodiment, each read data transaction is associated with metadata. In one embodiment, some of the read data transactions are associated with metadata. In one embodiment, each write data transaction is associated with metadata. In one embodiment, some of the write data transactions are associated with metadata. In one embodiment, each data transaction, including read and write data transactions, is associated with metadata. In one embodiment, some of the data transactions are associated with metadata. The metadata includes auxiliary and / or secondary information about user code or data associated with the data transaction. Examples of metadata include, but are not limited to, security metadata, which includes memory safety tags, access permissions, memory cryptographic information, and integrity information. In one embodiment, the metadata is stored in an isolated portion of memory 112.

[0031] The metadata cache 108 is configured to store a subset of the metadata stored in memory 112. In one embodiment, the metadata cache 108 is located near the memory traffic scheduler 106. In one embodiment, the metadata cache 108 is located near the memory controller 110. The metadata cache 108 is shared by the core 102. When access to user code and / or data triggers access to metadata associated with a data transaction, the memory traffic scheduler 106 is configured to schedule the transmission of a metadata request to the memory controller 112. The memory controller 110 is configured to fetch the metadata from memory 112. The fetched metadata is stored in the metadata cache 108 and is available to serve future requests for that metadata.

[0032] The memory traffic scheduler 106 is configured to schedule memory access requests for transmission to the memory controller 110. These memory access requests include read data transactions, write data transactions, and metadata requests. The memory traffic scheduler 106 is configured to send these memory access requests to the memory controller 110 by partitioning a memory bandwidth, also referred to as the memory request access bandwidth, among different classes of memory traffic. For example, the memory request access bandwidth includes the read data transaction bandwidth, the write data transaction bandwidth, and the metadata bandwidth. The memory traffic scheduler 106 is configured to allocate read data transaction bandwidth for the transmission of read data transactions, write data transaction bandwidth for the transmission of write data transactions, and metadata bandwidth for the transmission of metadata requests. In one embodiment, the memory traffic scheduler 106 is configured to schedule the transmission of write data transactions by the write data transaction bandwidth in the order in which the write data transactions were received by the memory traffic scheduler 106, and to schedule the transmission of read data transactions by the read data transaction bandwidth in the order in which the read data transactions were received by the memory traffic scheduler 106.

[0033] Metadata bandwidth includes high-priority metadata bandwidth and low-priority metadata bandwidth. In one embodiment, metadata bandwidth is partitioned into high-priority metadata bandwidth and low-priority metadata bandwidth. The memory traffic scheduler 106 is configured to allocate high-priority metadata bandwidth for sending high-priority metadata requests and low-priority metadata bandwidth for sending low-priority metadata requests. The low-priority metadata bandwidth is typically less than the high-priority metadata bandwidth. In one embodiment, the memory traffic scheduler 106 is configured to schedule the transmission of high-priority metadata requests based on the high-priority metadata bandwidth and the order in which the high-priority metadata requests were received by the memory traffic scheduler 106, and to schedule the transmission of low-priority metadata requests based on the low-priority metadata bandwidth and the order in which the low-priority metadata requests were received by the memory traffic scheduler 106.

[0034] In one embodiment, the portion of metadata bandwidth designated as high-priority metadata bandwidth and the portion designated as low-priority metadata bandwidth are defined by the user. In one embodiment, the portion of metadata bandwidth designated as high-priority metadata bandwidth and the portion designated as low-priority metadata bandwidth are dynamically adjusted based on the portion of metadata request that is a high-priority metadata request and the portion of metadata request that is a low-priority metadata request. In one embodiment, each high-priority metadata request may be associated with a high-priority sublevel, and each low-priority metadata request may be associated with a low-priority sublevel. The high bandwidth of high-priority metadata may be partitioned into multiple high-priority sublevel metadata bandwidths, in which case each high-priority sublevel metadata bandwidth is allocated to the transmission of metadata requests associated with the same associated metadata high-priority sublevel. Similarly, the high bandwidth of low-priority metadata may be partitioned into multiple low-priority sublevel metadata bandwidths, in which case each low-priority sublevel metadata bandwidth is allocated to the transmission of metadata requests associated with the same associated metadata low-priority sublevel. In an alternative embodiment, the metadata bandwidth may include two or more metadata priority level bandwidths, in which case each metadata priority bandwidth is allocated to the transmission of metadata requests having a particular metadata priority level.

[0035] In one embodiment, the read data transaction bandwidth includes high-priority read data transaction bandwidth and low-priority read data transaction bandwidth. In one embodiment, the read data transaction bandwidth is partitioned into high-priority read data transaction bandwidth and low-priority read data transaction bandwidth. The memory traffic scheduler 106 is configured to allocate high-priority read data transaction bandwidth for sending high-priority read data transactions and low-priority read data transaction bandwidth for sending low-priority read data transactions. The low-priority read data transaction bandwidth is typically less than the high-priority read data transaction bandwidth. In one embodiment, the memory traffic scheduler 106 is configured to schedule the transmission of high-priority read data transactions based on the high-priority read data transaction bandwidth and the order in which the high-priority read data transactions were received by the memory traffic scheduler 106, and to schedule the transmission of low-priority read data transactions based on the low-priority read data transaction bandwidth and the order in which the low-priority read data transactions were received by the memory traffic scheduler 106.

[0036] In one embodiment, the portion of the read data transaction bandwidth designated as high-priority read data transaction bandwidth and the portion designated as low-priority read data transaction bandwidth are defined by the user. In one embodiment, the portion of the read data transaction bandwidth designated as high-priority read data transaction bandwidth and the portion designated as low-priority read data transaction bandwidth are dynamically adjusted based on the portion of the read data transaction that is a high-priority read data transaction and the portion of the read data transaction that is a low-priority read data transaction. In an alternative embodiment, the read data transaction bandwidth may include two or more read data transaction priority level bandwidths, in which case each read data transaction priority bandwidth is allocated to the transmission of a read data transaction having a particular read data transaction priority level.

[0037] In one embodiment, the write data transaction bandwidth includes high-priority write data transaction bandwidth and low-priority write data transaction bandwidth. In one embodiment, the write data transaction bandwidth is partitioned into high-priority write data transaction bandwidth and low-priority write data transaction bandwidth. The memory traffic scheduler 106 is configured to allocate high-priority write data transaction bandwidth for sending high-priority write data transactions and low-priority write data transaction bandwidth for sending low-priority write data transactions. The low-priority write data transaction bandwidth is typically less than the high-priority write data transaction bandwidth. In one embodiment, the memory traffic scheduler 106 is configured to schedule the transmission of high-priority write data transactions based on the high-priority write data transaction bandwidth and the order in which the high-priority write data transactions were received by the memory traffic scheduler 106, and to schedule the transmission of low-priority write data transactions based on the low-priority write data transaction bandwidth and the order in which the low-priority write data transactions were received by the memory traffic scheduler 106.

[0038] In one embodiment, the portion of the write data transaction bandwidth designated as high-priority write data transaction bandwidth and the portion designated as low-priority write data transaction bandwidth are defined by the user. In one embodiment, the portion of the write data transaction bandwidth designated as high-priority write data transaction bandwidth and the portion designated as low-priority write data transaction bandwidth are dynamically adjusted based on the portion of the write data transaction that is a high-priority write data transaction and the portion of the write data transaction that is a low-priority write data transaction. In an alternative embodiment, the write data transaction bandwidth may include two or more write data transaction priority level bandwidths, in which case each write data transaction priority bandwidth is allocated to the transmission of a write data transaction having a particular write data transaction priority level.

[0039] When the memory controller 110 receives a memory request from the memory traffic scheduler 106, it retrieves the data requested in the memory request from the memory 112.

[0040] Referring to Figure 2, a block diagram representation of one embodiment of the memory traffic scheduler 106 is shown. The memory traffic scheduler 106 includes a scheduler 200 which is communicatively coupled to the scheduler memory 202. The memory traffic scheduler 106 may include additional components that facilitate the operation of the memory traffic scheduler 106. The scheduler 200 schedules the transmission of memory access requests to the memory controller 110. Memory access requests include read data transactions, write data transactions, and metadata requests. In one embodiment, metadata requests include high-priority metadata requests and low-priority metadata requests. In an alternative embodiment, metadata requests may include metadata requests associated with additional metadata priority levels.

[0041] In one embodiment, the scheduler memory 202 includes a plurality of memory access request queues. In one embodiment, the memory access request queues in the scheduler memory 202 include a read data transaction queue 204, a write data transaction queue 206, a high-priority metadata request queue 208, and a low-priority metadata request queue 210. In one embodiment, the read data transaction queue 204, the write data transaction queue 206, the high-priority metadata request queue 208, and the low-priority metadata request queue 210 are first-in, first-out (FIFO) queues. In an alternative embodiment, the scheduler memory 202 may include additional metadata request queues, each of which is associated with metadata requests having additional metadata priority levels.

[0042] When the scheduler 200 receives a read data transaction from core 102, it is configured to place the read data transaction in the read data transaction queue 204. When the scheduler 200 receives a write data transaction from core 102, it is configured to place the write data transaction in the write data transaction queue 206. If the scheduler 200 determines that there is metadata associated with the received data transaction and that this metadata is not available in the metadata cache 108, the scheduler 200 is configured to determine whether the metadata associated with the data transaction is high-priority metadata or low-priority metadata. If the scheduler 200 determines that the metadata is high-priority metadata, it is configured to generate a high-priority metadata request for the high-priority metadata and place the high-priority metadata request in the high-priority metadata request queue 208. If the scheduler 200 determines that the metadata is low-priority metadata, it is configured to generate a low-priority metadata request for the low-priority metadata and place the low-priority metadata request in the low-priority metadata request queue 210.

[0043] The scheduler 200 schedules the transmission of individual read data transactions based on the read data transaction bandwidth and the position of the read data transaction in the read data transaction queue 204. The scheduler 200 schedules the transmission of individual write data transactions based on the write data transaction bandwidth and the position of the write data transaction in the write data transaction queue 206. The scheduler 200 schedules the transmission of individual high-priority metadata requests based on the high-priority metadata bandwidth and the position of the high-priority metadata requests in the high-priority metadata request queue 208. The scheduler 200 schedules the transmission of individual low-priority metadata requests based on the low-priority metadata bandwidth and the position of the low-priority metadata requests in the low-priority metadata request queue 210. The low-priority metadata bandwidth is typically lower than the high-priority metadata bandwidth.

[0044] In one embodiment, the scheduler 200 is configured to send a memory access request to the memory controller 110 when the memory access request is pulled from the associated memory access request queue. In one embodiment, the scheduler memory 202 includes a metadata transaction schedule queue 212. The scheduler 202 is configured to place the scheduled memory access request into the metadata transaction schedule queue 212 when the memory access request is scheduled.

[0045] In one embodiment, the scheduler memory may include two or more high-priority sublevel metadata queues and two or more low-priority sublevel metadata queues. Each high-priority metadata request may be associated with a high-priority sublevel, and each low-priority metadata request may be associated with a low-priority sublevel. High-priority metadata requests associated with a particular high-priority sublevel are placed in the high-priority sublevel metadata queue associated with the same particular high-priority sublevel. Similarly, low-priority metadata requests associated with a particular low-priority sublevel are placed in the low-priority sublevel metadata queue associated with the same particular low-priority sublevel.

[0046] In one embodiment, the scheduler memory may include a high-priority read data transaction queue and a low-priority read data transaction queue. When the scheduler receives a read data transaction from the core, it is configured to determine whether the read data transaction is a high-priority read data transaction or a low-priority read data transaction. If the scheduler determines that the read data transaction is a high-priority read data transaction, it is configured to place the high-priority read data transaction in the high-priority read data transaction queue. If the scheduler determines that the read data transaction is a low-priority read data transaction, it is configured to place the low-priority read data transaction in the low-priority read data transaction queue.

[0047] In one embodiment, the scheduler memory may include a high-priority write data transaction queue and a low-priority write data transaction queue. Upon receiving a write data transaction from a core, the scheduler is configured to determine whether the write data transaction is a high-priority write data transaction or a low-priority write data transaction. If the scheduler determines that the write data transaction is a high-priority write data transaction, it is configured to place the high-priority write data transaction in the high-priority write data transaction queue. If the scheduler determines that the write data transaction is a low-priority write data transaction, it is configured to place the low-priority write data transaction in the low-priority write data transaction queue.

[0048] Referring to Figure 3, a flowchart of one embodiment of method 300 for sending data transactions from core 102 to memory traffic scheduler 106 is shown. Method 300 is performed when core 102 generates data transactions. Method 300 may be performed by core 102 in combination with additional components of system 100. Method 300 may be performed by hardware circuitry, firmware, software, and / or a combination thereof.

[0049] In step 302, core 102 generates a data transaction. In step 304, core 102 determines whether the data associated with the data transaction exists in the data cache 104. If core 102 determines that the data associated with the data transaction exists in the data cache 104, in step 306, core 102 retrieves the data from the data cache 104. If core 102 determines that the data associated with the data transaction does not exist in the data cache 104, in step 308, core 102 sends the data transaction to the memory traffic scheduler 106. Method 300 is shown at a high level in Figure 3, and it should be understood that many variations and alternatives to Method 300 are possible.

[0050] Referring to Figure 4, a flowchart of one embodiment of method 400 for placing memory access requests into the memory access request queue is shown. Method 400 is executed when the memory traffic scheduler 106 receives a data transaction from the core 102. Method 400 may be executed by the memory traffic scheduler 106 in combination with additional components of the system 100. Method 400 may be executed by hardware circuitry, firmware, software, and / or a combination thereof.

[0051] In step 402, the memory traffic scheduler 106 receives the data transaction. In step 404, the memory traffic scheduler 106 determines whether the data transaction is a read data transaction. If the memory traffic scheduler 106 determines that the data transaction is not a read data transaction, in step 406, the memory traffic scheduler 106 determines that the data transaction is a write data transaction and places the write data transaction in the write data transaction queue. If the memory traffic scheduler 106 determines that the data transaction is a read data transaction, in step 408, the memory traffic scheduler 106 places the read data transaction in the read data transaction queue 204.

[0052] In 410, the memory traffic scheduler 106 determines whether metadata associated with a data transaction exists in the metadata cache 108. In one embodiment, the memory traffic scheduler 106 determines whether metadata associated with a data transaction exists in the metadata cache 108 only if the data transaction is a read data transaction. In one embodiment, the memory traffic scheduler 106 determines whether metadata associated with a data transaction exists in the metadata cache 108 only if the data transaction is a write data transaction. In one embodiment, the memory traffic scheduler 106 determines whether metadata associated with a data transaction exists in the metadata cache 108 for both read and write data transactions.

[0053] If the memory traffic scheduler 106 determines that metadata associated with a data transaction exists in the metadata cache 108, in step 412, the memory traffic scheduler 106 retrieves the metadata from the metadata cache 108. If the memory traffic scheduler 106 determines that metadata associated with a data transaction does not exist in the metadata cache 108, in step 414, the memory traffic scheduler 106 generates a metadata request for the metadata.

[0054] The memory traffic scheduler 106 identifies the metadata priority level for a metadata request in 416. In one embodiment, a data transaction includes a data transaction priority tag. The data transaction priority tag defines the data transaction priority level for the data transaction. In one embodiment, the data transaction priority level includes a high data transaction priority level and a low data transaction priority level. In an alternative embodiment, the data transaction priority level may include additional data transaction priority levels. The metadata priority level for a metadata request is inherited from the data transaction priority level of the associated data transaction. The memory traffic scheduler 106 identifies the metadata priority level for a metadata request in 416 as the data transaction priority level associated with the data transaction.

[0055] In one embodiment, a data transaction includes a core identifier associated with the core 102 that generated the data transaction. Each core 102 is configured to generate data transactions having a specific data transaction priority level. The core identifier of a core 102 is associated with a specific data transaction priority level. In one embodiment, the data transaction priority levels include high and low data transaction priority levels. In an alternative embodiment, the data transaction priority levels may include additional data transaction priority levels. The metadata priority level for a metadata request is inherited from the data transaction priority level of the associated data transaction. The memory traffic scheduler 106 identifies the data transaction priority level for a data transaction based on the core identifier in the data transaction. In 416, the memory traffic scheduler 106 identifies the metadata priority level for a metadata request as the data transaction priority level associated with the data transaction.

[0056] In step 418, the memory traffic scheduler 106 places the metadata request into the metadata request queue associated with the identified metadata priority level for the metadata request. If the memory traffic scheduler 106 identifies the metadata priority level for the metadata request as a high metadata priority level, the metadata request is a high-priority metadata request, and the memory traffic scheduler 106 places the high-priority metadata request into the high-priority metadata request queue 208. If the memory traffic scheduler 106 identifies the metadata priority level for the metadata request as a low metadata priority level, the metadata request is a low-priority metadata request, and the memory traffic scheduler 106 places the low-priority metadata request into the low-priority metadata request queue 210.

[0057] Method 400 is demonstrated at a high level in Figure 4, and it should be understood that many variations and alternatives to Method 400 are possible.

[0058] Referring to Figure 5, a flowchart of one embodiment of method 500 for scheduling the transmission of memory access requests to the memory controller 110 is shown. Method 500 is performed by the memory traffic scheduler 106 when it schedules the transmission of memory access requests to the memory controller 110. Memory access requests include read data transactions, write data transactions, and metadata requests. Method 500 may be performed by the memory traffic scheduler 106 in combination with additional components of the system 100. Method 500 may be performed by hardware circuitry, firmware, software, and / or a combination thereof.

[0059] In 502, the memory traffic scheduler 106 schedules the transmission of write data transactions from the write data transaction queue 206. The memory traffic scheduler 106 is configured to send memory access requests to the memory controller 110 by partitioning the memory access request bandwidth. The memory access request bandwidth includes the read data transaction bandwidth, the write data transaction bandwidth, and the metadata bandwidth. The memory traffic scheduler 106 is configured to allocate the write data transaction bandwidth to the transmission of write data transactions. In one embodiment, the write data transaction bandwidth is one-third of the memory access request bandwidth. The memory traffic scheduler 106 schedules the transmission of write data transactions based on the write data transaction bandwidth and the position of the write data transaction in the write data transaction queue 206. In one embodiment, the write data transaction queue 206 is a FIFO queue. By using a FIFO queue as the write data transaction queue 206, the memory traffic scheduler 106 can schedule the transmission of write data transactions in the order in which they are received by the memory traffic scheduler 106.

[0060] In 504, the memory traffic scheduler 106 schedules the transmission of read data transactions from the read data transaction queue 204. The memory traffic scheduler 106 is configured to allocate read data transaction bandwidth to the transmission of read data transactions. In one embodiment, the read data transaction bandwidth is one-third of the memory access request bandwidth. The memory traffic scheduler 106 schedules the transmission of read data transactions based on the read data transaction bandwidth and the position of the read data transaction in the read data transaction queue 204. In one embodiment, the read data transaction queue 204 is a FIFO queue. By using a FIFO queue as the read data transaction queue 204, the memory traffic scheduler 106 can schedule the transmission of read data transactions in the order in which they were received by the memory traffic scheduler 106.

[0061] In 506, the memory traffic scheduler 106 determines whether a sequence of metadata requests scheduled from the high-priority metadata request queue 208 is equal to a low-priority metadata weight. In one embodiment, low-priority metadata requests are assigned a low-priority metadata weight. In one embodiment, the low-priority metadata weight is provided by the user. The low-priority metadata weight defines a sequence of high-priority metadata requests that the memory traffic scheduler 106 schedules to send to the memory controller 110 before scheduling the sending of the low-priority metadata requests to the memory controller 110.

[0062] If the memory traffic scheduler 106 determines that a sequentially numbered metadata request scheduled from the high-priority metadata request queue 208 is not equal to a low-priority metadata weight, then in 508, the memory traffic scheduler 106 schedules the transmission of the high-priority metadata request from the high-priority metadata request queue 208. The memory traffic scheduler 106 is configured to allocate metadata bandwidth for the transmission of the metadata request. The metadata bandwidth includes high-priority metadata bandwidth and low-priority metadata bandwidth. The low-priority metadata weight defines the allocation of a portion of the metadata bandwidth as high-priority metadata bandwidth and the allocation of a portion of the metadata bandwidth as low-priority metadata bandwidth. The memory traffic scheduler 106 is configured to allocate high-priority metadata bandwidth for the transmission of the high-priority metadata request. The memory traffic scheduler 106 schedules the transmission of the high-priority metadata request based on the high-priority metadata bandwidth as defined by the low-priority metadata weight and the position of the high-priority metadata request in the high-priority metadata request queue 208. In one embodiment, the high-priority metadata request queue 208 is a FIFO queue. By using a FIFO queue as the high-priority metadata request queue 208, the memory traffic scheduler 106 can schedule the transmission of high-priority metadata requests in the order in which they are generated by the memory traffic scheduler 106.

[0063] Method 500 further returns to 502 by having the memory traffic scheduler 106 schedule the transmission of the next write data transaction from the write data transaction queue 206, thereby implementing a round-robin scheme. The round-robin scheme includes scheduling the transmission of write data transactions, followed by read data transactions, and then metadata requests. While a specific order for scheduling the transmission of write data transactions, read data transactions, and metadata requests is described, alternative embodiments may schedule the transmission of write data transactions, read data transactions, and metadata requests in a different order.

[0064] If the memory traffic scheduler 106 determines that a sequentially numbered metadata request scheduled from the high-priority metadata request queue 208 is equal to the low-priority metadata weight, the memory traffic scheduler 106 schedules the transmission of the low-priority metadata request from the low-priority metadata request queue 210. As described above, the low-priority metadata weight defines the allocation of a portion of the metadata bandwidth as high-priority metadata bandwidth and the allocation of a portion of the metadata bandwidth as low-priority metadata bandwidth. The memory traffic scheduler 106 is configured to allocate the low-priority metadata bandwidth to the transmission of the low-priority metadata request. The memory traffic scheduler 106 schedules the transmission of the low-priority metadata request based on the low-priority metadata bandwidth as defined by the low-priority metadata weight and the position of the low-priority metadata request in the low-priority metadata request queue 210. In one embodiment, the low-priority metadata request queue 210 is a FIFO queue. By using a FIFO queue as the low-priority metadata request queue 210, the memory traffic scheduler 106 is able to schedule the transmission of low-priority metadata requests in the order in which they are generated by the memory traffic scheduler 106. Method 500 then returns to 502, where the memory traffic scheduler 106 schedules the transmission of the next write data transaction in the write data transaction queue 206.

[0065] It should be understood that Method 500 is demonstrated at a high level in Figure 5, and that many variations and alternatives to Method 500 are possible.

[0066] Referring to Figure 6, an example 600 of one embodiment of a memory transaction scheduling queue 212 including weighted metadata requests is shown. The memory traffic scheduler 106 is configured to place scheduled memory access requests into the metadata transaction scheduling queue 212 once each individual memory access request is scheduled. The memory access request includes a write data transaction W, a read data transaction R, a high-priority metadata request MH, and a low-priority metadata request ML. Each cycle 1-18 represents a memory access request transmission cycle. The memory access request bandwidth is divided into three equal bandwidths: the write data transaction bandwidth, the read data transaction bandwidth, and the metadata bandwidth.

[0067] The memory traffic scheduler 106 schedules the transmission of individual write data transactions W based on the write data transaction bandwidth and the position of write data transaction W in the write data transaction queue 206, and schedules the transmission of individual read data transactions R based on the read data transaction bandwidth and the position of read data transaction R in the read data transaction queue 204. The memory traffic scheduler 106 schedules write data transactions W, then read data transactions R, then metadata requests MH / ML, and repeats the sequence according to the division of memory access request bandwidth and a round-robin method.

[0068] In the illustrated example, the low-priority metadata weight has a value of 2. The metadata bandwidth is divided into high-priority metadata bandwidth and low-priority metadata bandwidth according to the value of the low-priority metadata weight. Since the low-priority metadata weight has a value of 2, the memory traffic scheduler 106 schedules two consecutive high-priority metadata requests MH from the high-priority metadata request queue 208, followed by a low-priority metadata request ML from the low-priority metadata request queue 210, according to the metadata bandwidth division, and repeats the metadata request scheduling sequence.

[0069] The memory traffic scheduler 106 schedules the transmission of individual high-priority metadata requests MH based on the high-priority metadata bandwidth and the position of high-priority metadata requests MH in the high-priority metadata request queue 208, and schedules the transmission of individual low-priority metadata requests ML based on the low-priority metadata bandwidth and the position of low-priority metadata requests ML in the low-priority metadata request queue 210.

[0070] Referring to Figure 7, an example 700 of one embodiment of a memory transaction scheduling queue 212 including weighted metadata requests is shown. The memory traffic scheduler 106 is configured to place scheduled memory access requests into the metadata transaction scheduling queue 212 once each individual memory access request is scheduled. The memory access request includes a write data transaction W, a read data transaction R, a high-priority metadata request MH, and a low-priority metadata request ML. Each cycle 1-18 represents a memory access request transmission cycle. The memory access request bandwidth is divided into three equal bandwidths: the write data transaction bandwidth, the read data transaction bandwidth, and the metadata bandwidth.

[0071] The memory traffic scheduler 106 schedules the transmission of individual write data transactions W based on the write data transaction bandwidth and the position of the write data transaction in the write data transaction queue 206, and schedules the transmission of individual read data transactions R based on the read data transaction bandwidth and the position of the read data transaction R in the read data transaction queue 204. The memory traffic scheduler 106 schedules write data transactions W, then read data transactions R, then metadata requests MH / ML, and repeats the sequence according to the division and round-robin method of the memory access request bandwidth.

[0072] In the illustrated example, the low-priority metadata weight has a value of 4. The metadata bandwidth is divided into high-priority metadata bandwidth and low-priority metadata bandwidth according to the value of the low-priority metadata weight. Since the low-priority metadata weight has a value of 4, the memory traffic scheduler 106 schedules four consecutive high-priority metadata requests MH from the high-priority metadata request queue 208, followed by low-priority metadata requests ML from the low-priority metadata request queue 210, according to the metadata bandwidth division, and repeats the metadata request scheduling sequence.

[0073] The memory traffic scheduler 106 schedules the transmission of individual high-priority metadata requests MH based on the high-priority metadata bandwidth and the position of high-priority metadata requests MH in the high-priority metadata request queue 208, and schedules the transmission of individual low-priority metadata requests ML based on the low-priority metadata bandwidth and the position of low-priority metadata requests ML in the low-priority metadata request queue 210.

[0074] In an alternative embodiment, metadata bandwidth is associated with the metadata request transmission repetition cycle. The metadata traffic scheduler 106 allocates the first portion of the metadata request transmission repetition cycle to the transmission of low-priority metadata requests and the second portion to the transmission of high-priority metadata requests. Scheduling requests from the low-priority metadata request queue at regular intervals over a fixed period can prevent starvation of low-priority workloads.

[0075] Referring to Figure 8, a flowchart of one embodiment of method 800 for managing the transmission of data transactions from core 102 to memory traffic scheduler 106 is shown. Method 800 is performed by the memory traffic scheduler 106 to manage the transmission of data transactions from core 102 to the memory traffic scheduler 106 using a credit-based feedback system. Method 800 may be performed by the memory traffic scheduler 106 in combination with additional components of system 100. Method 800 may be performed by hardware circuitry, firmware, software, and / or a combination thereof.

[0076] In one embodiment, one of a plurality of cores 102 is responsible for generating data transactions associated with low-priority metadata requests. In 802, the memory traffic scheduler 106 determines the amount of space available in the low-priority metadata request data queue 210. In 804, the memory traffic scheduler 106 identifies one of the plurality of cores 102 responsible for generating data transactions associated with metadata requests having a low metadata priority level. In 806, the memory traffic scheduler 106 sends several credits associated with the amount of space available in the low-priority metadata request queue 210 to the identified core 102. The core 102 uses the number of credits received from the memory traffic scheduler 106 to determine the number of data transactions that the core 102 is permitted to send to the memory traffic scheduler 106. The memory traffic scheduler 106 periodically executes method 800 to periodically provide the core 102 with the updated number of credits. It should be understood that Method 800 is demonstrated at a high level in Figure 8, and that many variations and alternatives to Method 800 are possible.

[0077] Referring to Figure 9, a flowchart of one embodiment of method 900 for dynamically adjusting the allocation of metadata bandwidth for sending high-priority metadata requests and low-priority metadata requests is shown. Method 900 is performed by a memory traffic scheduler 106 to dynamically adjust the division of metadata bandwidth into high-priority and low-priority metadata bandwidths. Method 900 may be performed by the memory traffic scheduler 106 in combination with additional components of the system 100. Method 900 may be performed by hardware circuitry, firmware, software, and / or a combination thereof.

[0078] In step 902, the memory traffic scheduler 106 determines whether the number of high-priority metadata requests in the high-priority metadata request queue 208 is below the bandwidth throttling threshold. When the number of high-priority metadata requests in the high-priority metadata request queue 208 is below the bandwidth throttling threshold, the memory traffic scheduler 106 may not be able to efficiently utilize metadata bandwidth for sending metadata requests.

[0079] If the memory traffic scheduler 106 determines that the number of high-priority metadata requests in the high-priority metadata request queue 208 is below the bandwidth adjustment threshold, the memory traffic scheduler 106 increases the portion of the metadata bandwidth designated as low-priority metadata bandwidth in 904, while decreasing the portion designated as high-priority metadata bandwidth. This allows the memory traffic scheduler 106 to efficiently utilize metadata bandwidth for sending metadata requests to the memory controller 110.

[0080] If the memory traffic scheduler 106 determines that the number of high-priority metadata requests in the high-priority metadata request queue 208 is not below the bandwidth adjustment threshold, the memory traffic scheduler 106 maintains the current allocation of metadata bandwidth to high-priority metadata bandwidth and low-priority metadata bandwidth in 906. The memory traffic scheduler 106 periodically executes method 900 to dynamically adjust the allocation of metadata bandwidth to high-priority metadata bandwidth and low-priority metadata bandwidth. It should be understood that method 900 is shown at high level in Figure 9, and that many variations and alternatives to method 900 are possible.

[0081] Referring to Figure 10, a flowchart of one embodiment of method 1000 for managing the transmission of data transactions from core 102 to memory traffic scheduler 106 is shown. Method 1000 is performed by the memory traffic scheduler 106 to manage the transmission of data transactions from core 102 to the memory traffic scheduler 106. Method 1000 may be performed by the memory traffic scheduler 106 in combination with additional components of system 100. Method 1000 may be performed by hardware circuitry, firmware, software, and / or a combination thereof.

[0082] In one embodiment, one of the multiple cores 102 is responsible for generating data transactions associated with low-priority metadata requests. In 1002, the memory traffic scheduler 106 determines whether the number of low-priority metadata requests generated by the memory traffic scheduler 106 is greater than the core throttling threshold. If the memory traffic scheduler 106 determines that the number of low-priority metadata requests generated by the memory traffic scheduler 106 is greater than the core throttling threshold, the memory traffic scheduler 106 identifies in 1004 one of the multiple cores 102 responsible for generating data transactions associated with metadata requests having a low metadata priority level.

[0083] The memory traffic scheduler 106 sends a core throttling request to the identified core 102 at 1006. Upon receiving the core throttling request, core 102 reduces the number of low-priority metadata requests generated by the memory traffic scheduler 106 by limiting the number of data transactions that core 102 sends to the memory traffic scheduler 106.

[0084] If the memory traffic scheduler 106 determines that the number of low-priority metadata requests generated by the memory traffic scheduler 106 is not greater than the core throttling threshold, then no further action is taken by 1008. The memory traffic scheduler 106 periodically executes method 1000. It should be understood that method 1000 is shown at high level in Figure 10, and that many variations and alternatives to method 1000 are possible.

[0085] Referring to Figure 11, a flowchart of one embodiment of method 1100 for scheduling metadata requests to the memory controller 110 is shown. Method 1100 is performed by the memory traffic scheduler 106 to manage the transmission of metadata requests from the memory traffic scheduler 106 to the memory controller 110. Method 1100 may be performed by the memory traffic scheduler 106 in combination with additional components of the system 100. Method 1100 may be performed by hardware circuitry, firmware, software, and / or a combination thereof.

[0086] As described above, the metadata bandwidth is divided into high-priority metadata bandwidth and low-priority metadata bandwidth according to the value of the low-priority metadata weight. For example, if the low-priority metadata weight has a value of X, the memory traffic scheduler 106 schedules consecutive high-priority metadata requests for X from the high-priority metadata request queue 208, and then low-priority metadata requests from the low-priority metadata request queue 210, and repeats the metadata request scheduling sequence. If the high-priority metadata request queue 208 is empty, the memory traffic scheduler 106 may not be able to schedule a high-priority metadata request in one of the consecutive high-priority metadata request slots for X, and the high-priority metadata request slot becomes unused. Similarly, if the low-priority metadata request queue 210 is empty, the memory traffic scheduler 106 may not be able to schedule a low-priority metadata request in one of the low-priority metadata request slots after consecutive high-priority metadata request slots for X, and the low-priority metadata request slot becomes unused. Method 1100 attempts to fill empty metadata request slots when either the request queue for high-priority metadata queue 208 is empty or the request queue for low-priority metadata queue 210 is empty.

[0087] In step 1102, the memory traffic scheduler 106 determines whether one of the high-priority metadata request queues 208 or low-priority metadata request queues 210 is empty. If the memory traffic scheduler 106 determines that one of the high-priority metadata request queues 208 or low-priority metadata request queues 210 is empty, in step 1104, the memory traffic scheduler 106 schedules the transmission of metadata requests from the other of the high-priority metadata request queues 208 or low-priority metadata request queues 210 using the available metadata request slots. If the memory traffic scheduler 106 determines that one of the high-priority metadata request queues 208 or low-priority metadata request queues 210 is not empty, in step 1106, the memory traffic scheduler 106 maintains the transmission of metadata requests according to the lower metadata priority weights. It should be understood that method 1100 is shown at a high level in Figure 11, and that many variations and alternatives to method 1100 are possible.

[0088] Implementing a Quality of Service (QoS) scheme to manage the transmission of high-priority and low-priority metadata requests based on the allocation of high-priority metadata bandwidth for high-priority metadata requests and low-priority metadata bandwidth for low-priority metadata requests can ensure that a workload that does not function properly on a given core / thread does not adversely impact the performance of other workloads coexisting on the platform. The QoS scheme may rely on limiting the allocation rate to the metadata cache by limiting the memory bandwidth available for metadata lookups based on the class of service associated with the metadata request. The QoS associated with the metadata request corresponds to the metadata priority level associated with the metadata request.

[0089] To implement QoS for the metadata cache, system 100 may rely on handling memory traffic corresponding to metadata requests based on a weighted metadata priority scheduling scheme. Metadata requests inherit the QoS service parameters of their parent data transactions and are scheduled based on these priorities instead of a simple first-in, first-out (FIFO) scheme. This contributes to improving the performance of higher-priority threads by indirectly controlling the proportion of lower-priority threads that allocate entries to the metadata cache, i.e., the proportion that could potentially pollute it.

[0090] The metadata traffic scheduler 106 maintains separate metadata request queues based on the QoS of the parent read / write data transactions. This can ensure that metadata requests from high-priority workloads take precedence over those from low-priority workloads.

[0091] In an alternative embodiment, a leaky bucket implementation can be used to precisely partition the available bandwidth between metadata queues (or even all queues) by revealing traffic bursts and their priorities. In another embodiment, the memory traffic scheduler 106 may allocate a fixed percentage of the available metadata bandwidth to each class of service. In an alternative embodiment, the memory traffic scheduler 106 may also maintain separate queues for each QoS class for read data transactions and write data transactions.

[0092] Figure 12A is a block diagram showing both an exemplary in-order pipeline and an exemplary register-renaming out-of-order issue / execution pipeline according to embodiments of the present invention. Figure 12B is a block diagram showing both an exemplary embodiment of an in-order architecture core and an exemplary register-renaming out-of-order issue / execution architecture core included in a processor according to embodiments of the present invention. In Figures 12A and 12B, boxes enclosed by solid lines indicate in-order pipelines and in-order cores, while any additional dashed boxes indicate register-renaming out-of-order issue / execution pipelines and cores. The out-of-order configuration will be described assuming that the in-order configuration is a subset of the out-of-order configuration.

[0093] In Figure 12A, the processor pipeline 1200 includes a fetch stage 1202, a length decode stage 1204, a decode stage 1206, an allocation stage 1208, a renaming stage 1210, a scheduling stage 1212 (also known as dispatch or issue), a register read / memory read stage 1214, an execution stage 1216, a write-back / memory write stage 1218, an exception handling stage 1222, and a commit stage 1224. Note that in a given embodiment, as described herein, the core may include multiple processing pipelines such as pipeline 1200.

[0094] Figure 12B shows a processor core 1290, which includes a front-end unit 1230 coupled to an execution engine unit 1250, both of which are coupled to a memory unit 1270. Core 1290 may be a reduced instruction set computing (RISC) core, a composite instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. Further options include a special-purpose core such as a network or communications core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, or a graphics core.

[0095] The front-end unit 1230 includes a branch prediction unit 1232 coupled to an instruction cache unit 1234, the instruction cache unit 1234 coupled to an instruction translation lookaside buffer (TLB) 1236, the instruction translation lookaside buffer 1236 coupled to an instruction fetch unit 1238, and the instruction fetch unit 1238 coupled to a decode unit 1240. The decode unit 1240 (or decoder) decodes instructions and may generate microcode entry points, microinstructions, other instructions, or other control signals as the output of one or more microoperations, which are decoded from the original instructions, or otherwise reflected in or derived therefrom. The decode unit 1240 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), and microcode read-only memory (ROM). In one embodiment, the core 1290 includes a microcode ROM or other medium for storing microcode for specific macro instructions (for example, in the decode unit 1240, or otherwise in the front-end unit 1230). The decode unit 1240 is coupled to a renaming / allocator unit 1252 in the execution engine unit 1250.

[0096] The execution engine unit 1250 includes a renaming / allocator unit 1252 coupled to a retirement unit 1254, and a set of one or more scheduler units 1256. The scheduler units 1256 represent any number of different schedulers, including reserved stations, a central instruction window, etc. The scheduler units 1256 are coupled to a physical register file unit 1258. Each of the physical register file units 1258 represents one or more physical register files, these different ones storing one or more different data types, such as scalar integers, scalar floating-point numbers, packed integers, packed floating-point numbers, vector integers, vector floating-point numbers, status (e.g., an instruction pointer, which is the address of the next instruction to be executed). In one embodiment, the physical register file unit 1258 includes a vector register unit, a write mask register unit, and a scalar register unit. These register units may provide architecture vector registers, vector mask registers, and general-purpose registers. The physical register file unit 1258 overlaps with the retirement unit 1254 to show various ways in which register renaming and out-of-order execution can be performed (e.g., using a reorder buffer and retirement register file, using a future file, history buffer and retirement register file, using a register map and register pool, etc.). The retirement unit 1254 and the physical register file unit 1258 are joined to an execution cluster 1260. The execution cluster 1260 includes a set of one or more execution units 1262 and a set of one or more memory access units 1264. The execution units 1262 can perform various operations (e.g., shift, add, subtract, multiply) on various types of data (e.g., scalar floating-point, packed integer, packed floating-point, vector integer, vector floating-point).Some embodiments may include several execution units dedicated to a particular function or set of functions, while other embodiments may include only one execution unit, or multiple execution units, all of which perform all functions. The scheduler unit 1256, the physical register file unit 1258, and the execution cluster 1260 are shown as having multiple possibilities because a particular embodiment results in the creation of separate pipelines for a particular type of data / operation (e.g., a scalar integer pipeline, a scalar floating-point / packed integer / packed floating-point / vector integer / vector floating-point pipeline, and / or memory access pipeline, each having its own scheduler unit, physical register file unit, and / or execution cluster, and in the case of a separate memory access pipeline, a particular embodiment will implement where only the execution cluster of this pipeline has the memory access unit 1264). It should also be understood that, where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution, while the rest may be in-order.

[0097] The set of memory access units 1264 is also coupled to a memory unit 1270, which includes a data TLB unit 1272 coupled to a data cache unit 1274, which is coupled to a level 2 (L2) cache unit 1276. In one exemplary embodiment, the memory access unit 1264 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 1272 in the memory unit 1270. The instruction cache unit 1234 is further coupled to the level 2 (L2) cache unit 1276 in the memory unit 1270. The L2 cache unit 1276 is coupled to one or more other levels of cache and ultimately to main memory.

[0098] As an example, an exemplary register renaming out-of-order issue / execution core architecture may implement pipeline 1200 as follows: 1) Instruction fetch 1238 executes fetch stage 1202 and length decode stage 1204; 2) Decode unit 1240 executes decode stage 1206; 3) Renaming / allocator unit 1252 executes allocation stage 1208 and renaming stage 1210; 4) Scheduler unit 1256 executes scheduling stage 1212. 5) The physical register file unit 1258 and the memory unit 1270 execute the register read / memory read stage 1214, the execution cluster 1260 executes the execution stage 1216, 6) the memory unit 1270 and the physical register file unit 1258 execute the write-back / memory write stage 1218, 7) various units may be included in the exception handling stage 1222, and 8) the retirement unit 1254 and the physical register file unit 1258 execute the commit stage 1224.

[0099] The Core 1290 may support one or more instruction sets (e.g., the x86 instruction set (with several extensions, including newer versions), the MIPS instruction set from MIPS Technology, Sunnyvale, California, and the ARM instruction set (with optional additional extensions, such as NEON from ARM Holding, Sunnyvale, California)), including the instructions described herein. In one embodiment, the Core 1290 includes logic to support packed data instruction set extensions (e.g., AVX1, AVX2), enabling it to perform operations used by many multimedia applications using packed data.

[0100] It should be understood that a core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in various ways, including time-sliced ​​multithreading, concurrent multithreading (where one physical core provides a logical core to each of the threads that the physical core multithreads simultaneously), or a combination thereof (e.g., time-sliced ​​fetch and decode followed by concurrent multithreading, such as Intel®'s Hyper-Threading technology).

[0101] While register renaming is described in the context of out-of-order execution, it should be understood that register renaming can also be used in in-order architectures. The shown embodiment of the processor also includes separate instruction and data cache units 1234 / 1274 and a shared L2 cache unit 1276, but alternative embodiments may have a single internal cache for both instructions and data, such as a level 1 (L1) internal cache or multiple levels of internal caches. In some embodiments, the system may include a combination of internal caches and external caches located outside the core and / or processor. Alternatively, all caches may be located outside the core and / or processor.

[0102] Figure 13 is a block diagram of a processor 1300 according to an embodiment of the present invention, which may have multiple cores, an integrated memory controller, and integrated graphics. The solid box in Figure 13 shows a processor 1300 having a single core 1302A, a system agent 1310, and a set of one or more bus controller units 1316, while the optionally added dashed box shows an alternative processor 1300 having multiple cores 1302A-N, a set of one or more integrated memory controller units in the system agent unit 910, and dedicated logic 1308.

[0103] Therefore, different implementations of the processor 1300 may include: 1) a CPU having dedicated logic 1308 which is integrated graphics and / or scientific (throughput) logic (which may include one or more cores), and cores 1302A-N which are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of the two); 2) a coprocessor having cores 1302A-N which are a large number of application-specific cores mainly for graphics and / or scientific (throughput); and 3) a coprocessor having cores 1302A-N which are a large number of general-purpose in-order cores. Therefore, the processor 1300 may be a general-purpose processor, coprocessor, or dedicated processor, such as a network or communications processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), or an embedded processor. The processor may be implemented on one or more chips. The processor 1300 may be part of one or more substrates and / or may be mounted on one or more substrates using one of several process technologies, such as BiCMOS, CMOS, or NMOS.

[0104] The memory hierarchy includes one or more levels of cache units 1304A-N within the core, one or more sets of shared cache units 1306, and external memory (not shown) coupled to a set of integrated memory controller units 1314. The set of shared cache units 1306 may include one or more mid-level caches such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of caches, a last-level cache (LLC), and / or a combination thereof. In one embodiment, a ring-based interconnection unit 1312 interconnects dedicated logic 1308, the set of shared cache units 1306, and the system agent unit 1310 / integrated memory controller unit 1314, but in alternative embodiments, any number of known techniques for interconnecting such units may be used. In one embodiment, coherency is maintained between one or more cache units 1306 and the cores 1302A-N.

[0105] The system agent unit 1310 includes components that coordinate and operate the cores 1302A-N. The system agent unit 1310 may include, for example, a power control unit (PCU) and a display unit. The PCU may include, or may include, the logic and components necessary to regulate the power state of the cores 1302A-N and dedicated logic 1308. The display unit is for driving one or more externally connected displays.

[0106] Cores 1302A-N can be homogeneous or heterogeneous in terms of their architectural instruction sets; that is, two or more cores 1302A-N may be able to execute the same instruction set, while others may be able to execute only a subset of this instruction set or a different instruction set.

[0107] Figures 14-15 are block diagrams of exemplary computer architectures. Other system designs and configurations known in the art for laptops, desktops, handheld PCs, personal digital assistants, engineering workstations, servers, network devices, network hubs, switches, embedded processors, digital signal processors (DSPs), graphics devices, video game devices, set-top boxes, microcontrollers, mobile phones, portable media players, handheld devices, and various other electronic devices are also suitable. Generally, a variety of systems or electronic devices capable of incorporating processors and / or other execution logic as disclosed herein are generally preferred.

[0108] Referring now to Figure 14, a block diagram of a first more specific and exemplary system 1400 according to one embodiment of the present invention is shown. As shown in Figure 14, the multiprocessor system 1400 is a point-to-point interconnection system and includes a first processor 1470 and a second processor 1480 coupled via a point-to-point interconnection 1450. Each of the processors 1470 and 1480 may be a version of processor 1400.

[0109] Processors 1470 and 1480 are shown, each including an Integrated Memory Controller (IMC) unit 1472 and 1482, respectively. Processor 1470 also includes point-to-point (P-P) interfaces 1476 and 1478 as part of this bus controller unit, and similarly, the second processor 1480 includes P-P interfaces 1486 and 1488. Processors 1470 and 1480 can exchange information via point-to-point (PP) interface 1450 using PP interface circuits 1478 and 1488. As shown in Figure 14, the IMCs 1472 and 1482 connect the processors to their respective memories, i.e., memories 1432 and 1434, which may be portions of main memory locally attached to their respective processors.

[0110] Processors 1470 and 1480 may exchange information with chipset 1490 via individual P-P interfaces 1452 and 1454 using point-to-point interface circuits 1476, 1494, 1486, and 1498, respectively. Chipset 1490 may optionally exchange information with coprocessor 1438 via high-performance interface 1439. In one embodiment, coprocessor 1438 is a dedicated processor such as a high-throughput MIC processor, a network or communications processor, a compression engine, a graphics processor, a GPGPU, or an embedded processor.

[0111] The (not shown) shared cache may be located outside of either processor or both processors, still connected to the processors via a P-P interconnect, and local cache information of either or both processors may be stored in the shared cache when the processor is put into low-power mode.

[0112] The chipset 1490 may be coupled to the first bus 1416 via interface 1496. In one embodiment, the first bus 1416 may be a Peripheral Components Interconnect (PCI) bus, or a PCI Express bus or another third-generation I / O interconnect bus, but the scope of the present invention is not limited in that way.

[0113] As shown in Figure 14, various I / O devices 1414 may be coupled to the first bus 1416 together with a bus bridge 1418 that connects the first bus 1416 to the second bus 1420. In one embodiment, one or more additional processors 1415, such as a coprocessor, a high-throughput MIC processor, a GPGPU accelerator (such as a graphics accelerator or digital signal processing (DSP) unit), a field-programmable gate array, or any other processor, are coupled to the first bus 1416. In one embodiment, the second bus 1420 may be a low-pin-count (LPC) bus. In one embodiment, various devices, such as a keyboard and / or mouse 1422, a communication device 1427, and a storage unit 1428, such as a disk drive or other mass storage device that may contain instructions / code and data 1430, may be coupled to the second bus 1420. Furthermore, audio I / O 1424 may be coupled to the second bus 1420. It should be noted that other architectures are possible. For example, instead of the point-to-point architecture in Figure 14, the system could implement a multidrop bus or other such architecture.

[0114] Referring now to Figure 15, a block diagram of SoC 1500 according to one embodiment of the present invention is shown. Dashed boxes represent optional features for a more advanced SoC. In Figure 15, the interconnection unit 1502 is coupled to an application processor 1510 including one or more sets of cores 1502A-N (including configuration cache units 1504A-N) and a shared cache unit 1506, a system agent unit 1510, a bus controller unit 1516, an integrated memory controller unit 1514, one or more coprocessors 1520 which may include integrated graphics logic, an image processor, an audio processor, and a video processor, a static random access memory (SRAM) unit 1530, a direct memory access (DMA) unit 1532, and a display unit 1540 for coupling to one or more external displays. In one embodiment, the coprocessors 1520 include dedicated processors such as a network or communications processor, a compression engine, a GPGPU, a high-throughput MIC processor, or an embedded processor.

[0115] Embodiments of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Embodiments of the present invention may be implemented as a computer program or program code that runs on a programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0116] Program code such as code 1430 shown in Figure 14 may be applied to input instructions to perform the functions described herein and generate output information. The output information may be applied to one or more output devices in known manner. For the purposes of this application, the processing system includes any system having a processor such as a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.

[0117] The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with the processing system. The program code may also be implemented in assembly language or machine code, as needed. In practice, the mechanisms described herein are not limited to any particular programming language. In any case, the language may be a compiled language or an interpreted language.

[0118] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium representing various logic within a processor, which, when read by a machine, cause the machine to generate logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that actually produce logic or processors.

[0119] Such machine-readable storage media may include, but are not limited to, any other type of disk including hard disks, floppy disks, optical disks, compact disk read-only memory (CD-ROM), rewritable compact disks (CD-RW), and magneto-optical disks; semiconductor devices such as read-only memory (ROM); random access memory (RAM) such as dynamic random access memory (DRAM) and static random access memory (SRAM); erasable programmable read-only memory (EPROM); flash memory; electrically erasable programmable read-only memory (EEPROM); phase-change memory (PCM); magnetic or optical cards; or other types of media suitable for storing electronic instructions; and may include non-temporary tangible structures of articles manufactured or formed by machines or devices.

[0120] Accordingly, embodiments of the present invention also include non-temporary, tangible, machine-readable media containing instructions or design data, such as a hardware description language (HDL), which defines structures, circuits, devices, processors, and / or system functions as described herein. Such embodiments may also be referred to as program products.

[0121] In some cases, instruction converters may be used to translate instructions from a source instruction set to a target instruction set. For example, an instruction converter may translate, morph, emulate, or otherwise transform an instruction into one or more other instructions that can be processed by the core (e.g., using static binary translation, dynamic binary translation including dynamic compilation). Instruction converters can be implemented in software, hardware, firmware, or a combination of these. An instruction converter may reside in the processor, be detached from the processor, or be part of the processor and detached from the processor.

[0122] Figure 16 is a block diagram illustrating the use of a software instruction converter to translate binary instructions in a source instruction set to binary instructions in a target instruction set, according to an embodiment of the present invention. In the shown embodiment, the instruction converter is a software instruction converter, but alternatively, the instruction converter may be implemented in software, firmware, hardware, or various combinations thereof. Figure 16 shows that a program in high-level language 1602 may be compiled using an x86 compiler 1604 to produce x86 binary code 1606 that can be executed natively by a processor on at least one x86 instruction set core 1616. A processor having at least one x86 instruction set core 1616 represents any processor capable of performing multiple functions that are substantially the same as those of an Intel® processor having at least one x86 instruction set core, by (1) running or otherwise processing a large portion of the instruction set of an Intel® x86 instruction set core, or (2) running an object code version of an application or other software intended to run on an Intel® processor having at least one x86 instruction set core, in order to achieve substantially the same results as an Intel® processor having at least one x86 instruction set core. An x86 compiler 1604 represents a compiler capable of generating x86 binary code 1606 (e.g., object code) that is executable on a processor having at least one x186 instruction set core 1616, with or without additional linkage processing.Similarly, Figure 16 shows that a program in high-level language 1602 can be compiled using an alternative instruction set compiler 1608 to generate alternative instruction set binary code 1610 that can be natively executed by a processor 1614 that lacks at least one x86 instruction set core (e.g., a processor with cores that run the MIPS instruction set from MIPS Technology, Sunnyvale, California, and / or the ARM instruction set from ARM Holding, Sunnyvale, California). An instruction converter 1612 is used to convert the x86 binary code 1606 into code that can be natively executed by the processor 1614 that lacks an x86 instruction set core. The converted code may not be identical to the alternative instruction set binary code 1610 because it is difficult to manufacture an instruction converter capable of doing so, but the converted code will achieve the general operation and will construct instructions from the alternative instruction set. Therefore, the instruction converter 1612 represents software, firmware, hardware, or a combination thereof that enables a processor or other electronic device without an x86 instruction set processor or core to execute the x86 binary code 1606 by emulation, simulation, or any other process.

[0123] The following examples relate to further embodiments.

[0124] In one example, the device includes a memory for storing a plurality of metadata requests, each of which metadata requests is associated with one of a plurality of metadata priority levels, and a scheduler coupled to the memory and the memory controller, the scheduler scheduling the transmission of a first metadata request of the plurality of metadata requests to the memory controller on at least a portion of a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth allocated to the transmission of the metadata request to the memory controller, the first bandwidth portion of the metadata bandwidth being allocated to the transmission of the metadata request associated with the first metadata priority level.

[0125] In one example, the scheduler receives a first data transaction associated with a first data transaction priority level for transmission to the memory controller, determines whether the metadata associated with the first data transaction is available in the metadata cache, and, based on the determination, generates a first metadata request associated with the metadata so that it has a first metadata priority level inherited from the first data transaction priority level.

[0126] In one example, the scheduler receives a first data transaction containing a data transaction priority tag associated with a first data transaction priority level, and generates a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, the first metadata priority level being inherited from the first data transaction priority level.

[0127] For example, the scheduler receives a first data transaction from a first core among multiple cores, the first core being associated with a first core priority level, and generates a first metadata priority level to associate with a first metadata request for metadata associated with the first data transaction, the first metadata priority level being inherited from the first core priority level.

[0128] In one example, the memory further includes multiple metadata request queues, each of which is associated with one of multiple metadata priority levels, and the scheduler generates a first metadata request associated with a first metadata priority level, places the first metadata request into a first metadata request queue associated with the first metadata priority level, and schedules the transmission of the first metadata request to the memory controller based at least partially on the position of the first metadata request in the first metadata request queue.

[0129] In one example, the scheduler identifies a first core among several cores responsible for generating data transactions associated with metadata requests having a first metadata priority level, generates bandwidth availability data associated with a first bandwidth portion of the metadata bandwidth, and sends the bandwidth availability data to the first core so that the first core can manage several data transactions sent to the device based on the bandwidth availability data.

[0130] In one example, the scheduler compares some metadata requests among several metadata requests associated with a first metadata priority level with a bandwidth adjustment threshold, and then dynamically adjusts the first bandwidth portion of the metadata bandwidth based on the comparison.

[0131] In one example, the scheduler determines whether some of the metadata requests among several metadata requests associated with a first metadata priority level exceed a core throttling threshold, that the first metadata priority level is a low priority level, and based on this determination, identifies a first core among several cores responsible for generating data transactions associated with the metadata requests having the first metadata priority level, and sends a data transaction throttling request to the first core.

[0132] In one example, each of several metadata priority levels is associated with a metadata priority level weight, and the scheduler allocates a first portion of the metadata bandwidth to metadata requests associated with a first metadata priority level, based at least in part on the first metadata priority level weight associated with that first metadata priority level.

[0133] In one example, the memory includes at least two metadata request queues, each of which is associated with one of several metadata priority levels, and the scheduler further generates a first metadata request associated with a first metadata priority level, places the first metadata request into a first metadata request queue associated with the first metadata priority level, and schedules the transmission of the first metadata request to the memory controller based at least partially on the position of the first metadata request in the first metadata request queue.

[0134] In one example, the scheduler determines whether multiple metadata requests include another metadata request associated with a first metadata priority level, and based on that determination, schedules the transmission of a second metadata request of the multiple metadata requests to the memory controller using the bandwidth of the first portion of the metadata bandwidth, wherein the second metadata request has a second metadata priority level among the multiple metadata priority levels.

[0135] In one example, the scheduler schedules the transmission of a second metadata request among a group of metadata requests to the memory controller based at least partially on a second metadata priority level associated with the second metadata request and a second bandwidth portion of the metadata request bandwidth, wherein the second bandwidth portion is allocated to the transmission of metadata requests associated with the second metadata priority level, and the first bandwidth portion of the metadata bandwidth is scheduled to be less than the second bandwidth portion of the metadata bandwidth, based at least partially on the first metadata priority level being lower than the second metadata priority level.

[0136] In one example, a machine-readable medium contains stored instructions, and when executed by a machine, the instructions cause the machine to receive a plurality of data transactions in a memory traffic scheduler, each of which data transactions is associated with a transaction receive time and a data transaction priority level; generate a plurality of metadata requests in the memory traffic scheduler, each of which metadata requests is associated with one of the plurality of data transactions and a metadata priority level among a plurality of metadata priority levels inherited from the data transaction priority level of one of the plurality of data transactions; and schedule the transmission of a first metadata request among a plurality of metadata requests associated with a first data transaction to a memory controller, at least partially based on a first metadata priority level associated with the first metadata request, a first receive time associated with the first data transaction, and a first bandwidth portion of the metadata request bandwidth allocated for the transmission of the metadata request to the memory controller, the first bandwidth portion of the metadata bandwidth being allocated for the transmission of the metadata request associated with the first metadata priority level.

[0137] In one example, the machine-readable medium includes an instruction causing the machine to schedule the transmission of a second metadata request among a plurality of metadata requests associated with a second data transaction to a memory controller, at least in part on a second metadata priority level associated with the second metadata request, a second time associated with the second data transaction, and a second bandwidth portion of the metadata request bandwidth allocated to the transmission of the metadata request associated with the second metadata priority level, wherein the first bandwidth portion of the metadata bandwidth is less than the second bandwidth portion of the metadata bandwidth, at least in part on the first metadata priority level being lower than the second metadata priority level.

[0138] In one example, the machine-readable medium includes instructions that cause the machine to associate each of a plurality of metadata priority levels with a metadata priority level weight, and to allocate a first bandwidth portion of the metadata bandwidth to the metadata request associated with the first metadata priority level, at least in part, on the first metadata priority level weight associated with the first metadata priority level.

[0139] In one example, the system includes multiple cores, a memory controller, a metadata cache, and a memory traffic scheduler coupled to the multiple cores, the memory controller, and the metadata cache. The memory traffic scheduler stores multiple metadata requests, each of which is associated with one of multiple metadata priority levels, and schedules the transmission of a first metadata request among the multiple metadata requests to the memory controller based at least partially on the first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth allocated to the transmission of the metadata request to the memory controller, the first bandwidth portion of the metadata bandwidth being allocated to the transmission of the metadata request associated with the first metadata priority level.

[0140] In one example, the memory traffic scheduler stores a plurality of read data transactions, each of which is associated with one of a plurality of read data transaction priority levels, and schedules the transmission of the first of the plurality of read data transactions to the memory controller based at least partially on the first read data transaction priority level associated with the first read data transaction and a first bandwidth portion of the read data transaction bandwidth allocated to the transmission of the read data transaction to the memory controller, wherein the first bandwidth portion of the read data transaction bandwidth is allocated to the transmission of the read data transaction associated with the first read data transaction priority level.

[0141] In one example, the memory traffic scheduler stores a plurality of write data transactions, each of which is associated with one of a plurality of write data transaction priority levels, and schedules the transmission of a write data transaction from the plurality of write data transactions to the memory controller, at least partially based on a first write data transaction priority level associated with a first write data transaction and a first bandwidth portion of the write data transaction bandwidth allocated to the transmission of the write data transaction to the memory controller, wherein the first bandwidth portion of the write data transaction bandwidth is allocated to the transmission of the write data transaction associated with the first write data transaction priority level.

[0142] In one example, the memory traffic scheduler includes at least two metadata request queues, each of which is associated with one of several metadata priority levels, and the memory traffic scheduler generates a first metadata request associated with a first metadata priority level, places the first metadata request into a first metadata request queue associated with the first metadata priority level, and schedules the transmission of the first metadata request to the memory controller based at least partially on the position of the first metadata request in the first metadata request queue.

[0143] In one example, the memory traffic scheduler includes a read data transaction queue and a write data transaction queue, and the memory traffic scheduler further schedules the transmission of a first read data transaction from the read data transaction queue to the memory controller based at least partially on the position of the first read data transaction in the read data transaction queue and the read data transaction bandwidth, and schedules the transmission of a first write data transaction from the write data transaction queue to the memory controller based at least partially on the position of the first write data transaction in the write data transaction queue and the write data transaction bandwidth.

[0144] It should be noted that the terms “circuit” and “circuitry” are used interchangeably herein. As used herein, these terms and the term “logic” are used alone or in any combination to refer to analog circuits, digital circuits, hardwired circuits, programmable circuits, processor circuits, microcontroller circuits, hardware logic circuits, state-machine circuits, and / or any other type of physical hardware component. Embodiments can be used in many different types of systems. For example, in one embodiment, a communication device can be configured to perform various methods and techniques described herein. Naturally, the scope of the invention is not limited to communication devices, and instead, other embodiments may cover other types of devices for processing instructions, or one or more machine-readable media containing instructions that cause a device to perform one or more of the methods and techniques described herein in response to being executed on a computing device.

[0145] Embodiments may be implemented in code and stored on a non-temporary storage medium on which instructions are stored, and the non-temporary storage medium may be used to program a system for executing instructions. Embodiments may also be implemented in data and, when used by at least one machine, may be stored on a non-temporary storage medium that causes at least one machine to create at least one integrated circuit for performing one or more operations. In addition, further embodiments may be implemented on a computer-readable storage medium that, when made into a product of an SoC or other processor, contains information that configures the SoC or other processor to perform one or more operations. Storage media may include, but are not limited to, any type of disk, including floppy disks, optical disks, solid-state drives (SSDs), compact disk read-on memory (CD-ROMs), rewritable compact disks (CD-RWs), and magneto-optical disks; semiconductor devices such as read-on memory (ROMs); random access memory (RAMs) such as dynamic random access memory (DRAMs) and static random access memory (SRAMs); erasable programmable read-on memory (EPROMs); flash memory; electrically erasable programmable read-on memory (EEPROMs); magnetic or optical cards; or any other type of media suitable for storing electronic instructions.

[0146] Although the present invention has been described in relation to a limited number of embodiments, those skilled in the art will recognize many modifications and variations therefrom. The appended claims are intended to encompass all such modifications and variations that fall within the true spirit and scope of the invention. [Other adjacent items] (Item 1) A memory for storing multiple metadata requests, each of which is associated with one of a plurality of metadata priority levels, A device comprising a memory and a memory controller, the scheduler which schedules the transmission of a first metadata request of a plurality of metadata requests to the memory controller on at least partially a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth allocated for the transmission of the metadata request to the memory controller, wherein the first bandwidth portion of the metadata bandwidth is allocated for the transmission of metadata requests associated with the first metadata priority level. (Item 2) The apparatus according to item 1, wherein the scheduler further receives a first data transaction associated with a first data transaction priority level for transmission to the memory controller, determines whether metadata associated with the first data transaction is available in the metadata cache, and generates the first metadata request associated with the metadata so as to have a first metadata priority level inherited from the first data transaction priority level based on the determination. (Item 3) The apparatus according to item 1, wherein the scheduler further receives a first data transaction including a data transaction priority tag associated with a first data transaction priority level, and generates a first metadata priority level for associating with the first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first data transaction priority level. (Item 4) The apparatus according to item 1, wherein the scheduler further receives a first data transaction from a first core among a plurality of cores, the first core being associated with a first core priority level, and generates a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, the first metadata priority level being inherited from the first core priority level. (Item 5) The apparatus according to item 1, wherein the memory further comprises a plurality of metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the scheduler further generates the first metadata request associated with the first metadata priority level, places the first metadata request into the first metadata request queue associated with the first metadata priority level, and schedules the transmission of the first metadata request to the memory controller based at least partially on the position of the first metadata request in the first metadata request queue. (Item 6) The apparatus according to item 1, wherein the scheduler further identifies a first core among a plurality of cores responsible for generating data transactions associated with metadata requests having the first metadata priority level, generates bandwidth availability data associated with the first bandwidth portion of the metadata bandwidth, and transmits the bandwidth availability data to the first core so that the first core can manage several data transactions sent to the apparatus based on the bandwidth availability data. (Item 7) The apparatus according to item 1, wherein the scheduler further compares some of the plurality of metadata requests associated with the first metadata priority level with a bandwidth adjustment threshold, and dynamically adjusts the first bandwidth portion of the metadata bandwidth based on the comparison. (Item 8) The apparatus according to item 1, wherein the scheduler further determines whether some of the plurality of metadata requests associated with the first metadata priority level exceed a core throttling threshold, that the first metadata priority level is a low priority level, and identifies a first core among a plurality of cores responsible for generating data transactions associated with the metadata requests having the first metadata priority level, and sends a data transaction throttling request to the first core based on the determination. (Item 9) The apparatus according to item 1, wherein each of the plurality of metadata priority levels is associated with a metadata priority level weight, and the scheduler further allocates the first bandwidth portion of the metadata bandwidth to metadata requests associated with the first metadata priority level based at least in part on the first metadata priority level weight associated with the first metadata priority level. (Item 10) The apparatus according to item 1, wherein the memory includes at least two metadata request queues, each of the at least two metadata request queues being associated with one of the plurality of metadata priority levels, and the scheduler further generates the first metadata request associated with the first metadata priority level, places the first metadata request into the first metadata request queue associated with the first metadata priority level, and schedules the transmission of the first metadata request to the memory controller based at least partially on the position of the first metadata request in the first metadata request queue. (Item 11) The apparatus according to item 1, further comprising the scheduler determining whether the plurality of metadata requests include another metadata request associated with the first metadata priority level, and scheduling the transmission of a second metadata request of the plurality of metadata requests to the memory controller using the bandwidth of the first bandwidth portion of the metadata bandwidth based on the determination, wherein the second metadata request has a second metadata priority level among the plurality of metadata priority levels. (Item 12) The apparatus according to item 1, wherein the scheduler further schedules the transmission of a second metadata request among the plurality of metadata requests to the memory controller based at least in part on a second metadata priority level associated with the second metadata request and a second bandwidth portion of the metadata request bandwidth, wherein the second bandwidth portion is allocated to the transmission of metadata requests associated with the second metadata priority level, and the first bandwidth portion of the metadata bandwidth is less than the second bandwidth portion of the metadata bandwidth based at least in part on the first metadata priority level being lower than the second metadata priority level. (Item 13) This includes stored instructions, and if the instructions are to be executed by the machine, the machine will be given the following: Receiving multiple data transactions in a memory traffic scheduler, each of which is associated with a transaction reception time and a data transaction priority level, The memory traffic scheduler generates a plurality of metadata requests, each of which is associated with one of the plurality of data transactions and a metadata priority level among a plurality of metadata priority levels inherited from the data transaction priority level of one of the plurality of data transactions, and A machine-readable medium that causes the transmission of a first metadata request among a plurality of metadata requests associated with a first data transaction to a memory controller to be scheduled at least partially based on a first metadata priority level associated with the first metadata request, a first reception time associated with the first data transaction, and a first bandwidth portion of the metadata request bandwidth allocated for the transmission of the metadata request to the memory controller, wherein the first bandwidth portion of the metadata bandwidth is allocated for the transmission of the metadata request associated with the first metadata priority level. (Item 14) The machine-readable medium according to item 13, further comprising an instruction causing the machine to schedule the transmission of a second metadata request among a plurality of metadata requests associated with a second data transaction to the memory controller, at least in part, based on a second metadata priority level associated with the second metadata request, a second time associated with the second data transaction, and a second bandwidth portion of the metadata request bandwidth allocated to the transmission of the metadata request associated with the second metadata priority level, wherein the first bandwidth portion of the metadata bandwidth is less than the second bandwidth portion of the metadata bandwidth, at least in part, based on the first metadata priority level being lower than the second metadata priority level. (Item 15) The machine-readable medium according to item 13, further comprising instructions causing the machine to associate each of the plurality of metadata priority levels with a metadata priority level weight, and to allocate the first bandwidth portion of the metadata bandwidth to the metadata request associated with the first metadata priority level, at least on a part basis with respect to the first metadata priority level weight associated with the first metadata priority level. (Item 16) Multiple cores, The memory controller, Metadata cache and A memory traffic scheduler coupled to the plurality of cores, the memory controller, and the metadata cache, wherein the memory traffic scheduler is The storage of multiple metadata requests, each of which is associated with one of a plurality of metadata priority levels, and A system comprising a memory traffic scheduler that schedules the transmission of a first metadata request among a plurality of metadata requests to the memory controller based at least partially on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth allocated for the transmission of the metadata request to the memory controller, wherein the first bandwidth portion of the metadata bandwidth is allocated for the transmission of the metadata request associated with the first metadata priority level. (Item 17) The system according to item 16, wherein the memory traffic scheduler stores a plurality of read data transactions, each of which is associated with one of a plurality of read data transaction priority levels, and schedules the transmission of a first read data transaction from the plurality of read data transactions to the memory controller at least partially based on a first read data transaction priority level associated with the first read data transaction and a first bandwidth portion of the read data transaction bandwidth allocated for the transmission of the read data transaction to the memory controller, wherein the first bandwidth portion of the read data transaction bandwidth is allocated for the transmission of the read data transaction associated with the first read data transaction priority level. (Item 18) The system according to item 16, wherein the memory traffic scheduler stores a plurality of write data transactions, each of which is associated with one of a plurality of write data transaction priority levels, and schedules the transmission of a write data transaction from the plurality of write data transactions to the memory controller at least partially based on a first write data transaction priority level associated with a first write data transaction and a first bandwidth portion of the write data transaction bandwidth allocated for the transmission of the write data transaction to the memory controller, wherein the first bandwidth portion of the write data transaction bandwidth is allocated for the transmission of the write data transaction associated with the first write data transaction priority level. (Item 19) The system according to item 16, wherein the memory traffic scheduler includes at least two metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the memory traffic scheduler further generates the first metadata request associated with the first metadata priority level, places the first metadata request into the first metadata request queue associated with the first metadata priority level, and schedules the transmission of the first metadata request to the memory controller based at least partially on the position of the first metadata request in the first metadata request queue. (Item 20) The system according to item 19, wherein the memory traffic scheduler includes a read data transaction queue and a write data transaction queue, and the memory traffic scheduler further schedules the transmission of a first read data transaction from the read data transaction queue to the memory controller based at least partially on the position of the first read data transaction in the read data transaction queue and the read data transaction bandwidth, and further schedules the transmission of a first write data transaction from the write data transaction queue to the memory controller based at least partially on the position of the first write data transaction in the write data transaction queue and the write data transaction bandwidth. According to this specification, the following items are also disclosed: [Item 1] A memory for storing multiple metadata requests, each of which is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. A device equipped with the following features. [Item 2] The aforementioned scheduler further, To receive a first data transaction associated with a first data transaction priority level for transmission to the memory controller, To determine whether the metadata associated with the first data transaction is available in the metadata cache, and Based on the above determination, generate the first metadata request associated with the metadata such that it has a first metadata priority level inherited from the first data transaction priority level. To do The device described in item 1. [Item 3] The aforementioned scheduler further, Receiving a first data transaction that includes a data transaction priority tag associated with a first data transaction priority level, and, To generate a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first data transaction priority level. To do The device described in item 1. [Item 4] The aforementioned scheduler further, Receiving a first data transaction from a first core among multiple cores, wherein the first core is associated with a first core priority level, and To generate a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first core priority level. To do The device described in item 1. [Item 5] The memory further includes a plurality of metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the scheduler further includes To generate the first metadata request associated with the first metadata priority level, Placing the first metadata request in a first metadata request queue associated with the first metadata priority level, and Scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. To do The device described in item 1. [Item 6] The aforementioned scheduler further, Identifying the first core among multiple cores responsible for generating data transactions associated with metadata requests having the first metadata priority level, To generate bandwidth availability data associated with the first bandwidth portion of the metadata request bandwidth, and The bandwidth availability data is transmitted to the first core so that the first core can manage several data transactions transmitted to the device based on the bandwidth availability data. To do The device described in item 1. [Item 7] The aforementioned scheduler further, Comparing some of the metadata requests among the plurality of metadata requests associated with the first metadata priority level with a bandwidth adjustment threshold, Dynamically adjust the first bandwidth portion of the metadata request bandwidth based on the comparison. To do The device described in item 1. [Item 8] The aforementioned scheduler further, Determining whether some of the metadata requests among the plurality of metadata requests associated with the first metadata priority level exceed the core throttling threshold, wherein the first metadata priority level is a low priority level, and Identifying a first core among a plurality of cores responsible for generating data transactions associated with metadata requests having the first metadata priority level, and sending a data transaction throttling request to the first core based on the determination. To do The device described in item 1. [Item 9] The apparatus according to item 1, wherein each of the plurality of metadata priority levels is associated with a metadata priority level weight, and the scheduler further allocates the first bandwidth portion of the metadata request bandwidth to the metadata request associated with the first metadata priority level based at least in part on the first metadata priority level weight associated with the first metadata priority level. [Item 10] The memory includes at least two metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the scheduler further, To generate the first metadata request associated with the first metadata priority level, Placing the first metadata request in a first metadata request queue associated with the first metadata priority level, and Scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. To do The device described in item 1. [Item 11] The aforementioned scheduler further, Determining whether the plurality of metadata requests include another metadata request associated with the first metadata priority level, Based on the above determination, scheduling the transmission of a second metadata request of the plurality of metadata requests to the memory controller using the bandwidth of the first bandwidth portion of the metadata request bandwidth, wherein the second metadata request has a second metadata priority level among the plurality of metadata priority levels. To do The apparatus described in any one of items 1 through 10. [Item 12] The aforementioned scheduler further, Scheduling the transmission of a second metadata request among the plurality of metadata requests to the memory controller, at least partially based on a second metadata priority level associated with the second metadata request and a second bandwidth portion of the metadata request bandwidth, wherein the second bandwidth portion is allocated to the transmission of metadata requests associated with the second metadata priority level, and the first bandwidth portion of the metadata request bandwidth is scheduled to be less than the second bandwidth portion of the metadata request bandwidth, at least partially based on the first metadata priority level being lower than the second metadata priority level. To do The apparatus described in any one of items 1 through 11. [Item 13] A memory traffic scheduler receives multiple data transactions, each of which is associated with a transaction reception time and a data transaction priority level. The memory traffic scheduler generates a plurality of metadata requests, each of which is associated with one of the plurality of data transactions and a metadata priority level among a plurality of metadata priority levels inherited from the data transaction priority level of one of the plurality of data transactions. A method comprising the step of scheduling the transmission of a first metadata request among a plurality of metadata requests to a memory controller, at least in part on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. [Item 14] The method according to item 13, further comprising the step of scheduling the transmission of a second metadata request among a plurality of metadata requests associated with a second data transaction to the memory controller, at least in part, on a second metadata priority level associated with the second metadata request, a second time associated with the second data transaction, and a second bandwidth portion of the metadata request bandwidth allocated to the transmission of the metadata request associated with the second metadata priority level, wherein the first bandwidth portion of the metadata request bandwidth is less than the second bandwidth portion of the metadata request bandwidth, at least in part on the first metadata priority level being lower than the second metadata priority level. [Item 15] The steps include associating each of the aforementioned multiple metadata priority levels with a metadata priority level weight, A step of allocating the first bandwidth portion of the metadata request bandwidth to a metadata request associated with the first metadata priority level, at least in part, based on the first metadata priority level weight associated with the first metadata priority level; Further including, The method described in item 13. [Item 16] A computer program that causes a processor to perform an action described in any one of items 13 through 15. [Item 17] Multiple cores, The memory controller, Metadata cache and A memory traffic scheduler coupled to the plurality of cores, the memory controller, and the metadata cache, wherein the memory traffic scheduler is The storage of multiple metadata requests, each of which is associated with one of a plurality of metadata priority levels, and A system comprising a memory traffic scheduler that schedules the transmission of a first metadata request among a plurality of metadata requests to the memory controller, at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. [Item 18] The aforementioned memory traffic scheduler further, The storage of multiple read data transactions, wherein each of the multiple read data transactions is associated with one of the multiple read data transaction priority levels, and Scheduling the transmission of a first read data transaction among the plurality of read data transactions to the memory controller is at least partially based on a first read data transaction priority level associated with the first read data transaction and a first bandwidth portion of the read data transaction bandwidth allocated for the transmission of the read data transaction to the memory controller, wherein the first bandwidth portion of the read data transaction bandwidth is allocated for the transmission of the read data transaction associated with the first read data transaction priority level. To do The system described in item 17. [Item 19] The aforementioned memory traffic scheduler further, The storage of multiple write data transactions, wherein each of the multiple write data transactions is associated with one of the multiple write data transaction priority levels, and Scheduling the transmission of a write data transaction from the plurality of write data transactions to the memory controller is performed at least partially based on a first write data transaction priority level associated with a first write data transaction and a first bandwidth portion of the write data transaction bandwidth allocated for the transmission of the write data transaction to the memory controller, wherein the first bandwidth portion of the write data transaction bandwidth is allocated for the transmission of the write data transaction associated with the first write data transaction priority level. To do The system described in item 17. [Item 20] The memory traffic scheduler includes at least two metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the memory traffic scheduler further includes: Generating the first metadata request associated with the first metadata priority level, placing the first metadata request in the first metadata request queue associated with the first metadata priority level, and Scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. To do The system described in item 17. [Item 21] The memory traffic scheduler includes a read data transaction queue and a write data transaction queue, and the memory traffic scheduler further includes: The transmission of a first read data transaction from the read data transaction queue to the memory controller is scheduled at least partially based on the position of the first read data transaction in the read data transaction queue and the read data transaction bandwidth, and The transmission of a first write data transaction from the write data transaction queue to the memory controller is scheduled at least partially based on the position of the first write data transaction in the write data transaction queue and the write data transaction bandwidth. To do The system described in item 20. [Item 22] A memory means for storing multiple metadata requests, wherein each of the multiple metadata requests is associated with one of a plurality of metadata priority levels, A scheduler means coupled to the memory means and the memory controller means, the scheduler means for scheduling the transmission of the first metadata request of the plurality of metadata requests to the memory controller means at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. A device that includes this. [Item 23] The aforementioned scheduler means further, To receive a first data transaction associated with a first data transaction priority level for transmission to the memory controller means, To determine whether the metadata associated with the first data transaction is available in the metadata cache means, and Based on the above determination, generate the first metadata request associated with the metadata such that it has a first metadata priority level inherited from the first data transaction priority level. It is for the purpose of doing so. The device described in item 22. [Item 24] The aforementioned scheduler means further, Receiving a first data transaction that includes a data transaction priority tag associated with a first data transaction priority level, and, To generate a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first data transaction priority level. It is for the purpose of doing so. The device described in item 22. [Item 25] The aforementioned scheduler means further, Receiving a first data transaction from a first core among multiple cores, wherein the first core is associated with a first core priority level, and To generate a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first core priority level. It is for the purpose of doing so. The apparatus described in any one of items 22 to 24.

Claims

1. A memory for storing multiple metadata requests, wherein each of the multiple metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. Equipped with, The apparatus wherein each of the plurality of metadata priority levels is associated with a metadata priority level weight, and the scheduler further allocates the first bandwidth portion of the metadata request bandwidth to the metadata request associated with the first metadata priority level based at least in part on the first metadata priority level weight associated with the first metadata priority level.

2. A memory for storing a plurality of metadata requests, wherein each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. Equipped with, The aforementioned scheduler further, To receive a first data transaction associated with a first data transaction priority level for transmission to the memory controller, To determine whether the metadata associated with the first data transaction is available in the metadata cache, and Based on the above determination, generate the first metadata request associated with the metadata such that it has a first metadata priority level inherited from the first data transaction priority level. A device that performs this task.

3. A memory for storing a plurality of metadata requests, wherein each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. Equipped with, The aforementioned scheduler further, Receiving a first data transaction that includes a data transaction priority tag associated with a first data transaction priority level, and To generate a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first data transaction priority level. A device that performs this task.

4. A memory for storing a plurality of metadata requests, wherein each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. Equipped with, The aforementioned scheduler further, Receiving a first data transaction from a first core among multiple cores, wherein the first core is associated with a first core priority level, and To generate a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first core priority level. A device that performs this task.

5. A memory for storing a plurality of metadata requests, wherein each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. A device equipped with, The aforementioned scheduler further, Identifying a first core among a plurality of cores responsible for generating data transactions associated with metadata requests having the first metadata priority level, To generate bandwidth availability data associated with the first bandwidth portion of the metadata request bandwidth, and The bandwidth availability data is transmitted to the first core so that the first core can manage several data transactions transmitted to the device based on the bandwidth availability data. A device that performs this task.

6. A memory for storing a plurality of metadata requests, wherein each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. Equipped with, The aforementioned scheduler further, Comparing some of the metadata requests among the plurality of metadata requests associated with the first metadata priority level with a bandwidth adjustment threshold, Dynamically adjust the first bandwidth portion of the metadata request bandwidth based on the comparison. A device that performs this task.

7. A memory for storing a plurality of metadata requests, wherein each of the plurality of metadata requests is associated with one of a plurality of metadata priority levels, A scheduler coupled to the memory and the memory controller, the scheduler schedules the transmission of the first metadata request of the plurality of metadata requests to the memory controller at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. Equipped with, The aforementioned scheduler further, Determining whether some of the plurality of metadata requests associated with the first metadata priority level exceed the core throttling threshold, wherein the first metadata priority level is a low priority level, and Identifying a first core among a plurality of cores responsible for generating data transactions associated with metadata requests having the first metadata priority level, and sending a data transaction throttling request to the first core based on the determination. A device that performs this task.

8. The memory further includes a plurality of metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the scheduler further includes To generate the first metadata request associated with the first metadata priority level, The first metadata request is placed in a first metadata request queue associated with the first metadata priority level, and Scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. To do The apparatus according to claim 1, or any one of claims 3 to 7.

9. The memory includes at least two metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the scheduler further, To generate the first metadata request associated with the first metadata priority level, The first metadata request is placed in a first metadata request queue associated with the first metadata priority level, and Scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. To do The apparatus according to claim 1, or any one of claims 3 to 7.

10. The aforementioned scheduler further, Determining whether the plurality of metadata requests include another metadata request associated with the first metadata priority level, Based on the above determination, scheduling the transmission of a second metadata request of the plurality of metadata requests to the memory controller using the bandwidth of the first bandwidth portion of the metadata request bandwidth, wherein the second metadata request has a second metadata priority level among the plurality of metadata priority levels. To do The apparatus according to any one of claims 1 to 9.

11. The aforementioned scheduler further, Scheduling the transmission of a second metadata request among the plurality of metadata requests to the memory controller at least partially based on a second metadata priority level associated with the second metadata request and a second bandwidth portion of the metadata request bandwidth, wherein the second bandwidth portion is allocated to the transmission of metadata requests associated with the second metadata priority level, and the first bandwidth portion of the metadata request bandwidth is scheduled to be less than the second bandwidth portion of the metadata request bandwidth, at least partially based on the first metadata priority level being lower than the second metadata priority level. To do The apparatus according to any one of claims 1 to 10.

12. A memory traffic scheduler receives multiple data transactions, each of which is associated with a transaction reception time and a data transaction priority level. The memory traffic scheduler generates a plurality of metadata requests, each of which is associated with one of the plurality of data transactions and a metadata priority level among a plurality of metadata priority levels inherited from the data transaction priority level of one of the plurality of data transactions. A method comprising the step of scheduling the transmission of a first metadata request among a plurality of metadata requests to a memory controller, at least in part on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level.

13. The steps include associating each of the aforementioned multiple metadata priority levels with a metadata priority level weight, A step of allocating the first bandwidth portion of the metadata request bandwidth to a metadata request associated with the first metadata priority level, at least in part, based on the first metadata priority level weight associated with the first metadata priority level; Further including, The method according to claim 12.

14. The steps of receiving a first data transaction associated with a first data transaction priority level for transmission to the memory controller, A step of determining whether the metadata associated with the first data transaction is available in the metadata cache, A step of generating the first metadata request associated with the metadata so as to have a first metadata priority level inherited from the first data transaction priority level based on the above determination. Further including, The method according to claim 12 or 13.

15. A step of receiving a first data transaction which includes a data transaction priority tag associated with a first data transaction priority level, A step of generating a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from the first data transaction priority level. Further including, The method according to claim 12 or 13.

16. A receiving step of receiving a first data transaction from a first core among a plurality of cores, wherein the first core is associated with a first core priority level. A step of generating a first metadata priority level for associating with a first metadata request for metadata associated with the first data transaction, wherein the first metadata priority level is inherited from a first core priority level. Further including, The method according to claim 12 or 13.

17. A step of generating the first metadata request associated with the first metadata priority level, The steps include: placing the first metadata request into a first metadata request queue associated with the first metadata priority level; A step of scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. Further including, The method according to any one of claims 12, 13, 15, and 16.

18. The steps of identifying a first core among a plurality of cores responsible for generating a data transaction associated with a metadata request having the first metadata priority level, A step of generating bandwidth availability data associated with the first bandwidth portion of the metadata request bandwidth, The first core transmits the bandwidth availability data to the first core so that the first core can manage several data transactions sent to the memory traffic scheduler based on the bandwidth availability data. Further including, The method according to any one of claims 12 to 17.

19. A step of comparing some metadata requests among the plurality of metadata requests associated with the first metadata priority level with a bandwidth adjustment threshold, A step of dynamically adjusting the first bandwidth portion of the metadata request bandwidth based on the comparison above. Further including, The method according to any one of claims 12 to 18.

20. A step of determining whether some of the plurality of metadata requests associated with the first metadata priority level exceed a core throttling threshold, wherein the first metadata priority level is a low priority level. The steps include: identifying a first core among a plurality of cores responsible for generating data transactions associated with a metadata request having the first metadata priority level, and sending a data transaction throttling request to the first core based on the determination; Further including, The method according to any one of claims 12 to 19.

21. The step of generating the first metadata request associated with the first metadata priority level, The steps include: placing the first metadata request into a first metadata request queue associated with the first metadata priority level; A step of scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. Further including, The method according to any one of claims 12 to 16 and any one of claims 18 to 20 that does not refer to claim 17.

22. A step of determining whether the plurality of metadata requests include another metadata request associated with the first metadata priority level, A step of scheduling the transmission of a second metadata request of the plurality of metadata requests to the memory controller using the bandwidth of the first bandwidth portion of the metadata request bandwidth based on the above determination, wherein the second metadata request has a second metadata priority level among the plurality of metadata priority levels. Further including, The method according to any one of claims 12 to 21.

23. The method according to any one of claims 12 to 22, further comprising the step of scheduling the transmission of a second metadata request among a plurality of metadata requests associated with a second data transaction to the memory controller, at least in part on a second metadata priority level associated with the second metadata request, a second time associated with the second data transaction, and a second bandwidth portion of the metadata request bandwidth allocated to the transmission of the metadata request associated with the second metadata priority level, wherein the first bandwidth portion of the metadata request bandwidth is less than the second bandwidth portion of the metadata request bandwidth, at least in part on the first metadata priority level being lower than the second metadata priority level.

24. A computer program that causes a processor to perform the method according to any one of claims 12 to 23.

25. Multiple cores, The memory controller, Metadata cache and A memory traffic scheduler coupled to the plurality of cores, the memory controller, and the metadata cache, wherein the memory traffic scheduler is The storage of multiple metadata requests, each of which is associated with one of a plurality of metadata priority levels, and A memory traffic scheduler that schedules the transmission of a first metadata request among the plurality of metadata requests to the memory controller, at least partially based on a first metadata priority level associated with the first metadata request and a first bandwidth portion of the metadata request bandwidth, wherein the first bandwidth portion is associated with the first metadata priority level. A system in which each of the plurality of metadata priority levels is associated with a metadata priority level weight, and the memory traffic scheduler further allocates the first bandwidth portion of the metadata request bandwidth to the metadata request associated with the first metadata priority level based at least in part on the first metadata priority level weight associated with the first metadata priority level.

26. The aforementioned memory traffic scheduler further, The storage of multiple read data transactions, wherein each of the multiple read data transactions is associated with one of the multiple read data transaction priority levels, and Scheduling the transmission of a first read data transaction among the plurality of read data transactions to the memory controller is at least partially based on a first read data transaction priority level associated with the first read data transaction and a first bandwidth portion of the read data transaction bandwidth allocated for the transmission of the read data transaction to the memory controller, wherein the first bandwidth portion of the read data transaction bandwidth is allocated for the transmission of the read data transaction associated with the first read data transaction priority level. To do The system according to claim 25.

27. The aforementioned memory traffic scheduler further, The storage of multiple write data transactions, wherein each of the multiple write data transactions is associated with one of the multiple write data transaction priority levels, and Scheduling the transmission of a write data transaction from the plurality of write data transactions to the memory controller is performed at least partially based on a first write data transaction priority level associated with a first write data transaction and a first bandwidth portion of the write data transaction bandwidth allocated for the transmission of the write data transaction to the memory controller, wherein the first bandwidth portion of the write data transaction bandwidth is allocated for the transmission of the write data transaction associated with the first write data transaction priority level. To do The system according to claim 25.

28. The memory traffic scheduler includes at least two metadata request queues, each of which is associated with one of the plurality of metadata priority levels, and the memory traffic scheduler further includes: Generating the first metadata request associated with the first metadata priority level, placing the first metadata request in the first metadata request queue associated with the first metadata priority level, and Scheduling the transmission of the first metadata request to the memory controller based at least partially on the location of the first metadata request in the first metadata request queue. To do The system according to claim 25.

29. The memory traffic scheduler includes a read data transaction queue and a write data transaction queue, and the memory traffic scheduler further includes: The transmission of the first read data transaction from the read data transaction queue to the memory controller is scheduled at least partially based on the position of the first read data transaction in the read data transaction queue and the read data transaction bandwidth, and The transmission of a first write data transaction from the write data transaction queue to the memory controller is scheduled at least partially based on the position of the first write data transaction in the write data transaction queue and the write data transaction bandwidth. To do The system according to claim 28.

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