Silicon carbide semiconductor equipment

Abstract

To provide a highly reliable silicon carbide semiconductor device having a breakdown voltage structure which can be easily formed and which can stably secure a predetermined breakdown voltage.SOLUTION: In an edge termination region 2, a plurality of p-type regions 31 and a plurality of p-type regions 32 constituting a spatial modulation JTE structure 30 are selectively formed at depth positions away from the front surface of a semiconductor substrate 40. The bottoms of the p-type region 31 and the p-type region 32 are located deeper from the front surface of the semiconductor substrate 40 than the bottom of a p-type peripheral region 24 in ab outer peripheral portion 1b of an active region 1. An outer corner portion 24b of the bottom of the p-type peripheral region 24 is surrounded by the innermost p-type region 31 and is not contact with an n-type drift region 12 of the edge termination region 2.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to a silicon carbide semiconductor device. [Background technology]

[0002] Conventionally, the voltage-resistant structure of a power semiconductor device is located in the edge termination region between the active region and the edge of the semiconductor substrate (semiconductor chip), and in the edge termination region, n is exposed on the front surface of the semiconductor substrate. - It consists of multiple p-type regions selectively provided on the surface region of the type drift region. When the semiconductor material of a power semiconductor device is silicon carbide (SiC), it is known that a junction termination extension (JTE) structure is used as the breakdown structure.

[0003] The JTE structure is a structure in which multiple p-type regions (hereinafter referred to as JTE regions) are arranged concentrically adjacent to the active region, such that the JTE regions have lower impurity concentrations as they move from the inside (towards the center of the semiconductor substrate (chip center)) to the outside (towards the edge of the semiconductor substrate (chip edge)). The electric field strength tends to decrease as it moves away from the active region. By lowering the impurity concentration of the JTE regions as they are located further away from the active region, in accordance with the trend of the electric field strength distribution, a predetermined breakdown voltage of the edge termination region can be stably ensured.

[0004] A spatially modulated JTE structure is an improved structure of the JTE structure, consisting of adjacent JTE regions (if it consists of only one JTE region, then one JTE region and the n regions outside of it). - This structure involves placing a spatial modulation region between the p-type drift regions, having an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between these two regions, thereby gradually decreasing the overall p-type impurity concentration from the inside to the outside. The spatial modulation region is formed by repeatedly arranging two small regions with approximately the same impurity concentration as the adjacent region on each side of itself in a predetermined pattern.

[0005] The spatial impurity concentration distribution of the entire spatially modulated region is determined by the widths of the two small regions and the impurity concentration ratio. The spatially modulated JTE structure can more stably ensure a predetermined breakdown voltage in the edge termination region compared to a general JTE structure without a spatially modulated region. Thus, by disposing a predetermined breakdown voltage structure in the edge termination region to relax or disperse the electric field in the edge termination region, the breakdown voltage of the edge termination region is improved, and the breakdown voltage of the entire semiconductor device is improved. A description will be given of the structure of a conventional silicon carbide semiconductor device.

[0006] FIG. 13 is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. The conventional silicon carbide semiconductor device 110 shown in FIG. 13 is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS type field effect transistor having an insulated gate (MOS gate) composed of a three-layer structure of metal - oxide film - semiconductor) with a trench gate structure provided with a spatially modulated JTE structure 130 in an edge termination region 102 of a semiconductor substrate (semiconductor chip) 140 made of silicon carbide.

[0007] The semiconductor substrate 140 is formed by epitaxially growing an n + -type drift region 112 on an n - -type silicon carbide layer 142 on an n - -type starting substrate 141. The semiconductor substrate 140 has a main surface on the n - -type silicon carbide layer 142 side as the front surface and a main surface on the n + -type starting substrate 141 side as the back surface. The front surface of the semiconductor substrate 140 is a flat surface throughout, and no step is formed between the active region 101 and the edge termination region 102. A plurality of unit cells (functional units of the element) of the MOSFET are provided adjacent to each other at the central portion 101a of the active region 101.

[0008] On the outer peripheral portion 101b of the active region 101, throughout the entire area between the front surface of the semiconductor substrate 140 and the n - -type drift region 112, in the depth direction adjacent to each other in order from the front surface side of the semiconductor substrate 140, p ++Type contact extension 115a, p-type base extension 113a and p + A mold extension portion 122a is provided. ++ The type contact extension portion 115a is exposed on the front surface of the semiconductor substrate 140 and is in contact with the insulating layer (field oxide film 125 and interlayer insulating film 119) on the front surface of the semiconductor substrate 140.

[0009] p ++ Type contact extension 115a, p-type base extension 113a and p + Each type extension portion 122a is the p of the outermost unit cell of the central portion 101a of the active region 101. ++ Type contact area 115, p-type base area 113 and p + This is an extension of the type region 122, surrounding the central part 101a of the active region 101. ++ Type contact extension 115a, p-type base extension 113a and p + Both the outer ends of the mold extension portion 122a terminate at the same position in the normal direction from the inside to the outside, and lie on the same plane perpendicular to the front surface of the semiconductor substrate 140.

[0010] The edge termination region 102 surrounds the active region 101. The edge termination region 102 is provided with a spatial modulation JTE structure 130 as a breakdown structure. The spatial modulation JTE structure 130 is connected to the front surface of the semiconductor substrate 140 and n - Multiple p-type regions 131 and multiple p-type regions selectively provided between the type drift region 112 and the p-type drift region 112 - It consists of type region 132. All of these p-type regions 131 and p - The mold region 132 is exposed on the front surface of the semiconductor substrate 140 and is in contact with the insulating layer on the front surface of the semiconductor substrate 140.

[0011] Multiple p-type regions 131 are arranged concentrically around the active region 101, separated from each other. The innermost p-type region 131 is p ++ Outside the type contact extension portion 115a, p ++ It is positioned adjacent to the type contact extension portion 115a. Multiple p -The type regions 132 are arranged concentrically and spaced apart from each other, surrounding the active region 101. The innermost p - The p-type region 132 is provided between all adjacent p-type regions 131 and is adjacent to the p-type regions 131 on both sides in the normal direction.

[0012] innermost p - Type region 132 extends outward beyond the outermost p-type region 131. All p-type regions 131 and the innermost p - Type region 132 is p ++ The type contact extension portion 115a is fixed to the potential of the source electrode 120. - p outside of type region 132 - The type region 132 is located outside the p-type region 131. - The drift region 112 is comprised of all p adjacent to each other. - Provided between type regions 132, and adjacent to each other p - The mold regions 132 are exposed on the front surface of the semiconductor substrate 140.

[0013] Reference numerals 113 to 118 respectively indicate p-type base regions 113 and n-type base regions 113 and n-type base regions 140, which are provided on the front side of the semiconductor substrate 140 in the active region 101 and constitute a trench gate structure. + Type source region 114 and p ++ These are the type contact region 115, the trench 116, the gate insulating film 117, and the gate electrode 118. Reference numerals 111, 123, 126, and 133 respectively represent n + Type drain region 111, drain electrode 123, gate polysilicon wiring layer 126 and n + This is a type channel stopper region 133. Reference numerals 121 and 122 indicate the p-type channel stopper region 133 which relaxes the electric field applied to the gate insulating film 117 at the bottom of the trench 116. + The type regions are 121 and 122.

[0014] In conventional semiconductor devices, a device has been proposed in which the p-type region constituting the breakdown structure is positioned at a depth away from the front surface of the semiconductor substrate such that its bottom (the back edge of the semiconductor substrate) is at the same depth as the bottom of the p-type region that forms the outermost edge (hereinafter referred to as the main junction edge) of the main junction (pn junction) of the active region (see, for example, Patent Documents 1 to 3 below). In Patent Document 1 below, electric field concentration at the main junction edge of the active region is suppressed by using adjacent JTE structure p-type regions outside the p-type region that forms the main junction edge of the active region, with their bottoms aligned at the same depth.

[0015] Furthermore, in Patent Document 1 below, in a structure in which the entire surface of the semiconductor substrate is a flat surface, the p-type region of the active region and the p-type region constituting the JTE structure are formed at the same depth from the surface of the semiconductor substrate, thereby improving the alignment accuracy by photolithography. In Patent Document 2 below, a low impurity concentration n is placed between the surface of the semiconductor substrate and the breakdown structure. - type or p - The silicon carbide layer protects the pressure-resistant structure and mitigates the electric field on the surface of the semiconductor substrate.

[0016] In Patent Document 3 below, the breakdown voltage is improved by forming an impurity concentration distribution in the field limiting ring (FLR), which is the p-type region of the floating potential that constitutes the breakdown structure, in which the impurity concentration is relatively low on the back side of the semiconductor substrate and relatively high on the front side of the semiconductor substrate. Furthermore, in Patent Documents 2 and 3 below, the number of processes is reduced by simultaneously forming the p-type region that constitutes the breakdown structure and the p-type region of the active region at the same depth.

[0017] Furthermore, as another conventional semiconductor device, an embedded FLR has been proposed in which embedded FLRs are selectively provided at a depth away from the surface of the semiconductor substrate so as to individually surround areas prone to electric field concentration, such as the outer corners at the bottom of the p-type region that forms the main junction edge of the active region and the outer corners at the bottom of the FLR in the edge termination region (see, for example, Patent Document 4 below). In Patent Document 4 below, localized electric field concentration in areas prone to electric field concentration is suppressed by the embedded FLR.

[0018] Another conventional semiconductor device has been proposed that uses a superjunction (SJ) structure in which the drift layer is a parallel pn layer in which n-type and p-type regions are alternately and repeatedly arranged in a direction parallel to the surface of the semiconductor substrate. In this device, the p-type region of the parallel pn layer in the edge termination region is located at a depth away from the surface of the semiconductor substrate, and the length in the depth direction is shortened as it is located further outwards (see, for example, Patent Document 5 below). Patent Document 5 below achieves high breakdown voltage by increasing the radius of curvature of the equipotential lines in the edge termination region. [Prior art documents] [Patent Documents]

[0019] [Patent Document 1] Japanese Patent Publication No. 2020-202404 [Patent Document 2] Japanese Patent Publication No. 2021-048423 [Patent Document 3] Japanese Patent Publication No. 2007-173705 [Patent Document 4] Japanese Patent Publication No. 2008-004643 [Patent Document 5] Japanese Patent Publication No. 2000-183350 [Overview of the project] [Problems that the invention aims to solve]

[0020] In a structure (not shown) in which a p-type silicon carbide layer, which forms a p-type base region only in the active region, is formed by epitaxial growth, a step is formed on the front surface of the semiconductor substrate, where the front surface of the semiconductor substrate is lower on the drain electrode side in the edge termination region than the active region. Outside of this step, the n- - Type silicon carbide layer (n - A pressure-resistant structure is formed on the surface region of the p-type drift region. The p-type region, which forms the main junction end of the active region, extends beyond the step and is exposed on the front surface of the semiconductor substrate, with the outer corner of the bottom surrounded by the pressure-resistant structure.

[0021] However, in conventional silicon carbide semiconductor devices 110 (see Figure 13), the entire surface of the semiconductor substrate is flat. Therefore, when an element structure such as a trench gate structure is formed in the active region 101, reaching a deep position from the surface of the semiconductor substrate 140, the bottom of the p-type region that forms the main junction end of the active region 101 (p + With respect to the depth position of the bottom of the mold extension portion 122a, the pressure-resistant structure (p-type region 131 and p - The depth position of the bottom of the mold region 132) (the back edge of the semiconductor substrate 140) becomes shallower from the front surface of the semiconductor substrate 140.

[0022] Because the depth position of the bottom of the p-type region constituting the pressure-resistant structure is shallow, the outer corner portion 122b of the bottom of the p-type region that forms the main junction end of the active region 101 is n - The structure is surrounded by a drift region 112. As a result, the electric field concentrates in this portion 122b, making it prone to avalanche breakdown, and the breakdown voltage of the edge termination region 102 becomes lower than that of the active region 101. Since the breakdown voltage of the edge termination region 102 determines the overall breakdown voltage of the silicon carbide semiconductor device 110, reliability decreases.

[0023] Even if the breakdown voltage of the edge termination region 102 can be made higher than that of the active region 101, the breakdown voltage difference is small, and if the breakdown voltage of the active region 101 is made higher due to other factors, the breakdown voltage of the edge termination region 102 may become lower than that of the active region 101. In order to suppress such a decrease in the breakdown voltage of the edge termination region, devices have been proposed, as described in the above-mentioned Patent Documents 1 to 4, in which the p-type regions constituting the breakdown structure are arranged so that their bottoms are at the same depth as the bottoms of the p-type regions that form the main junction ends of the active region, thereby suppressing localized electric field concentration.

[0024] Furthermore, in typical pressure-resistant structures, the number of processes and costs are reduced by forming the p-type regions constituting the pressure-resistant structure simultaneously with p-type regions of the same impurity concentration and depth in the active region using the same ion implantation method. For this reason, as described in Patent Documents 2 and 3 above, when a pressure-resistant structure is constructed using multiple p-type regions (FLRs) of the same impurity concentration and depth as the p-type region of the active region, the number of processes can be reduced, and the bottom of the p-type region of the active region and the bottom of the p-type region constituting the pressure-resistant structure can be easily aligned at the same depth.

[0025] However, as in the JTE structure of Patent Document 1 mentioned above, when the impurity concentration of the p-type region of the active region and the impurity concentration of the p-type region constituting the pressure-resistant structure are different, the p-type region of the active region and the p-type region constituting the pressure-resistant structure are formed by different ion implantation processes. Since the impurity concentrations of these p-type regions are adjusted by ion implantation under different conditions (number of stages and dose amount) set as appropriate, it is difficult to align the bottom of the p-type region constituting the pressure-resistant structure with the bottom of the outermost p-type region of the active region at the same depth.

[0026] Furthermore, in the above-mentioned Patent Documents 1 to 5, in the edge termination region, there is a gap between the front surface of the semiconductor substrate and the breakdown structure (SJ structure in Patent Document 5) n -The structure retains a type drift region. As a result, when the semiconductor device operates for a long time, the insulating layer on the surface of the semiconductor substrate in the edge termination region becomes negatively charged (negative charge accumulates). This negative charge accumulated in the insulating layer has a significant adverse effect, causing the breakdown voltage of the edge termination region to fluctuate and reducing reliability over time.

[0027] The purpose of this invention is to provide a highly reliable silicon carbide semiconductor device that has a pressure-resistant structure that can be easily formed and stably ensure a predetermined pressure resistance, in order to solve the problems of the conventional technology described above. [Means for solving the problem]

[0028] To solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: The semiconductor substrate is made of silicon carbide and has a first main surface that is flat over its entire surface. An active region and a termination region are provided on the semiconductor substrate. The termination region surrounds the periphery of the active region. A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, extending from the active region to the termination region. A second semiconductor region of a second conductivity type is provided between the first main surface and the first semiconductor region in the active region. The device structure includes a pn junction between the first semiconductor region and the second semiconductor region. Current flows through the device structure through the pn junction. A second conductivity type outer peripheral region is provided between the first main surface and the first semiconductor region between the device structure and the termination region. The second conductivity type outer peripheral region surrounds the periphery of the device structure.

[0029] The first electrode is provided on the first main surface and is electrically connected to the second semiconductor region and the second conductivity type peripheral region. The second electrode is provided on the second main surface of the semiconductor substrate and is electrically connected to the first semiconductor region. In the terminal region, a plurality of second conductivity type breakdown regions are provided within the first semiconductor region at a depth away from the first main surface, concentrically separated from each other and surrounding the active region. The breakdown structure is composed of a plurality of second conductivity type breakdown regions. The overall second conductivity type impurity concentration of the breakdown structure gradually decreases from the inside to the outside. The outer edge of the second conductivity type peripheral region is perpendicular to the first main surface. The bottom of the second conductivity type breakdown region is located deeper from the first main surface than the bottom of the second conductivity type peripheral region. The innermost first second conductivity type breakdown region among the plurality of second conductivity type breakdown regions surrounds the outer corner portion of the bottom of the second conductivity type peripheral region.

[0030] Furthermore, the silicon carbide semiconductor device according to this invention, in the invention described above, has an element structure comprising a third semiconductor region of a first conductivity type, a trench, a gate electrode, and a high-concentration region of a second conductivity type. The third semiconductor region is selectively provided between the first main surface and the second semiconductor region and is electrically connected to the first electrode. The trench penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film. The high-concentration region of the second conductivity type is selectively provided between the first semiconductor region and the second semiconductor region, on the side of the second main surface that is below the bottom surface of the trench. The high-concentration region of the second conductivity type has a higher impurity concentration than the second semiconductor region.

[0031] The second conductivity type outer peripheral region comprises a first outer peripheral region, a second outer peripheral region, and a third outer peripheral region. The first outer peripheral region is the portion of the second semiconductor region located outside the device structure. The second outer peripheral region is the portion of the second conductivity type high-concentration region located outside the device structure, and is provided between the first outer peripheral region and the first semiconductor region, in contact with the first outer peripheral region and the first semiconductor region. The third outer peripheral region is provided between the first main surface and the first outer peripheral region, in contact with the first outer peripheral region. The third outer peripheral region has a higher impurity concentration than the first outer peripheral region. The first second conductivity type breakdown voltage region is characterized by surrounding the outer corner portion of the bottom of the second outer peripheral region.

[0032] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the silicon carbide semiconductor device according to this invention has the following features: The semiconductor substrate is made of silicon carbide and has a first main surface that is flat over its entire surface. An active region and a termination region are provided on the semiconductor substrate. The termination region surrounds the active region. A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, extending from the active region to the termination region. A second semiconductor region of a second conductivity type is provided between the first main surface and the first semiconductor region in the active region. The device structure includes a pn junction between the first semiconductor region and the second semiconductor region. Current flows through the pn junction in the device structure.

[0033] Between the device structure and the termination region, a second conductivity type peripheral region is provided between the first main surface and the first semiconductor region. The second conductivity type peripheral region surrounds the device structure. A first electrode is provided on the first main surface and electrically connected to the second semiconductor region and the second conductivity type peripheral region. A second electrode is provided on the second main surface of the semiconductor substrate and electrically connected to the first semiconductor region. Within the first semiconductor region in the termination region, at a depth away from the first main surface, a plurality of second conductivity type breakdown regions are provided concentrically, spaced apart from each other, surrounding the periphery of the active region. The breakdown structure is composed of a plurality of the second conductivity type breakdown regions. The overall second conductivity type impurity concentration of the breakdown structure gradually decreases from the inside to the outside.

[0034] The outer edge of the second conductivity type outer peripheral region has multiple steps formed, which are recessed inward by a predetermined width in stages as they move away from the first main surface in the depth direction, and has multiple extending portions that extend outward in the normal direction according to these steps, terminating further outward as they get closer to the first main surface. The bottom of the second conductivity type withstand voltage region is at a depth shallower on the first main surface side than the bottom of the second conductivity type outer peripheral region. The upper surface of the second conductivity type withstand voltage region is at the same depth as the bottom of the first extending portion that is closest to the first main surface among the multiple extending portions, or at a depth shallower on the first main surface side than the bottom of the first extending portion. The innermost first second conductivity type withstand voltage region among the multiple second conductivity type withstand voltage regions is in contact with the outer corner portion of the bottom of the first extending portion, or surrounds the outer corner portion of the bottom of the first extending portion.

[0035] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the predetermined width is 2 μm or more.

[0036] Furthermore, in the silicon carbide semiconductor device according to this invention, in the invention described above, the second conductivity type impurity concentration in the portion of the outer peripheral region of the second conductivity type that is deeper on the second main surface side than the breakdown structure is 1 × 10 19 / cm 3 The following characteristics apply:

[0037] Furthermore, in the silicon carbide semiconductor device according to this invention, the element structure comprises a third semiconductor region of a first conductivity type, a trench, a gate electrode, and a high-concentration region of a second conductivity type. The third semiconductor region is selectively provided between the first main surface and the second semiconductor region and is electrically connected to the first electrode. The trench penetrates the third semiconductor region and the second semiconductor region to reach the first semiconductor region. The gate electrode is provided inside the trench via a gate insulating film. The high-concentration region of the second conductivity type is selectively provided between the first semiconductor region and the second semiconductor region, on the side of the second main surface that is below the bottom surface of the trench.

[0038] The second conductivity type high-concentration region has a higher impurity concentration than the second semiconductor region. The second conductivity type outer peripheral region has a first outer peripheral region, a second outer peripheral region, and a third outer peripheral region. The first outer peripheral region is the portion of the second semiconductor region located outside the device structure. The second outer peripheral region is the portion of the second conductivity type high-concentration region located outside the device structure, and is provided between the first outer peripheral region and the first semiconductor region, in contact with the first outer peripheral region and the first semiconductor region. The third outer peripheral region is provided between the first main surface and the first outer peripheral region, in contact with the first outer peripheral region.

[0039] The third outer peripheral region has a higher impurity concentration than the first outer peripheral region. The step at the outer end of the second conductivity type outer peripheral region is formed by the first outer peripheral region ending inward of the third outer peripheral region, and the second outer peripheral region ending inward of the first outer peripheral region. The first extended portion of the outer end of the second conductivity type outer peripheral region is the portion of the third outer peripheral region that is located outside the first outer peripheral region. The first second conductivity type breakdown region is characterized by being in contact with the outer corner portion of the bottom of the third outer peripheral region, or surrounding the outer corner portion of the bottom of the third outer peripheral region.

[0040] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, a fourth semiconductor region of a first conductivity type with a higher impurity concentration than the first semiconductor region is provided between the first main surface and the breakdown structure.

[0041] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the carrier concentration in the second conductivity type breakdown voltage region is equal to or greater than the carrier concentration in the second semiconductor region and lower than the carrier concentration in the second conductivity type high concentration region.

[0042] Furthermore, in the silicon carbide semiconductor device according to the present invention, the breakdown structure has a first second conductivity type breakdown region, a plurality of second second conductivity type breakdown regions, a third second conductivity type breakdown region, and a plurality of fourth second conductivity type breakdown regions. The breakdown structure is formed by arranging a first spatial modulation region and a second spatial modulation region, The pressure-resistant structure The structure is such that the overall concentration of second conductivity type impurities decreases gradually from the inside to the outside. The second second conductivity type breakdown region is a region adjacent to the outside of the first second conductivity type breakdown region, among a plurality of the second conductivity type breakdown regions. The second second conductivity type breakdown region has the same impurity concentration as the first second conductivity type breakdown region.

[0043] The third second conductivity type breakdown region is located among the plurality of second conductivity type breakdown regions, adjacent to the outside of the first second conductivity type breakdown region, and situated between all adjacent second second conductivity type breakdown regions, and is the outermost Second This region extends beyond the second conductivity type breakdown region. The third second conductivity type breakdown region has a lower impurity concentration than the first second conductivity type breakdown region. The fourth second conductivity type breakdown region is the remaining region of the plurality of second conductivity type breakdown regions excluding the first second conductivity type breakdown region, the second second conductivity type breakdown region, and the third second conductivity type breakdown region, and is adjacent to the outside of the third second conductivity type breakdown region. The fourth second conductivity type breakdown region has the same impurity concentration as the third second conductivity type breakdown region.

[0044] The first spatial modulation region is located outside the first second conductivity type breakdown region and adjacent to the first second conductivity type breakdown region. The first spatial modulation region has an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration between the impurity concentration of the first second conductivity type breakdown region and the impurity concentration of the third second conductivity type breakdown region. The second spatial modulation region is located outside the third second conductivity type breakdown region and adjacent to the third second conductivity type breakdown region. The second spatial modulation region has an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration between the impurity concentration of the third second conductivity type breakdown region and the impurity concentration of the first semiconductor region. The first spatial modulation region is formed by arranging the second second conductivity type breakdown region and a part of the third second conductivity type breakdown region alternately and repeatedly adjacent to each other in a predetermined pattern. The second spatial modulation region is characterized by arranging the fourth second conductivity type breakdown region and the first semiconductor region alternately and repeatedly adjacent to each other in a predetermined pattern.

[0045] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, a fifth semiconductor region of a first conductivity type with a higher impurity concentration than the fourth semiconductor region is provided on the surface region of the fourth semiconductor region.

[0046] Furthermore, the silicon carbide semiconductor device according to this invention further comprises a sixth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region, located between the first main surface and the first semiconductor region, and positioned outside the fourth semiconductor region. The thickness of the fifth semiconductor region is characterized by being thinner than the thickness of the sixth semiconductor region.

[0047] Furthermore, the silicon carbide semiconductor device according to this invention is characterized in that, in the invention described above, the thickness of the fifth semiconductor region is 0.1 μm or more.

[0048] According to the invention described above, when the silicon carbide semiconductor device is turned off, the electric field can be concentrated at the bottom of the first second conductivity type breakdown voltage region and then dispersed and relaxed throughout the entire breakdown voltage structure outward from the first second conductivity type breakdown voltage region. This suppresses the occurrence of avalanche breakdown at the outer corner of the bottom of the p-type outer peripheral region, thereby suppressing a decrease in breakdown voltage in the edge termination region and preventing the breakdown voltage of the edge termination region from becoming lower than the breakdown voltage of the active region. As a result, the breakdown voltage of the active region can determine the overall breakdown voltage of the silicon carbide semiconductor device.

[0049] According to the invention described above, a breakdown structure can be easily formed by performing ion implantation for forming a second conductivity type breakdown region at a predetermined timing without changing the method for forming the element structure of the active region. Furthermore, a breakdown structure can be constructed by forming a second conductivity type breakdown region with a different impurity concentration from the second conductivity type region at a different timing than the formation of the second conductivity type region of the active region. In this case, a predetermined breakdown pressure can be secured in the edge termination region by appropriately setting the mask pattern and dose amount of ion implantation for forming the second conductivity type breakdown region. [Effects of the Invention]

[0050] The silicon carbide semiconductor device according to the present invention has the advantage of providing a highly reliable silicon carbide semiconductor device that can be easily formed and has a pressure-resistant structure that can stably ensure a predetermined withstand voltage. [Brief explanation of the drawing]

[0051] [Figure 1] This is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. [Figure 2] This is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. [Figure 3] This is a cross-sectional view (part 1) showing the state of a silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. [Figure 4]This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 1 in the process of manufacturing. [Figure 5] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 1. [Figure 6] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 2. [Figure 7] This is a cross-sectional view (part 1) showing the silicon carbide semiconductor device in the process of being manufactured according to Embodiment 2. [Figure 8] This is a cross-sectional view (part 2) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 9] This is a cross-sectional view (part 3) showing the silicon carbide semiconductor device according to Embodiment 2 in the process of manufacturing. [Figure 10] This is a characteristic diagram showing the results of a simulation of the pressure resistance characteristics of Example 1. [Figure 11] This is a characteristic diagram showing the results of a simulation of the pressure resistance characteristics of the comparative example. [Figure 12] This is a cross-sectional view showing the pressure-resistant structure of a comparative example. [Figure 13] This is a cross-sectional view showing the structure of a conventional silicon carbide semiconductor device. [Figure 14] This is a cross-sectional view showing the structure of a silicon carbide semiconductor device according to Embodiment 3. [Figure 15] This is a characteristic diagram showing the results of a simulation of the pressure resistance characteristics of Example 2. [Modes for carrying out the invention]

[0052] Preferred embodiments of the silicon carbide semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers or regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to n and p indicate higher and lower impurity concentrations, respectively, compared to layers or regions without these signs. In the following description of embodiments and in the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations are omitted.

[0053] (Embodiment 1) The structure of the silicon carbide semiconductor device according to Embodiment 1 will now be described. Figure 1 is a plan view showing the layout of the silicon carbide semiconductor device according to Embodiment 1 as seen from the front side of the semiconductor substrate. Figure 2 is a cross-sectional view showing the cross-sectional structure along the cutting line A-A' in Figure 1. The silicon carbide semiconductor device 10 according to Embodiment 1 shown in Figures 1 and 2 is a vertical MOSFET equipped with a trench gate structure (device structure) in the active region 1 of a semiconductor substrate (semiconductor chip) 40 made of silicon carbide (SiC), and a spatial modulation JTE structure 30 in the edge termination region 2.

[0054] The active region 1 is the region through which the main current (drift current) flows when the MOSFET is turned on. The active region 1 has a roughly rectangular planar shape and is located approximately in the center of the semiconductor substrate 40 (center of the chip). The active region 1 is described later as p ++ This is the portion from the outer edge (the edge (chip edge) side of the semiconductor substrate 40) to the inner (the central side of the semiconductor substrate 40) of the type contact extension portion 15a. In the central portion 1a of the active region 1, multiple unit cells (functional units of the element) of the same trench gate structure connected in parallel by the MOSFETs are arranged adjacent to each other.

[0055] The edge termination region 2 is the region between the active region 1 and the tip edge, and surrounds the active region 1 in a roughly rectangular shape. The breakdown voltage is the limit voltage at which the drain-source voltage does not increase further even if the drain-source current increases due to avalanche breakdown at the pn junction. A spatial modulation JTE structure 30 is provided in the edge termination region as a breakdown voltage structure. The spatial modulation JTE structure 30 has the function of maintaining the breakdown voltage by mitigating the electric field near the boundary between the active region 1 and the edge termination region 2. The configuration of the spatial modulation JTE structure 30 will be described later.

[0056] The semiconductor substrate 40 is made of n + n - The semiconductor substrate 40 is formed by epitaxially growing an n-type silicon carbide layer 42 which becomes a type drift region (first semiconductor region) 12. The main surface of the semiconductor substrate 40 with the silicon carbide layer 42 side is the front surface (first main surface), and n + The main surface on the mold starting substrate 41 side is designated as the back surface (second main surface). The front surface of the semiconductor substrate 40 is substantially flat throughout, and there is no step between the active region 1 and the edge termination region 2. Substantially flat means that it is a horizontal plane within the range that includes tolerances due to process variations.

[0057] n + The starting substrate 41 is n + This is a type drain region 11. The silicon carbide layer 42 is n - n is in the drift region 12. - This is an n-type epitaxial layer formed by sequentially stacking n-type silicon carbide layers 42a and 42b and an n-type silicon carbide layer 42c which becomes the first n-type surface region (fourth semiconductor region) 34. - The drift region 12 is n - These are the parts of the silicon carbide layers 42a and 42b where the impurity concentration remains the same as during epitaxial growth, without the formation of a diffusion region due to ion implantation. - The drift region 12 is n + It is in contact with the mold starting substrate 41 and extends from the active region 1 to the edge termination region 2.

[0058] The trench gate structure consists of a p-type base region (second semiconductor region) 13, n + Type source region (third semiconductor region) 14, p ++ It consists of a p-type contact region 15, a trench 16, a gate insulating film 17, and a gate electrode 18, and is located on the front side of the semiconductor substrate 40 in the central part 1a of the active region 1. + Type source region 14 and p ++ The n-type contact region 15 is a diffusion region formed by ion implantation inside the n-type silicon carbide layer 42c. The p-type base region 13 is formed in the active region 1 between the front surface of the semiconductor substrate 40 and the n-type - It is provided between the type drift region 12.

[0059] n + Type source region 14 and p ++ The type contact region 15 is selectively provided between the front surface of the semiconductor substrate 40 and the p-type base region 13, contacting the p-type base region 13 at its bottom (lower surface: the back edge of the semiconductor substrate 40) and exposed to the front surface of the semiconductor substrate 40 at its top (front edge of the semiconductor substrate 40). In the active region 1, exposure to the front surface of the semiconductor substrate 40 means contact with the source electrode 20 at the contact hole of the interlayer insulating film 19. + The type source region 14 is provided only in the central part 1a of the active region 1.

[0060] p-type base region 13 and p of the outermost unit cell ++ The type contact region 15 extends to the outer periphery 1b of the active region 1 and terminates at the boundary between the active region 1 and the edge termination region 2. p ++ Type contact region 15 (i.e., p ++ A type contact extension portion 15a) may be provided. In this case, in the central portion 1a of the active region 1, p ++ Instead of the type contact region 15, the p-type base region 13 extends to the front surface of the semiconductor substrate 40 and is exposed on the front surface of the semiconductor substrate 40.

[0061] In the central part 1a of the active region 1, n- An n-type current spreading region (not shown) may be provided between the p-type drift region 12 and the p-type base region 13. The n-type current spreading region is a so-called current spreading layer (CSL) that reduces the carrier spreading resistance. The n-type current spreading region is n - This is a diffusion region formed by ion implantation inside the n-type silicon carbide layers 42a and 42b. The n-type current diffusion region is n-type from the bottom surface of the trench 16. + It reaches a deep position on the drain region 11 side (the back side of the semiconductor substrate 40).

[0062] The n-type current diffusion region is in contact with the p-type base region 13 at its upper surface, and at its bottom, n - It is in contact with the n-type drift region 12. If an n-type current diffusion region is not provided, n - The upper surface of the type drift region 12 reaches the p-type base region 13. Also, the n-type current diffusion region (if the n-type current diffusion region is not provided, n - The n-type drift region 12) extends to the trench 16 in a direction parallel to the front surface of the semiconductor substrate 40 and contacts the gate insulating film 17. The n-type current diffusion region may extend to the outer periphery 1b of the active region 1 to the extent that it does not reach the spatial modulation JTE structure 30.

[0063] n - Between the p-type drift region 12 and the p-type base region 13, n is greater than the bottom surface of the trench 16. + Deep within the drain region 11, p + Type regions (second conductivity type high concentration regions) 21 and 22 are selectively provided. + Type regions 21 and 22 are n - This is a diffusion region formed by ion implantation inside the silicon carbide layers 42a and 42b. + The mold regions 21 and 22 have the function of mitigating the electric field applied to the gate insulating film 17 at the bottom surface of the trench 16. + Type regions 21 and 22 are n-type current diffusion regions and n - It is in contact with the drift region 12.

[0064] p +The p-type region 21 is provided apart from the p-type base region 13 and faces the bottom surface of the trench 16 in the depth direction. p + The p-type region 21 may be in contact with the gate insulating film 17 at the bottom surface of the trench 16. p + The p-type region 22 is provided between adjacent trenches 16, p + apart from the p-type region 21 and the trench 16, and is in contact with the p-type base region 13 at the upper surface. The p-type region 22 of the outermost unit cell + extends to the outer peripheral portion 1b of the active region 1 and terminates at the boundary between the active region 1 and the edge termination region 2.

[0065] The trench 16 penetrates the n-type source region 14 and the p-type base region 13 in the depth direction and reaches the n + -type drift region 12 (when an n-type current diffusion region is provided, it reaches the n-type current diffusion region). The trench 16 extends, for example, in a stripe shape in a direction parallel to the front surface of the semiconductor substrate 40 and reaches the outer peripheral portion 1b of the active region 1. Between adjacent trenches 16, the p-type base region 13, n - -type source region 14, p + -type contact region 15 and p ++ -type region 22 extend linearly in parallel with the longitudinal direction of the trench 16. + The trench 16 extends linearly in parallel with the longitudinal direction of the trench 16 at a position facing the bottom surface of the trench 16. Inside the trench 16, a gate electrode 18 is provided via a gate insulating film 17. All the gate electrodes 18 are electrically connected to a gate pad (electrode pad: not shown) via a gate polysilicon wiring layer 26 and a gate metal wiring layer (not shown).

[0066] Between adjacent trenches 16, p ++ -type contact region 15 may be scattered in the longitudinal direction of the trench 16. p + The p-type region 21 extends linearly in parallel with the longitudinal direction of the trench 16 at a position facing the bottom surface of the trench 16. Inside the trench 16, a gate electrode 18 is provided via a gate insulating film 17. All the gate electrodes 18 are electrically connected to a gate pad (electrode pad: not shown) via a gate polysilicon wiring layer 26 and a gate metal wiring layer (not shown).

[0067] The outer peripheral portion 1b of the active region 1 surrounds the central portion 1a of the active region 1 in a substantially rectangular shape. In the longitudinal direction of the trench 16, the outer peripheral portion 1b of the active region 1 is n +This refers to the portion from the outermost edge of the type source region 14 to the boundary between the active region 1 and the edge termination region 2. In the short direction of the trench 16, the outer periphery 1b of the active region 1 refers to the portion from the outermost side wall of the outermost trench 16 to the boundary between the active region 1 and the edge termination region 2.

[0068] The outer periphery 1b of the active region 1 has the front surface of the semiconductor substrate 40 and n - In the entire area between the type drift region 12, adjacent to each other in the depth direction from the front side of the semiconductor substrate 40, p ++ Type contact extension portion (third outer peripheral region) 15a, p-type base extension portion (first outer peripheral region) 13a and p + A mold extension portion (second outer peripheral region) 22a is provided. ++ Type contact extension 15a, p-type base extension 13a and p + The mold extension portion 22a is a diffusion region formed inside the silicon carbide layer 42 by ion implantation.

[0069] p ++ Type contact extension 15a, p-type base extension 13a and p + Each type-extended portion 22a is the p of the outermost unit cell of the central portion 1a of the active region 1. ++ Type contact area 15, p-type base area 13 and p + This is an extension of the type region 22, and it surrounds the central part 1a of the active region 1 in a roughly rectangular shape. ++ Type contact extension 15a, p-type base extension 13a and p + Both the outer end of the mold extension portion 22a terminates at approximately the same position in the normal direction from the inside to the outside (specifically, at the boundary between the active region 1 and the edge termination region 2).

[0070] The p-type base extension 13a is connected to the front surface of the semiconductor substrate 40 and n - Between the drift region 12 and n - It is provided in contact with the drift region 12. ++ The p-type contact extension portion 15a is provided between the front surface of the semiconductor substrate 40 and the p-type base extension portion 13a, in contact with the p-type base extension portion 13a. ++The type contact extension portion 15a is exposed on the front surface of the semiconductor substrate 40 and is in contact with the insulating layer on the front surface of the semiconductor substrate 40 (an insulating layer formed by laminating a field oxide film 25 and an interlayer insulating film 19 in that order).

[0071] p + The type extension portion 22a is formed from the p-type base extension portion 13a and n - These regions are provided in contact with the drift region 12. + In the mold extension portion 22a, all p + The longitudinal ends of type regions 21 and 22 are connected. ++ Type contact extension 15a, p-type base extension 13a and p + In the extended portion 22a, the outer peripheral portion 1b of the active region 1 is connected to the front surface of the semiconductor substrate 40. - A single p-type outer region (second conductivity type outer region) 24 is formed across the entire area between the type drift region 12 and the other region.

[0072] As described above, the p-type outer region 24 is composed of p ++ Type contact extension 15a, p-type base extension 13a and p + Both the p-type extension portion 22a and the outer end terminate at approximately the same position in the normal direction and lie on the same plane perpendicular to the front surface of the semiconductor substrate 40. That is, the outer end of the p-type outer peripheral region 24 is substantially perpendicular to the front surface of the semiconductor substrate 40 throughout its entire depth. The p-type outer peripheral region 24 has the function of making the electric field uniform in the plane of the front surface of the semiconductor substrate 40 in the outer peripheral portion 1b of the active region 1.

[0073] Furthermore, the p-type outer peripheral region 24 is the n-type of the edge termination region 2 when the MOSFET (silicon carbide semiconductor device 10) is turned off. - This region is for drawing out the hole (positive) current generated in the drift region 12 and flowing toward the active region 1 to the source electrode 20, and is electrically connected to the source electrode 20. When the MOSFET is off, the n of the edge termination region 2 -The Hall current generated in the p-type drift region 12 is drawn out to the source electrode 20 via the p-type outer peripheral region 24, thereby suppressing hole current concentration during avalanche breakdown in the edge termination region 2.

[0074] The interlayer insulating film 19 is provided over the entire surface of the front surface of the semiconductor substrate 40 and covers the gate electrode 18 and the gate polysilicon wiring layer 26. A field oxide film 25 is provided between the front surface of the semiconductor substrate 40 and the interlayer insulating film 19 in the outer periphery 1b and edge termination region 2 of the active region 1. The gate polysilicon wiring layer 26 is positioned between the field oxide film 25 and the interlayer insulating film 19 in the outer periphery 1b of the active region 1. The gate polysilicon wiring layer 26 surrounds the central part 1a of the active region 1.

[0075] A gate metal wiring layer (not shown) is provided on the gate polysilicon wiring layer 26 via contact holes in the interlayer insulating film 19. The gate polysilicon wiring layer 26 and the gate metal wiring layer constitute the gate runner. It is preferable that the structure directly beneath the gate runner is the same, and the front surface of the semiconductor substrate 40 and n - Only the p-type outer region 24 is located between the type drift region 12 and the other region. The gate runner is located inside the spatial modulation JTE structure 30 of the edge termination region 2.

[0076] The source electrode (first electrode) 20 is provided on the interlayer insulating film 19 so as to fill the contact holes in the interlayer insulating film 19. The source electrode 20 is located in the central part 1a of the active region 1 and is connected to the interlayer insulating film 19 through the contact holes provided in the interlayer insulating film 19. + Type source region 14 and p ++ Type contact area 15(p ++ If the type contact region 15 is not provided, ohmic contact is made with the p-type base region 13), and n + Type source area 14, p ++ Type contact area 15, p-type base area 13 and p + It is electrically connected to type regions 21 and 22.

[0077] The source electrode 20 is connected to the interlayer insulating film 19 via a contact hole in the outer peripheral portion 1b of the active region 1. ++ Ohmic contact is made with the type contact extension portion 15a, p ++ Type contact extension 15a, p-type base extension 13a and p + It is electrically connected to the mold extension portion 22a. The drain electrode (second electrode) 23 is on the back surface (n) of the semiconductor substrate 40. + The entire surface of the back surface of the mold starting substrate 41 is provided, n + Type drain region 11(n + Ohmic contact is made with the starting substrate 41), n + It is electrically connected to the drain region 11.

[0078] In the edge termination region 2, at a depth position away from the front surface of the semiconductor substrate 40, the front surface of the semiconductor substrate 40 and n - Between the drift region 12 and the spatial modulation JTE structure 30 are a plurality of p-type regions (second conductivity type breakdown region) 31 and a plurality of p - Each type region (second conductivity type breakdown region) 32 is selectively provided. The area between the front surface of the semiconductor substrate 40 and the spatial modulation JTE structure 30 is the first n-type surface region 34. - Between the type drift region 12 and the first n-type surface region 34, n + A channel stopper region (sixth semiconductor region) 33 is selectively provided.

[0079] p-type region 31 and p - Type region 32 is n - Inside the silicon carbide layer 42a (or in the depth direction n - n spans the silicon carbide layers 42a and 42b - This is a diffusion region formed by ion implantation inside the p-type silicon carbide layer 42a. Figure 2 shows the p-type region 31 and p -Each type region 32 is given a different hatching pattern. Multiple p-type regions 31 are arranged concentrically, spaced apart from each other, surrounding the active region 1. The p-type regions 31 located further out are narrower in width (width in the normal direction) and have a wider spacing between them and adjacent p-type regions 31 located further inside.

[0080] The innermost p-type region (first second conductivity type breakdown voltage region) 31 is p + Outside the mold extension portion 22a, p + It is positioned adjacent to the extended part 22a of the p-type region. The innermost p-type region 31 is located at the outer corner portion 24b (i.e., p) of the bottom of the p-type outer peripheral region 24. + It surrounds the outer corner portion 22b) of the bottom of the mold extension portion 22a. The inner end of the innermost p-type region 31 is preferably terminated outside the gate polysilicon wiring layer 26. The inner end of the innermost p-type region 31 is p + so as to overlap the mold extension portion 22a, p + It extends inward from the outer end of the mold extension portion 22a, p + The outer portion of the bottom of the mold extension 22a may also be enclosed.

[0081] multiple p - The type regions 32 are arranged concentrically around the active region 1, spaced apart from each other. The p regions are located on the outside. - Type region 32, narrow in width (width in the normal direction), and adjacent to each other inside p - The spacing with type region 32 is wide. The outermost p - The width of type region 32 is the width of adjacent p inside. - The width of the type region 32 may be wider. The innermost p - The type region 32 is positioned between all adjacent p-type regions 31, adjacent to the p-type regions 31 on both sides in the normal direction, and encloses the bottom corner portions of all p-type regions 31.

[0082] innermost p - The inner edge of type region 32 terminates either at the same position as the inner edge of the innermost p-type region 31, or outside the inner edge of the innermost p-type region 31. -The p-type region 32 extends outward beyond the outermost p-type region 31. - p other than type region 32 - The p-type region 32 is located outside the p-type region 31. All adjacent p - n between type region 32 - The drift region 12 extends, and both sides of p in the normal direction - It is adjacent to type region 32.

[0083] All p-type regions 31 and the innermost p - The p-type region 32 is fixed to the potential of the source electrode 20 via the p-type outer peripheral region 24. The innermost p-type region 31 (JTE region 30a) and the innermost p - The double-zone JTE structure is formed by the portion (JTE region) 30c that is outside the outermost p-type region 31 of the type region 32. The p-type region other than the JTE region 30a (second second conductivity type breakdown voltage region) 31 and the innermost p - The type region (third second conductivity type breakdown voltage region) 32 and the spatial modulation region (first spatial modulation region) 30b between the JTE regions 30a and 30c are formed. The innermost p - p other than type region 32 - Type region (fourth second conductivity type breakdown voltage region) 32 and n - A type drift region 12 and a spatial modulation region (second spatial modulation region) 30d adjacent to the outside of the JTE region 30c are formed.

[0084] The spatial modulation region 30b has two sub-regions (p-type region 31 and p-type region 31) with approximately the same impurity concentration as the adjacent regions (JTE regions 30a and 30c) on each side of it. - The spatial modulation region 30d is formed by repeatedly arranging adjacent regions (JTE regions 30c and n) alternately in a predetermined pattern. - Type drift region 12) and two small regions (p) with approximately the same impurity concentration - Type region 32 and n - The drift regions 12) are arranged alternately and repeatedly adjacent to each other in a predetermined pattern. The spatial impurity concentration distribution of the entire spatial modulation regions 30b and 30d is determined by the width and impurity concentration ratio of the two sub-regions.

[0085] The spatial modulation JTE structure 30 has a spatial modulation region 30b between adjacent JTE regions 30a and 30c, which has an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between these two regions, and the JTE region 30c and the n outside of it - A spatial modulation region 30d, which has an impurity concentration distribution spatially equivalent to the intermediate impurity concentration between these two regions, is placed between the type drift region 12 and the other region, resulting in a structure in which the overall p-type impurity concentration is gradually decreased from the inside to the outside. The spatial modulation JTE structure 30 is n - Type silicon carbide layer 42a (or n - It is positioned so as to be embedded inside the silicon carbide layers 42a and 42b).

[0086] Specifically, p-type region 31 and p - Each upper surface of the type region 32 is p + A position deeper from the front surface of the semiconductor substrate 40 than the upper surface of the mold extension portion 22a (n + It is located in a deep position on the side of the p-type drain region 11. The upper surface of the p-type region 31 and p - The top surface of the type region 32 is at approximately the same depth. "Approximately the same depth" means that it lies on the same plane parallel to the front surface of the semiconductor substrate 40, within a range that includes tolerances due to process variations. For example, p-type region 31 and p - The depth position of each upper surface of the mold region 32 is p + Lower part of mold extension portion 22a (n + The depth position of the upper surface of the part 52 (see Figures 3-5 described later) on the drain region 11 side may be approximately the same.

[0087] p-type region 31 and p - Each upper surface of the type region 32 and p + When the upper surface of the lower part 52 of the mold extension portion 22a is at approximately the same depth, - The p-type region formed in the type silicon carbide layer 42b is p + Upper part of type region 22 (n + (Part on the source region 14 side) and p +This applies only to the upper part 53 of the mold extension portion 22a (see Figures 3-5), and to other regions with the same impurity concentration as these areas. + No type region is formed. Therefore, the p of the conventional structure (see Figure 13) + Upper part and p of type region 122 + Using the same ion implantation mask pattern as used for forming the upper part of the mold extension portion 122a, the p of Embodiment 1 + Upper part of type region 22 and p + The upper part 53 of the mold extension portion 22a can be formed.

[0088] Also, p + Upper part of type region 22 and p + The ion implantation mask pattern for forming the upper part 53 of the mold extension portion 22a is p + Lower part of type region 22 and p + It is a simpler pattern compared to the ion implantation mask pattern used to form the lower part 52 of the mold extension portion 22a. Therefore, p + Upper part of type region 22 and p + The upper part 53 of the mold extension portion 22a can be formed in a self-aligned manner by appropriately using an ion implantation mask pattern for forming other regions. + Upper part of type region 22 and p + By forming the upper part 53 of the mold extension portion 22a in a self-aligned manner, the number of mask patterns can be reduced.

[0089] p + When the upper part of the type region 22 is formed in a self-aligned manner, p + The outer end of the mold extension portion 22a is oriented in the direction of the normal to p ++ This is the same position as the outer edges of the type contact extension 15a and the p-type base extension 13a. Therefore, among these regions, the p-type is located at the deepest position from the front surface of the semiconductor substrate 40. + The outer corner portion 22b at the bottom of the mold extension portion 22a becomes the electric field concentration point. In this embodiment 1, as will be described later, the innermost p-type region 31 can be arranged to surround the portion 22b.

[0090] p-type region 31 and p -Each bottom of the p-type region 32 is located deeper from the surface of the semiconductor substrate 40 than the bottom of the p-type outer peripheral region 24. The outer corner portion 24b of the bottom of the p-type outer peripheral region 24 (i.e., p + The outer corner portion 22b at the bottom of the extended shape portion 22a is surrounded by the innermost p-shaped region 31, and the n edge termination region 2 - It does not touch the p-type drift region 12. Therefore, when the MOSFET is off, it is possible to suppress the local concentration of the electric field at the outer corner portion 24b of the bottom of the p-type outer peripheral region 24. The bottom of the p-type region 31 and p - This is at approximately the same depth as the bottom of mold region 32.

[0091] The carrier concentration (concentration of activated impurities) in the p-type region 31 is higher than the carrier concentration in the p-type base extension 13a (i.e., the p-type base region 13), and p + Type extension portion 22a (i.e., p + It is lower than the carrier concentration in the type region 21,22). Specifically, in a typical MOSFET using silicon carbide as the semiconductor material, p ++ Type contact extension portion 15a (i.e., p ++ The carrier concentration in the contact area 15) is, for example, 1 × 10⁻⁶ 20 / cm 3 It is approximately such that the carrier concentration in the p-type base region 13 is, for example, 1 × 10⁻⁶. 17 / cm 3 It is to that extent.

[0092] p + The carrier concentration in type regions 21 and 22 is, for example, 1 × 10⁻⁶. 19 / cm 3 It is approximately as follows, roughly 10 18 / cm 3 It is approximately 10. The carrier concentration in the p-type region 31 is, for example, 10 17 / cm 3 It's somewhere between the first and second halves of the scale, more specifically 1.4 × 10 17 / cm 3 The above 1.0 × 10 18 / cm 3 It is less than p. -The carrier concentration in the p-type region 32 is approximately the same as that of the p-type base region 13. By appropriately adjusting the carrier concentration in the p-type region 31, the breakdown voltage of the edge termination region 2 can be stably ensured to be higher than or equal to that of the active region 1.

[0093] Stable breakdown voltage of edge termination region 2 means that even if the insulating layer (field oxide film 25 and interlayer insulating film 19) on the front surface of the semiconductor substrate 40 in edge termination region 2 becomes positively or negatively charged due to long-term operation of the silicon carbide semiconductor device 10, the breakdown voltage of edge termination region 2 does not fluctuate, and the breakdown voltage of edge termination region 2 is maintained at approximately the same level as the breakdown voltage of edge termination region 2 under normal conditions (zero charge) when neither positive nor negative charge is accumulated in the insulating layer.

[0094] Generally, the activation rate of impurities ion-implanted into the silicon carbide layer (= [concentration of activated impurities] / [concentration of ion-implanted impurities] × 100) is around 70% to 80%, so the concentration of ion-implanted impurities in each region is higher than its own carrier concentration. Specifically, for example, if the activation rate of the impurities is 70%, the carrier concentration in the p-type region 31 is 1.4 × 10⁻⁶. 17 / cm 3 To achieve this, the target impurity concentration in the p-type region 31 by ion implantation must be 2.0 × 10⁻⁶. 17 / cm 3 The above level (roughly 1.4 times the carrier concentration) should suffice.

[0095] n + The n-type channel stopper region 33 is a diffusion region formed by ion implantation in the surface region of the n-type silicon carbide layer 42c. + The channel stopper region 33 is located outside the spatial modulation JTE structure 30 and is separated from the spatial modulation JTE structure 30. + The channel stopper region 33 is exposed on the front surface of the semiconductor substrate 40 and is in contact with the insulating layer on the front surface of the semiconductor substrate 40 in the edge termination region 2. + The type channel stopper region 33 is exposed at the tip end.

[0096] n + The area between the type channel stopper region 33 and the p-type outer peripheral region 24 is the first n-type surface region 34. + The bottom of the type channel stopper region 33 is n - It may be in contact with the drift region 12. + The channel stopper region 33 has a floating potential. No field plate (FP) or channel stopper electrode is provided on the front surface of the semiconductor substrate 40 in the edge termination region 2. + Instead of the type channel stopper region 33, p + A channel stopper region may be provided.

[0097] The first n-type surface region 34 is the n-type silicon carbide layer 42c, n + The portion between the p-type channel stopper region 33 and the p-type outer peripheral region 24 is the portion where the impurity concentration from the time of epitaxial growth is retained. The first n-type surface region 34 is exposed on the front surface of the semiconductor substrate 40 and is in contact with the insulating layer on the front surface of the semiconductor substrate 40. The first n-type surface region 34 faces the entire area of ​​the spatially modulated JTE structure 30 in the depth direction. Between the first n-type surface region 34 and the spatially modulated JTE structure 30 is the n-type region where the silicon carbide layer 42 is retained at the impurity concentration from the time of epitaxial growth. - This is the drift region 12.

[0098] The first n-type surface region 34 is formed by epitaxially growing n instead of the n-type silicon carbide layer 42c. - n is in the drift region 12. - This may also be a diffusion region formed by ion implantation in the surface region of the n-type silicon carbide layer. In this case, the ion implantation depth (thickness) of the first n-type surface region 34 is p ++ The ion implantation depth may be shallower than that of the type contact extension portion 15a. The thickness t1 of the first n-type surface region 34 is preferably in the range of, for example, 0.1 μm to 0.2 μm, and is preferably as thin as possible.

[0099] The impurity concentration in the first n-type surface region 34 is n -Higher than the impurity concentration in the n-type drift region 12, for example, the impurity concentration in the n-type current diffusion region or the p-type region 31 or p of the spatial modulation JTE structure 30. - The impurity concentration in type region 32 may be approximately the same. Approximately the same impurity concentration means that the impurity concentration is the same within a range that includes tolerances due to process variations. The impurity concentration in the first n-type surface region 34 is n - By making the impurity concentration higher than that of the mold drift region 12, the breakdown voltage of the edge termination region can be stabilized.

[0100] By positioning the spatial modulation JTE structure 30 away from the front surface of the semiconductor substrate 40, the electric field on the front surface of the semiconductor substrate 40 in the edge termination region 2 is mitigated, improving the reliability of various parts of the front surface of the semiconductor substrate 40 that have low resistance to high electric fields, such as a surface protective film made of polyimide. The thinner the thickness t1 of the n-type region between the front surface of the semiconductor substrate 40 and the spatial modulation JTE structure 30, the higher the breakdown voltage of the edge termination region 2 can be.

[0101] The operation of the silicon carbide semiconductor device 10 according to Embodiment 1 will now be described. When a positive voltage (forward voltage) is applied to the drain electrode 23 relative to the source electrode 20, and a voltage greater than or equal to the gate threshold voltage is applied to the gate electrode 18, a channel (n-type inversion layer) is formed in the portion of the p-type base region 13 along the trench 16. As a result, n + Type drain region 11 to n - Type drift region 12 and through the channel n + A current flows towards the source region 14, and the MOSFET (silicon carbide semiconductor device 10) turns on.

[0102] On the other hand, when a forward voltage is applied between the source and drain, and a voltage less than the gate threshold voltage is applied to the gate electrode 18, the p-type base region 13, p + Type regions 21, 22 and p + mold extension portion 22a and n -The pn junction with the drift region 12 (the main junction of the active region 1) is reverse-biased, and the MOSFET remains in the off state. At this time, the n - As the depletion layer spreads within the drift region 12, the electric field applied to the gate insulating film 17 at the bottom of the trench 16 is relaxed.

[0103] Furthermore, when the MOSFET is off, the depletion layer is n of the edge termination region 2. - The amount that extends outward (towards the tip end) within the type drift region 12 ensures a predetermined withstand voltage based on the dielectric breakdown field strength of silicon carbide and the depletion layer width (width in the normal direction). In addition, the p-type region 31 and p of the spatial modulation JTE structure 30 - Because each bottom of the p-type region 32 is located deeper from the surface of the semiconductor substrate 40 than the bottom of the p-type outer peripheral region 24, the electric field can be concentrated at the bottom of the innermost p-type region 31 of the spatial modulation JTE structure 30 when the MOSFET is off.

[0104] The electric field concentrated in the innermost p-type region 31 is dispersed and relaxed outward throughout the entire spatial modulation JTE structure 30. Therefore, when the MOSFET is off, it is possible to suppress the local concentration of the electric field at the outermost edge of the main junction of the active region 1 (hereinafter referred to as the main junction edge). The main junction edge of the active region 1 is the outer corner portion 24b at the bottom of the p-type outer peripheral region 24. As a result, the avalanche yield withstand capability at the main junction edge of the active region 1 is improved, and the breakdown voltage of the edge termination region 2 can be suppressed.

[0105] Furthermore, because the spatial modulation JTE structure 30 is positioned at a depth away from the surface of the semiconductor substrate 40, the electric field on the surface of the semiconductor substrate 40 is mitigated when the MOSFET is turned off. In addition, by appropriately setting the impurity concentration of the p-type region 31 of the spatial modulation JTE structure 30, even if charge accumulates on the insulating layer on the surface of the semiconductor substrate 40 in the edge termination region 2 due to the long-term operation of the silicon carbide semiconductor device 10, the adverse effects of such charge can be reduced.

[0106] Next, a method for manufacturing the silicon carbide semiconductor device 10 according to Embodiment 1 will be described. Figures 3 to 5 are cross-sectional views showing the silicon carbide semiconductor device during the manufacturing process according to Embodiment 1. Figures 3 to 5 show one of the multiple chip regions 50a of the semiconductor wafer 50. Figures 3 to 5 show only the outer periphery 1b and edge termination region 2 of the active region 1 in Figure 2. For the central part 1a of the active region 1, refer to Figure 2. Multiple silicon carbide semiconductor devices 10 with the same element structure are fabricated in the multiple chip regions 50a of the semiconductor wafer 50.

[0107] The chip region 50a is a roughly rectangular, planar region that becomes a semiconductor chip (semiconductor substrate 40) after the semiconductor wafer 50 is diced (cut) along the dicing lines 50b, and multiple chip regions 50a are arranged in a matrix-like pattern in the center of the semiconductor wafer 50. Each chip region 50a is surrounded by groove-shaped dicing lines 50b formed on the front surface of the semiconductor wafer 50. The dicing lines 50b are formed in a grid pattern that surrounds each chip region 50a.

[0108] First, as shown in Figure 3, n + n + On the front surface of the mold starting wafer 51, n - n is in the drift region 12. - A type silicon carbide layer 42a is epitaxially grown. Next, photolithography and ion implantation of p-type impurities are performed in each chip region 50a. - In the surface region of the type silicon carbide layer 42a, the p of the central part 1a of the active region 1 + Type region 21 and the central part 1a of the active region 1 + The lower part of type region 22 and the outer peripheral part 1b of active region 1 + The lower part 52 of the mold extension portion 22a and the other part are formed simultaneously and selectively.

[0109] Photolithography and ion implantation of p-type impurities were performed in the edge termination region 2 of each chip region 50a. -On the surface region of the p-type silicon carbide layer 42a, a plurality of p-type regions 31 of the spatially-modulated JTE structure 30 are selectively formed. By photolithography and ion implantation of p-type impurities, in the edge termination region 2 of each chip region 50a, n - On the surface region of the p-type silicon carbide layer 42a, a plurality of p - type regions 32 of the spatially-modulated JTE structure 30 are selectively formed. The p-type regions 31 and p - type regions 32 are formed deeper than the lower part 52 of the p + type extension part 22a.

[0110] The p-type regions 31 and p - type regions 32 are formed at a timing different from that of the formation of the diffusion regions (p - type regions 21, p + type regions 22 at the lower part, and p + type extension part 22a at the lower part 52) in the n + type silicon carbide layer 42a in the active region 1 by ion implantation. The p-type regions 31 and p - type regions 32 are formed at different timings. The order of performing the formation of the diffusion region in the n - type silicon carbide layer 42a in the active region 1, the formation of the p-type regions 31, and the formation of the p - type regions 32 can be changed as appropriate.

[0111] Next, as shown in FIG. 4, on the n - type silicon carbide layer 42a, an n - type silicon carbide layer 42b serving as the n - type drift region 12 is epitaxially grown. Next, by photolithography and ion implantation of p-type impurities, in each chip region 50a, on the n - type silicon carbide layer 42b, the upper part of the p + type region 22 and the upper part 53 of the p + type extension part 22a are selectively formed simultaneously. At this time, the upper and lower parts of the p + type region 22 are connected in the depth direction. The upper part 53 and the lower part 52 of the p + type extension part 22a are connected in the depth direction.

[0112] In the edge termination region 2, n- No ion implantation (nothing is formed) is performed on the n-type silicon carbide layer 42b.n - The portions of the n-type and p-type silicon carbide layers 42a and 42b that remain at the impurity concentration during epitaxial growth without ion implantation become the n - type drift region 12. In the edge termination region 2, the n - type drift region 12 that remains as the n - type silicon carbide layer 42b covers all the p-type regions 31 and all the p - type regions 32. The upper part of the p + type region 22 and the upper part 53 of the p + type extension 22a may be formed self-aligned using an ion implantation mask for forming other regions.

[0113] Next, as shown in FIG. ⑤, an n-type silicon carbide layer 42c that becomes the first n-type surface region 34 is epitaxially grown on the n-type silicon carbide layer 42b. In the steps up to this point, an n - type semiconductor wafer 50 with a predetermined thickness in which n-type silicon carbide layers 42 (42a to 42c) are stacked on the n-type starting wafer 51 is completed. When forming an n-type current diffusion region (not shown), an n + type silicon carbide layer 42a, 42b may be epitaxially grown, and the lower and upper parts of the n-type current diffusion region may be formed in the entire active region 1, respectively. - type silicon carbide layers 42a, 42b, respectively. - type silicon carbide layers 42a, 42b may be formed in the lower and upper parts of the n-type current diffusion region over the entire active region 1, respectively.

[0114] Next, by photolithography and ion implantation of p-type impurities, a p-type base region 13 and a p-type base extension 13a are simultaneously formed in the n-type silicon carbide layer 42c in the active region 1 of each chip region 50a. The p-type base region 13 and the p-type base extension 13a are connected to the p + type region 22 and the p + type extension 22a in the depth direction, respectively. By photolithography and ion implantation of n-type impurities, an n + type source region 14 is selectively formed on the surface region of the n-type silicon carbide layer 42c in the active region 1 of each chip region 50a.

[0115] By photolithography and ion implantation of p-type impurities, p-type impurities were implanted in the surface region of the n-type silicon carbide layer 42c in the active region 1 of each chip region 50a. ++ Type contact area 15 and p ++ The type contact extension portion 15a is formed simultaneously and selectively. As a result, the outer peripheral portion 1b of the active region 1 of each chip region 50a is connected to the front surface of the semiconductor wafer 50. - In the entire region between the type drift region 12, p ++ Type contact extension 15a, p-type base extension 13a and p + The p-type outer peripheral region 24 is formed by the mold extension portion 22a.

[0116] By photolithography and ion implantation of n-type impurities, the surface region of the n-type silicon carbide layer 42c in the edge termination region 2 of each chip region 50a spans across the edges of adjacent chip regions 50a. + A type channel stopper region 33 is selectively formed. + The channel stopper region 33 is n + The type source region 14 may be formed at the same time. The portion of the n-type silicon carbide layer 42c that is not ion-implanted and remains at the same impurity concentration as during epitaxial growth becomes the first n-type surface region 34.

[0117] Instead of the n-type silicon carbide layer 42c, n - n is in the drift region 12. - The silicon carbide layer is epitaxially grown, and the n - A first n-type surface region 34 may be formed by ion implantation of n-type impurities into the silicon carbide layer. Next, a heat treatment is performed to activate the ion-implanted impurities in the silicon carbide layer 42. This heat treatment for impurity activation may be performed each time impurities are ion-implanted into the silicon carbide layers 42a to 42c.

[0118] Next, a trench 16, a gate insulating film 17, and a gate electrode 18 are formed in the central portion 1a of the active region 1 of each chip region 50a using a general method. A field oxide film 25 and a gate polysilicon wiring layer 26 are formed in the outer peripheral portion 1b of the active region 1 of each chip region 50a using a general method. The gate electrode 18 and the gate polysilicon wiring layer 26 may be formed simultaneously. Next, an interlayer insulating film 19 is formed over the entire surface of the front surface of the semiconductor wafer 50.

[0119] Next, the source electrode 20, gate pad, gate metal wiring layer (not shown), passivation film (surface protective film: not shown), and drain electrode 23 are formed using a general method. Then, the portion of the passivation film on the dicing line 50b is removed. After that, the semiconductor wafer 50 is diced along the dicing line 50b to separate the chip region 50a into individual semiconductor chips (semiconductor substrate 40), thereby completing the silicon carbide semiconductor device 10 shown in Figures 1 and 2.

[0120] As described above, according to Embodiment 1, a spatial modulation JTE structure is provided as a voltage-resistant structure in the edge termination region. The spatial modulation JTE structure has its upper surface at a depth away from the front surface of the semiconductor substrate, n - n constitutes the drift region of type - It is positioned so as to be embedded inside the silicon carbide layer. This reduces the electric field on the surface of the semiconductor substrate, and suppresses the electric field acting on parts of the semiconductor substrate that have low resistance to high electric fields, thereby improving reliability. In addition, it suppresses voltage fluctuations caused by charge accumulation in the insulating layer on the surface of the semiconductor substrate during long-term operation of the silicon carbide semiconductor device.

[0121] Furthermore, the bottom of the spatially modulated JTE structure is located deeper from the surface of the semiconductor substrate than the bottom of the p-type outer region on the outer periphery of the active region. For this reason, the most n is near the main junction edge of the active region. + The innermost p-type region of the spatial modulation JTE structure is located deep within the drain region. insideThe p-type region surrounds the outer corner of the bottom of the p-type outer peripheral region (the main junction end of the active region). This allows the electric field to be concentrated at the bottom of the innermost p-type region of the spatial modulation JTE structure when the silicon carbide semiconductor device is off, and the electric field concentrated at the bottom of this p-type region is then dispersed and relaxed outward throughout the entire spatial modulation JTE structure.

[0122] Therefore, even if the outer edge of the p-type outer periphery region at the outer edge of the active region is substantially perpendicular to the surface of the semiconductor substrate throughout its entire depth, the spatially modulated JTE structure can suppress the occurrence of avalanche yield at the outer corner of the bottom of the p-type outer periphery region (the main junction end of the active region). This suppresses a decrease in breakdown voltage in the edge termination region and prevents the breakdown voltage of the edge termination region from becoming lower than the breakdown voltage of the active region. As a result, the breakdown voltage of the silicon carbide semiconductor device can be determined by the breakdown voltage of the active region, thereby improving reliability.

[0123] Furthermore, according to Embodiment 1, n - n is the drift region of type - Ion implantation is performed as needed each time the silicon carbide layer is epitaxially grown in multiple stages to form the device structure of the active region. At this time, in the edge termination region, n is at the same depth position as the spatially modulated JTE structure. - By appropriately implanting ions into the silicon carbide layer, a spatially modulated JTE structure can be easily formed without changing the method of forming the device structure of the active region. Furthermore, a spatially modulated JTE structure can be constructed by forming a p-type region with a different impurity concentration from the p-type region at a different timing than the formation of the p-type region of the active region.

[0124] Furthermore, by appropriately adjusting the normal position, normal width, thickness, and depth of the p-type region constituting the spatial modulation JTE structure, the predetermined withstand voltage of the edge termination region can be ensured. In the p-type region constituting the spatial modulation JTE structure, the normal position and normal width can be easily adjusted by appropriately setting the ion implantation mask pattern, and the thickness and depth are at the same depth as the spatial modulation JTE structure. -The silicon carbide layer can be easily adjusted by appropriately implanting ions into it. Therefore, it is possible to provide a highly reliable silicon carbide semiconductor device that can be easily formed and has a pressure-resistant structure that can stably ensure a predetermined pressure resistance.

[0125] (Embodiment 2) Next, the structure of the silicon carbide semiconductor device according to Embodiment 2 will be described. Figure 6 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 2. The layout of the silicon carbide semiconductor device 60 according to Embodiment 2, as viewed from the front side of the semiconductor substrate 40, is the same as in Figure 1. Figure 6 shows the cross-sectional structure along the cutting line A-A' in Figure 1. The silicon carbide semiconductor device 60 according to Embodiment 2 differs from the silicon carbide semiconductor device 10 according to Embodiment 1 (see Figure 2) in the following two points.

[0126] The first difference is that at the outer edge of the p-type outer peripheral region 65 of the outer peripheral portion 1b of the active region 1, multiple steps are formed that are recessed inward in stages with predetermined widths w1, w2, and w3, as they move away from the surface of the semiconductor substrate 40 in the depth direction. The p-type outer peripheral region 65 is the same as the surface of the semiconductor substrate 40. - p adjacent in the depth direction between the drift region 12 and the type drift region 12 ++ Type contact extension 15a, p-type base extension 64 and p + It is composed of a mold extension portion 61. ++ The outer end of the type contact extension 15a is located at the boundary between the active region 1 and the edge termination region 2.

[0127] The outer end of the p-type base extension 64 is p ++ It terminates inside the outer end of the type contact extension 15a. + The outer end of the upper part 63 of the mold extension 61 terminates inward from the outer end of the p-type base extension 64. + The outer end of the lower part 62 of the mold extension 61 is p + The mold extension portion 61 terminates inside the outer end of the upper part 63. p-type base extension portion 64 and p +The configuration of the mold extension portion 61, other than the position of the outer end, is the same as that of the p-type base extension portion 13a and p in Embodiment 1. + This is the same as the mold extension portion 22a.

[0128] The widths w1, w2, and w3 of the steps at the outer ends of the p-type base extension 64 should preferably be, for example, 2 μm or more. The widths w1, w2, and w3 of the steps at the outer ends of the p-type base extension 64 are, respectively, p ++ The width in the normal direction from the outer end of the type contact extension 15a to the outer end of the p-type base extension 64, and the distance from the outer end of the p-type base extension 64 to the p + The width in the normal direction from the upper part 63 of the mold extension 61 to the outer end, and p + From the outer end of the upper part 63 of the mold extension 61 to p + This is the width in the normal direction from the lower end 62 of the mold extension portion 61 to its outer end.

[0129] The second difference is that the spatial modulation JTE structure 70 consists of multiple p-type regions 71 and multiple p - The depth position of each bottom of the type region 72 is the bottom of the p-type outer peripheral region 65 (i.e., p + This is a point shallower than the depth position of the bottom of the type extension portion 61. The p-type region 71 and p of the spatial modulation JTE structure 70 - The layout of the type region 72 as viewed from the front side of the semiconductor substrate 40 (i.e., its position and width in the normal direction) is the same as that of the p-type region 31 and p-type region 31 of the spatial modulation JTE structure 30 of Embodiment 1. - This is similar to type region 32.

[0130] The spatial modulation JTE structure 70, similar to Embodiment 1, has JTE regions 70a, 70b, 70c, and 70d arranged sequentially in the normal direction from the inside out, with the overall p-type impurity concentration gradually decreasing from the inside out. The configuration of the spatial modulation JTE structure 70, other than the depth positions of the JTE regions 70a, 70c and spatial modulation regions 70b, 70d, is the same as that of the JTE regions 30a, 30c and spatial modulation regions 30b, 30d of the spatial modulation JTE structure 30 of Embodiment 1, respectively.

[0131] The spatially-modulated JTE structure 70 is disposed so as to be embedded inside the n-type silicon carbide layer 42c or across the n-type silicon carbide layer 42c and the n - type silicon carbide layer 42b, inside the silicon carbide layer 42. The p-type region 71 and the p - type region 72 of the spatially-modulated JTE structure 70 are disposed at a depth position away from the front surface of the semiconductor substrate 40 in the edge termination region 2, and the bottom is at a depth position shallower than the bottom of the p-type outer peripheral region 65 from the front surface of the semiconductor substrate 40. The innermost p-type region 71 extends inward such that the bottom contacts the p-type outer peripheral region 65.

[0132] As described above, among the p ++ type contact extension portion 15a, the p-type base extension portion 64, and the p + type extension portion 61 that form the p-type outer peripheral region 65 at the outer peripheral portion 1b of the active region 1, the p ++ type contact extension portion 15a closest to the front surface side of the semiconductor substrate 40 is extended to the outermost side. In this way, the outer corner portion 15b at the bottom of the p ++ type contact extension portion 15a is set as an electric field concentration point, and the electric field applied to the portion 15b is relaxed by the spatially-modulated JTE structure 70 adjacent to the outside of the outer corner portion 15b at the bottom of the p ++ type contact extension portion 15a.

[0133] Specifically, the innermost p-type region 71 is disposed outside the p ++ type contact extension portion 15a and the p-type base extension portion 64, adjacent to these regions. The innermost p-type region 71 contacts the outer corner portion 15b at the bottom of the p ++ type contact extension portion 15a or surrounds the outer corner portion 15b at the bottom of the p ++ type contact extension portion 15a. The electric field applied to the outer corner portion 15b at the bottom of the p ++ type contact extension portion 15a is dispersed from the innermost p-type region 71 adjacent to the outside thereof to the whole of the spatially-modulated JTE structure 70 toward the outside.

[0134] The innermost p-type region 71 may further surround the outer corner portion of the bottom of the p-type base extension 64. In this case, the innermost p-type region 71 is p ++ Type contact extension 15a, p-type base extension 64 and p + It is located outside the extended p-type portion 61, adjacent to these regions. The innermost end of the innermost p-type region 71 is p ++ Type-type contact extension 15a and p-type base extension 64 (if the innermost p-type region 71 surrounds the outer corner portion of the bottom of the p-type base extension 64, then further p + It may extend inward so as to overlap the mold extension portion 61).

[0135] p-type region 71 and p - Each upper surface of the type region 72 is p ++ The bottom of the type contact extension portion 15a is at approximately the same depth position (i.e., p ++ The bottom of the type contact extension portion 15a is approximately flush with the surface, or at a depth away from the front surface of the semiconductor substrate 40, and p ++ It is located at a depth shallower from the surface of the semiconductor substrate 40 than the bottom of the p-type contact extension portion 15a. The depth position of the upper surface of the p-type region 71 and p - The depth position of the upper surface of the type region 72 is approximately the same. The area between the semiconductor substrate 40 and the spatially modulated JTE structure 70 is the first n-type surface region 34.

[0136] The impurity concentration in the p-type outer peripheral region 65, in the portion deeper from the surface of the semiconductor substrate 40 than the spatial modulation JTE structure 70, is, for example, 1 × 10⁻⁶. 19 / cm 3 The extent is as follows. Specifically, p-type region 71 and p - Each bottom of the p-type region 72 is the bottom of the p-type outer region 65 (i.e., p + It is located at a shallower depth from the front surface of the semiconductor substrate 40 than the bottom of the lower part 62 of the mold extension portion 61. + The outer corner portion of the bottom of the lower part 62 of the mold extension portion 61 is n - It is surrounded by a type drift region 12.

[0137] p-type region 71 and p -Each bottom of type region 72 is p + The bottom of the upper part 63 of the mold extension portion 61 may be located at a shallower depth from the front surface of the semiconductor substrate 40 than the bottom of the upper part 63. In this case, further, p + The outer corner portion of the bottom of the upper part 63 of the mold extension portion 61 is n - Surrounded by the p-type drift region 12. p-type region 71 and p - Each bottom of the mold region 72 may be located at a shallower depth from the surface of the semiconductor substrate 40 than the bottom of the p-type base extension 64. In this case, further, the outer corner portion of the bottom of the p-type base extension 64 may be n - It is surrounded by a drift region 12.

[0138] The depth position of the bottom of the p-type region 71 and p - The depth position at the bottom of the mold region 72 is approximately the same. As mentioned above, p + The lower part 62 of the type extension 61 is located deeper from the surface of the semiconductor substrate 40 than the spatial modulation JTE structure 70, p + p adjacent to the lower part 62 of the mold extension portion 61 (on the front side of the semiconductor substrate 40) + The mold extension portion 61 terminates inside the outer end of the upper part 63. Therefore, p + This makes it possible to suppress the application of a localized electric field to the outer corner portion of the bottom of the lower part 62 of the mold extension 61.

[0139] p + Even when the upper part 63 of the type extension portion 61 is located deeper from the surface of the semiconductor substrate 40 than the spatial modulation JTE structure 70, as described above, p + The upper part 63 of the mold extension portion 61 is p + The extension of the molded extension 61 terminates inward from the outer end of the p-shaped base extension 64, which is adjacent to the upper layer of the upper part 63 of the molded extension 61. Therefore, p + This makes it possible to suppress the application of a localized electric field to the outer corner portion of the bottom of the upper part 63 of the mold extension 61.

[0140] Even if the p-type base extension 64 is located deeper from the surface of the semiconductor substrate 40 than the spatial modulation JTE structure 70, as described above, the p-type base extension 64 is adjacent to the upper layer of the p-type base extension 64. ++ The extension of the type contact portion 15a terminates inward from its outer end. Therefore, it is possible to suppress the application of a localized electric field to the outer corner portion of the bottom of the p-type base extension portion 64.

[0141] A method for manufacturing the silicon carbide semiconductor device 60 according to Embodiment 2 will now be described. Figures 7 to 9 are cross-sectional views showing the silicon carbide semiconductor device during the manufacturing process according to Embodiment 2. Figures 7 to 9 show one of the multiple chip regions 50a of the semiconductor wafer 50. Figures 7 to 9 show only the outer periphery 1b and edge termination region 2 of the active region 1 in Figure 6. Refer to Figure 6 for the central part 1a of the active region 1. Multiple silicon carbide semiconductor devices 60 with the same element structure are fabricated in the multiple chip regions 50a of the semiconductor wafer 50.

[0142] The manufacturing method for the silicon carbide semiconductor device 60 according to Embodiment 2 differs from the manufacturing method for the silicon carbide semiconductor device 10 according to Embodiment 1 in the timing of forming the spatial modulation JTE structure 70. Here, the p-type region 71 and p of the spatial modulation JTE structure 70 - The type region 72 has a top surface p ++ The bottom of the type contact extension 15a is positioned at a shallower depth from the front surface of the semiconductor substrate 40 than the bottom of the p-type base extension 64, and the bottom is positioned deeper from the front surface of the semiconductor substrate 40 than the bottom of the p-type base extension 64, and p + The depth position is shallower than the bottom of the upper part 63 of the mold extension portion 61.

[0143] Specifically, as shown in Figure 7, similar to Embodiment 1, n - n is in the drift region 12. - From the process of epitaxially growing the type silicon carbide layer 42a, n - In the type silicon carbide layer 42a, the p of the active region 1 + Type region 21 and p + The process is carried out sequentially until the lower part of the mold region 22 is formed.+ Type region 21 and p + The lower part of type region 22 and simultaneously, n - P + The lower part 62 of the mold extension portion 61 is formed. + The outer end of the lower part 62 of the mold extension 61 is terminated inside the boundary between the active region 1 and the edge termination region 2. n - No ion implantation is performed on the silicon carbide layer 42a (nothing is formed).

[0144] Next, as shown in Figure 8, n - n is in the drift region 12. - From the process of epitaxially growing the type silicon carbide layer 42b, n - In the type silicon carbide layer 42b, the p of the active region 1 + The process is carried out sequentially until the upper part of the mold region 22 is formed. + The upper part of type region 22 and simultaneously, n - P + The upper part 63 of the mold extension portion 61 is formed. + The outer end of the upper part 63 of the mold extension 61 is p + The extended portion 61 extends outward beyond the outer end of the lower part 62 (extended portion), p + A step is formed between the outer end of the lower part 62 of the mold extension 61 and the inner side, recessed by a predetermined width w3.

[0145] Furthermore, by photolithography and ion implantation of p-type impurities, n - The lower part 71a of multiple p-type regions 71 of the spatially modulated JTE structure 70 is selectively formed on the surface region of the type silicon carbide layer 42b. By photolithography and ion implantation of p-type impurities, n - Multiple p of the spatially modulated JTE structure 70 are present in the surface region of the silicon carbide layer 42b. - The lower part 72a of the mold region 72 is selectively formed.

[0146] lower part 71a and p of p-type region 71 -The lower part 72a of type region 72 is n in active region 1 - The diffusion region formed by ion implantation within the silicon carbide layer 42b is formed at a different timing than p + It is made shallower than the upper part 63 of the mold extension 61. The lower part 71a of the p-type region 71 and p - n in the active region 1 is formed at a different timing than the lower part 72a of the type region 72. - Formation of a diffusion region within the type silicon carbide layer 42b, and formation of the lower part 71a of the p-type region 71, - The order in which the lower part 72a of the mold region 72 is formed can be changed as appropriate.

[0147] Next, as shown in Figure 9, similar to Embodiment 1, n - An n-type silicon carbide layer 42c, which will become the first n-type surface region 34, is epitaxially grown on the n-type silicon carbide layer 42b to complete the semiconductor wafer 50. Next, similar to Embodiment 1, the p-type base region 13, the p-type base extension 13a, and n-type silicon carbide layer 42c are formed on the surface region of the active region 1. + Type source area 14, p ++ Type contact area 15 and p ++ The type contact extension portion 15a and the n edge termination region 2 + A channel stopper region 33 is selectively formed, and the other is also selectively formed.

[0148] The outer end of the p-type base extension 13a is p + The extended portion 61 extends outward beyond the outer end of the upper part 63 (extended portion), p + A step is formed between the outer end of the upper part 63 of the mold extension 61 and the inner side, recessed by a predetermined width w2. ++ The outer end of the type contact extension 15a is terminated at the boundary between the active region 1 and the edge termination region 2 (first extension), forming a step recessed inward by a predetermined width w1 between it and the outer end of the p-type base extension 13a. ++ The distance from the outer end of the type contact extension portion 15a to the outer end of the p-type base extension portion 64 is set to a predetermined width w1.

[0149] As a result, the outer peripheral portion 1b of the active region 1 of each chip region 50a is connected to the front surface of the semiconductor wafer 50 and n - Between the type drift region 12, p ++ Type contact extension 15a, p-type base extension 64 and p + A p-type outer peripheral region 65 is formed by the mold extension portion 61. At the outer edge of the p-type outer peripheral region 65, steps are formed that are recessed inward in stages with predetermined widths w1, w2, and w3, as they move away from the surface of the semiconductor substrate 40 in the depth direction.

[0150] Furthermore, by photolithography and ion implantation of p-type impurities, the upper parts 71b of multiple p-type regions 71 of the spatially modulated JTE structure 70 are selectively formed inside the n-type silicon carbide layer 42c in the edge termination region 2 of each chip region 50a. In the upper part 71b of the innermost p-type region 71, p ++ It surrounds the outer corner portion of the bottom of the type contact extension portion 15a. By photolithography and ion implantation of p-type impurities, multiple p-type silicon carbide layers 42c are implanted within the edge termination region 2 of each chip region 50a, forming a spatially modulated JTE structure 70. - The upper part 72b of the mold region 72 is selectively formed.

[0151] Upper part 71b and p of the p-type region 71 of the spatially modulated JTE structure 70 - The upper part 72b of the type region 72 is formed at a depth position away from the front surface of the semiconductor wafer 50, and the lower part 71a and p of the lower p-type region 71 in the depth direction, respectively. - It is connected to the lower part 72a of the type region 72. The portion of the n-type silicon carbide layer 42c with a predetermined thickness t2 that remains at the same impurity concentration as during epitaxial growth without ion implantation between the front surface of the semiconductor substrate 40 and the spatially modulated JTE structure 70 becomes the first n-type surface region 34.

[0152] upper part 71b and p of p-type region 71 - The upper part 72b of the type region 72 is formed at a different timing than the formation of the diffusion region by ion implantation in the n-type silicon carbide layer 42c in the active region 1. The upper part 71b of the p-type region 71 and p -It is formed at a different timing than the upper part 72b of the type region 72. Formation of the diffusion region within the n-type silicon carbide layer 42c in the active region 1, and formation of the upper part 71b of the p-type region 71, and p - The order in which the upper part 72b of the mold region 72 is formed can be changed as appropriate.

[0153] Subsequently, similar to Embodiment 1, the silicon carbide semiconductor device 60 shown in Figure 6 is completed by sequentially performing the steps from the heat treatment for impurity activation onward.

[0154] As described above, according to Embodiment 2, a step is formed at the outer edge of the p-type outer peripheral region of the outer peripheral of the active region, which is recessed inward by a predetermined width in stages as it moves away from the surface of the semiconductor substrate. Therefore, even if the bottom of the spatial modulation JTE structure is at a shallower depth from the surface of the semiconductor substrate than the bottom of the p-type outer peripheral region, the same effects as in Embodiment 1 can be obtained.

[0155] (Example 1) The breakdown voltage characteristics of the silicon carbide semiconductor device 60 according to the above-described embodiment 2 (hereinafter referred to as Example 1: see Figure 6) were verified. Figures 10 and 11 are characteristic diagrams showing the simulation results of the breakdown voltage characteristics of Example 1 and the comparative example, respectively. The horizontal axis of Figures 10 and 11 represents the amount of aluminum (Al) ion implantation dose (JTE dose) required to form the p-type regions 71 and 201 of the spatially modulated JTE structures 70 and 200 for Example 1 and the comparative example, respectively. The vertical axis of Figures 10 and 11 represents the breakdown voltage of the edge termination region 2 for Example 1 and the comparative example, respectively.

[0156] Figures 10 and 11 show three results: when the insulating layer (field oxide film 25 and interlayer insulating film 19) on the front surface of the semiconductor substrate 40 becomes positively charged (accumulates positive charge) due to long-term operation of the MOSFET (Example 1 and Comparative Example); when the insulating layer becomes negatively charged (accumulates negative charge) due to long-term operation of the MOSFET; and when the insulating layer is uncharged (zero charge). Figure 12 is a cross-sectional view showing the breakdown voltage structure of the Comparative Example.

[0157] In Example 1, the upper surface of the spatial modulation JTE structure 70 (p-type region 71 and p - (Each upper surface of type region 72) ++ The bottom of the type contact extension 15a is at the same depth position, and the bottom of the spatial modulation JTE structure 70 is at p + The position of the active region 1 was shallower from the front surface of the semiconductor substrate 40 than the bottom of the lower part 62 of the mold extension 61, and deeper from the front surface of the semiconductor substrate 40 than the bottom of the p-type base extension 64. The withstand voltage of the active region 1 was set to 1600V.

[0158] The difference between Comparative Example 210 shown in Figure 12 and Example 1 is that the first n-type surface region 34 is not provided, and the upper surface of the spatial modulation JTE structure 200 (p-type region 201 and p - The key feature is that each upper surface of the mold region 202 is exposed on the front surface of the semiconductor substrate 40. The layout of the spatial modulation JTE structure 200 of Comparative Example 210, as viewed from the front surface side of the semiconductor substrate 40 (i.e., the position and width in the normal direction), is the same as that of the spatial modulation JTE structure 70 of Example 1.

[0159] Conventional silicon carbide semiconductor device 110 (hereinafter referred to as the conventional example: see Figure 13) has p ++ Type contact extension 115a, p-type base extension 113a and p + The outer edge of the p-type peripheral region formed by the type extension portion 122a is perpendicular to the front surface of the semiconductor substrate 140, and the upper surface (p-type region 131 and p) is on the front surface of the semiconductor substrate 140. - It comprises a spatial modulation JTE structure 130 with each upper surface of the mold region 132 exposed.

[0160] The layout of the conventional spatial modulation JTE structure 130 as viewed from the front side of the semiconductor substrate 140 is the same as that of the spatial modulation JTE structure 70 in Example 1. The simulation results of the conventional example are not shown, but in the conventional example, p + It was confirmed that the electric field concentrates at the outer corner portion 122b of the bottom of the type region 122 (the outer corner portion of the bottom of the p-type outer peripheral region), causing the breakdown voltage of the edge termination region 102 to decrease and become lower than the breakdown voltage of the active region 101.

[0161] On the other hand, as shown in Figure 11, in the comparative example, steps were formed at the outer edge of the p-type outer peripheral region 65 of the outer peripheral portion 1b of the active region 1, with steps of predetermined widths w1, w2, and w3 that gradually move inward in the depth direction as they move away from the surface of the semiconductor substrate 40. This resolved the problem that occurred in the conventional example (suppressing the breakdown voltage of the edge termination region 2), and it was confirmed that the breakdown voltage of the edge termination region 2 could be made slightly higher than that of the active region 1. The carrier concentration of the p-type region 201 of the spatially modulated JTE structure 200 was 1 × 10⁻⁶. 17 / cm 3 The above 2.8 × 10 17 / cm 3 When the following range B2 was observed, the breakdown voltage of the edge termination region 2 stabilized at a breakdown voltage equal to or greater than the breakdown voltage of the active region 1, regardless of whether the insulating layer on the front surface of the semiconductor substrate 40 was charged or not.

[0162] However, in the comparative example, the difference between the breakdown voltage of edge-terminal region 2 and the breakdown voltage of active region 1 is small, and if the breakdown voltage of active region 1 is ensured to be high due to other factors, there is a risk that avalanche yielding will occur in edge-terminal region 2, causing the breakdown voltage of edge-terminal region 2 to be lower than that of active region 1. For this reason, it is unreliable against avalanche yielding. The numerical range of the carrier concentration in the p-type region 201 of the spatially modulated JTE structure 200 described above is the numerical range when the activation rate of the aluminum ion-implanted to form the p-type region 201 is 100%. Here, the carrier concentration of p-type region 201 [ / cm³] 3 Regarding ], since the thickness of the JTE is approximately 0.5 μm, the horizontal axis of Figure 11 represents the JTE dose [ / cm 2 ] to 2 × 10 4 It is considered to be roughly the same as the value doubled.

[0163] In contrast, the results shown in Figure 10 confirm that in Example 1, the breakdown voltage of the edge termination region 2 can be made significantly higher than that of the active region 1 compared to the comparative example, and sufficient reliability against avalanche yield can be expected. The carrier concentration in the p-type region 71 of the spatially modulated JTE structure 70 is 1.4 × 10⁻⁶. 17 / cm 3 The above 2.0 × 10 17 / cm3 When the following range B1 was observed, the breakdown voltage of the edge termination region 2 stabilized at a breakdown voltage equal to or greater than that of the active region 1, regardless of whether the insulating layer on the front surface of the semiconductor substrate 40 was charged or not. Therefore, the target carrier concentration of the p-type region 71 was set to the average value of the carrier concentration range B1, which is 1.7 × 10⁻⁶. 17 / cm 3 This allows for a carrier concentration variation of approximately ±20% in the p-type region 71.

[0164] Generally, the range of variation in impurity concentration during ion implantation is less than ±10% from the target impurity concentration. Therefore, in Example 1, it can be seen that the acceptable range of variation in carrier concentration in the p-type region 71 of the spatially modulated JTE structure 70 can be secured over a wider range than the range of variation in impurity concentration during ion implantation. The numerical range of carrier concentration in the p-type region 71 of the spatially modulated JTE structure 70 described above is the numerical range when the activation rate of the aluminum ion-implanted to form the p-type region 71 is 100%. Here, the carrier concentration of the p-type region 71 [ / cm³] 3 Regarding ], since the thickness of the JTE is approximately 0.5 μm, the horizontal axis of Figure 10 represents the JTE dose [ / cm 2 ] to 2 × 10 4 It is considered to be roughly the same as the value doubled.

[0165] As mentioned above, the activation rate of impurities ion-implanted into the silicon carbide layer (= concentration of activated impurities / concentration of ion-implanted impurities × 100) is generally between 70% and 80%. Therefore, for example, if the activation rate of impurities is 70%, the carrier concentration in the p-type region 71 is 1.7 × 10⁻⁶. 17 / cm 3 To achieve this, the target impurity concentration in the p-type region 71 by ion implantation should be 2.4 × 10⁻⁶. 17 / cm 3 The concentration should be approximately 1.4 times the carrier concentration. Thus, in Example 1, the impurity concentration of the p-type region 71 of the spatially modulated JTE structure 70 can be obtained by simulation, and the spatially modulated JTE structure 70 can be designed using the conventional method based on the impurity concentration of the p-type region 71.

[0166] Although not shown in the figures, the inventors have confirmed that, in the silicon carbide semiconductor device 10 according to Embodiment 1 described above, the breakdown voltage of the edge termination region 2 can be made sufficiently higher than the breakdown voltage of the active region 1, similar to Embodiment 1, and sufficient reliability against avalanche yielding can be expected.

[0167] (Embodiment 3) Next, the structure of the silicon carbide semiconductor device according to Embodiment 3 will be described. Figure 14 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to Embodiment 3. The layout of the silicon carbide semiconductor device 80 according to Embodiment 3, as viewed from the front side of the semiconductor substrate 40, is the same as in Figure 1. Figure 14 shows the cross-sectional structure along the cutting line A-A' in Figure 1. The difference between the silicon carbide semiconductor device 80 according to Embodiment 3 and the silicon carbide semiconductor device 60 according to Embodiment 2 (see Figure 6) is that the surface area of ​​the first n-type surface area 34 of the edge termination region 2 has the first n-type surface area 34 and n - The key feature is the provision of a second n-type surface region (fifth semiconductor region) 81 with a higher impurity concentration than the type drift region 12.

[0168] The second n-type surface region 81 is a diffusion region formed by ion implantation within the first n-type surface region 34 (n-type silicon carbide layer 42c). The second n-type surface region 81 is p ++ Type contact extension portion 15a and n + Between the channel stopper region 33 and the edge termination region 2, p ++ Type contact extensions 15a and n + It is provided in contact with the type channel stopper region 33. The second n-type surface region 81 is in contact with the insulating layer (field oxide film 25 and interlayer insulating film 19) on the front surface of the semiconductor substrate 40 in the edge termination region 2. The thickness t3 of the second n-type surface region 81 is n + It is preferable that the thickness is thinner than the thickness of the type channel stopper region 33. The thickness t3 of the second n-type surface region 81 is, for example, about 0.1 μm or more. The second n-type surface region 81 is a spatially modulated JTE structure 70 (p-type region 71 and p -It is preferable that the depth is such that it does not touch the mold region 72), and that it is as thin as possible.

[0169] The second n-type surface region 81 has the function of mitigating the adverse effects on the first n-type surface region 34 caused by charges accumulated in the insulating layer on the front surface of the semiconductor substrate 40. For example, if negative charges accumulate between the passivation film (not shown) and the interlayer insulating film 19, there is a risk that holes will accumulate in the surface region of the first n-type surface region 34 and a p-type inversion layer will be formed. If the surface region of the first n-type surface region 34 is inverted to p-type, the adverse effects on the breakdown voltage characteristics will increase, and the breakdown voltage will drop sharply. In Embodiment 3, the second n-type surface region 81 suppresses the inversion of the surface region of the first n-type surface region 34 to p-type due to negative charges accumulated in the insulating layer on the front surface of the semiconductor substrate 40. For example, the impurity concentration of the second n-type surface region 81 is set to approximately the same level as the impurity concentration of the n-type current diffusion region (not shown) and the spatial modulation JTE structure 70 (e.g., 10 17 / cm 3 By reducing the number of units to approximately [number], the pressure resistance characteristics can be made more stable.

[0170] The method for manufacturing the silicon carbide semiconductor device 80 according to Embodiment 3 is obtained by adding an ion implantation step for forming a second n-type surface region to the method for manufacturing the silicon carbide semiconductor device 60 according to Embodiment 2.

[0171] As described above, according to Embodiment 3, by providing a second n-type surface region, the adverse effects of charge accumulated on the insulating layer on the surface of the semiconductor substrate due to the long-term operation of the silicon carbide semiconductor device can be mitigated, and the same effects as in Embodiments 1 and 2 (suppression of breakdown voltage fluctuations and improvement of reliability) can be further obtained. Furthermore, according to Embodiment 3, since the adverse effects of charge accumulated on the insulating layer on the surface of the semiconductor substrate are mitigated by the second n-type surface region, breakdown voltage fluctuations can be suppressed even if the manufacturing variation of the impurity concentration of the spatially modulated JTE structure becomes large.

[0172] (Example 2) The breakdown voltage characteristics of the silicon carbide semiconductor device 80 according to the above-described embodiment 3 (hereinafter referred to as Embodiment 2: see Figure 14) were verified. Figure 15 is a characteristic diagram showing the simulation results of the breakdown voltage characteristics of Embodiment 2. The horizontal axis of Figure 15 represents the amount of aluminum ion implantation dose (JTE dose) required to form the p-type region 71 of the spatial modulation JTE structure 70 of Embodiment 2. The vertical axis of Figure 15 represents the breakdown voltage of the edge termination region 2 of Embodiment 2.

[0173] Figure 15 shows three results: when the insulating layer (field oxide film 25 and interlayer insulating film 19) on the front surface of the semiconductor substrate 40 becomes positively charged (positive charge accumulates) due to long-term operation of the MOSFET (Example 2); when the insulating layer becomes negatively charged (negative charge accumulates) due to long-term operation of the MOSFET; and when the insulating layer is uncharged (zero charge). The difference between Example 2 and Example 1 is that a second n-type surface region 81 is provided on the surface region of the first n-type surface region 34 of the edge termination region 2.

[0174] As shown in Figure 15, in Example 2, the breakdown voltage of the edge termination region 2 was made significantly higher than that of the active region 1 compared to the comparative example described above (see Figure 11), confirming that sufficient reliability against avalanche yielding can be expected. Furthermore, in Example 2, the carrier concentration in the p-type region 71 of the spatially modulated JTE structure 70 was 1.6 × 10⁻⁶. 17 / cm 3 The above 3.8 × 10 17 / cm 3 When C1 was within the following range, the breakdown voltage of the edge termination region 2 stabilized at a breakdown voltage equal to or greater than the breakdown voltage of the active region 1, regardless of whether the insulating layer on the front surface of the semiconductor substrate 40 was charged or not.

[0175] Therefore, in Example 2, the range C1 of the carrier concentration in the p-type region 71 of the spatially modulated JTE structure 70 can be made wider than the range B1 of the carrier concentration in the p-type region 71 of the spatially modulated JTE structure 70 in Example 1 (see Figure 10). That is, in Example 2, the spatially modulated JTE structure 70 (p-type region 71 and p -It was confirmed that even if the manufacturing variation in the impurity concentration of the mold region 72) becomes large, the breakdown voltage of the edge termination region 2 can be stably ensured to be higher than or equal to the breakdown voltage of the active region 1.

[0176] In Example 2, the target carrier concentration in the p-type region 71 is set to the average value of the carrier concentration range C1, which is 2.7 × 10⁻⁶. 17 / cm 3 This allows for a variation of approximately ±40% in the carrier concentration of the p-type region 71. The numerical range of the carrier concentration of the p-type region 71 of the spatially modulated JTE structure 70 described above is the numerical range when the activation rate of the aluminum ion-implanted to form the p-type region 71 is 100%. Here, the carrier concentration of the p-type region 71 [ / cm³] 3 Regarding ], since the thickness of the JTE is approximately 0.5 μm, the horizontal axis of Figure 15 represents the JTE dose [ / cm 2 ] to 2 × 10 4 It is considered to be roughly the same as the value doubled.

[0177] In summary, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit of the invention. For example, the spatial modulation JTE structure is the JTE region (first second conductivity type breakdown voltage region) that constitutes the single-zone JTE structure (the JTE region and the n outside of it). - Between the drift region and the JTE region, adjacent to the JTE region, the impurity concentration of the JTE region and n - The structure may also include a spatial modulation region having an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration with respect to the impurity concentration of the drift region. In this case, the spatial modulation region may consist of a p-type region with the same impurity concentration as the JTE region and an n-type region. - The present invention is formed by repeatedly arranging type drift regions and other elements adjacent to each other in a predetermined pattern. Furthermore, the present invention also holds true when the conductivity type (n-type, p-type) is reversed. [Industrial applicability]

[0178] As described above, the silicon carbide semiconductor device according to the present invention is useful as a power semiconductor device used in power conversion devices, power supply devices for various industrial machines, and the like. [Explanation of symbols]

[0179] 1 active area 1a Central part of the active region 1b Periphery of the active region 2 Edge Termination Region 10,60,80 Silicon Carbide Semiconductor Device 11 n + Type drain region 12 n - Type drift region 13 p-type base region 13a,64 p type base extension 14 n + Type source area 15 p ++ Type Contact Area 15a p ++ Type Contact Extension 15b p ++ Outer corner portion of the bottom of the extended contact section 16 Trench 17 Gate insulating film 18 Guard gate 19 Interlayer insulating film 20 source electrodes pp. 21, 22 + type area 22a,61 p + Mold extension 22b p + Outer corner portion of the bottom of the mold extension 23 Drain electrode 24,65 p-type outer region 24b p-type outer corner at the bottom 25 Field Oxide Film 26-gate polysilicon wiring layer 30,70 Spatial Modulation JTE Structure 30a, 30c ,70a,70c JTE area 30b, 30d ,70b,70d Spatial modulation domain 31,71 p-type region of spatially modulated JTE structure 32,72 p of spatially modulated JTE structure- type area 33 n + Type channel stopper region 34 First n-type surface region of the edge termination region 40 Semiconductor substrates 41 n + Mold starting substrate 42,42a,42b,42c n-type silicon carbide layers 50 semiconductor wafers 50a Chip area 50b Dicing Line 51 n + Mold starting wafer 52,62 p + Lower part of the mold extension 53,63 p + Upper part of the mold extension 71a Lower part of the p-type region of the spatially modulated JTE structure 72a p of spatially modulated JTE structure - Lower part of the type domain 71b Upper part of the p-type region of the spatially modulated JTE structure 72b p of spatially modulated JTE structure - Top of the type region 81 Second n-type surface region of the edge termination region t1,t2 Thickness of the first n-type surface region in the edge termination area t3 Thickness of the 2n-type surface region in the edge termination area w1, w2, w3 Width of the step at the outer edge of the p-type outer peripheral region

Claims

1. A semiconductor substrate made of silicon carbide and having a first main surface that is flat over its entire surface, An active region provided on the semiconductor substrate, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, extending from the active region to the terminal region, In the active region, a second semiconductor region of a second conductivity type is provided between the first main surface and the first semiconductor region, A device structure comprising a pn junction between the first semiconductor region and the second semiconductor region, wherein a current flows through the pn junction, Between the element structure and the termination region, a second conductivity type outer peripheral region is provided between the first main surface and the first semiconductor region, surrounding the periphery of the element structure, A first electrode provided on the first main surface and electrically connected to the second semiconductor region and the second conductivity type outer peripheral region, A second electrode is provided on the second main surface of the semiconductor substrate and is electrically connected to the first semiconductor region, Within the terminal region, a plurality of second conductivity type breakdown voltage regions are provided concentrically and at a distance from each other, surrounding the active region, at a depth position away from the first main surface, within the first semiconductor region, A breakdown structure comprising multiple second conductivity type breakdown regions, wherein the overall second conductivity type impurity concentration is gradually reduced from the inside to the outside, Equipped with, The outer end of the second conductive outer peripheral region is a plane perpendicular to the first main surface, The bottom of the second conductivity type breakdown region is located deeper from the first main surface than the bottom of the second conductivity type outer peripheral region. The innermost first second conductivity type breakdown region among the multiple second conductivity type breakdown regions surrounds the outer corner portion of the bottom of the second conductivity type outer peripheral region, The aforementioned device structure is A third semiconductor region of a first conductivity type is selectively provided between the first main surface and the second semiconductor region and is electrically connected to the first electrode, A trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region, A gate electrode is provided inside the trench via a gate insulating film, Between the first semiconductor region and the second semiconductor region, a second conductivity type high-concentration region with a higher impurity concentration than the second semiconductor region is selectively provided on the second main surface side of the bottom surface of the trench, Equipped with, The aforementioned second conductive outer region is, A first outer peripheral region is a portion of the second semiconductor region that is located outside the element structure, This is a portion located outside the element structure of the second conductivity type high-concentration region, and is provided between the first outer peripheral region and the first semiconductor region, with the second outer peripheral region being in contact with the first outer peripheral region and the first semiconductor region. Between the first main surface and the first outer peripheral region, there is a third outer peripheral region provided in contact with the first outer peripheral region, which has a higher impurity concentration than the first outer peripheral region. The first second conductivity type breakdown region surrounds the outer corner portion of the bottom of the second outer peripheral region, A silicon carbide semiconductor device characterized in that the carrier concentration in the second conductivity type breakdown voltage region is greater than or equal to the carrier concentration in the second semiconductor region and less than the carrier concentration in the second conductivity type high concentration region.

2. A semiconductor substrate made of silicon carbide and having a first main surface that is flat over its entire surface, An active region provided on the semiconductor substrate, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, extending from the active region to the terminal region, In the active region, a second semiconductor region of a second conductivity type is provided between the first main surface and the first semiconductor region, A device structure comprising a pn junction between the first semiconductor region and the second semiconductor region, wherein a current flows through the pn junction, Between the element structure and the termination region, a second conductivity type outer peripheral region is provided between the first main surface and the first semiconductor region, surrounding the periphery of the element structure, A first electrode provided on the first main surface and electrically connected to the second semiconductor region and the second conductivity type outer peripheral region, A second electrode is provided on the second main surface of the semiconductor substrate and is electrically connected to the first semiconductor region, Within the terminal region, a plurality of second conductivity type breakdown voltage regions are provided concentrically and at a distance from each other, surrounding the active region, at a depth position away from the first main surface, within the first semiconductor region, A breakdown structure comprising multiple second conductivity type breakdown regions, wherein the overall second conductivity type impurity concentration is gradually reduced from the inside to the outside, Equipped with, The outer end of the second conductive outer peripheral region is a plane perpendicular to the first main surface, The bottom of the second conductivity type breakdown region is located deeper from the first main surface than the bottom of the second conductivity type outer peripheral region. The innermost first second conductivity type breakdown region among the multiple second conductivity type breakdown regions surrounds the outer corner portion of the bottom of the second conductivity type outer peripheral region, The aforementioned pressure-resistant structure is The first second conductivity type breakdown voltage region and, Among the plurality of second conductivity type breakdown pressure regions, a plurality of second second conductivity type breakdown pressure regions having the same impurity concentration as the first second conductivity type breakdown pressure region, adjacent to the outside of the first second conductivity type breakdown pressure region, Among the plurality of second conductivity type breakdown regions, a third second conductivity type breakdown region is adjacent to the outside of the first second conductivity type breakdown region, located between all adjacent second second conductivity type breakdown regions, and extends beyond the outermost second second conductivity type breakdown region, and has a lower impurity concentration than the first second conductivity type breakdown region. It comprises a plurality of fourth second conductivity type breakdown regions having the same impurity concentration as the third second conductivity type breakdown region, excluding the first second conductivity type breakdown region, the second second conductivity type breakdown region, and the third second conductivity type breakdown region from among the plurality of second conductivity type breakdown regions, and adjacent to the outside of the third second conductivity type breakdown region. Outside the first second conductivity type breakdown region, adjacent to the first second conductivity type breakdown region, a first spatial modulation region is arranged having an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration between the impurity concentration of the first second conductivity type breakdown region and the impurity concentration of the third second conductivity type breakdown region. Furthermore, by arranging a second spatial modulation region adjacent to the third second conductivity type breakdown region outside the third second conductivity type breakdown region, and having an impurity concentration distribution spatially equivalent to an intermediate impurity concentration between the impurity concentration of the third second conductivity type breakdown region and the impurity concentration of the first semiconductor region, the overall second conductivity type impurity concentration of the breakdown structure is gradually reduced from the inside to the outside. The first spatial modulation region is formed by repeatedly arranging the second second conductivity type breakdown voltage region and a part of the third second conductivity type breakdown voltage region adjacent to each other in a predetermined pattern. The silicon carbide semiconductor device is characterized in that the second spatial modulation region is formed by repeatedly arranging the fourth second conductivity type breakdown voltage region and the first semiconductor region alternately in a predetermined pattern.

3. A semiconductor substrate made of silicon carbide and having a first main surface that is flat over its entire surface, An active region provided on the semiconductor substrate, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, extending from the active region to the terminal region, In the active region, a second semiconductor region of a second conductivity type is provided between the first main surface and the first semiconductor region, A device structure comprising a pn junction between the first semiconductor region and the second semiconductor region, wherein a current flows through the pn junction, Between the element structure and the termination region, a second conductivity type outer peripheral region is provided between the first main surface and the first semiconductor region, surrounding the periphery of the element structure, A first electrode provided on the first main surface and electrically connected to the second semiconductor region and the second conductivity type outer peripheral region, A second electrode is provided on the second main surface of the semiconductor substrate and is electrically connected to the first semiconductor region, Within the terminal region, a plurality of second conductivity type breakdown voltage regions are provided concentrically and at a distance from each other, surrounding the active region, at a depth position away from the first main surface, within the first semiconductor region, A breakdown structure comprising multiple second conductivity type breakdown regions, wherein the overall second conductivity type impurity concentration is gradually reduced from the inside to the outside, Equipped with, The outer end of the second conductive outer peripheral region is a plane perpendicular to the first main surface, The bottom of the second conductivity type breakdown region is located deeper from the first main surface than the bottom of the second conductivity type outer peripheral region. The innermost first second conductivity type breakdown region among the multiple second conductivity type breakdown regions surrounds the outer corner portion of the bottom of the second conductivity type outer peripheral region, A fourth semiconductor region of a first conductivity type with a higher impurity concentration than the first semiconductor region is provided between the first main surface and the breakdown structure. A silicon carbide semiconductor device characterized in that a fifth semiconductor region of a first conductivity type having a higher impurity concentration than the fourth semiconductor region is provided on the surface region of the fourth semiconductor region.

4. A semiconductor substrate made of silicon carbide and having a first main surface that is flat over its entire surface, An active region provided on the semiconductor substrate, The semiconductor substrate is provided with a terminal region that surrounds the active region, A first semiconductor region of a first conductivity type is provided inside the semiconductor substrate, extending from the active region to the terminal region, In the active region, a second semiconductor region of a second conductivity type is provided between the first main surface and the first semiconductor region, A device structure comprising a pn junction between the first semiconductor region and the second semiconductor region, wherein a current flows through the pn junction, Between the element structure and the termination region, a second conductivity type outer peripheral region is provided between the first main surface and the first semiconductor region, surrounding the periphery of the element structure, A first electrode provided on the first main surface and electrically connected to the second semiconductor region and the second conductivity type outer peripheral region, A second electrode is provided on the second main surface of the semiconductor substrate and is electrically connected to the first semiconductor region, Within the terminal region, a plurality of second conductivity type breakdown voltage regions are provided concentrically and at a distance from each other, surrounding the active region, at a depth position away from the first main surface, within the first semiconductor region, A breakdown structure comprising multiple second conductivity type breakdown regions, wherein the overall second conductivity type impurity concentration is gradually reduced from the inside to the outside, Equipped with, The outer edge of the second conductive outer peripheral region has multiple steps formed, which are recessed inward by a predetermined width in the depth direction as they move away from the first main surface, and has multiple extending portions that extend outward in the normal direction according to these steps, terminating further outward as they get closer to the first main surface. The bottom of the second conductivity type breakdown voltage region is located at a shallower depth on the first main surface side than the bottom of the second conductivity type outer peripheral region. The upper surface of the second conductivity type breakdown region is at the same depth as the bottom of the first extension portion that is closest to the first main surface among the plurality of extension portions, or at a depth shallower on the first main surface side than the bottom of the first extension portion. A silicon carbide semiconductor device characterized in that the innermost first second conductivity type breakdown region among the plurality of second conductivity type breakdown regions is in contact with the outer corner portion of the bottom of the first extension portion or surrounds the outer corner portion of the bottom of the first extension portion.

5. The silicon carbide semiconductor device according to claim 4, characterized in that the predetermined width is 2 μm or more.

6. The silicon carbide semiconductor device according to claim 4 or 5, characterized in that the concentration of the second conductivity type impurity in the portion of the outer peripheral region of the second conductivity type that is deeper on the second main surface side than the breakdown structure is 1 × 10¹⁹ / cm³ or less.

7. The element structure is A third semiconductor region of a first conductivity type is selectively provided between the first main surface and the second semiconductor region and is electrically connected to the first electrode, A trench that penetrates the third semiconductor region and the second semiconductor region and reaches the first semiconductor region, A gate electrode is provided inside the trench via a gate insulating film, Between the first semiconductor region and the second semiconductor region, a second conductivity type high-concentration region with a higher impurity concentration than the second semiconductor region is selectively provided on the second main surface side of the bottom surface of the trench, Equipped with, The aforementioned second conductive outer region is, A first outer peripheral region is a portion of the second semiconductor region that is located outside the element structure, This is a portion located outside the element structure of the second conductivity type high-concentration region, and is provided between the first outer peripheral region and the first semiconductor region, with the second outer peripheral region being in contact with the first outer peripheral region and the first semiconductor region. Between the first main surface and the first outer peripheral region, there is a third outer peripheral region provided in contact with the first outer peripheral region, which has a higher impurity concentration than the first outer peripheral region. The step at the outer end of the second conductive outer region is formed by the first outer region ending inward of the third outer region, and the second outer region ending inward of the first outer region. The first extended portion of the outer end of the second conductive outer peripheral region is a portion of the third outer peripheral region located outside the first outer peripheral region, The silicon carbide semiconductor device according to any one of 4 to 6, characterized in that the first second conductivity type breakdown voltage region is in contact with the outer corner portion of the bottom of the third outer peripheral region or surrounds the outer corner portion of the bottom of the third outer peripheral region.

8. A silicon carbide semiconductor device according to any one of claims 1, 2, 4 to 7, characterized in that a fourth semiconductor region of a first conductivity type with a higher impurity concentration than the first semiconductor region is provided between the first main surface and the pressure-resistant structure.

9. The silicon carbide semiconductor device according to claim 7, characterized in that the carrier concentration in the second conductivity type breakdown region is equal to or greater than the carrier concentration in the second semiconductor region and lower than the carrier concentration in the second conductivity type high concentration region.

10. The pressure-resistant structure is The first second conductivity type breakdown voltage region and, Among the plurality of second conductivity type breakdown pressure regions, a plurality of second second conductivity type breakdown pressure regions having the same impurity concentration as the first second conductivity type breakdown pressure region, adjacent to the outside of the first second conductivity type breakdown pressure region, Among the plurality of second conductivity type breakdown regions, a third second conductivity type breakdown region is adjacent to the outside of the first second conductivity type breakdown region, located between all adjacent second second conductivity type breakdown regions, and extends beyond the outermost second second conductivity type breakdown region, and has a lower impurity concentration than the first second conductivity type breakdown region. It comprises a plurality of fourth second conductivity type breakdown regions having the same impurity concentration as the third second conductivity type breakdown region, excluding the first second conductivity type breakdown region, the second second conductivity type breakdown region, and the third second conductivity type breakdown region from among the plurality of second conductivity type breakdown regions, and adjacent to the outside of the third second conductivity type breakdown region. Outside the first second conductivity type breakdown region, adjacent to the first second conductivity type breakdown region, a first spatial modulation region is arranged having an impurity concentration distribution that is spatially equivalent to an intermediate impurity concentration between the impurity concentration of the first second conductivity type breakdown region and the impurity concentration of the third second conductivity type breakdown region. Furthermore, by arranging a second spatial modulation region adjacent to the third second conductivity type breakdown region outside the third second conductivity type breakdown region, and having an impurity concentration distribution spatially equivalent to an intermediate impurity concentration between the impurity concentration of the third second conductivity type breakdown region and the impurity concentration of the first semiconductor region, the overall second conductivity type impurity concentration of the breakdown structure is gradually reduced from the inside to the outside. The first spatial modulation region is formed by repeatedly arranging the second second conductivity type breakdown voltage region and a part of the third second conductivity type breakdown voltage region adjacent to each other in a predetermined pattern. The silicon carbide semiconductor device according to any one of 1, 4 to 7, 9, characterized in that the second spatial modulation region is formed by repeatedly arranging the fourth second conductivity type breakdown voltage region and the first semiconductor region alternately in a predetermined pattern.

11. Between the first main surface and the first semiconductor region, further comprising a sixth semiconductor region of a first conductivity type having a higher impurity concentration than the first semiconductor region, located outside the fourth semiconductor region, The silicon carbide semiconductor device according to claim 3, characterized in that the thickness of the fifth semiconductor region is thinner than the thickness of the sixth semiconductor region.

12. The silicon carbide semiconductor device according to claim 3 or 11, characterized in that the thickness of the fifth semiconductor region is 0.1 μm or more.

Images